diff --git a/source/daplink/cmsis-dap/DAP_vendor.c b/source/daplink/cmsis-dap/DAP_vendor.c index 72b74fb0f0..cac707aa17 100644 --- a/source/daplink/cmsis-dap/DAP_vendor.c +++ b/source/daplink/cmsis-dap/DAP_vendor.c @@ -41,6 +41,7 @@ #include "util.h" #include #include "daplink_vendor_commands.h" +#include "daplink_swd_dynamic_pins.h" #ifdef DRAG_N_DROP_SUPPORT #include "file_stream.h" @@ -233,7 +234,19 @@ uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { case ID_DAP_Vendor20: break; case ID_DAP_Vendor21: break; case ID_DAP_Vendor22: break; - case ID_DAP_Vendor23: break; + case ID_DAP_SWDConfigurePins: { + // Select SWD output port configuration. + const int pin_set_as_int = (int)*request; + if (pin_set_as_int > (int)SWD_PIN_SET_MAX_ALLOWED) { + // Report invalid selection with 0xFF. + *response = 0xFF; + } else { + *response = + (uint8_t)swd_configure_pins((swd_pin_set_t)pin_set_as_int); + } + num += (1 << 16) | 1; + break; + } case ID_DAP_Vendor24: break; case ID_DAP_Vendor25: break; case ID_DAP_Vendor26: break; diff --git a/source/daplink/cmsis-dap/DAP_vendor.c.orig b/source/daplink/cmsis-dap/DAP_vendor.c.orig new file mode 100644 index 0000000000..72b74fb0f0 --- /dev/null +++ b/source/daplink/cmsis-dap/DAP_vendor.c.orig @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2013-2020 Arm Limited. All rights reserved. + * Copyright 2019, Cypress Semiconductor Corporation + * or a subsidiary of Cypress Semiconductor Corporation. + * Copyright (c) 2021 Chris Reed + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 20. May 2015 + * $Revision: V1.10 + * + * Project: CMSIS-DAP Source + * Title: DAP_vendor.c CMSIS-DAP Vendor Commands + * + *---------------------------------------------------------------------------*/ + +#include "rl_usb.h" +#include "DAP_config.h" +#include "DAP.h" +#include "info.h" +#include "daplink.h" +#include DAPLINK_MAIN_HEADER +#include "uart.h" +#include "settings.h" +#include "target_family.h" +#include "flash_manager.h" +#include "util.h" +#include +#include "daplink_vendor_commands.h" + +#ifdef DRAG_N_DROP_SUPPORT +#include "file_stream.h" + +// Reusing the MSC sector buffer from vfs_manager.c to save memory +// as using both at the same time will break anyway +extern uint32_t usb_buffer[VFS_SECTOR_SIZE / sizeof(uint32_t)]; +static uint8_t *file_stream_buffer = (uint8_t *)usb_buffer; +static const uint32_t file_stream_buffer_size = sizeof(usb_buffer); +static uint16_t file_stream_buffer_pos = 0; +#endif + +//************************************************************************************************** +/** +\defgroup DAP_Vendor_Adapt_gr Adapt Vendor Commands +\ingroup DAP_Vendor_gr +@{ + +The file DAP_vendor.c provides template source code for extension of a Debug Unit with +Vendor Commands. Copy this file to the project folder of the Debug Unit and add the +file to the MDK-ARM project under the file group Configuration. +*/ + +/** Process DAP Vendor Command and prepare Response Data +\param request pointer to request data +\param response pointer to response data +\return number of bytes in response (lower 16 bits) + number of bytes in request (upper 16 bits) +*/ +uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) { + uint32_t num = (1U << 16) | 1U; + + *response++ = *request; // copy Command ID + + switch (*request++) { // first byte in request is Command ID + case ID_DAP_GetUniqueID: { + const char *id_str = info_get_unique_id(); + uint8_t len = strlen(id_str); + *response++ = len; + memcpy(response, id_str, len); + num += (len + 1); // increment response count by ID length + length byte + break; + } + case ID_DAP_UART_GetLineCoding: { + // get line coding + int32_t read_len = sizeof(CDC_LINE_CODING); + CDC_LINE_CODING cdc_line_coding; + USBD_CDC_ACM_PortGetLineCoding(&cdc_line_coding); + memcpy(response, &cdc_line_coding, read_len); + num += (read_len + 1); + break; + } + case ID_DAP_UART_SetConfiguration: { + // set uart configuration + CDC_LINE_CODING cdc_line_coding; + USBD_CDC_ACM_PortGetLineCoding(&cdc_line_coding); + //set BaudRate + uint32_t baud_rate = 0; + memcpy(&baud_rate, request, sizeof(uint32_t)); + cdc_line_coding.dwDTERate = baud_rate; + USBD_CDC_ACM_PortSetLineCoding(&cdc_line_coding); + USBD_CDC_ACM_SendBreak(0); + *response = 1; + num += (sizeof(uint32_t) << 16) | 1; + break; + } + case ID_DAP_UART_Read: { + // uart read + int32_t read_len = 62; + read_len = uart_read_data(response + 1, read_len); + if (read_len) { + main_blink_cdc_led(MAIN_LED_FLASH); + } + response[0] = read_len; + // increment request and response count + num += (read_len + 1); + break; + } + case ID_DAP_UART_Write: { + // uart write + int32_t write_len = *request; + request++; + uart_write_data((uint8_t *)request, write_len); + main_blink_cdc_led(MAIN_LED_FLASH); + *response = 1; + num += ((write_len + 1) << 16) | 1; + break; + } + case ID_DAP_Vendor5: break; + case ID_DAP_Vendor6: break; + case ID_DAP_Vendor7: break; + case ID_DAP_SetUSBTestMode: { + *response = 1; + if (0 == *request) { + main_usb_set_test_mode(false); + } else if (1 == *request) { + main_usb_set_test_mode(true); + } else { + *response = 0; + } + num += (1U << 16) | 1U; // increment request and response count each by 1 + break; + } + case ID_DAP_ResetTargetIfNoAutoReset: { + // reset target + *response = 1; + if (!config_get_auto_rst()) { + target_set_state(RESET_RUN); + } + num += 1; + break; + } +#ifdef DRAG_N_DROP_SUPPORT + case ID_DAP_MSD_Open: { + // open mass storage device stream + *response = stream_open((stream_type_t)(*request)); + num += (1 << 16) | 1; + file_stream_buffer_pos = 0; + break; + } + case ID_DAP_MSD_Close: { + // write the remaining data in the buffer + if (file_stream_buffer_pos) { + *response = stream_write(file_stream_buffer, file_stream_buffer_pos); + file_stream_buffer_pos = 0; + if (ERROR_SUCCESS != *response && + ERROR_SUCCESS_DONE != *response && + ERROR_SUCCESS_DONE_OR_CONTINUE != *response) { + num += 1; + break; + } + } + // close mass storage device stream + *response = stream_close(); + num += 1; + break; + } + case ID_DAP_MSD_Write: { + // write to mass storage device in blocks of length == vfs sector size + uint32_t write_len = *request; + request++; + main_blink_msc_led(MAIN_LED_FLASH); + if (file_stream_buffer_pos || (write_len % VFS_SECTOR_SIZE)) { + uint32_t write_len_left = write_len; + while (write_len_left > 0) { + uint16_t copy_len = MIN(VFS_SECTOR_SIZE - file_stream_buffer_pos, write_len_left); + memcpy(file_stream_buffer + file_stream_buffer_pos, request, copy_len); + file_stream_buffer_pos += copy_len; + write_len_left -= copy_len; + request += copy_len; + if (file_stream_buffer_pos >= VFS_SECTOR_SIZE) { + *response = stream_write(file_stream_buffer, VFS_SECTOR_SIZE); + file_stream_buffer_pos = 0; + } else { + *response = ERROR_SUCCESS; + } + } + } else { + *response = stream_write((uint8_t *)request, write_len); + } + num += ((write_len + 1) << 16) | 1; + break; + } +#endif + case ID_DAP_SelectEraseMode: { + // switching between chip erase and page erase + // COMMAND(OUT Packet) + // BYTE 0 1000 1110 0x8D + // BYTE 1 Desired Mode: + // 0x00 - Chip Erase + // nonzero - Page Erase + // RESPONSE(IN Packet) + // BYTE 0 + // 0x00 - OK + *response = DAP_OK; + if (0x00U == *request) { + flash_manager_set_page_erase(false); + } else { + flash_manager_set_page_erase(true); + } + num += (1U << 16) | 1U; // increment request and response count each by 1 + break; + } + case ID_DAP_Vendor14: break; + case ID_DAP_Vendor15: break; + case ID_DAP_Vendor16: break; + case ID_DAP_Vendor17: break; + case ID_DAP_Vendor18: break; + case ID_DAP_Vendor19: break; + case ID_DAP_Vendor20: break; + case ID_DAP_Vendor21: break; + case ID_DAP_Vendor22: break; + case ID_DAP_Vendor23: break; + case ID_DAP_Vendor24: break; + case ID_DAP_Vendor25: break; + case ID_DAP_Vendor26: break; + case ID_DAP_Vendor27: break; + case ID_DAP_Vendor28: break; + case ID_DAP_Vendor29: break; + case ID_DAP_Vendor30: break; + case ID_DAP_Vendor31: break; + default: break; + } + + return (num); +} + +///@} diff --git a/source/daplink/cmsis-dap/daplink_swd_dynamic_pins.c b/source/daplink/cmsis-dap/daplink_swd_dynamic_pins.c new file mode 100644 index 0000000000..7512a3959c --- /dev/null +++ b/source/daplink/cmsis-dap/daplink_swd_dynamic_pins.c @@ -0,0 +1,17 @@ +#include "daplink_swd_dynamic_pins.h" + +static swd_pin_set_t latched_configured_pins = SWD_PIN_SET_DEFAULT; +static swd_pin_set_t pending_configured_pins = SWD_PIN_SET_DEFAULT; + +swd_pin_set_t swd_configure_pins(swd_pin_set_t pin_set) { + pending_configured_pins = pin_set; + return latched_configured_pins; +} + +swd_pin_set_t swd_get_configured_pins(void) { + return latched_configured_pins; +} + +void swd_configure_latch_pins(void) { + latched_configured_pins = pending_configured_pins; +} diff --git a/source/daplink/cmsis-dap/daplink_swd_dynamic_pins.h b/source/daplink/cmsis-dap/daplink_swd_dynamic_pins.h new file mode 100644 index 0000000000..3f99db0bfc --- /dev/null +++ b/source/daplink/cmsis-dap/daplink_swd_dynamic_pins.h @@ -0,0 +1,22 @@ +#ifndef DAPLINK_SWD_DYNAMIC_PINS_H_ +#define DAPLINK_SWD_DYNAMIC_PINS_H_ + +typedef enum { + SWD_PIN_SET_DEFAULT, + SWD_PIN_SET_ALT_1, + + SWD_PIN_SET_MAX_ALLOWED = SWD_PIN_SET_ALT_1, +} swd_pin_set_t; + +// Stages the provided `pin_set` for latching on the next target connection. +// +// Returns the currently latched `swd_pin_set_t`. +swd_pin_set_t swd_configure_pins(swd_pin_set_t pin_set); + +// Gets the currently latched `swd_pin_set_t`. +swd_pin_set_t swd_get_configured_pins(void); + +// Latches the last configured `swd_pin_set_t` choice. +void swd_configure_latch_pins(void); + +#endif // DAPLINK_SWD_DYNAMIC_PINS_H_ diff --git a/source/daplink/cmsis-dap/daplink_vendor_commands.h b/source/daplink/cmsis-dap/daplink_vendor_commands.h index 18aee7492b..3b3b1d75e4 100644 --- a/source/daplink/cmsis-dap/daplink_vendor_commands.h +++ b/source/daplink/cmsis-dap/daplink_vendor_commands.h @@ -35,5 +35,6 @@ #define ID_DAP_MSD_Close ID_DAP_Vendor11 #define ID_DAP_MSD_Write ID_DAP_Vendor12 #define ID_DAP_SelectEraseMode ID_DAP_Vendor13 +#define ID_DAP_SWDConfigurePins ID_DAP_Vendor23 //@} diff --git a/source/hic_hal/atmel/sam3u2c/DAP_config.h b/source/hic_hal/atmel/sam3u2c/DAP_config.h index 22b5c04780..868c79263f 100644 --- a/source/hic_hal/atmel/sam3u2c/DAP_config.h +++ b/source/hic_hal/atmel/sam3u2c/DAP_config.h @@ -23,6 +23,7 @@ #define __DAP_CONFIG_H__ #include "IO_Config.h" +#include "daplink_swd_dynamic_pins.h" //************************************************************************************************** /** @@ -198,23 +199,49 @@ __STATIC_INLINE void PORT_SWD_SETUP(void) { PMC->PMC_PCER0 = (1 << 10) | (1 << 11) | (1 << 12); // Enable clock for all PIOs - PIN_nRESET_PORT->PIO_MDDR = PIN_nRESET; // Disable multi drive - PIN_nRESET_PORT->PIO_PUER = PIN_nRESET; // pull-up enable - PIN_nRESET_PORT->PIO_SODR = PIN_nRESET; // HIGH - PIN_nRESET_PORT->PIO_OER = PIN_nRESET; // output - PIN_nRESET_PORT->PIO_PER = PIN_nRESET; // GPIO control - - PIN_SWCLK_PORT->PIO_MDDR = PIN_SWCLK; // Disable multi drive - PIN_SWCLK_PORT->PIO_PUER = PIN_SWCLK; // pull-up enable - PIN_SWCLK_PORT->PIO_SODR = PIN_SWCLK; // HIGH - PIN_SWCLK_PORT->PIO_OER = PIN_SWCLK; // output - PIN_SWCLK_PORT->PIO_PER = PIN_SWCLK; // GPIO control - - PIN_SWDIO_PORT->PIO_MDDR = PIN_SWDIO; // Disable multi drive - PIN_SWDIO_PORT->PIO_PUER = PIN_SWDIO; // pull-up enable - PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; // HIGH - PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO; // output - PIN_SWDIO_PORT->PIO_PER = PIN_SWDIO; // GPIO control + swd_configure_latch_pins(); + + switch (swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + PIN_nRESET_PORT_ALT_1->PIO_MDER = PIN_nRESET_ALT_1; // Enable multi drive (open-drain on nRST) + PIN_nRESET_PORT_ALT_1->PIO_PUER = PIN_nRESET_ALT_1; // pull-up enable + PIN_nRESET_PORT_ALT_1->PIO_SODR = PIN_nRESET_ALT_1; // HIGH + PIN_nRESET_PORT_ALT_1->PIO_OER = PIN_nRESET_ALT_1; // output + PIN_nRESET_PORT_ALT_1->PIO_PER = PIN_nRESET_ALT_1; // GPIO control + + PIN_SWCLK_PORT_ALT_1->PIO_MDDR = PIN_SWCLK_ALT_1; // Disable multi drive + PIN_SWCLK_PORT_ALT_1->PIO_PUER = PIN_SWCLK_ALT_1; // pull-up enable + PIN_SWCLK_PORT_ALT_1->PIO_SODR = PIN_SWCLK_ALT_1; // HIGH + PIN_SWCLK_PORT_ALT_1->PIO_OER = PIN_SWCLK_ALT_1; // output + PIN_SWCLK_PORT_ALT_1->PIO_PER = PIN_SWCLK_ALT_1; // GPIO control + + PIN_SWDIO_PORT_ALT_1->PIO_MDDR = PIN_SWDIO_ALT_1; // Disable multi drive + PIN_SWDIO_PORT_ALT_1->PIO_PUER = PIN_SWDIO_ALT_1; // pull-up enable + PIN_SWDIO_PORT_ALT_1->PIO_SODR = PIN_SWDIO_ALT_1; // HIGH + PIN_SWDIO_PORT_ALT_1->PIO_OER = PIN_SWDIO_ALT_1; // output + PIN_SWDIO_PORT_ALT_1->PIO_PER = PIN_SWDIO_ALT_1; // GPIO control + break; + + default: + PIN_nRESET_PORT_DEFAULT->PIO_MDER = PIN_nRESET_DEFAULT; // Enable multi drive (open-drain on nRST) + PIN_nRESET_PORT_DEFAULT->PIO_PUER = PIN_nRESET_DEFAULT; // pull-up enable + PIN_nRESET_PORT_DEFAULT->PIO_SODR = PIN_nRESET_DEFAULT; // HIGH + PIN_nRESET_PORT_DEFAULT->PIO_OER = PIN_nRESET_DEFAULT; // output + PIN_nRESET_PORT_DEFAULT->PIO_PER = PIN_nRESET_DEFAULT; // GPIO control + + PIN_SWCLK_PORT_DEFAULT->PIO_MDDR = PIN_SWCLK_DEFAULT; // Disable multi drive + PIN_SWCLK_PORT_DEFAULT->PIO_PUER = PIN_SWCLK_DEFAULT; // pull-up enable + PIN_SWCLK_PORT_DEFAULT->PIO_SODR = PIN_SWCLK_DEFAULT; // HIGH + PIN_SWCLK_PORT_DEFAULT->PIO_OER = PIN_SWCLK_DEFAULT; // output + PIN_SWCLK_PORT_DEFAULT->PIO_PER = PIN_SWCLK_DEFAULT; // GPIO control + + PIN_SWDIO_PORT_DEFAULT->PIO_MDDR = PIN_SWDIO_DEFAULT; // Disable multi drive + PIN_SWDIO_PORT_DEFAULT->PIO_PUER = PIN_SWDIO_DEFAULT; // pull-up enable + PIN_SWDIO_PORT_DEFAULT->PIO_SODR = PIN_SWDIO_DEFAULT; // HIGH + PIN_SWDIO_PORT_DEFAULT->PIO_OER = PIN_SWDIO_DEFAULT; // output + PIN_SWDIO_PORT_DEFAULT->PIO_PER = PIN_SWDIO_DEFAULT; // GPIO control + break; + } } /** Disable JTAG/SWD I/O Pins. @@ -223,18 +250,34 @@ Disables the DAP Hardware I/O pins which configures: */ __STATIC_INLINE void PORT_OFF(void) { - PIN_nRESET_PORT->PIO_PUER = PIN_nRESET; // pull-up enable - PIN_nRESET_PORT->PIO_ODR = PIN_nRESET; // input - PIN_nRESET_PORT->PIO_PER = PIN_nRESET; // GPIO control - - PIN_SWCLK_PORT->PIO_PUER = PIN_SWCLK; // pull-up enable - PIN_SWCLK_PORT->PIO_ODR = PIN_SWCLK; // input - PIN_SWCLK_PORT->PIO_PER = PIN_SWCLK; // GPIO control - - PIN_SWDIO_PORT->PIO_PUER = PIN_SWDIO; // pull-up enable - PIN_SWDIO_PORT->PIO_ODR = PIN_SWDIO; // input - PIN_SWDIO_PORT->PIO_PER = PIN_SWDIO; // GPIO control - + switch (swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + PIN_nRESET_PORT_ALT_1->PIO_PUER = PIN_nRESET_ALT_1; // pull-up enable + PIN_nRESET_PORT_ALT_1->PIO_ODR = PIN_nRESET_ALT_1; // input + PIN_nRESET_PORT_ALT_1->PIO_PER = PIN_nRESET_ALT_1; // GPIO control + + PIN_SWCLK_PORT_ALT_1->PIO_PUER = PIN_SWCLK_ALT_1; // pull-up enable + PIN_SWCLK_PORT_ALT_1->PIO_ODR = PIN_SWCLK_ALT_1; // input + PIN_SWCLK_PORT_ALT_1->PIO_PER = PIN_SWCLK_ALT_1; // GPIO control + + PIN_SWDIO_PORT_ALT_1->PIO_PUER = PIN_SWDIO_ALT_1; // pull-up enable + PIN_SWDIO_PORT_ALT_1->PIO_ODR = PIN_SWDIO_ALT_1; // input + PIN_SWDIO_PORT_ALT_1->PIO_PER = PIN_SWDIO_ALT_1; // GPIO control + break; + default: + PIN_nRESET_PORT_DEFAULT->PIO_PUER = PIN_nRESET_DEFAULT; // pull-up enable + PIN_nRESET_PORT_DEFAULT->PIO_ODR = PIN_nRESET_DEFAULT; // input + PIN_nRESET_PORT_DEFAULT->PIO_PER = PIN_nRESET_DEFAULT; // GPIO control + + PIN_SWCLK_PORT_DEFAULT->PIO_PUER = PIN_SWCLK_DEFAULT; // pull-up enable + PIN_SWCLK_PORT_DEFAULT->PIO_ODR = PIN_SWCLK_DEFAULT; // input + PIN_SWCLK_PORT_DEFAULT->PIO_PER = PIN_SWCLK_DEFAULT; // GPIO control + + PIN_SWDIO_PORT_DEFAULT->PIO_PUER = PIN_SWDIO_DEFAULT; // pull-up enable + PIN_SWDIO_PORT_DEFAULT->PIO_ODR = PIN_SWDIO_DEFAULT; // input + PIN_SWDIO_PORT_DEFAULT->PIO_PER = PIN_SWDIO_DEFAULT; // GPIO control + break; + } } // SWCLK/TCK I/O pin ------------------------------------- @@ -244,7 +287,12 @@ __STATIC_INLINE void PORT_OFF(void) */ __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void) { - return ((PIN_SWCLK_PORT->PIO_PDSR >> PIN_SWCLK_BIT) & 1); + switch(swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + return (PIN_SWCLK_PORT_ALT_1->PIO_PDSR >> PIN_SWCLK_BIT_ALT_1) & 1; + default: + return (PIN_SWCLK_PORT_DEFAULT->PIO_PDSR >> PIN_SWCLK_BIT_DEFAULT) & 1; + } } /** SWCLK/TCK I/O pin: Set Output to High. @@ -252,7 +300,14 @@ Set the SWCLK/TCK DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void) { - PIN_SWCLK_PORT->PIO_SODR = PIN_SWCLK; + switch (swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + PIN_SWCLK_PORT_ALT_1->PIO_SODR = PIN_SWCLK_ALT_1; + break; + default: + PIN_SWCLK_PORT_DEFAULT->PIO_SODR = PIN_SWCLK_DEFAULT; + break; + } } /** SWCLK/TCK I/O pin: Set Output to Low. @@ -260,7 +315,14 @@ Set the SWCLK/TCK DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void) { - PIN_SWCLK_PORT->PIO_CODR = PIN_SWCLK; + switch (swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + PIN_SWCLK_PORT_ALT_1->PIO_CODR = PIN_SWCLK_ALT_1; + break; + default: + PIN_SWCLK_PORT_DEFAULT->PIO_CODR = PIN_SWCLK_DEFAULT; + break; + } } // SWDIO/TMS Pin I/O -------------------------------------- @@ -270,7 +332,12 @@ __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void) */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void) { - return ((PIN_SWDIO_PORT->PIO_PDSR >> PIN_SWDIO_BIT) & 1); + switch(swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + return (PIN_SWDIO_PORT_ALT_1->PIO_PDSR >> PIN_SWDIO_BIT_ALT_1) & 1; + default: + return (PIN_SWDIO_PORT_DEFAULT->PIO_PDSR >> PIN_SWDIO_BIT_DEFAULT) & 1; + } } /** SWDIO/TMS I/O pin: Set Output to High. @@ -278,7 +345,14 @@ Set the SWDIO/TMS DAP hardware I/O pin to high level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void) { - PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; + switch (swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + PIN_SWDIO_PORT_ALT_1->PIO_SODR = PIN_SWDIO_ALT_1; + break; + default: + PIN_SWDIO_PORT_DEFAULT->PIO_SODR = PIN_SWDIO_DEFAULT; + break; + } } /** SWDIO/TMS I/O pin: Set Output to Low. @@ -286,7 +360,14 @@ Set the SWDIO/TMS DAP hardware I/O pin to low level. */ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void) { - PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO; + switch (swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + PIN_SWDIO_PORT_ALT_1->PIO_CODR = PIN_SWDIO_ALT_1; + break; + default: + PIN_SWDIO_PORT_DEFAULT->PIO_CODR = PIN_SWDIO_DEFAULT; + break; + } } /** SWDIO I/O pin: Get Input (used in SWD mode only). @@ -294,7 +375,12 @@ __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void) */ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void) { - return ((PIN_SWDIO_PORT->PIO_PDSR >> PIN_SWDIO_BIT) & 1); + switch(swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + return (PIN_SWDIO_PORT_ALT_1->PIO_PDSR >> PIN_SWDIO_BIT_ALT_1) & 1; + default: + return (PIN_SWDIO_PORT_DEFAULT->PIO_PDSR >> PIN_SWDIO_BIT_DEFAULT) & 1; + } } /** SWDIO I/O pin: Set Output (used in SWD mode only). @@ -302,11 +388,21 @@ __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void) */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit) { - if (bit & 1) { - PIN_SWDIO_PORT->PIO_SODR = PIN_SWDIO; - - } else { - PIN_SWDIO_PORT->PIO_CODR = PIN_SWDIO; + switch (swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + if (bit & 1) { + PIN_SWDIO_PORT_ALT_1->PIO_SODR = PIN_SWDIO_ALT_1; + } else { + PIN_SWDIO_PORT_ALT_1->PIO_CODR = PIN_SWDIO_ALT_1; + } + break; + default: + if (bit & 1) { + PIN_SWDIO_PORT_DEFAULT->PIO_SODR = PIN_SWDIO_DEFAULT; + } else { + PIN_SWDIO_PORT_DEFAULT->PIO_CODR = PIN_SWDIO_DEFAULT; + } + break; } } @@ -316,7 +412,14 @@ called prior \ref PIN_SWDIO_OUT function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void) { - PIN_SWDIO_PORT->PIO_OER = PIN_SWDIO; + switch (swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + PIN_SWDIO_PORT_ALT_1->PIO_OER = PIN_SWDIO_ALT_1; + break; + default: + PIN_SWDIO_PORT_DEFAULT->PIO_OER = PIN_SWDIO_DEFAULT; + break; + } } /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). @@ -325,7 +428,14 @@ called prior \ref PIN_SWDIO_IN function calls. */ __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void) { - PIN_SWDIO_PORT->PIO_ODR = PIN_SWDIO; + switch (swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + PIN_SWDIO_PORT_ALT_1->PIO_ODR = PIN_SWDIO_ALT_1; + break; + default: + PIN_SWDIO_PORT_DEFAULT->PIO_ODR = PIN_SWDIO_DEFAULT; + break; + } } @@ -386,7 +496,12 @@ __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit) */ __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void) { - return ((PIN_nRESET_PORT->PIO_PDSR >> PIN_nRESET_BIT) & 1); + switch(swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + return (PIN_nRESET_PORT_ALT_1->PIO_PDSR >> PIN_nRESET_BIT_ALT_1) & 1; + default: + return (PIN_nRESET_PORT_DEFAULT->PIO_PDSR >> PIN_nRESET_BIT_DEFAULT) & 1; + } } /** nRESET I/O pin: Set Output. @@ -428,15 +543,26 @@ __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) PIN_SWCLK_PORT->PIO_CODR = PIN_SWCLK; osDelay(1); } +#error "NLK: Not using nRF51822AA" } #else __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) { - if (bit & 1) { - PIN_nRESET_PORT->PIO_SODR = PIN_nRESET; - - } else { - PIN_nRESET_PORT->PIO_CODR = PIN_nRESET; + switch (swd_get_configured_pins()) { + case SWD_PIN_SET_ALT_1: + if (bit & 1) { + PIN_nRESET_PORT_ALT_1->PIO_SODR = PIN_nRESET_ALT_1; + } else { + PIN_nRESET_PORT_ALT_1->PIO_CODR = PIN_nRESET_ALT_1; + } + break; + default: + if (bit & 1) { + PIN_nRESET_PORT_DEFAULT->PIO_SODR = PIN_nRESET_DEFAULT; + } else { + PIN_nRESET_PORT_DEFAULT->PIO_CODR = PIN_nRESET_DEFAULT; + } + break; } } #endif diff --git a/source/hic_hal/atmel/sam3u2c/IO_Config.h b/source/hic_hal/atmel/sam3u2c/IO_Config.h index fdea409dcc..f4e6923b2b 100644 --- a/source/hic_hal/atmel/sam3u2c/IO_Config.h +++ b/source/hic_hal/atmel/sam3u2c/IO_Config.h @@ -58,20 +58,43 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_SAM3U2C); #define PIN_RESET_IN_FWRD_BIT 25 #define PIN_RESET_IN_FWRD (1UL << PIN_RESET_IN_FWRD_BIT) +// +// PIN CONFIGURATIONS FOR SWD +// + +// DEFAULT CONFIG +// +// nRESET OUT Pin +#define PIN_nRESET_PORT_DEFAULT PIOA +#define PIN_nRESET_BIT_DEFAULT 4 +#define PIN_nRESET_DEFAULT (1UL << PIN_nRESET_BIT_DEFAULT) + +// SWCLK/TCK Pin +#define PIN_SWCLK_PORT_DEFAULT PIOA +#define PIN_SWCLK_BIT_DEFAULT 17 +#define PIN_SWCLK_DEFAULT (1UL << PIN_SWCLK_BIT_DEFAULT) + +// SWDIO/TMS In/Out Pin +#define PIN_SWDIO_PORT_DEFAULT PIOA +#define PIN_SWDIO_BIT_DEFAULT 18 +#define PIN_SWDIO_DEFAULT (1UL << PIN_SWDIO_BIT_DEFAULT) + +// ALT_1 CONFIG +// // nRESET OUT Pin -#define PIN_nRESET_PORT PIOA -#define PIN_nRESET_BIT 4 -#define PIN_nRESET (1UL << PIN_nRESET_BIT) +#define PIN_nRESET_PORT_ALT_1 PIOA +#define PIN_nRESET_BIT_ALT_1 3 +#define PIN_nRESET_ALT_1 (1UL << PIN_nRESET_BIT_ALT_1) // SWCLK/TCK Pin -#define PIN_SWCLK_PORT PIOA -#define PIN_SWCLK_BIT 17 -#define PIN_SWCLK (1UL << PIN_SWCLK_BIT) +#define PIN_SWCLK_PORT_ALT_1 PIOA +#define PIN_SWCLK_BIT_ALT_1 22 +#define PIN_SWCLK_ALT_1 (1UL << PIN_SWCLK_BIT_ALT_1) // SWDIO/TMS In/Out Pin -#define PIN_SWDIO_PORT PIOA -#define PIN_SWDIO_BIT 18 -#define PIN_SWDIO (1UL << PIN_SWDIO_BIT) +#define PIN_SWDIO_PORT_ALT_1 PIOA +#define PIN_SWDIO_BIT_ALT_1 15 +#define PIN_SWDIO_ALT_1 (1UL << PIN_SWDIO_BIT_ALT_1) // TDI Pin - Not used