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| 1 | +/* |
| 2 | + * Copyright (c) 2019, ARM Limited, All Rights Reserved |
| 3 | + * SPDX-License-Identifier: Apache-2.0 |
| 4 | + * |
| 5 | + * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| 6 | + * not use this file except in compliance with the License. |
| 7 | + * You may obtain a copy of the License at |
| 8 | + * |
| 9 | + * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | + * |
| 11 | + * Unless required by applicable law or agreed to in writing, software |
| 12 | + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
| 13 | + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | + * See the License for the specific language governing permissions and |
| 15 | + * limitations under the License. |
| 16 | + */ |
| 17 | + |
| 18 | +#include "platform/mbed_assert.h" |
| 19 | +#include "platform/mbed_atomic.h" |
| 20 | + |
| 21 | +/* Inline bool implementations in the header use uint8_t versions to manipulate the bool */ |
| 22 | +MBED_STATIC_ASSERT(sizeof(bool) == sizeof(uint8_t), "Surely bool is a byte"); |
| 23 | + |
| 24 | +/* Inline implementations in the header use uint32_t versions to manipulate pointers */ |
| 25 | +MBED_STATIC_ASSERT(sizeof(void *) == sizeof(uint32_t), "Alas, pointers must be 32-bit"); |
| 26 | + |
| 27 | + |
| 28 | +#define DO_MBED_LOCKED_OP(name, OP, retValue, T, fn_suffix) \ |
| 29 | +T core_util_atomic_##name##_##fn_suffix(volatile T *valuePtr, T arg) \ |
| 30 | +{ \ |
| 31 | + T oldValue, newValue; \ |
| 32 | + core_util_critical_section_enter(); \ |
| 33 | + oldValue = *valuePtr; \ |
| 34 | + newValue = OP; \ |
| 35 | + *valuePtr = newValue; \ |
| 36 | + core_util_critical_section_exit(); \ |
| 37 | + return retValue; \ |
| 38 | +} |
| 39 | + |
| 40 | +#define DO_MBED_LOCKED_CAS_OP(T, fn_suffix) \ |
| 41 | +bool core_util_atomic_cas_##fn_suffix(volatile T *ptr, T *expectedCurrentValue, T desiredValue) \ |
| 42 | +{ \ |
| 43 | + bool success; \ |
| 44 | + T currentValue; \ |
| 45 | + core_util_critical_section_enter(); \ |
| 46 | + currentValue = *ptr; \ |
| 47 | + if (currentValue == *expectedCurrentValue) { \ |
| 48 | + *ptr = desiredValue; \ |
| 49 | + success = true; \ |
| 50 | + } else { \ |
| 51 | + *expectedCurrentValue = currentValue; \ |
| 52 | + success = false; \ |
| 53 | + } \ |
| 54 | + core_util_critical_section_exit(); \ |
| 55 | + return success; \ |
| 56 | +} \ |
| 57 | + \ |
| 58 | +bool core_util_atomic_compare_exchange_weak_##fn_suffix(volatile T *ptr, \ |
| 59 | + T *expectedCurrentValue, T desiredValue) \ |
| 60 | +{ \ |
| 61 | + return core_util_atomic_cas_##fn_suffix(ptr, expectedCurrentValue, desiredValue); \ |
| 62 | +} |
| 63 | + |
| 64 | +#if MBED_EXCLUSIVE_ACCESS |
| 65 | +/* These are the C99 external definitions for the inline functions */ |
| 66 | +/* We maintain external definitions rather than using "static inline" for backwards binary compatibility |
| 67 | + * and to give the compiler plenty of leeway to choose to not inline in both C and C++ modes |
| 68 | + */ |
| 69 | + |
| 70 | +extern inline bool core_util_atomic_flag_test_and_set(volatile core_util_atomic_flag *flagPtr); |
| 71 | + |
| 72 | +extern inline uint8_t core_util_atomic_exchange_u8(volatile uint8_t *valuePtr, uint8_t newValue); |
| 73 | +extern inline uint16_t core_util_atomic_exchange_u16(volatile uint16_t *valuePtr, uint16_t newValue); |
| 74 | +extern inline uint32_t core_util_atomic_exchange_u32(volatile uint32_t *valuePtr, uint32_t newValue); |
| 75 | +extern inline uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 76 | +extern inline uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 77 | +extern inline uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 78 | +extern inline uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 79 | +extern inline uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 80 | +extern inline uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 81 | +extern inline uint8_t core_util_atomic_fetch_add_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 82 | +extern inline uint16_t core_util_atomic_fetch_add_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 83 | +extern inline uint32_t core_util_atomic_fetch_add_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 84 | +extern inline uint8_t core_util_atomic_fetch_sub_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 85 | +extern inline uint16_t core_util_atomic_fetch_sub_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 86 | +extern inline uint32_t core_util_atomic_fetch_sub_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 87 | +extern inline uint8_t core_util_atomic_fetch_and_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 88 | +extern inline uint16_t core_util_atomic_fetch_and_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 89 | +extern inline uint32_t core_util_atomic_fetch_and_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 90 | +extern inline uint8_t core_util_atomic_fetch_or_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 91 | +extern inline uint16_t core_util_atomic_fetch_or_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 92 | +extern inline uint32_t core_util_atomic_fetch_or_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 93 | +extern inline uint8_t core_util_atomic_fetch_xor_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 94 | +extern inline uint16_t core_util_atomic_fetch_xor_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 95 | +extern inline uint32_t core_util_atomic_fetch_xor_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 96 | +extern inline bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue); |
| 97 | +extern inline bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue); |
| 98 | +extern inline bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue); |
| 99 | +extern inline bool core_util_atomic_compare_exchange_weak_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue); |
| 100 | +extern inline bool core_util_atomic_compare_exchange_weak_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue); |
| 101 | +extern inline bool core_util_atomic_compare_exchange_weak_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue); |
| 102 | + |
| 103 | +extern inline bool core_util_atomic_flag_test_and_set_relaxed(volatile core_util_atomic_flag *flagPtr); |
| 104 | + |
| 105 | +extern inline uint8_t core_util_atomic_exchange_relaxed_u8(volatile uint8_t *valuePtr, uint8_t newValue); |
| 106 | +extern inline uint16_t core_util_atomic_exchange_relaxed_u16(volatile uint16_t *valuePtr, uint16_t newValue); |
| 107 | +extern inline uint32_t core_util_atomic_exchange_relaxed_u32(volatile uint32_t *valuePtr, uint32_t newValue); |
| 108 | +extern inline uint8_t core_util_atomic_incr_relaxed_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 109 | +extern inline uint16_t core_util_atomic_incr_relaxed_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 110 | +extern inline uint32_t core_util_atomic_incr_relaxed_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 111 | +extern inline uint8_t core_util_atomic_decr_relaxed_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 112 | +extern inline uint16_t core_util_atomic_decr_relaxed_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 113 | +extern inline uint32_t core_util_atomic_decr_relaxed_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 114 | +extern inline uint8_t core_util_atomic_fetch_add_relaxed_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 115 | +extern inline uint16_t core_util_atomic_fetch_add_relaxed_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 116 | +extern inline uint32_t core_util_atomic_fetch_add_relaxed_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 117 | +extern inline uint8_t core_util_atomic_fetch_sub_relaxed_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 118 | +extern inline uint16_t core_util_atomic_fetch_sub_relaxed_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 119 | +extern inline uint32_t core_util_atomic_fetch_sub_relaxed_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 120 | +extern inline uint8_t core_util_atomic_fetch_and_relaxed_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 121 | +extern inline uint16_t core_util_atomic_fetch_and_relaxed_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 122 | +extern inline uint32_t core_util_atomic_fetch_and_relaxed_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 123 | +extern inline uint8_t core_util_atomic_fetch_or_relaxed_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 124 | +extern inline uint16_t core_util_atomic_fetch_or_relaxed_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 125 | +extern inline uint32_t core_util_atomic_fetch_or_relaxed_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 126 | +extern inline uint8_t core_util_atomic_fetch_xor_relaxed_u8(volatile uint8_t *valuePtr, uint8_t arg); |
| 127 | +extern inline uint16_t core_util_atomic_fetch_xor_relaxed_u16(volatile uint16_t *valuePtr, uint16_t arg); |
| 128 | +extern inline uint32_t core_util_atomic_fetch_xor_relaxed_u32(volatile uint32_t *valuePtr, uint32_t arg); |
| 129 | +extern inline bool core_util_atomic_cas_relaxed_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue); |
| 130 | +extern inline bool core_util_atomic_cas_relaxed_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue); |
| 131 | +extern inline bool core_util_atomic_cas_relaxed_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue); |
| 132 | +extern inline bool core_util_atomic_compare_exchange_weak_relaxed_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue); |
| 133 | +extern inline bool core_util_atomic_compare_exchange_weak_relaxed_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue); |
| 134 | +extern inline bool core_util_atomic_compare_exchange_weak_relaxed_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue); |
| 135 | + |
| 136 | +#else |
| 137 | + |
| 138 | +bool core_util_atomic_flag_test_and_set(volatile core_util_atomic_flag *flagPtr) |
| 139 | +{ |
| 140 | + core_util_critical_section_enter(); |
| 141 | + uint8_t currentValue = flagPtr->_flag; |
| 142 | + flagPtr->_flag = true; |
| 143 | + core_util_critical_section_exit(); |
| 144 | + return currentValue; |
| 145 | +} |
| 146 | +#endif |
| 147 | + |
| 148 | +/* No architecture we support has LDREXD/STREXD, so must always disable IRQs for 64-bit operations */ |
| 149 | +uint64_t core_util_atomic_load_u64(const volatile uint64_t *valuePtr) |
| 150 | +{ |
| 151 | + core_util_critical_section_enter(); |
| 152 | + uint64_t currentValue = *valuePtr; |
| 153 | + core_util_critical_section_exit(); |
| 154 | + return currentValue; |
| 155 | +} |
| 156 | + |
| 157 | +void core_util_atomic_store_u64(volatile uint64_t *valuePtr, uint64_t desiredValue) |
| 158 | +{ |
| 159 | + core_util_critical_section_enter(); |
| 160 | + *valuePtr = desiredValue; |
| 161 | + core_util_critical_section_exit(); |
| 162 | +} |
| 163 | + |
| 164 | +/* Now locked operations for whichever we don't have lock-free ones for */ |
| 165 | +#if MBED_EXCLUSIVE_ACCESS |
| 166 | +/* Just need 64-bit locked operations */ |
| 167 | +#define DO_MBED_LOCKED_OPS(name, OP, retValue) \ |
| 168 | + DO_MBED_LOCKED_OP(name, OP, retValue, uint64_t, u64) |
| 169 | +#define DO_MBED_LOCKED_CAS_OPS() \ |
| 170 | + DO_MBED_LOCKED_CAS_OP(uint64_t, u64) |
| 171 | +#else |
| 172 | +/* All the operations are locked */ |
| 173 | +#define DO_MBED_LOCKED_OPS(name, OP, retValue) \ |
| 174 | + DO_MBED_LOCKED_OP(name, OP, retValue, uint8_t, u8) \ |
| 175 | + DO_MBED_LOCKED_OP(name, OP, retValue, uint16_t, u16) \ |
| 176 | + DO_MBED_LOCKED_OP(name, OP, retValue, uint32_t, u32) \ |
| 177 | + DO_MBED_LOCKED_OP(name, OP, retValue, uint64_t, u64) |
| 178 | +#define DO_MBED_LOCKED_CAS_OPS() \ |
| 179 | + DO_MBED_LOCKED_CAS_OP(uint8_t, u8) \ |
| 180 | + DO_MBED_LOCKED_CAS_OP(uint16_t, u16) \ |
| 181 | + DO_MBED_LOCKED_CAS_OP(uint32_t, u32) \ |
| 182 | + DO_MBED_LOCKED_CAS_OP(uint64_t, u64) |
| 183 | +#endif |
| 184 | + |
| 185 | +DO_MBED_LOCKED_OPS(exchange, arg, oldValue) |
| 186 | +DO_MBED_LOCKED_OPS(incr, oldValue + arg, newValue) |
| 187 | +DO_MBED_LOCKED_OPS(decr, oldValue - arg, newValue) |
| 188 | +DO_MBED_LOCKED_OPS(fetch_add, oldValue + arg, oldValue) |
| 189 | +DO_MBED_LOCKED_OPS(fetch_sub, oldValue - arg, oldValue) |
| 190 | +DO_MBED_LOCKED_OPS(fetch_and, oldValue & arg, oldValue) |
| 191 | +DO_MBED_LOCKED_OPS(fetch_or, oldValue | arg, oldValue) |
| 192 | +DO_MBED_LOCKED_OPS(fetch_xor, oldValue ^ arg, oldValue) |
| 193 | +DO_MBED_LOCKED_CAS_OPS() |
| 194 | + |
| 195 | +/* Similar functions for s32 etc are static inline, but these are extern inline for legacy binary compatibility */ |
| 196 | +extern inline void *core_util_atomic_exchange_ptr(void *volatile *valuePtr, void *desiredValue); |
| 197 | +extern inline void *core_util_atomic_incr_ptr(void *volatile *valuePtr, ptrdiff_t delta); |
| 198 | +extern inline void *core_util_atomic_decr_ptr(void *volatile *valuePtr, ptrdiff_t delta); |
| 199 | +extern inline bool core_util_atomic_cas_ptr(void *volatile *ptr, void **expectedCurrentValue, void *desiredValue); |
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