From a03f5ff4e6f6f54904b18ebaa0119c714b041d89 Mon Sep 17 00:00:00 2001 From: Andrea Gilardoni Date: Fri, 28 Aug 2020 19:10:41 +0200 Subject: [PATCH 1/6] Adding a new target Adding STM32L071CXCTX as a generic target to be extended. This addition required to fix some issues on stml0 library --- .../TOOLCHAIN_ARM/startup_stm32l073xx.S | 218 + .../device/TOOLCHAIN_ARM/stm32l073xz.sct | 53 + .../TOOLCHAIN_GCC_ARM/STM32L071CXCTX.ld | 203 + .../TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S | 296 + .../TOOLCHAIN_IAR/startup_stm32l073xx.S | 348 + .../device/TOOLCHAIN_IAR/stm32l073xx.icf | 59 + .../TARGET_STM32L071CXCTX/device/cmsis_nvic.h | 39 + .../device/stm32l071xx.h | 6533 +++++++++++++++++ .../TARGET_STM32L071CXCTX/device/stm32l0xx.h | 236 + .../device/system_stm32l0xx.h | 126 + .../device/us_ticker_data.h | 45 + .../TARGET_STM32L071CXCTX/objects.h | 63 + .../device/stm32l0xx_hal_conf.h | 57 +- .../TARGET_STM32L0/device/stm32l0xx_hal_tsc.h | 5 +- targets/targets.json | 19 + 15 files changed, 8275 insertions(+), 25 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l073xx.S create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l073xz.sct create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/STM32L071CXCTX.ld create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l073xx.S create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l073xx.icf create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/cmsis_nvic.h create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/stm32l071xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/stm32l0xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/system_stm32l0xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/us_ticker_data.h create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/objects.h diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l073xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l073xx.S new file mode 100644 index 00000000000..821883957f6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l073xx.S @@ -0,0 +1,218 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l073xx.s +;* Author : MCD Application Team +;* Version : V1.7.1 +;* Date : 25-November-2016 +;* Description : STM32l073xx Devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD USART4_5_IRQHandler ; USART4 and USART5 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM21_IRQHandler ; TIM21 + DCD I2C3_IRQHandler ; I2C3 + DCD TIM22_IRQHandler ; TIM22 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD RNG_LPUART1_IRQHandler ; RNG and LPUART1 + DCD LCD_IRQHandler ; LCD + DCD USB_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT USART4_5_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM21_IRQHandler [WEAK] + EXPORT TIM22_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT I2C3_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT RNG_LPUART1_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_6_7_IRQHandler +ADC1_COMP_IRQHandler +LPTIM1_IRQHandler +USART4_5_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +TIM21_IRQHandler +TIM22_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +I2C3_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +RNG_LPUART1_IRQHandler +LCD_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l073xz.sct b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l073xz.sct new file mode 100644 index 00000000000..50f930c713d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l073xz.sct @@ -0,0 +1,53 @@ +#! armcc -E +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/STM32L071CXCTX.ld b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/STM32L071CXCTX.ld new file mode 100644 index 00000000000..214dccf361d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/STM32L071CXCTX.ld @@ -0,0 +1,203 @@ +/* Linker script to configure memory regions. */ +/* + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#include "../cmsis_nvic.h" + + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S new file mode 100644 index 00000000000..4713c5a1e39 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S @@ -0,0 +1,296 @@ +/** + ****************************************************************************** + * @file startup_stm32l071xx.s + * @author MCD Application Team + * @brief STM32L071xx Devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* Reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/ + .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word USART4_5_IRQHandler /* USART4 and USART 5 */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_IRQHandler /* TIM6 and DAC */ + .word TIM7_IRQHandler /* TIM7 */ + .word 0 /* Reserved */ + .word TIM21_IRQHandler /* TIM21 */ + .word I2C3_IRQHandler /* I2C3 */ + .word TIM22_IRQHandler /* TIM22 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word LPUART1_IRQHandler /* LPUART1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_6_7_IRQHandler + .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak USART4_5_IRQHandler + .thumb_set USART4_5_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM21_IRQHandler + .thumb_set TIM21_IRQHandler,Default_Handler + + .weak I2C3_IRQHandler + .thumb_set I2C3_IRQHandler,Default_Handler + + .weak TIM22_IRQHandler + .thumb_set TIM22_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l073xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l073xx.S new file mode 100644 index 00000000000..712035a55c9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l073xx.S @@ -0,0 +1,348 @@ +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l073xx.s +;* Author : MCD Application Team +;* Version : V1.7.1 +;* Date : 25-November-2016 +;* Description : STM32L073xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC_CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD USART4_5_IRQHandler ; USART4 and USART5 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM21_IRQHandler ; TIM21 + DCD I2C3_IRQHandler ; I2C3 + DCD TIM22_IRQHandler ; TIM22 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD RNG_LPUART1_IRQHandler ; RNG and LPUART1 + DCD LCD_IRQHandler ; LCD + DCD USB_IRQHandler ; USB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_CRS_IRQHandler + B RCC_CRS_IRQHandler + + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + + PUBWEAK DMA1_Channel4_5_6_7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_6_7_IRQHandler + B DMA1_Channel4_5_6_7_IRQHandler + + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + + PUBWEAK USART4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART4_5_IRQHandler + B USART4_5_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM21_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM21_IRQHandler + B TIM21_IRQHandler + + PUBWEAK I2C3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_IRQHandler + B I2C3_IRQHandler + + PUBWEAK TIM22_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM22_IRQHandler + B TIM22_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK RNG_LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_LPUART1_IRQHandler + B RNG_LPUART1_IRQHandler + + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l073xx.icf b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l073xx.icf new file mode 100644 index 00000000000..9d54f3418f7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l073xx.icf @@ -0,0 +1,59 @@ +/* Linker script to configure memory regions. + * + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ +define symbol HEAP_SIZE = 0x1000; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = MBED_ROM_START; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = MBED_ROM_SIZE; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + /* This value is normally defined by the tools + to 0x1000 for bare metal and 0x400 for RTOS */ + define symbol MBED_BOOT_STACK_SIZE = 0x400; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; + +define block CSTACK with alignment = 8, size = MBED_BOOT_STACK_SIZE { }; +define block HEAP with alignment = 8, size = HEAP_SIZE { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: MBED_APP_START { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/cmsis_nvic.h new file mode 100644 index 00000000000..4b4b07c8563 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/cmsis_nvic.h @@ -0,0 +1,39 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#if !defined(MBED_ROM_START) +#define MBED_ROM_START 0x8000000 +#endif + +#if !defined(MBED_ROM_SIZE) +#define MBED_ROM_SIZE 0x30000 // 192 KB +#endif + +#if !defined(MBED_RAM_START) +#define MBED_RAM_START 0x20000000 +#endif + +#if !defined(MBED_RAM_SIZE) +#define MBED_RAM_SIZE 0x5000 // 20 KB +#endif + +#define NVIC_NUM_VECTORS 32 +#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/stm32l071xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/stm32l071xx.h new file mode 100644 index 00000000000..387bc288c49 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/stm32l071xx.h @@ -0,0 +1,6533 @@ +#ifndef __STM32L071xx_H +#define __STM32L071xx_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1U /*!< STM32L0xx provides an MPU */ +#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32l071xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ + +/****** STM32L-0 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_IRQn = 4, /*!< RCC Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ + LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ + USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM6_IRQn = 17, /*!< TIM6 Interrupt */ + TIM7_IRQn = 18, /*!< TIM7 Interrupt */ + TIM21_IRQn = 20, /*!< TIM21 Interrupt */ + I2C3_IRQn = 21, /*!< I2C3 Interrupt */ + TIM22_IRQn = 22, /*!< TIM22 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" +#include "system_stm32l0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ + __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ + __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ + uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; +} ADC_Common_TypeDef; + + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + + +/** +* @brief CRC calculation unit +*/ + +typedef struct +{ +__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ +__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ +uint8_t RESERVED0; /*!< Reserved, 0x05 */ +uint16_t RESERVED1; /*!< Reserved, 0x06 */ +__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +uint32_t RESERVED2; /*!< Reserved, 0x0C */ +__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ +__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ +} DMA_Request_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l0xx + * @{ + */ + +#ifndef __STM32L0xx_H +#define __STM32L0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32L0) +#define STM32L0 +#endif /* STM32L0 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32L011xx) && !defined (STM32L021xx) && \ + !defined (STM32L031xx) && !defined (STM32L041xx) && \ + !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \ + !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \ + !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \ + !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \ + /* #define STM32L011xx */ + /* #define STM32L021xx */ + /* #define STM32L031xx */ /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */ + /* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */ + /* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */ + /* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */ + /* #define STM32L053xx */ /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */ + /* #define STM32L061xx */ /*!< */ + /* #define STM32L062xx */ /*!< STM32L062K8 */ + /* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */ + #define STM32L071xx /*!< */ + /* #define STM32L072xx */ /*!< */ + //#define STM32L073xx /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */ + /* #define STM32L081xx */ /*!< */ + /* #define STM32L082xx */ /*!< */ + /* #define STM32L083xx */ /*!< */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V1.7.1 + */ +#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ +#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\ + |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32L0xx_CMSIS_VERSION_RC)) + +/** @addtogroup Device_Included + * @{ + */ +#if defined(STM32L011xx) + #include "stm32l011xx.h" +#elif defined(STM32L021xx) + #include "stm32l021xx.h" +#elif defined(STM32L031xx) + #include "stm32l031xx.h" +#elif defined(STM32L041xx) + #include "stm32l041xx.h" +#elif defined(STM32L051xx) + #include "stm32l051xx.h" +#elif defined(STM32L052xx) + #include "stm32l052xx.h" +#elif defined(STM32L053xx) + #include "stm32l053xx.h" +#elif defined(STM32L062xx) + #include "stm32l062xx.h" +#elif defined(STM32L063xx) + #include "stm32l063xx.h" +#elif defined(STM32L061xx) + #include "stm32l061xx.h" +#elif defined(STM32L071xx) + //#include "stm32l073xx.h" + #include "stm32l071xx.h" +#elif defined(STM32L072xx) + #include "stm32l072xx.h" +#elif defined(STM32L073xx) + #include "stm32l071xx.h" + //#include "stm32l073xx.h" +#elif defined(STM32L082xx) + #include "stm32l082xx.h" +#elif defined(STM32L083xx) + #include "stm32l083xx.h" +#elif defined(STM32L081xx) + #include "stm32l081xx.h" +#else + #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) +#include "stm32l0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + + +#endif /* __STM32L0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/system_stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/system_stm32l0xx.h new file mode 100644 index 00000000000..df958f5bebc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/system_stm32l0xx.h @@ -0,0 +1,126 @@ +/** + ****************************************************************************** + * @file system_stm32l0xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32L0XX_H +#define __SYSTEM_STM32L0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32L0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32L0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/* +*/ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32L0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/us_ticker_data.h new file mode 100644 index 00000000000..1ae9b883759 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/us_ticker_data.h @@ -0,0 +1,45 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef __US_TICKER_DATA_H +#define __US_TICKER_DATA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32l0xx.h" +#include "stm32l0xx_ll_tim.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM21 +#define TIM_MST_IRQ TIM21_IRQn +#define TIM_MST_RCC __TIM21_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM21() + +#define TIM_MST_RESET_ON __TIM21_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM21_RELEASE_RESET() + +#define TIM_MST_BIT_WIDTH 16 // 16 or 32 + +#define TIM_MST_PCLK 2 // Select the peripheral clock number (1 or 2) + + +#ifdef __cplusplus +} +#endif + +#endif // __US_TICKER_DATA_H + diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/objects.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/objects.h new file mode 100644 index 00000000000..d0f3565f66d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/objects.h @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +#include "common_objects.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h index 364c00cbe74..a6cec8d7765 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h @@ -53,31 +53,43 @@ #define HAL_COMP_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED #define HAL_CRYP_MODULE_ENABLED -#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) + +#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071CxCTx) #define HAL_DAC_MODULE_ENABLED -#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 */ +#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ + #define HAL_DMA_MODULE_ENABLED + #if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) #define HAL_FIREWALL_MODULE_ENABLED -#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 */ +#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ + #define HAL_FLASH_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED -#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) + +#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071CxCTx) #define HAL_I2S_MODULE_ENABLED -#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 */ +#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ + #define HAL_IWDG_MODULE_ENABLED #define HAL_LCD_MODULE_ENABLED #define HAL_LPTIM_MODULE_ENABLED #define HAL_PWR_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED + +#if !defined (TARGET_STML071CxCTx) #define HAL_RNG_MODULE_ENABLED +#endif /* !TARGET_STML0CXCTX */ + #define HAL_RTC_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED -#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) + +#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071CxCTx) #define HAL_TSC_MODULE_ENABLED -#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 */ +#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ + #define HAL_UART_MODULE_ENABLED #define HAL_USART_MODULE_ENABLED #define HAL_IRDA_MODULE_ENABLED @@ -85,9 +97,10 @@ #define HAL_SMBUS_MODULE_ENABLED #define HAL_WWDG_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED -#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) + +#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071CxCTx) #define HAL_PCD_MODULE_ENABLED -#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 */ +#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ /* ########################## Oscillator Values adaptation ####################*/ /** @@ -223,55 +236,55 @@ #endif /* HAL_FLASH_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l0xx_hal_i2c.h" + #include "stm32l0xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ #ifdef HAL_I2S_MODULE_ENABLED - #include "stm32l0xx_hal_i2s.h" + #include "stm32l0xx_hal_i2s.h" #endif /* HAL_I2S_MODULE_ENABLED */ #ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l0xx_hal_iwdg.h" + #include "stm32l0xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l0xx_hal_lcd.h" + #include "stm32l0xx_hal_lcd.h" #endif /* HAL_LCD_MODULE_ENABLED */ #ifdef HAL_LPTIM_MODULE_ENABLED -#include "stm32l0xx_hal_lptim.h" + #include "stm32l0xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ #ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l0xx_hal_pwr.h" + #include "stm32l0xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ #ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l0xx_hal_rng.h" + #include "stm32l0xx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ #ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l0xx_hal_rtc.h" + #include "stm32l0xx_hal_rtc.h" #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l0xx_hal_spi.h" + #include "stm32l0xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ #ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l0xx_hal_tim.h" + #include "stm32l0xx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ #ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l0xx_hal_tsc.h" + #include "stm32l0xx_hal_tsc.h" #endif /* HAL_TSC_MODULE_ENABLED */ #ifdef HAL_UART_MODULE_ENABLED - #include "stm32l0xx_hal_uart.h" + #include "stm32l0xx_hal_uart.h" #endif /* HAL_UART_MODULE_ENABLED */ #ifdef HAL_USART_MODULE_ENABLED - #include "stm32l0xx_hal_usart.h" + #include "stm32l0xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ #ifdef HAL_IRDA_MODULE_ENABLED diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.h index cacef337c7f..c27cd2ebab3 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.h @@ -38,12 +38,11 @@ #ifndef __STM32L0xx_TSC_H #define __STM32L0xx_TSC_H +#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) + #ifdef __cplusplus extern "C" { #endif - -#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_def.h" diff --git a/targets/targets.json b/targets/targets.json index 03d72ce89cb..97f8e848ee8 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2786,6 +2786,25 @@ ], "device_name": "STM32L072CZ" }, + "STM32L071CXCTX": { + "inherits": [ + "MCU_STM32L0" + ], + "public": false, + "extra_labels_add": [ + "STM32L0", + "STML071CxCTx", + "STML071xx" + ], + "overrides": { + "lpticker_delay_ticks": 0 + }, + "device_has_remove": [ + "ANALOGOUT", + "TRNG" + ], + "device_name": "STM32L071CXCTX" + }, "NUCLEO_L073RZ": { "inherits": [ "MCU_STM32L0" From 0c0692a3d171350bbbd4c9f4f2b388a64de68e60 Mon Sep 17 00:00:00 2001 From: Andrea Gilardoni Date: Fri, 28 Aug 2020 19:12:37 +0200 Subject: [PATCH 2/6] fixing the issues --- .../TOOLCHAIN_ARM/startup_stm32l071xx.s | 259 ++++++++++++++ .../device/TOOLCHAIN_ARM/stm32l071xx.sct | 53 +++ .../TOOLCHAIN_IAR/startup_stm32l071xx.s | 329 ++++++++++++++++++ .../TOOLCHAIN_IAR/stm32l071xx_flash.icf | 33 ++ .../device/TOOLCHAIN_IAR/stm32l071xx_sram.icf | 33 ++ targets/targets.json | 8 + 6 files changed, 715 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l071xx.s create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l071xx.sct create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l071xx.s create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf create mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l071xx.s b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l071xx.s new file mode 100644 index 00000000000..93be51cf811 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l071xx.s @@ -0,0 +1,259 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l071xx.s +;* Author : MCD Application Team +;* Description : STM32l071xx Devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD USART4_5_IRQHandler ; USART4 and USART5 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM21_IRQHandler ; TIM21 + DCD I2C3_IRQHandler ; I2C3 + DCD TIM22_IRQHandler ; TIM22 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD LPUART1_IRQHandler ; LPUART1 + DCD 0 ; Reserved + DCD 0 ; Reserved + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT USART4_5_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM21_IRQHandler [WEAK] + EXPORT TIM22_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT I2C3_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_6_7_IRQHandler +ADC1_COMP_IRQHandler +LPTIM1_IRQHandler +USART4_5_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +TIM21_IRQHandler +TIM22_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +I2C3_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +LPUART1_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l071xx.sct b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l071xx.sct new file mode 100644 index 00000000000..50f930c713d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l071xx.sct @@ -0,0 +1,53 @@ +#! armcc -E +; Scatter-Loading Description File +; +; SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2016-2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +#include "../cmsis_nvic.h" + +#if !defined(MBED_APP_START) + #define MBED_APP_START MBED_ROM_START +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; Stack region growing down + } +} diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l071xx.s b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l071xx.s new file mode 100644 index 00000000000..efaba465bde --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l071xx.s @@ -0,0 +1,329 @@ +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l071xx.s +;* Author : MCD Application Team +;* Description : STM32L071xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD USART4_5_IRQHandler ; USART4 and USART5 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM21_IRQHandler ; TIM21 + DCD I2C3_IRQHandler ; I2C3 + DCD TIM22_IRQHandler ; TIM22 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD LPUART1_IRQHandler ; LPUART1 + DCD 0 ; Reserved + DCD 0 ; Reserved + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + + PUBWEAK DMA1_Channel4_5_6_7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_6_7_IRQHandler + B DMA1_Channel4_5_6_7_IRQHandler + + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + + PUBWEAK USART4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART4_5_IRQHandler + B USART4_5_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM21_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM21_IRQHandler + B TIM21_IRQHandler + + PUBWEAK I2C3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_IRQHandler + B I2C3_IRQHandler + + PUBWEAK TIM22_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM22_IRQHandler + B TIM22_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf new file mode 100644 index 00000000000..4b13211b588 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000 ; +define symbol __ICFEDIT_region_ROM_end__ = 0x0802FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf new file mode 100644 index 00000000000..be865fc2b47 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x20000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x20002FFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20003000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/targets/targets.json b/targets/targets.json index 97f8e848ee8..a55c6ab8b4d 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2411,7 +2411,15 @@ "inherits": [ "MCU_STM32G0" ], +<<<<<<< HEAD "public": false, +======= + "core": "Cortex-M7FD", + "mbed_rom_start": "0x08000000", + "mbed_rom_size": "0x200000", + "mbed_ram_start": "0x24000000", + "mbed_ram_size": "0x80000", +>>>>>>> 017a98b738... fixing the issues "extra_labels_add": [ "STM32G071xx" ], From c62fc559c9dae68b9fc1e77d310514f252ee7322 Mon Sep 17 00:00:00 2001 From: Andrea Gilardoni Date: Fri, 28 Aug 2020 19:24:43 +0200 Subject: [PATCH 3/6] renaming the mcu to stm32l071xx --- .../TOOLCHAIN_ARM/startup_stm32l073xx.S | 218 ----------- .../device/TOOLCHAIN_ARM/stm32l073xz.sct | 53 --- .../TOOLCHAIN_IAR/startup_stm32l073xx.S | 348 ------------------ .../device/TOOLCHAIN_IAR/stm32l073xx.icf | 59 --- .../TOOLCHAIN_ARM/startup_stm32l071xx.S} | 0 .../device/TOOLCHAIN_ARM/stm32l071xx.sct | 0 .../device/TOOLCHAIN_GCC_ARM/STM32L071xx.ld} | 0 .../TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S | 0 .../TOOLCHAIN_IAR/startup_stm32l071xx.S} | 0 .../TOOLCHAIN_IAR/stm32l071xx_flash.icf | 0 .../device/TOOLCHAIN_IAR/stm32l071xx_sram.icf | 0 .../device/cmsis_nvic.h | 0 .../device/stm32l071xx.h | 0 .../device/stm32l0xx.h | 0 .../device/system_stm32l0xx.h | 0 .../device/us_ticker_data.h | 0 .../objects.h | 0 targets/targets.json | 5 +- 18 files changed, 2 insertions(+), 681 deletions(-) delete mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l073xx.S delete mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l073xz.sct delete mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l073xx.S delete mode 100644 targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l073xx.icf rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l071xx.s => TARGET_STM32L071xx/device/TOOLCHAIN_ARM/startup_stm32l071xx.S} (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX => TARGET_STM32L071xx}/device/TOOLCHAIN_ARM/stm32l071xx.sct (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/STM32L071CXCTX.ld => TARGET_STM32L071xx/device/TOOLCHAIN_GCC_ARM/STM32L071xx.ld} (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX => TARGET_STM32L071xx}/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l071xx.s => TARGET_STM32L071xx/device/TOOLCHAIN_IAR/startup_stm32l071xx.S} (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX => TARGET_STM32L071xx}/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX => TARGET_STM32L071xx}/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX => TARGET_STM32L071xx}/device/cmsis_nvic.h (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX => TARGET_STM32L071xx}/device/stm32l071xx.h (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX => TARGET_STM32L071xx}/device/stm32l0xx.h (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX => TARGET_STM32L071xx}/device/system_stm32l0xx.h (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX => TARGET_STM32L071xx}/device/us_ticker_data.h (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071CXCTX => TARGET_STM32L071xx}/objects.h (100%) diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l073xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l073xx.S deleted file mode 100644 index 821883957f6..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l073xx.S +++ /dev/null @@ -1,218 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32l073xx.s -;* Author : MCD Application Team -;* Version : V1.7.1 -;* Date : 25-November-2016 -;* Description : STM32l073xx Devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M0+ processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_CRS_IRQHandler ; RCC and CRS - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TSC - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 - DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 - DCD LPTIM1_IRQHandler ; LPTIM1 - DCD USART4_5_IRQHandler ; USART4 and USART5 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC - DCD TIM7_IRQHandler ; TIM7 - DCD 0 ; Reserved - DCD TIM21_IRQHandler ; TIM21 - DCD I2C3_IRQHandler ; I2C3 - DCD TIM22_IRQHandler ; TIM22 - DCD I2C1_IRQHandler ; I2C1 - DCD I2C2_IRQHandler ; I2C2 - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD RNG_LPUART1_IRQHandler ; RNG and LPUART1 - DCD LCD_IRQHandler ; LCD - DCD USB_IRQHandler ; USB - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_CRS_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] - EXPORT ADC1_COMP_IRQHandler [WEAK] - EXPORT LPTIM1_IRQHandler [WEAK] - EXPORT USART4_5_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT TIM21_IRQHandler [WEAK] - EXPORT TIM22_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT I2C3_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT RNG_LPUART1_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_CRS_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -TSC_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_6_7_IRQHandler -ADC1_COMP_IRQHandler -LPTIM1_IRQHandler -USART4_5_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -TIM21_IRQHandler -TIM22_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -I2C3_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -RNG_LPUART1_IRQHandler -LCD_IRQHandler -USB_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l073xz.sct b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l073xz.sct deleted file mode 100644 index 50f930c713d..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l073xz.sct +++ /dev/null @@ -1,53 +0,0 @@ -#! armcc -E -; Scatter-Loading Description File -; -; SPDX-License-Identifier: BSD-3-Clause -;****************************************************************************** -;* @attention -;* -;* Copyright (c) 2016-2020 STMicroelectronics. -;* All rights reserved. -;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause -;* -;****************************************************************************** - -#include "../cmsis_nvic.h" - -#if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START -#endif - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE -#endif - -#if !defined(MBED_BOOT_STACK_SIZE) -/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -/* Round up VECTORS_SIZE to 8 bytes */ -#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up - } - - ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; Stack region growing down - } -} diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l073xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l073xx.S deleted file mode 100644 index 712035a55c9..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l073xx.S +++ /dev/null @@ -1,348 +0,0 @@ -;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32l073xx.s -;* Author : MCD Application Team -;* Version : V1.7.1 -;* Date : 25-November-2016 -;* Description : STM32L073xx Ultra Low Power Devices vector -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M0+ processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;*******************************************************************************/ -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_CRS_IRQHandler ; RCC_CRS - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TSC - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 - DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 - DCD LPTIM1_IRQHandler ; LPTIM1 - DCD USART4_5_IRQHandler ; USART4 and USART5 - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC - DCD TIM7_IRQHandler ; TIM7 - DCD 0 ; Reserved - DCD TIM21_IRQHandler ; TIM21 - DCD I2C3_IRQHandler ; I2C3 - DCD TIM22_IRQHandler ; TIM22 - DCD I2C1_IRQHandler ; I2C1 - DCD I2C2_IRQHandler ; I2C2 - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD RNG_LPUART1_IRQHandler ; RNG and LPUART1 - DCD LCD_IRQHandler ; LCD - DCD USB_IRQHandler ; USB - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -PVD_IRQHandler - B PVD_IRQHandler - - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - - PUBWEAK RCC_CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCC_CRS_IRQHandler - B RCC_CRS_IRQHandler - - - PUBWEAK EXTI0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_1_IRQHandler - B EXTI0_1_IRQHandler - - - PUBWEAK EXTI2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_3_IRQHandler - B EXTI2_3_IRQHandler - - - PUBWEAK EXTI4_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_15_IRQHandler - B EXTI4_15_IRQHandler - - - PUBWEAK TSC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TSC_IRQHandler - B TSC_IRQHandler - - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - - PUBWEAK DMA1_Channel2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_3_IRQHandler - B DMA1_Channel2_3_IRQHandler - - - PUBWEAK DMA1_Channel4_5_6_7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_5_6_7_IRQHandler - B DMA1_Channel4_5_6_7_IRQHandler - - - PUBWEAK ADC1_COMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC1_COMP_IRQHandler - B ADC1_COMP_IRQHandler - - - PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - - - PUBWEAK USART4_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART4_5_IRQHandler - B USART4_5_IRQHandler - - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK TIM21_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM21_IRQHandler - B TIM21_IRQHandler - - PUBWEAK I2C3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C3_IRQHandler - B I2C3_IRQHandler - - PUBWEAK TIM22_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM22_IRQHandler - B TIM22_IRQHandler - - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - - PUBWEAK I2C2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C2_IRQHandler - B I2C2_IRQHandler - - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - - PUBWEAK RNG_LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RNG_LPUART1_IRQHandler - B RNG_LPUART1_IRQHandler - - - PUBWEAK LCD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LCD_IRQHandler - B LCD_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USB_IRQHandler - B USB_IRQHandler - - END -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l073xx.icf b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l073xx.icf deleted file mode 100644 index 9d54f3418f7..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l073xx.icf +++ /dev/null @@ -1,59 +0,0 @@ -/* Linker script to configure memory regions. - * - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ -/* Device specific values */ - -/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ - -define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ -define symbol HEAP_SIZE = 0x1000; - -/* Common - Do not change */ - -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = MBED_ROM_START; -} - -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = MBED_ROM_SIZE; -} - -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} - -/* Round up VECTORS_SIZE to 8 bytes */ -define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; -define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; -define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; - -define memory mem with size = 4G; -define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; -define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; - -define block CSTACK with alignment = 8, size = MBED_BOOT_STACK_SIZE { }; -define block HEAP with alignment = 8, size = HEAP_SIZE { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem: MBED_APP_START { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l071xx.s b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_ARM/startup_stm32l071xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/startup_stm32l071xx.s rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_ARM/startup_stm32l071xx.S diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l071xx.sct b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_ARM/stm32l071xx.sct similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_ARM/stm32l071xx.sct rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_ARM/stm32l071xx.sct diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/STM32L071CXCTX.ld b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_GCC_ARM/STM32L071xx.ld similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/STM32L071CXCTX.ld rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_GCC_ARM/STM32L071xx.ld diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l071xx.s b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_IAR/startup_stm32l071xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/startup_stm32l071xx.s rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_IAR/startup_stm32l071xx.S diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/cmsis_nvic.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/cmsis_nvic.h diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/stm32l071xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/stm32l071xx.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/stm32l071xx.h rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/stm32l071xx.h diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/stm32l0xx.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/stm32l0xx.h rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/stm32l0xx.h diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/system_stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/system_stm32l0xx.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/system_stm32l0xx.h rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/system_stm32l0xx.h diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/us_ticker_data.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/device/us_ticker_data.h rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/us_ticker_data.h diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/objects.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/objects.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071CXCTX/objects.h rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/objects.h diff --git a/targets/targets.json b/targets/targets.json index a55c6ab8b4d..d5467f12d91 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2794,14 +2794,13 @@ ], "device_name": "STM32L072CZ" }, - "STM32L071CXCTX": { + "MCU_STM32L071xx": { "inherits": [ "MCU_STM32L0" ], "public": false, "extra_labels_add": [ "STM32L0", - "STML071CxCTx", "STML071xx" ], "overrides": { @@ -2811,7 +2810,7 @@ "ANALOGOUT", "TRNG" ], - "device_name": "STM32L071CXCTX" + "device_name": "STM32L071xx" }, "NUCLEO_L073RZ": { "inherits": [ From 23a3ea06cbc29766c333b5f05b08b7e2237cd4e9 Mon Sep 17 00:00:00 2001 From: Andrea Gilardoni Date: Fri, 28 Aug 2020 19:37:53 +0200 Subject: [PATCH 4/6] fixing the remaining parts after the rename --- .../device/TOOLCHAIN_ARM/startup_stm32l071xx.S | 0 .../device/TOOLCHAIN_ARM/stm32l071xx.sct | 0 .../device/TOOLCHAIN_GCC_ARM/STM32L071xx.ld | 0 .../device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S | 0 .../device/TOOLCHAIN_IAR/startup_stm32l071xx.S | 0 .../device/TOOLCHAIN_IAR/stm32l071xx_flash.icf | 0 .../device/TOOLCHAIN_IAR/stm32l071xx_sram.icf | 0 .../device/cmsis_nvic.h | 0 .../device/stm32l071xx.h | 0 .../device/stm32l0xx.h | 0 .../device/system_stm32l0xx.h | 0 .../device/us_ticker_data.h | 0 .../objects.h | 0 .../TARGET_STM32L0/device/stm32l0xx_hal_conf.h | 10 +++++----- targets/targets.json | 11 ----------- 15 files changed, 5 insertions(+), 16 deletions(-) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/device/TOOLCHAIN_ARM/startup_stm32l071xx.S (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/device/TOOLCHAIN_ARM/stm32l071xx.sct (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/device/TOOLCHAIN_GCC_ARM/STM32L071xx.ld (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/device/TOOLCHAIN_IAR/startup_stm32l071xx.S (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/device/cmsis_nvic.h (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/device/stm32l071xx.h (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/device/stm32l0xx.h (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/device/system_stm32l0xx.h (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/device/us_ticker_data.h (100%) rename targets/TARGET_STM/TARGET_STM32L0/{TARGET_STM32L071xx => TARGET_MCU_STM32L071xx}/objects.h (100%) diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_ARM/startup_stm32l071xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_ARM/startup_stm32l071xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_ARM/startup_stm32l071xx.S rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_ARM/startup_stm32l071xx.S diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_ARM/stm32l071xx.sct b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_ARM/stm32l071xx.sct similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_ARM/stm32l071xx.sct rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_ARM/stm32l071xx.sct diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_GCC_ARM/STM32L071xx.ld b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_GCC_ARM/STM32L071xx.ld similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_GCC_ARM/STM32L071xx.ld rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_GCC_ARM/STM32L071xx.ld diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_IAR/startup_stm32l071xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_IAR/startup_stm32l071xx.S similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_IAR/startup_stm32l071xx.S rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_IAR/startup_stm32l071xx.S diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_IAR/stm32l071xx_flash.icf diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_IAR/stm32l071xx_sram.icf diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/cmsis_nvic.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/cmsis_nvic.h rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/cmsis_nvic.h diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/stm32l071xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l071xx.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/stm32l071xx.h rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l071xx.h diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l0xx.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/stm32l0xx.h rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l0xx.h diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/system_stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/system_stm32l0xx.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/system_stm32l0xx.h rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/system_stm32l0xx.h diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/us_ticker_data.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/device/us_ticker_data.h rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/us_ticker_data.h diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/objects.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/objects.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L071xx/objects.h rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/objects.h diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h index a6cec8d7765..d26337aed9f 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h @@ -54,7 +54,7 @@ #define HAL_CRC_MODULE_ENABLED #define HAL_CRYP_MODULE_ENABLED -#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071CxCTx) +#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071xx) #define HAL_DAC_MODULE_ENABLED #endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ @@ -68,7 +68,7 @@ #define HAL_GPIO_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED -#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071CxCTx) +#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071xx) #define HAL_I2S_MODULE_ENABLED #endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ @@ -78,7 +78,7 @@ #define HAL_PWR_MODULE_ENABLED #define HAL_RCC_MODULE_ENABLED -#if !defined (TARGET_STML071CxCTx) +#if !defined (TARGET_STML071xx) #define HAL_RNG_MODULE_ENABLED #endif /* !TARGET_STML0CXCTX */ @@ -86,7 +86,7 @@ #define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED -#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071CxCTx) +#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071xx) #define HAL_TSC_MODULE_ENABLED #endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ @@ -98,7 +98,7 @@ #define HAL_WWDG_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED -#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071CxCTx) +#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071xx) #define HAL_PCD_MODULE_ENABLED #endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ diff --git a/targets/targets.json b/targets/targets.json index d5467f12d91..02a0ee2756a 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2411,15 +2411,7 @@ "inherits": [ "MCU_STM32G0" ], -<<<<<<< HEAD "public": false, -======= - "core": "Cortex-M7FD", - "mbed_rom_start": "0x08000000", - "mbed_rom_size": "0x200000", - "mbed_ram_start": "0x24000000", - "mbed_ram_size": "0x80000", ->>>>>>> 017a98b738... fixing the issues "extra_labels_add": [ "STM32G071xx" ], @@ -2803,9 +2795,6 @@ "STM32L0", "STML071xx" ], - "overrides": { - "lpticker_delay_ticks": 0 - }, "device_has_remove": [ "ANALOGOUT", "TRNG" From 15ca58b9c80a8236ec70235f5fda2ed49cfa024b Mon Sep 17 00:00:00 2001 From: Andrea Gilardoni Date: Mon, 31 Aug 2020 14:03:49 +0200 Subject: [PATCH 5/6] fixing small issues --- .../device/stm32l0xx_hal_conf.h | 20 +++++++++---------- targets/targets.json | 5 ++--- 2 files changed, 12 insertions(+), 13 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h index d26337aed9f..169d1235ebd 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_conf.h @@ -54,23 +54,23 @@ #define HAL_CRC_MODULE_ENABLED #define HAL_CRYP_MODULE_ENABLED -#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071xx) +#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STM32L071xx) #define HAL_DAC_MODULE_ENABLED -#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ +#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STM32L071xx */ #define HAL_DMA_MODULE_ENABLED #if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) #define HAL_FIREWALL_MODULE_ENABLED -#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ +#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 */ #define HAL_FLASH_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED -#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071xx) +#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STM32L071xx) #define HAL_I2S_MODULE_ENABLED -#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ +#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STM32L071xx */ #define HAL_IWDG_MODULE_ENABLED #define HAL_LCD_MODULE_ENABLED @@ -80,15 +80,15 @@ #if !defined (TARGET_STML071xx) #define HAL_RNG_MODULE_ENABLED -#endif /* !TARGET_STML0CXCTX */ +#endif /* !TARGET_STM32L071xx */ #define HAL_RTC_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED -#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071xx) +#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STM32L071xx) #define HAL_TSC_MODULE_ENABLED -#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ +#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STM32L071xx */ #define HAL_UART_MODULE_ENABLED #define HAL_USART_MODULE_ENABLED @@ -98,9 +98,9 @@ #define HAL_WWDG_MODULE_ENABLED #define HAL_CORTEX_MODULE_ENABLED -#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STML071xx) +#if !defined (TARGET_STM32L031K6) && !defined (TARGET_STM32L011K4) && !defined (TARGET_STM32L071xx) #define HAL_PCD_MODULE_ENABLED -#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STML0CXCTX */ +#endif /* !TARGET_STM32L031K6 && !TARGET_STM32L011K4 && !TARGET_STM32L071xx */ /* ########################## Oscillator Values adaptation ####################*/ /** diff --git a/targets/targets.json b/targets/targets.json index 02a0ee2756a..67b809954a2 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2793,13 +2793,12 @@ "public": false, "extra_labels_add": [ "STM32L0", - "STML071xx" + "STM32L071xx" ], "device_has_remove": [ "ANALOGOUT", "TRNG" - ], - "device_name": "STM32L071xx" + ] }, "NUCLEO_L073RZ": { "inherits": [ From 3c39eeb8ddd2b18a5584c1c53a4ca61b34666fad Mon Sep 17 00:00:00 2001 From: Andrea Gilardoni Date: Tue, 1 Sep 2020 10:08:41 +0200 Subject: [PATCH 6/6] fixing SPDX identifiers in all files --- .../TOOLCHAIN_ARM/startup_stm32l071xx.S | 40 ++++-------- .../TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S | 65 ++++++++----------- .../TOOLCHAIN_IAR/startup_stm32l071xx.S | 38 ++++------- .../device/cmsis_nvic.h | 9 ++- .../device/stm32l071xx.h | 15 +++++ .../TARGET_MCU_STM32L071xx/device/stm32l0xx.h | 60 ++++------------- .../device/system_stm32l0xx.h | 48 ++++---------- .../device/us_ticker_data.h | 20 +++--- .../TARGET_MCU_STM32L071xx/objects.h | 33 +++------- 9 files changed, 117 insertions(+), 211 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_ARM/startup_stm32l071xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_ARM/startup_stm32l071xx.S index 93be51cf811..cf252dadb77 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_ARM/startup_stm32l071xx.S +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_ARM/startup_stm32l071xx.S @@ -1,6 +1,16 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32l071xx.s -;* Author : MCD Application Team +;* mbed Microcontroller Library +;* SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* +;* Copyright (c) 2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** ;* Description : STM32l071xx Devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -11,30 +21,6 @@ ;* After Reset the Cortex-M0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************* -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* ; ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S index 4713c5a1e39..5407cee18d4 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_GCC_ARM/startup_stm32l071xx.S @@ -1,42 +1,29 @@ -/** - ****************************************************************************** - * @file startup_stm32l071xx.s - * @author MCD Application Team - * @brief STM32L071xx Devices vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M0+ processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * @file startup_stm32l071xx.s + * @author MCD Application Team + * @brief STM32L071xx Devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + */ .syntax unified .cpu cortex-m0plus diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_IAR/startup_stm32l071xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_IAR/startup_stm32l071xx.S index efaba465bde..a7a259ac5d7 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_IAR/startup_stm32l071xx.S +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/TOOLCHAIN_IAR/startup_stm32l071xx.S @@ -1,4 +1,15 @@ -;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* mbed Microcontroller Library +;* SPDX-License-Identifier: BSD-3-Clause +;****************************************************************************** +;* +;* Copyright (c) 2020 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* ;* File Name : startup_stm32l071xx.s ;* Author : MCD Application Team ;* Description : STM32L071xx Ultra Low Power Devices vector @@ -13,31 +24,6 @@ ;* After Reset the Cortex-M0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;*******************************************************************************/ -; ; ; The modules in this file are included in the libraries, and may be replaced ; by any user-defined modules that define the PUBLIC symbol _program_start or diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/cmsis_nvic.h index 4b4b07c8563..c4d7ddfcffe 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/cmsis_nvic.h @@ -1,18 +1,17 @@ /* mbed Microcontroller Library * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** - * @attention * - *

© Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the + * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** -*/ + */ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l071xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l071xx.h index 387bc288c49..01f9b9555aa 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l071xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l071xx.h @@ -1,3 +1,18 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + #ifndef __STM32L071xx_H #define __STM32L071xx_H diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l0xx.h index 9c2e5bdee84..e75088b2830 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l0xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/stm32l0xx.h @@ -1,49 +1,17 @@ -/** - ****************************************************************************** - * @file stm32l0xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32L0xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral's drivers in application code(i.e. - * code will be based on direct access to peripheral's registers - * rather than drivers API), this option is controlled by - * "#define USE_HAL_DRIVER" - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ /** @addtogroup CMSIS * @{ diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/system_stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/system_stm32l0xx.h index df958f5bebc..f28408e33b3 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/system_stm32l0xx.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/system_stm32l0xx.h @@ -1,37 +1,17 @@ -/** - ****************************************************************************** - * @file system_stm32l0xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ /** @addtogroup CMSIS * @{ diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/us_ticker_data.h index 1ae9b883759..da35c82b854 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/us_ticker_data.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/device/us_ticker_data.h @@ -1,18 +1,18 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2018 ARM Limited + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ + #ifndef __US_TICKER_DATA_H #define __US_TICKER_DATA_H diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/objects.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/objects.h index d0f3565f66d..e5833b4522b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/objects.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_MCU_STM32L071xx/objects.h @@ -1,31 +1,16 @@ /* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics - * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Copyright (c) 2020 STMicroelectronics. + * All rights reserved. * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* + ****************************************************************************** */ #ifndef MBED_OBJECTS_H #define MBED_OBJECTS_H