From 775c5c9eb242e2bd7d14351496ab7188ea6a8432 Mon Sep 17 00:00:00 2001
From: dc37 <rehdblob@gmail.com>
Date: Fri, 26 Feb 2016 19:42:23 -0600
Subject: [PATCH] Fix clock configuration for LPC1549.

Datasheet (Table 82) says MSEL bits should be 5, and the PSEL bits should
be 1, for the correct FCCO frequency of 288MHz. The current configuration
has FCCO = 144MHz, which is technically out of spec.
Tested on a custom LPC1549 board with crystal oscillator running at 12MHz.
---
 .../cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c        | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c
index 86dbd933ed0..e5704f1acfe 100644
--- a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/system_LPC15xx.c
@@ -73,14 +73,14 @@
 //       <o.0..5> MSEL: Feedback Divider Selection
 //              <i> M = MSEL + 1
 //            <0-31>
-//       <o.5..7> PSEL: Post Divider Selection
+//       <o.6..7> PSEL: Post Divider Selection
 //              <i> Post divider ratio P. Division ratio is 2 * P
 //            <0=> P = 1
 //            <1=> P = 2
 //            <2=> P = 4
 //            <3=> P = 8
 //     </h>
-#define SYSPLLCTRL_Val        0x00000005              // Reset value: 0x000
+#define SYSPLLCTRL_Val        0x00000045              // Reset value: 0x000
 //
 //     <o.0..7>   System AHB Clock Divider (SYSAHBCLKDIV.DIV)
 //            <i> Divides main clock to provide system clock to core, memories, and peripherals.
@@ -156,7 +156,7 @@
 //            <2=> P = 4
 //            <3=> P = 8
 //     </h>
-#define SCTPLLCTRL_Val        0x00000005              // Reset value: 0x000
+#define SCTPLLCTRL_Val        0x00000045              // Reset value: 0x000
 //
 //     <o.0..1> SCT PLL Clock Source Select (SCTPLLCLKSEL.SEL)
 //                   <0=> IRC Oscillator