+ *
+ * | Parameter Value |
+ * Description |
+ *
+ * | TC_IDR_COVFS | Disables the Counter Overflow Interrupt |
+ * | TC_IDR_LOVRS | Disables the Load Overrun Interrupt |
+ * | TC_IDR_CPAS | Disables the RA Compare Interrupt |
+ * | TC_IDR_CPBS | Disables the RB Compare Interrupt |
+ * | TC_IDR_CPCS | Disables the RC Compare Interrupt |
+ * | TC_IDR_LDRAS | Disables the RA Load Interrupt |
+ * | TC_IDR_LDRBS | Disables the RB Load Interrupt |
+ * | TC_IDR_ETRGS | Disables the External Trigger Interrupt |
+ *
+ */
+void tc_disable_interrupt(
+ Tc *p_tc,
+ uint32_t ul_channel,
+ uint32_t ul_sources)
+{
+ TcChannel *tc_channel;
+
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+ tc_channel = p_tc->TC_CHANNEL + ul_channel;
+ tc_channel->TC_IDR = ul_sources;
+}
+
+/**
+ * \brief Read the TC interrupt mask for the specified channel.
+ *
+ * \param[in] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel to read
+ *
+ * \return The TC interrupt mask value.
+ */
+uint32_t tc_get_interrupt_mask(
+ Tc *p_tc,
+ uint32_t ul_channel)
+{
+ TcChannel *tc_channel;
+
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+ tc_channel = p_tc->TC_CHANNEL + ul_channel;
+ return tc_channel->TC_IMR;
+}
+
+/**
+ * \brief Get the current status for the specified TC channel.
+ *
+ * \param[in] p_tc Module hardware register base address pointer
+ * \param[in] ul_channel Channel number
+ *
+ * \return The current TC status.
+ */
+uint32_t tc_get_status(
+ Tc *p_tc,
+ uint32_t ul_channel)
+{
+ TcChannel *tc_channel;
+
+ /* Validate inputs. */
+ Assert(p_tc);
+ Assert(ul_channel <
+ (sizeof(p_tc->TC_CHANNEL) / sizeof(p_tc->TC_CHANNEL[0])));
+
+ tc_channel = p_tc->TC_CHANNEL + ul_channel;
+ return tc_channel->TC_SR;
+}
+
+/* TC divisor used to find the lowest acceptable timer frequency */
+#define TC_DIV_FACTOR 65536
+
+#if (!SAM4L) && !defined(__DOXYGEN__)
+
+#ifndef FREQ_SLOW_CLOCK_EXT
+#define FREQ_SLOW_CLOCK_EXT 32768 /* External slow clock frequency (hz) */
+#endif
+
+/**
+ * \brief Find the best MCK divisor.
+ *
+ * Finds the best MCK divisor given the timer frequency and MCK. The result
+ * is guaranteed to satisfy the following equation:
+ * \code (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) \endcode
+ * With DIV being the lowest possible value, to maximize timing adjust resolution.
+ *
+ * \param[in] ul_freq Desired timer frequency
+ * \param[in] ul_mck Master clock frequency
+ * \param[out] p_uldiv Divisor value
+ * \param[out] p_ultcclks TCCLKS field value for divisor
+ * \param[in] ul_boardmck Board clock frequency
+ *
+ * \return The divisor found status.
+ * \retval 0 No suitable divisor was found
+ * \retval 1 A divisor was found
+ */
+uint32_t tc_find_mck_divisor(
+ uint32_t ul_freq,
+ uint32_t ul_mck,
+ uint32_t *p_uldiv,
+ uint32_t *p_ultcclks,
+ uint32_t ul_boardmck)
+{
+ const uint32_t divisors[5] = { 2, 8, 32, 128,
+ ul_boardmck / FREQ_SLOW_CLOCK_EXT
+ };
+ uint32_t ul_index;
+ uint32_t ul_high, ul_low;
+
+ /* Satisfy frequency bound. */
+ for (ul_index = 0;
+ ul_index < (sizeof(divisors) / sizeof(divisors[0]));
+ ul_index++) {
+ ul_high = ul_mck / divisors[ul_index];
+ ul_low = ul_high / TC_DIV_FACTOR;
+ if (ul_freq > ul_high) {
+ return 0;
+ } else if (ul_freq >= ul_low) {
+ break;
+ }
+ }
+ if (ul_index >= (sizeof(divisors) / sizeof(divisors[0]))) {
+ return 0;
+ }
+
+ /* Store results. */
+ if (p_uldiv) {
+ *p_uldiv = divisors[ul_index];
+ }
+
+ if (p_ultcclks) {
+ *p_ultcclks = ul_index;
+ }
+
+ return 1;
+}
+
+#endif /* (!SAM4L) */
+
+#if (SAM4L) || defined(__DOXYGEN__)
+/**
+ * \brief Find the best PBA/MCK divisor.
+ *
+ *