diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h index 708f2f5f7cb..2c3daebe5c5 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/objects.h @@ -60,11 +60,6 @@ struct analogin_s { uint8_t channel; }; -struct i2c_s { - I2CName i2c; - uint32_t slave; -}; - struct can_s { CANName can; int index; diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h index da4126e6ce5..30da1d85089 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/objects.h @@ -60,11 +60,6 @@ struct analogin_s { uint8_t channel; }; -struct i2c_s { - I2CName i2c; - uint32_t slave; -}; - #include "common_objects.h" #include "gpio_object.h" diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h index b0b234ba744..606f25cf942 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/objects.h @@ -60,11 +60,6 @@ struct analogin_s { uint8_t channel; }; -struct i2c_s { - I2CName i2c; - uint32_t slave; -}; - struct can_s { CANName can; int index; diff --git a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h index 07258e1e738..8aba9b424c6 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/common_objects.h +++ b/targets/TARGET_STM/TARGET_STM32F1/common_objects.h @@ -82,6 +82,34 @@ struct spi_s { #endif }; +struct i2c_s { + /* The 1st 2 members I2CName i2c + * and I2C_HandleTypeDef handle should + * be kept as the first members of this struct + * to ensure i2c_get_obj to work as expected + */ + I2CName i2c; + I2C_HandleTypeDef handle; + uint8_t index; + int hz; + PinName sda; + PinName scl; + IRQn_Type event_i2cIRQ; + IRQn_Type error_i2cIRQ; + uint32_t XferOperation; + volatile uint8_t event; +#if DEVICE_I2CSLAVE + uint8_t slave; + volatile uint8_t pending_slave_tx_master_rx; + volatile uint8_t pending_slave_rx_maxter_tx; +#endif +#if DEVICE_I2C_ASYNCH + uint32_t address; + uint8_t stop; + uint8_t available_events; +#endif +}; + #include "gpio_object.h" #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32f1xx_hal.html b/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32f1xx_hal.html index 4afa2c50a6a..9339962394e 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32f1xx_hal.html +++ b/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32f1xx_hal.html @@ -920,7 +920,39 @@

Update History

-

V1.0.4 / 29-April-2016

+

V1.0.5 / 06-December-2016

+ + + + + + + + + + + + + + + + + + + + +

Main +Changes

+

V1.0.4 / 29-April-2016

diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32_assert_template.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32_assert_template.h new file mode 100644 index 00000000000..d3c6502c9c8 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32_assert_template.h @@ -0,0 +1,75 @@ +/** + ****************************************************************************** + * @file stm32_assert.h + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief STM32 assert template file. + * This file should be copied to the application folder and renamed + * to stm32_assert.h. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.c index 0e0af6951d0..7cbec5a20b1 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -76,7 +76,7 @@ */ #define __STM32F1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F1xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32F1xx_HAL_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */ +#define __STM32F1xx_HAL_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ #define __STM32F1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\ |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.h index c2f16d61003..31b4e16395d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.c index 20ccbbef746..452186190eb 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_adc.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.h index cf2fe0a57d3..0b88d548357 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_adc.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.c index f806f88417f..b1c050f157e 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.h index e4a96af9afc..2337bf61f5b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of ADC HAL extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.c index 2304abd1e4a..df438113ad5 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_can.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief CAN HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: @@ -535,41 +535,39 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - - /* Select one empty transmit mailbox */ - if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) - { - transmitmailbox = 0; - } - else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) - { - transmitmailbox = 1; - } - else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME2)) - { - transmitmailbox = 2; - } - else - { - transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - } - if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX) - { + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) + { + /* Process locked */ + __HAL_LOCK(hcan); + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + + /* Select one empty transmit mailbox */ + if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) + { + transmitmailbox = 0; + } + else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) + { + transmitmailbox = 1; + } + else + { + transmitmailbox = 2; + } + /* Set up the Id */ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; if (hcan->pTxMsg->IDE == CAN_ID_STD) @@ -585,7 +583,7 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) hcan->pTxMsg->IDE | hcan->pTxMsg->RTR); } - + /* Set up the DLC */ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; @@ -602,10 +600,10 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_BIT_POSITION) ); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); - - /* Get timeout */ - tickstart = HAL_GetTick(); - + + /* Get tick */ + tickstart = HAL_GetTick(); + /* Check End of transmission flag */ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) { @@ -615,41 +613,33 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; } } } - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_RX; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); } else { /* Change CAN state */ hcan->State = HAL_CAN_STATE_READY; } - + /* Process unlocked */ __HAL_UNLOCK(hcan); - + /* Return function status */ return HAL_OK; } else { /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hcan); + hcan->State = HAL_CAN_STATE_ERROR; /* Return function status */ return HAL_ERROR; @@ -671,7 +661,9 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); - if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_RX)) + if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ + ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ + ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) { /* Process Locked */ __HAL_LOCK(hcan); @@ -685,88 +677,85 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) { transmitmailbox = 1; } - else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME2)) + else { transmitmailbox = 2; } + + /* Set up the Id */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; + if (hcan->pTxMsg->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_BIT_POSITION) | + hcan->pTxMsg->RTR); + } else { - transmitmailbox = CAN_TXSTATUS_NOMAILBOX; + assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_BIT_POSITION) | + hcan->pTxMsg->IDE | + hcan->pTxMsg->RTR); } - if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX) + /* Set up the DLC */ + hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_BIT_POSITION) | + ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_BIT_POSITION) | + ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_BIT_POSITION) | + ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_BIT_POSITION) ); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_BIT_POSITION) | + ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_BIT_POSITION) | + ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_BIT_POSITION) | + ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_BIT_POSITION) ); + + if(hcan->State == HAL_CAN_STATE_BUSY_RX) { - /* Set up the Id */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if (hcan->pTxMsg->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_BIT_POSITION) | - hcan->pTxMsg->RTR); - } - else - { - assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_BIT_POSITION) | - hcan->pTxMsg->IDE | - hcan->pTxMsg->RTR); - } - - /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; - - /* Set up the data field */ - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_BIT_POSITION) ); - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_BIT_POSITION) ); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcan); - - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - /* - Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME ); - - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX_RX; } + else + { + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + } + + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcan); + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME ); + + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; } else { - return HAL_BUSY; + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + /* Return function status */ + return HAL_ERROR; } - + return HAL_OK; } diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.h index dcb80955c03..3a1224bf457 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_can.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can_ex.h index 32911597eda..d7ea278000e 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_can_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of CAN HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.c index f6826a805cb..dc3ce1fd2c3 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_cec.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief CEC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.h index 7ced6beeeef..f0af5fcb0c0 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_cec.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of CEC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.c index 1c9d8869af3..29dd4f36016 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_cortex.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief CORTEX HAL module driver. * * This file provides firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.h index 30788b0aba7..a74f74d82a1 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_cortex.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.c index ad6a2b444c8..fe8195b06ee 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_crc.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.h index 4bee46d1394..83d0e078a14 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_crc.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.c index ced2c7526a4..f380eae018b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_dac.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.h index 897b655a2ac..6e095cfce5f 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_dac.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.c index 0fa52646324..38ebcecbd47 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.h index 3359a094d66..5f5c9c856a5 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention @@ -96,16 +96,6 @@ * @} */ -/** @defgroup DACEx_wave_generation DACEx wave generation - * @{ - */ -#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) - -/** - * @} - */ - /** @defgroup DACEx_trigger_selection DAC trigger selection * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_def.h index 00c29b47276..9f1eeeace33 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_def.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_def.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.c index 4a48d5f9bd4..76167bb4d8a 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_dma.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -422,6 +422,49 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) return HAL_OK; } +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + status = HAL_ERROR; + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Call User Abort callback */ + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + } + return status; +} + /** * @brief Polling for transfer complete. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.h index 5d344b28f4e..607a70b92ec 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_dma.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -142,6 +142,8 @@ typedef struct __DMA_HandleTypeDef void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ __IO uint32_t ErrorCode; /*!< DMA Error code */ } DMA_HandleTypeDef; @@ -158,9 +160,10 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Error_Code DMA Error Code * @{ */ - #define HAL_DMA_ERROR_NONE ((uint32_t)0x00) /*!< No error */ - #define HAL_DMA_ERROR_TE ((uint32_t)0x01) /*!< Transfer error */ - #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */ +#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ +#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoing transfer */ +#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ /** * @} @@ -387,6 +390,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); /** diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma_ex.h index 05d2d3a7e1d..b28cdeada70 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention @@ -124,6 +124,25 @@ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ DMA_FLAG_TE5) +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ + DMA_FLAG_GL5) + /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__: DMA handle @@ -205,6 +224,20 @@ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ DMA_FLAG_TE7) +/** + * @brief Return the current DMA Channel Global interrupt flag. + * @param __HANDLE__: DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ + DMA_FLAG_GL7) + /** * @brief Get the DMA Channel pending flags. * @param __HANDLE__: DMA handle diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.c index 11eb690db12..439cb7012c7 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_eth.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief ETH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h index 25afd51f4fb..8ec39a39ab4 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_eth.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of ETH HAL module. ****************************************************************************** * @attention @@ -1118,41 +1118,6 @@ typedef struct #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ -/** - * @} - */ - -/** @defgroup ETH_MAC_Debug_Flags ETH MAC Debug Flags - * @{ - */ -#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ -#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c index b5d6c1a9af9..5a3330d2585 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_flash.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.h index 1135f81e894..abb0fa4564c 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_flash.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of Flash HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.c index 91e4d5a786c..f37254bb4c0 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Extended FLASH HAL module driver. * * This file provides firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.h index 933a95e8644..a77c2a82ffc 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of Flash HAL Extended module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.c index 9e048ad50d2..0a920f194b1 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_gpio.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.h index 22cd0191c4f..1178290a5eb 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_gpio.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.c index 31493e65d03..ea3fc90b4a2 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_gpio_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief GPIO Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) extension peripheral. diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.h index 9d9c3b34810..e2f3479d864 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.c index fd7ae8a1cb6..cd05ea59ee2 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_hcd.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief HCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.h index ab01072e733..2d0437508fd 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_hcd.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c index 0ccc7ff87b7..7c72e1f840d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c @@ -2,16 +2,15 @@ ****************************************************************************** * @file stm32f1xx_hal_i2c.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * + * + Peripheral State, Mode and Error functions + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -67,74 +66,118 @@ *** Interrupt mode IO operation *** =================================== [..] - (+) The I2C interrupts should have the highest priority in the application in order - to make them uninterruptible. - (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback + (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback + (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback + (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + + *** Interrupt mode IO sequential operation *** + ============================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to transfer + if no direction change and with a final stop condition in both cases + + (+) Differents sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can + add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** Interrupt mode IO MEM operation *** ======================================= [..] - (+) The I2C interrupts should have the highest priority in the application in order - to make them uninterruptible. - (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback + (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() + add his own code by customization of function pointer HAL_I2C_ErrorCallback *** DMA mode IO operation *** ============================== [..] - (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + (+) Transmit in master mode an amount of data in non blocking mode (DMA) using HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback + (+) Receive in master mode an amount of data in non blocking mode (DMA) using HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback + (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback + (+) Receive in slave mode an amount of data in non blocking mode (DMA) using HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() + add his own code by customization of function pointer HAL_I2C_ErrorCallback + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() *** DMA mode IO MEM operation *** ================================= [..] - (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback + (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2C_ErrorCallback() + add his own code by customization of function pointer HAL_I2C_ErrorCallback *** I2C HAL driver macros list *** @@ -144,12 +187,13 @@ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt - (@) You can refer to the I2C HAL driver header file for more useful macros + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros *** I2C Workarounds linked to Silicon Limitation *** ==================================================== @@ -216,47 +260,59 @@ #ifdef HAL_I2C_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup I2C_Private_Constants I2C Private Constants +/* Private define ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Define * @{ - */ -#define I2C_TIMEOUT_FLAG ((uint32_t)35) /*!< Timeout 35 ms */ -#define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000) /*!< Timeout 10 s */ -#define I2C_TIMEOUT_BUSY_FLAG ((uint32_t)10000) /*!< Timeout 10 s */ + */ +#define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ +#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ +#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ + /** * @} - */ + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup I2C_Private_Functions I2C Private Functions +/** @addtogroup I2C_Private_Functions * @{ */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma); +/* Private functions to handle DMA transfer */ +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); static void I2C_DMAError(DMA_HandleTypeDef *hdma); - -static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout); -static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout); -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +static void I2C_ITError(I2C_HandleTypeDef *hi2c); + +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); +/* Private functions for I2C transfer IRQ handler */ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); +static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); @@ -265,14 +321,11 @@ static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c); static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c); - -static uint32_t I2C_Configure_Speed(I2C_HandleTypeDef *hi2c, uint32_t I2CClkSrcFreq); /** * @} - */ - -/* Exported functions ---------------------------------------------------------*/ + */ +/* Exported functions --------------------------------------------------------*/ /** @defgroup I2C_Exported_Functions I2C Exported Functions * @{ */ @@ -285,7 +338,7 @@ static uint32_t I2C_Configure_Speed(I2C_HandleTypeDef *hi2c, uint32_t I2CClkSrcF ##### Initialization and de-initialization functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to initialize and - de-initialiaze the I2Cx peripheral: + de-initialize the I2Cx peripheral: (+) User must Implement HAL_I2C_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). @@ -302,7 +355,7 @@ static uint32_t I2C_Configure_Speed(I2C_HandleTypeDef *hi2c, uint32_t I2CClkSrcF (++) Nostretch mode (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx periperal. + of the selected I2Cx peripheral. @endverbatim * @{ @@ -310,15 +363,15 @@ static uint32_t I2C_Configure_Speed(I2C_HandleTypeDef *hi2c, uint32_t I2CClkSrcF /** * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and initialize the associated handle. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * in the I2C_InitTypeDef and create the associated handle. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { - uint32_t freqrange = 0; - uint32_t pclk1 = 0; + uint32_t freqrange = 0U; + uint32_t pclk1 = 0U; /* Check the I2C handle allocation */ if(hi2c == NULL) @@ -341,7 +394,6 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) { /* Allocate lock resource and initialize it */ hi2c->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_I2C_MspInit(hi2c); } @@ -355,7 +407,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) pclk1 = HAL_RCC_GetPCLK1Freq(); /* Calculate frequency range */ - freqrange = I2C_FREQ_RANGE(pclk1); + freqrange = I2C_FREQRANGE(pclk1); /*---------------------------- I2Cx CR2 Configuration ----------------------*/ /* Configure I2Cx: Frequency range */ @@ -367,7 +419,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) /*---------------------------- I2Cx CCR Configuration ----------------------*/ /* Configure I2Cx: Speed */ - hi2c->Instance->CCR = I2C_Configure_Speed(hi2c, pclk1); + hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle); /*---------------------------- I2Cx CR1 Configuration ----------------------*/ /* Configure I2Cx: Generalcall and NoStretch mode */ @@ -386,15 +438,16 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; return HAL_OK; } /** - * @brief DeInitialize the I2C peripheral. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief DeInitializes the I2C peripheral. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) @@ -416,9 +469,10 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ HAL_I2C_MspDeInit(hi2c); - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_RESET; - hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; /* Release Lock */ __HAL_UNLOCK(hi2c); @@ -427,31 +481,31 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) } /** - * @brief Initialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief I2C MSP Init. + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval None */ __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2C_MspInit could be implemented in the user file */ } /** - * @brief DeInitialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * @brief I2C MSP DeInit + * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module * @retval None */ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - /* NOTE : This function should not be modified, when the callback is needed, + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2C_MspDeInit could be implemented in the user file */ } @@ -460,7 +514,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) * @} */ -/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions +/** @defgroup I2C_Exported_Functions_Group2 IO operation functions * @brief Data transfers functions * @verbatim @@ -475,7 +529,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) (++) Blocking mode : The communication is performed in the polling mode. The status of all data processing is returned by the same function after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts + (++) No-Blocking mode : The communication is performed using Interrupts or DMA. These functions return the status of the transfer startup. The end of the data processing will be indicated through the dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when @@ -495,6 +549,10 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) (++) HAL_I2C_Master_Receive_IT() (++) HAL_I2C_Slave_Transmit_IT() (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Master_Sequential_Transmit_IT() + (++) HAL_I2C_Master_Sequential_Receive_IT() + (++) HAL_I2C_Slave_Sequential_Transmit_IT() + (++) HAL_I2C_Slave_Sequential_Receive_IT() (++) HAL_I2C_Mem_Write_IT() (++) HAL_I2C_Mem_Read_IT() @@ -514,6 +572,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) (++) HAL_I2C_SlaveTxCpltCallback() (++) HAL_I2C_SlaveRxCpltCallback() (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() @endverbatim * @{ @@ -523,7 +582,8 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) * @brief Transmits in master mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -531,15 +591,15 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) { return HAL_BUSY; } @@ -547,15 +607,28 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Locked */ __HAL_LOCK(hi2c); + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + /* Send Slave Address */ - if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout) != HAL_OK) + if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -574,15 +647,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - while(Size > 0) + while(hi2c->XferSize > 0U) { /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; return HAL_ERROR; } else @@ -592,37 +665,40 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA } /* Write data to DR */ - hi2c->Instance->DR = (*pData++); - Size--; + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0)) + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U)) { /* Write data to DR */ - hi2c->Instance->DR = (*pData++); - Size--; - } - } - - /* Wait until BTF flag is set */ - if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - return HAL_ERROR; + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; } - else + + /* Wait until BTF flag is set */ + if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + return HAL_ERROR; + } + else + { + return HAL_TIMEOUT; + } } } /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; hi2c->State = HAL_I2C_STATE_READY; - + hi2c->Mode = HAL_I2C_MODE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -638,7 +714,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @brief Receives in master mode an amount of data in blocking mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -646,15 +723,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA */ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) { return HAL_BUSY; } @@ -662,15 +739,28 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd /* Process Locked */ __HAL_LOCK(hi2c); + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; /* Send Slave Address */ - if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout) != HAL_OK) + if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -686,60 +776,68 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } } - if(Size == 1) + if(hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 1U) { /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 - software sequence must complete before the current byte end of transfer */ + software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); - + hi2c->Instance->CR1 |= I2C_CR1_STOP; + /* Re-enable IRQs */ __enable_irq(); } - else if(Size == 2) + else if(hi2c->XferSize == 2U) { /* Enable Pos */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 |= I2C_CR1_POS; /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 - software sequence must complete before the current byte end of transfer */ + software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - /* Re-enable IRQs */ - __enable_irq(); + /* Re-enable IRQs */ + __enable_irq(); } else { /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 |= I2C_CR1_ACK; /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); } - while(Size > 0) + while(hi2c->XferSize > 0U) { - if(Size <= 3) + if(hi2c->XferSize <= 3U) { /* One byte */ - if(Size == 1) + if(hi2c->XferSize == 1U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { @@ -752,14 +850,15 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; } /* Two bytes */ - else if(Size == 2) + else if(hi2c->XferSize == 2U) { /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -769,64 +868,69 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd __disable_irq(); /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; } /* 3 Last bytes */ else { /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; - + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; + /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; } } else { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { @@ -839,14 +943,16 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd } /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) { /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; } } } @@ -876,34 +982,46 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd */ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; /* Enable Address Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 |= I2C_CR1_ACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -915,7 +1033,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) { /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -924,13 +1042,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData __HAL_I2C_CLEAR_ADDRFLAG(hi2c); } - while(Size > 0) + while(hi2c->XferSize > 0U) { /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { return HAL_ERROR; @@ -942,19 +1061,21 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData } /* Write data to DR */ - hi2c->Instance->DR = (*pData++); - Size--; + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0)) + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U)) { /* Write data to DR */ - hi2c->Instance->DR = (*pData++); - Size--; + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + hi2c->XferSize--; } } /* Wait until AF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -963,7 +1084,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Disable Address Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; @@ -982,7 +1103,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData /** * @brief Receive in slave mode an amount of data in blocking mode * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @param Timeout Timeout duration @@ -990,34 +1111,46 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData */ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; /* Enable Address Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 |= I2C_CR1_ACK; /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1025,13 +1158,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - while(Size > 0) + while(hi2c->XferSize > 0U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { return HAL_TIMEOUT; @@ -1043,19 +1177,21 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, } /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0)) + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U)) { /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; } } /* Wait until STOP flag is set */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_FLAG) != HAL_OK) + if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hi2c->Instance->CR1 &= ~I2C_CR1_ACK; @@ -1074,7 +1210,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, __HAL_I2C_CLEAR_STOPFLAG(hi2c); /* Disable Address Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; @@ -1094,59 +1230,61 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { + __IO uint32_t count = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do { - return HAL_BUSY; + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); /* Process Locked */ __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Send Slave Address */ - if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1154,7 +1292,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Note : The I2C interrupts must be enabled after unlocking current process to avoid the risk of I2C interrupt handle execution before current process unlock */ - /* Enable EVT, BUF and ERR interrupt */ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); @@ -1170,94 +1307,71 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) { + __IO uint32_t count = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Send Slave Address */ - if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else + if(count-- == 0U) { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + + return HAL_TIMEOUT; } } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); - if(hi2c->XferCount == 1) + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); - } - else if(hi2c->XferCount == 2) - { - /* Enable Pos */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - } - else - { - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ + to avoid the risk of I2C interrupt handle execution before current + process unlock */ /* Enable EVT, BUF and ERR interrupt */ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); @@ -1271,51 +1385,96 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De } /** - * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + __IO uint32_t Prev_State = 0x00U; + __IO uint32_t count = 0x00U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + /* Check Busy Flag only if FIRST call of Master interface */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) { - return HAL_ERROR; - } - - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) - { - return HAL_BUSY; + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); } /* Process Locked */ __HAL_LOCK(hi2c); + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; - /* Enable Address Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + Prev_State = hi2c->PreviousState; + + /* Generate Start */ + if((Prev_State == I2C_STATE_MASTER_BUSY_RX) || (Prev_State == I2C_STATE_NONE)) + { + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(Prev_State == I2C_STATE_MASTER_BUSY_RX) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ + to avoid the risk of I2C interrupt handle execution before current + process unlock */ /* Enable EVT, BUF and ERR interrupt */ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); @@ -1329,50 +1488,98 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD } /** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param pData Pointer to data buffer * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + __IO uint32_t count = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + /* Check Busy Flag only if FIRST call of Master interface */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) { - return HAL_ERROR; - } + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) - { - return HAL_BUSY; + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); } /* Process Locked */ __HAL_LOCK(hi2c); + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; hi2c->XferCount = Size; - - /* Enable Address Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) || (hi2c->PreviousState == I2C_STATE_NONE)) + { + /* Generate Start condition if first transfer */ + if((XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_NO_OPTION_FRAME)) + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + } /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ + to avoid the risk of I2C interrupt handle execution before current + process unlock */ /* Enable EVT, BUF and ERR interrupt */ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); @@ -1385,80 +1592,78 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa } } - /** - * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address + * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { + __IO uint32_t count = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do { - return HAL_BUSY; + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); /* Process Locked */ __HAL_LOCK(hi2c); + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size); - - /* Send Slave Address */ - if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + return HAL_OK; } else @@ -1468,89 +1673,77 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t } /** - * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. - * @param DevAddress Target device address * @param pData Pointer to data buffer * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) { + __IO uint32_t count = 0U; + if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do { - return HAL_BUSY; + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); /* Process Locked */ __HAL_LOCK(hi2c); + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferSize = Size; hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size); - - /* Send Slave Address */ - if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - if(Size == 1) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - } - else - { - /* Enable Last DMA bit */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); - } - - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + return HAL_OK; } else @@ -1560,87 +1753,63 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D } /** - * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @param pData Pointer to data buffer * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { - if(hi2c->State == HAL_I2C_STATE_READY) + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); - /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size); - - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - /* Enable Address Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK) + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) { - return HAL_TIMEOUT; + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); } - /* If 7bit addressing mode is selected */ - if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK) - { - return HAL_TIMEOUT; - } + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + return HAL_OK; } else @@ -1650,69 +1819,602 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p } /** - * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for the specified I2C. * @param pData Pointer to data buffer * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { - if(hi2c->State == HAL_I2C_STATE_READY) + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if(hi2c->State == HAL_I2C_STATE_LISTEN) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) - { - return HAL_BUSY; - } - /* Process Locked */ __HAL_LOCK(hi2c); + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; - hi2c->XferCount = Size; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferSize = hi2c->XferCount; - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if(hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if(hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable Address Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + hi2c->Devaddress = DevAddress; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C process communication with Interrupt. + * @note This abort can be called only if state is ready + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + /* Abort Master transfer during Receive or Transmit process */ + if(hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->XferCount = 0U; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; + /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size); + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; - /* Enable Address Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} - /* Wait until ADDR flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK) +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + __IO uint32_t count = 0U; + + if(hi2c->State == HAL_I2C_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) { - return HAL_TIMEOUT; + return HAL_ERROR; } - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + /* Wait until BUSY flag is reset */ + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do + { + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } + } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + + /* Disable Pos */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); + + /* Enable Address Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; /* Process Unlocked */ __HAL_UNLOCK(hi2c); + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + return HAL_OK; } else @@ -1720,7 +2422,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD return HAL_BUSY; } } - /** * @brief Write an amount of data in blocking mode to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -1735,34 +2436,47 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD */ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1778,15 +2492,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - while(Size > 0) + while(hi2c->XferSize > 0U) { /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; return HAL_ERROR; } else @@ -1796,24 +2510,26 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } /* Write data to DR */ - hi2c->Instance->DR = (*pData++); - Size--; + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferSize--; + hi2c->XferCount--; - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0)) + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) { /* Write data to DR */ - hi2c->Instance->DR = (*pData++); - Size--; + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferSize--; + hi2c->XferCount--; } } - - /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + + /* Wait until BTF flag is set */ + if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; return HAL_ERROR; } else @@ -1823,11 +2539,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1853,34 +2569,47 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress */ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK) + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -1896,10 +2625,18 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } } - if(Size == 1) + if(hi2c->XferSize == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferSize == 1U) { /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ @@ -1909,15 +2646,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; /* Re-enable IRQs */ - __enable_irq(); + __enable_irq(); } - else if(Size == 2) + else if(hi2c->XferSize == 2U) { /* Enable Pos */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 |= I2C_CR1_POS; /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ @@ -1925,10 +2662,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, /* Clear ADDR flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - + /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + /* Re-enable IRQs */ __enable_irq(); } @@ -1941,15 +2678,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, __HAL_I2C_CLEAR_ADDRFLAG(hi2c); } - while(Size > 0) + while(hi2c->XferSize > 0U) { - if(Size <= 3) + if(hi2c->XferSize <= 3U) { /* One byte */ - if(Size== 1) + if(hi2c->XferSize== 1U) { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { @@ -1962,14 +2699,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; } /* Two bytes */ - else if(Size == 2) + else if(Size == 2U) { /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -1979,64 +2717,69 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, __disable_irq(); /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; /* Re-enable IRQs */ __enable_irq(); /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; } /* 3 Last bytes */ else { /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 software sequence must complete before the current byte end of transfer */ __disable_irq(); /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; /* Wait until BTF flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; /* Re-enable IRQs */ - __enable_irq(); + __enable_irq(); /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; } } else { /* Wait until RXNE flag is set */ - if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) { @@ -2049,21 +2792,23 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, } /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) { /* Read data from DR */ - (*pData++) = hi2c->Instance->DR; - Size--; + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferSize--; + hi2c->XferCount--; } } } hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2088,59 +2833,66 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, */ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + __IO uint32_t count = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do { - return HAL_BUSY; + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); /* Process Locked */ __HAL_LOCK(hi2c); + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; hi2c->State = HAL_I2C_STATE_BUSY_TX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferSize = Size; hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; /* Process Unlocked */ __HAL_UNLOCK(hi2c); /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ + to avoid the risk of I2C interrupt handle execution before current + process unlock */ /* Enable EVT, BUF and ERR interrupt */ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); @@ -2166,94 +2918,75 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr */ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + __IO uint32_t count = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do { - return HAL_BUSY; + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); /* Process Locked */ __HAL_LOCK(hi2c); + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; hi2c->State = HAL_I2C_STATE_BUSY_RX; hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferSize = Size; - hi2c->XferCount = Size; - - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; - } - } - - if(hi2c->XferCount == 1) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); - } - else if(hi2c->XferCount == 2) - { - /* Enable Pos */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - } - else - { - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - } + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; /* Process Unlocked */ __HAL_UNLOCK(hi2c); - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable EVT, BUF and ERR interrupt */ - __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - + if(hi2c->XferSize > 0U) + { + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable EVT, BUF and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + } return HAL_OK; } else @@ -2262,7 +2995,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre } } - /** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains @@ -2276,68 +3008,105 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre */ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + __IO uint32_t count = 0U; + + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do { - return HAL_BUSY; + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); /* Process Locked */ __HAL_LOCK(hi2c); + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; hi2c->XferSize = Size; hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt; + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size); + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - else + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); + + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } } - } - - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; + } return HAL_OK; } else @@ -2359,81 +3128,145 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd */ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { + uint32_t tickstart = 0x00U; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + __IO uint32_t count = 0U; + /* Check the parameters */ assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U); + do { - return HAL_BUSY; + if(count-- == 0U) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; + } } + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); /* Process Locked */ __HAL_LOCK(hi2c); + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } + /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + /* Prepare transfer parameters */ hi2c->pBuffPtr = pData; - hi2c->XferSize = Size; hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferSize = hi2c->XferCount; + + if(hi2c->XferSize > 0U) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; - /* Set the I2C DMA transfert complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt; + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferAbortCallback = NULL; - /* Enable the DMA channel */ - HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size); + /* Enable the DMA channel */ + HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); - /* Send Slave Address and Memory Address */ - if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } + + if(Size == 1U) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; } else { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_TIMEOUT; + /* Enable Last DMA bit */ + hi2c->Instance->CR2 |= I2C_CR2_LAST; } - } - if(Size == 1) - { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); + + /* Enable DMA Request */ + hi2c->Instance->CR2 |= I2C_CR2_DMAEN; } else { - /* Enable Last DMA bit */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); - } + /* Send Slave Address and Memory Address */ + if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + { + if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_TIMEOUT; + } + } - /* Enable DMA Request */ - SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } return HAL_OK; } @@ -2443,7 +3276,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr } } - /** * @brief Checks if target device is ready for communication. * @note This function is used with Memory devices @@ -2456,39 +3288,50 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr */ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) { - uint32_t tickstart = 0, tmp1 = 0, tmp2 = 0, tmp3 = 0, I2C_Trials = 1; + uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U; + + /* Get tick */ + tickstart = HAL_GetTick(); if(hi2c->State == HAL_I2C_STATE_READY) { /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) { return HAL_BUSY; } /* Process Locked */ __HAL_LOCK(hi2c); + + /* Check if the I2C is already enabled */ + if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) + { + /* Enable I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + } /* Disable Pos */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); + hi2c->Instance->CR1 &= ~I2C_CR1_POS; hi2c->State = HAL_I2C_STATE_BUSY; hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + do { /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + hi2c->Instance->CR1 |= I2C_CR1_START; /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } /* Send slave address */ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); - + /* Wait until ADDR or AF flag are set */ /* Get tick */ tickstart = HAL_GetTick(); @@ -2498,7 +3341,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd tmp3 = hi2c->State; while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT)) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hi2c->State = HAL_I2C_STATE_TIMEOUT; } @@ -2513,13 +3356,13 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) { /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; /* Clear ADDR Flag */ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2534,13 +3377,13 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd else { /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; /* Clear AF Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); /* Wait until BUSY flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -2559,13 +3402,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd return HAL_BUSY; } } -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group4 IRQ Handler and Callbacks - * @{ - */ /** * @brief This function handles I2C event interrupt request. @@ -2575,25 +3411,41 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) { - uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0, tmp4 = 0; + uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2); + uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); + uint32_t itsources = READ_REG(hi2c->Instance->CR2); + + uint32_t CurrentMode = hi2c->Mode; + /* Master or Memory mode selected */ - if((hi2c->Mode == HAL_I2C_MODE_MASTER) || \ - (hi2c->Mode == HAL_I2C_MODE_MEM)) + if((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) { + /* SB Set ----------------------------------------------------------------*/ + if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Master_SB(hi2c); + } + /* ADD10 Set -------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Master_ADD10(hi2c); + } + /* ADDR Set --------------------------------------------------------------*/ + else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) + { + I2C_Master_ADDR(hi2c); + } + /* I2C in mode Transmitter -----------------------------------------------*/ - if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET) + if((sr2itflags & I2C_FLAG_TRA) != RESET) { - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE); - tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF); - tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF); - tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT); /* TXE set and BTF reset -----------------------------------------------*/ - if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) + if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) { I2C_MasterTransmit_TXE(hi2c); } /* BTF set -------------------------------------------------------------*/ - else if((tmp3 == SET) && (tmp4 == SET)) + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) { I2C_MasterTransmit_BTF(hi2c); } @@ -2601,17 +3453,13 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* I2C in mode Receiver --------------------------------------------------*/ else { - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE); - tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF); - tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF); - tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT); /* RXNE set and BTF reset -----------------------------------------------*/ - if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) + if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) { I2C_MasterReceive_RXNE(hi2c); } /* BTF set -------------------------------------------------------------*/ - else if((tmp3 == SET) && (tmp4 == SET)) + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) { I2C_MasterReceive_BTF(hi2c); } @@ -2620,34 +3468,26 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Slave mode selected */ else { - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); - tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT)); - tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); - tmp4 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA); /* ADDR set --------------------------------------------------------------*/ - if((tmp1 == SET) && (tmp2 == SET)) + if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) { I2C_Slave_ADDR(hi2c); } /* STOPF set --------------------------------------------------------------*/ - else if((tmp3 == SET) && (tmp2 == SET)) + else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) { I2C_Slave_STOPF(hi2c); } /* I2C in mode Transmitter -----------------------------------------------*/ - else if(tmp4 == SET) + else if((sr2itflags & I2C_FLAG_TRA) != RESET) { - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE); - tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF); - tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF); - tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT); /* TXE set and BTF reset -----------------------------------------------*/ - if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) + if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) { I2C_SlaveTransmit_TXE(hi2c); } /* BTF set -------------------------------------------------------------*/ - else if((tmp3 == SET) && (tmp4 == SET)) + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) { I2C_SlaveTransmit_BTF(hi2c); } @@ -2655,17 +3495,13 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* I2C in mode Receiver --------------------------------------------------*/ else { - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE); - tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF); - tmp3 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF); - tmp4 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT); /* RXNE set and BTF reset ----------------------------------------------*/ - if((tmp1 == SET) && (tmp2 == SET) && (tmp3 == RESET)) + if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET)) { I2C_SlaveReceive_RXNE(hi2c); } /* BTF set -------------------------------------------------------------*/ - else if((tmp3 == SET) && (tmp4 == SET)) + else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET)) { I2C_SlaveReceive_BTF(hi2c); } @@ -2675,32 +3511,30 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /** * @brief This function handles I2C error interrupt request. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL status + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None */ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) { - uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0; + uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U; + uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); + uint32_t itsources = READ_REG(hi2c->Instance->CR2); - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR); - tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR); /* I2C Bus error interrupt occurred ----------------------------------------*/ - if((tmp1 == SET) && (tmp2 == SET)) + if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; /* Clear BERR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - + /* Workaround: Start cannot be generated after a misplaced Stop */ SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST); } - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO); - tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR); /* I2C Arbitration Loss error interrupt occurred ---------------------------*/ - if((tmp1 == SET) && (tmp2 == SET)) + if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; @@ -2708,153 +3542,210 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); } - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); - tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR); /* I2C Acknowledge failure error interrupt occurred ------------------------*/ - if((tmp1 == SET) && (tmp2 == SET)) + if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) { tmp1 = hi2c->Mode; tmp2 = hi2c->XferCount; tmp3 = hi2c->State; - if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0) && \ - (tmp3 == HAL_I2C_STATE_BUSY_TX)) + tmp4 = hi2c->PreviousState; + if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ + ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ + ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) { I2C_Slave_AF(hi2c); } else { hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); - + + /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ + if(hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Generate Stop */ + SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + } + /* Clear AF flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); } } - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR); - tmp2 = __HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR); /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ - if((tmp1 == SET) && (tmp2 == SET)) + if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET)) { hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; /* Clear OVR flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); } + /* Call the Error Callback in case of Error detected -----------------------*/ if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Disable Pos bit in I2C CR1 when error occured in Master/Mem Receive IT Process */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); - - HAL_I2C_ErrorCallback(hi2c); + I2C_ITError(hi2c); } } /** - * @brief Master Tx Transfer completed callback. + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback can be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file */ } /** - * @brief Master Rx Transfer completed callback. + * @brief Slave Address Match callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition + * @param AddrMatchCode Address Match Code * @retval None */ -__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + the HAL_I2C_AddrCallback can be implemented in the user file */ } -/** @brief Slave Tx Transfer completed callback. +/** + * @brief Listen Complete callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback can be implemented in the user file */ } /** - * @brief Slave Rx Transfer completed callback. + * @brief Memory Tx Transfer completed callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ -__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + the HAL_I2C_MemTxCpltCallback can be implemented in the user file */ } /** - * @brief Memory Tx Transfer completed callback. + * @brief Memory Rx Transfer completed callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + the HAL_I2C_MemRxCpltCallback can be implemented in the user file */ } /** - * @brief Memory Rx Transfer completed callback. + * @brief I2C error callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ -__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_TxCpltCallback could be implemented in the user file + the HAL_I2C_ErrorCallback can be implemented in the user file */ } /** - * @brief I2C error callback. + * @brief I2C abort callback. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval None */ - __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) { /* Prevent unused argument(s) compilation warning */ UNUSED(hi2c); + /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ErrorCallback could be implemented in the user file + the HAL_I2C_AbortCpltCallback could be implemented in the user file */ } @@ -2862,13 +3753,12 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) * @} */ - -/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State and Errors functions + * @verbatim =============================================================================== - ##### Peripheral State and Errors functions ##### + ##### Peripheral State, Mode and Error functions ##### =============================================================================== [..] This subsection permits to get in run-time the status of the peripheral @@ -2891,218 +3781,617 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) } /** - * @brief Return the I2C error code. + * @brief Return the I2C Master, Slave, Memory or no mode. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. -* @retval I2C Error Code -*/ -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) { - return hi2c->ErrorCode; + return hi2c->Mode; } /** - * @} + * @brief Return the I2C error code + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code */ +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} /** * @} */ -/** @addtogroup I2C_Private_Functions - * @{ - */ - /** - * @brief Handle TXE flag for Master Transmit Mode + * @brief Handle TXE flag for Master * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) { - if(hi2c->XferCount == 0) + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + uint32_t CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) { - /* Disable BUF interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + /* Call TxCpltCallback() directly if no stop mode is set */ + if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } } - else + else if((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ + ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; + if(hi2c->XferCount == 0U) + { + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + } + else + { + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + if(hi2c->EventCount == 0) + { + /* If Memory address size is 8Bit */ + if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount += 2; + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + } + else if(hi2c->EventCount == 1) + { + /* Send LSB of Memory Address */ + hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); + + hi2c->EventCount++; + } + else if(hi2c->EventCount == 2) + { + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + } + } + else + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + } } - return HAL_OK; } /** - * @brief Handle BTF flag for Master Transmit Mode + * @brief Handle BTF flag for Master transmitter * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) { - if(hi2c->XferCount != 0) - { - /* Write data to DR */ - hi2c->Instance->DR = (*hi2c->pBuffPtr++); - hi2c->XferCount--; + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + if(hi2c->XferCount != 0U) + { + /* Write data to DR */ + hi2c->Instance->DR = (*hi2c->pBuffPtr++); + hi2c->XferCount--; + } + else + { + /* Call TxCpltCallback() directly if no stop mode is set */ + if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + else /* Generate Stop condition then Call TxCpltCallback() */ + { + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MemTxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + HAL_I2C_MasterTxCpltCallback(hi2c); + } + } + } } - else - { - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + return HAL_OK; +} - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); - if(hi2c->Mode == HAL_I2C_MODE_MEM) +/** + * @brief Handle RXNE flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) +{ + + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + uint32_t tmp = 0U; + + tmp = hi2c->XferCount; + if(tmp > 3U) { - hi2c->State = HAL_I2C_STATE_READY; + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + else if((tmp == 2U) || (tmp == 3U)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - HAL_I2C_MemTxCpltCallback(hi2c); + /* Enable Pos */ + hi2c->Instance->CR1 |= I2C_CR1_POS; + + /* Disable BUF interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); } else { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if(hi2c->XferOptions == I2C_NEXT_FRAME) + { + /* Enable Pos */ + hi2c->Instance->CR1 |= I2C_CR1_POS; + } + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); hi2c->State = HAL_I2C_STATE_READY; - HAL_I2C_MasterTxCpltCallback(hi2c); + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MasterRxCpltCallback(hi2c); + } } } return HAL_OK; } /** - * @brief Handle RXNE flag for Master Receive Mode + * @brief Handle BTF flag for Master receiver * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @retval HAL status */ -static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) +static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) { - uint32_t tmp = 0; + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t tmp; + uint32_t CurrentXferOptions = hi2c->XferOptions; - tmp = hi2c->XferCount; - if(tmp > 3) + if(hi2c->XferCount == 3U) { + if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + } + /* Read data from DR */ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; hi2c->XferCount--; } - else if((tmp == 2) || (tmp == 3)) + else if(hi2c->XferCount == 2U) { - /* Disable BUF interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); - } - else - { - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + /* Prepare next transfer or stop current transfer */ + if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + if((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + } + else + { + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; /* Read data from DR */ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; hi2c->XferCount--; + /* Disable EVT and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + if(hi2c->Mode == HAL_I2C_MODE_MEM) { - hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; HAL_I2C_MemRxCpltCallback(hi2c); } else { - hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; HAL_I2C_MasterRxCpltCallback(hi2c); } } + else + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } return HAL_OK; } + /** - * @brief Handle BTF flag for Master Receive Mode + * @brief Handle SB flag for Master * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @retval HAL status */ -static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) +static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c) { - if(hi2c->XferCount == 3) + if(hi2c->Mode == HAL_I2C_MODE_MEM) { - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; + if(hi2c->EventCount == 0U) + { + /* Send slave address */ + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } } - else if(hi2c->XferCount == 2) + else { - /* Disable EVT and ERR interrupt */ - /* Workaround - Wong data read into data register */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); + if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + /* Send slave 7 Bits address */ + if(hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); + } + else + { + hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); + } + } + else + { + if(hi2c->EventCount == 0U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); + } + else if(hi2c->EventCount == 1U) + { + /* Send header of slave address */ + hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); + } + } + } - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + return HAL_OK; +} - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; +/** + * @brief Handle ADD10 flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) +{ + /* Send slave address */ + hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; + return HAL_OK; +} + +/** + * @brief Handle ADDR flag for Master + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentMode = hi2c->Mode; + uint32_t CurrentXferOptions = hi2c->XferOptions; + uint32_t Prev_State = hi2c->PreviousState; - if(hi2c->Mode == HAL_I2C_MODE_MEM) + if(hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) { - hi2c->State = HAL_I2C_STATE_READY; - - HAL_I2C_MemRxCpltCallback(hi2c); + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Restart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + + hi2c->EventCount++; } else { - hi2c->State = HAL_I2C_STATE_READY; + if(hi2c->XferCount == 0U) + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + else if(hi2c->XferCount == 1U) + { + if(CurrentXferOptions == I2C_NO_OPTION_FRAME) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - HAL_I2C_MasterRxCpltCallback(hi2c); + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + } + /* Prepare next transfer or stop current transfer */ + else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ + && (Prev_State != I2C_STATE_MASTER_BUSY_RX)) + { + if(hi2c->XferOptions != I2C_NEXT_FRAME) + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + else + { + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + } + } + else if(hi2c->XferCount == 2U) + { + if(hi2c->XferOptions != I2C_NEXT_FRAME) + { + /* Enable Pos */ + hi2c->Instance->CR1 |= I2C_CR1_POS; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Enable Last DMA bit */ + hi2c->Instance->CR2 |= I2C_CR2_LAST; + } + } + else + { + /* Enable Acknowledge */ + hi2c->Instance->CR1 |= I2C_CR1_ACK; + + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + /* Enable Last DMA bit */ + hi2c->Instance->CR2 |= I2C_CR2_LAST; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + } + + /* Reset Event counter */ + hi2c->EventCount = 0U; } } else { - /* Read data from DR */ - (*hi2c->pBuffPtr++) = hi2c->Instance->DR; - hi2c->XferCount--; + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); } + return HAL_OK; } /** - * @brief Handle TXE flag for Slave Transmit Mode + * @brief Handle TXE flag for Slave * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) { - if(hi2c->XferCount != 0) + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + if(hi2c->XferCount != 0U) { /* Write data to DR */ hi2c->Instance->DR = (*hi2c->pBuffPtr++); hi2c->XferCount--; + + if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the Tx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveTxCpltCallback(hi2c); + } } return HAL_OK; } /** - * @brief Handle BTF flag for Slave Transmit Mode + * @brief Handle BTF flag for Slave transmitter * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) { - if(hi2c->XferCount != 0) + if(hi2c->XferCount != 0U) { /* Write data to DR */ hi2c->Instance->DR = (*hi2c->pBuffPtr++); @@ -3112,31 +4401,47 @@ static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) } /** - * @brief Handle RXNE flag for Slave Receive Mode + * @brief Handle RXNE flag for Slave * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) { - if(hi2c->XferCount != 0) + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + if(hi2c->XferCount != 0U) { /* Read data from DR */ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; hi2c->XferCount--; + + if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Last Byte is received, disable Interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); + + /* Set state at HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + hi2c->State = HAL_I2C_STATE_LISTEN; + + /* Call the Rx complete callback to inform upper layer of the end of receive process */ + HAL_I2C_SlaveRxCpltCallback(hi2c); + } } return HAL_OK; } /** - * @brief Handle BTF flag for Slave Receive Mode + * @brief Handle BTF flag for Slave receiver * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) { - if(hi2c->XferCount != 0) + if(hi2c->XferCount != 0U) { /* Read data from DR */ (*hi2c->pBuffPtr++) = hi2c->Instance->DR; @@ -3148,25 +4453,46 @@ static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) /** * @brief Handle ADD flag for Slave * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c) { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_ADDRFLAG(hi2c); + uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; + uint16_t SlaveAddrCode = 0U; + + /* Transfer Direction requested by Master */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET) + { + TransferDirection = I2C_DIRECTION_TRANSMIT; + } + + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET) + { + SlaveAddrCode = hi2c->Init.OwnAddress1; + } + else + { + SlaveAddrCode = hi2c->Init.OwnAddress2; + } + + /* Call Slave Addr callback */ + HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); return HAL_OK; } /** - * @brief Handle STOPF flag for Slave Mode + * @brief Handle STOPF flag for Slave * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) { + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + /* Disable EVT, BUF and ERR interrupt */ __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); @@ -3174,54 +4500,288 @@ static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) __HAL_I2C_CLEAR_STOPFLAG(hi2c); /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - hi2c->State = HAL_I2C_STATE_READY; + /* If a DMA is ongoing, Update handle size context */ + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + if((hi2c->State == HAL_I2C_STATE_BUSY_RX) || (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx); + } + else + { + hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx); + } + } + + /* All data are not transferred, so set error code accordingly */ + if(hi2c->XferCount != 0U) + { + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + hi2c->XferCount--; + } + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c); + } + else + { + if((CurrentState == HAL_I2C_STATE_LISTEN ) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) || \ + (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - HAL_I2C_SlaveRxCpltCallback(hi2c); + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + else + { + if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_SlaveRxCpltCallback(hi2c); + } + } + } return HAL_OK; } /** - * @brief Handle Acknowledge Failed for Slave Mode * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @retval HAL status */ static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c) { - /* Disable EVT, BUF and ERR interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + uint32_t CurrentXferOptions = hi2c->XferOptions; - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ + (CurrentState == HAL_I2C_STATE_LISTEN)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - hi2c->State = HAL_I2C_STATE_READY; + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } + else if(CurrentState == HAL_I2C_STATE_BUSY_TX) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); - HAL_I2C_SlaveTxCpltCallback(hi2c); + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + HAL_I2C_SlaveTxCpltCallback(hi2c); + } + else + { + /* Clear AF flag only */ + /* State Listen, but XferOptions == FIRST or NEXT */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + return HAL_OK; } /** - * @brief Master sends target device address followed by internal memory address for write request. + * @brief I2C interrupts error process + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + + if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* keep HAL_I2C_STATE_LISTEN */ + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_LISTEN; + } + else + { + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN)) + { + hi2c->State = HAL_I2C_STATE_READY; + } + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + } + + /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ + hi2c->Instance->CR1 &= ~I2C_CR1_POS; + + /* Abort DMA transfer */ + if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) + { + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + if(hi2c->hdmatx->State != HAL_DMA_STATE_READY) + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + /* Set the DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + else if(hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + } + + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); + } + else + { + /* Store Last receive data if any */ + if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from DR */ + (*hi2c->pBuffPtr++) = hi2c->Instance->DR; + } + + /* Call user error callback */ + HAL_I2C_ErrorCallback(hi2c); + } + /* STOP Flag is not set after a NACK reception */ + /* So may inform upper layer that listen phase is stopped */ + /* during NACK error treatment */ + if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)) + { + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + HAL_I2C_ListenCpltCallback(hi2c); + } +} + +/** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout) +static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) { - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + + /* Generate Start condition if first transfer */ + if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -3237,7 +4797,7 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); /* Wait until ADD10 flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK) + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3254,7 +4814,7 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_ } /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3270,23 +4830,37 @@ static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_ } /** - * @brief Master sends target device address followed by internal memory address for read request. + * @brief Master sends target device address for read request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address + * the configuration information for I2C module + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shift at right before call interface * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout) +static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) { + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentXferOptions = hi2c->XferOptions; + /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 |= I2C_CR1_ACK; - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + /* Generate Start condition if first transfer */ + if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) + { + /* Generate Start */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } + else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + { + /* Generate ReStart */ + hi2c->Instance->CR1 |= I2C_CR1_START; + } /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -3302,7 +4876,7 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); /* Wait until ADD10 flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK) + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3318,7 +4892,7 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3334,10 +4908,10 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Generate Restart */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + hi2c->Instance->CR1 |= I2C_CR1_START; /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -3347,7 +4921,7 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t } /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3365,20 +4939,21 @@ static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t /** * @brief Master sends target device address followed by internal memory address for write request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @param DevAddress Target device address * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + hi2c->Instance->CR1 |= I2C_CR1_START; /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -3387,7 +4962,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3403,12 +4978,12 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; return HAL_ERROR; } else @@ -3430,12 +5005,12 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; return HAL_ERROR; } else @@ -3454,23 +5029,24 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ /** * @brief Master sends target device address followed by internal memory address for read request. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. + * the configuration information for I2C module * @param DevAddress Target device address * @param MemAddress Internal memory address * @param MemAddSize Size of internal memory address * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout) +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 |= I2C_CR1_ACK; /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + hi2c->Instance->CR1 |= I2C_CR1_START; /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -3479,7 +5055,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3495,12 +5071,12 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; return HAL_ERROR; } else @@ -3522,12 +5098,12 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; return HAL_ERROR; } else @@ -3541,12 +5117,12 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* Wait until TXE flag is set */ - if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout) != HAL_OK) + if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; return HAL_ERROR; } else @@ -3556,10 +5132,10 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* Generate Restart */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + hi2c->Instance->CR1 |= I2C_CR1_START; /* Wait until SB flag is set */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK) + if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -3568,7 +5144,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); /* Wait until ADDR flag is set */ - if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK) + if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) { if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) { @@ -3584,400 +5160,194 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /** - * @brief DMA I2C master transmit process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Wait until BTF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); - - /* Disable DMA Request */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_MasterTxCpltCallback(hi2c); - } -} - -/** - * @brief DMA I2C slave transmit process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Wait until AF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Disable Address Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Disable DMA Request */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_SlaveTxCpltCallback(hi2c); - } -} - -/** - * @brief DMA I2C master receive process complete callback - * @param hdma: DMA handle + * @brief DMA I2C process complete callback. + * @param hdma DMA handle * @retval None */ -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + + /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ + uint32_t CurrentState = hi2c->State; + uint32_t CurrentMode = hi2c->Mode; - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); - - /* Disable Last DMA */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); - - /* Disable DMA Request */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + if((CurrentState == HAL_I2C_STATE_BUSY_TX) || ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) { - HAL_I2C_ErrorCallback(hi2c); + /* Disable DMA Request */ + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + hi2c->XferCount = 0U; + + /* Enable EVT and ERR interrupt */ + __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); } else { - HAL_I2C_MasterRxCpltCallback(hi2c); - } -} - -/** - * @brief DMA I2C slave receive process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + /* Generate Stop */ + hi2c->Instance->CR1 |= I2C_CR1_STOP; + + /* Disable Last DMA */ + hi2c->Instance->CR2 &= ~I2C_CR2_LAST; + + /* Disable DMA Request */ + hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; + + hi2c->XferCount = 0U; - /* Wait until STOPF flag is reset */ - if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, I2C_TIMEOUT_FLAG) != HAL_OK) - { - if(hi2c->ErrorCode == HAL_I2C_ERROR_AF) + /* Check if Errors has been detected during transfer */ + if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) { - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + HAL_I2C_ErrorCallback(hi2c); } else { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - } - - /* Clear STOPF flag */ - __HAL_I2C_CLEAR_STOPFLAG(hi2c); - - /* Disable Address Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Disable DMA Request */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + hi2c->State = HAL_I2C_STATE_READY; - hi2c->XferCount = 0; + if(hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + HAL_I2C_MemRxCpltCallback(hi2c); + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_SlaveRxCpltCallback(hi2c); + HAL_I2C_MasterRxCpltCallback(hi2c); + } + } } } /** - * @brief DMA I2C Memory Write process complete callback - * @param hdma: DMA handle + * @brief DMA I2C communication error callback. + * @param hdma DMA handle * @retval None */ -static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) +static void I2C_DMAError(DMA_HandleTypeDef *hdma) { I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Wait until BTF flag is reset */ - if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - } - - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); - - /* Disable DMA Request */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - hi2c->XferCount = 0; - + + /* Disable Acknowledge */ + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; + + hi2c->XferCount = 0U; + hi2c->State = HAL_I2C_STATE_READY; hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { + + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + HAL_I2C_ErrorCallback(hi2c); - } - else - { - HAL_I2C_MemTxCpltCallback(hi2c); - } } /** - * @brief DMA I2C Memory Read process complete callback - * @param hdma: DMA handle + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma: DMA handle. * @retval None */ -static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) { - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + hi2c->Instance->CR1 &= ~I2C_CR1_ACK; - /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + hi2c->XferCount = 0U; - /* Disable Last DMA */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); + /* Reset XferAbortCallback */ + hi2c->hdmatx->XferAbortCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; - /* Disable DMA Request */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); - - hi2c->XferCount = 0; + /* Check if come from abort from user */ + if(hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); - /* Check if Errors has been detected during transfer */ - if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - HAL_I2C_ErrorCallback(hi2c); + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_AbortCpltCallback(hi2c); } else { - HAL_I2C_MemRxCpltCallback(hi2c); - } -} + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; -/** - * @brief I2C Configuration Speed function - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param I2CClkSrcFreq: PCLK frequency from RCC. - * @retval CCR Speed: Speed to set in I2C CCR Register - */ -static uint32_t I2C_Configure_Speed(I2C_HandleTypeDef *hi2c, uint32_t I2CClkSrcFreq) -{ - uint32_t tmp1 = 0; - - /* Clock Standard Mode */ - if(hi2c->Init.ClockSpeed <= I2C_STANDARD_MODE_MAX_CLK) - { - /* Calculate Value to be set in CCR register */ - tmp1 = (I2CClkSrcFreq/(hi2c->Init.ClockSpeed << 1)); - - /* The minimum allowed value set in CCR register is 0x04 for Standard Mode */ - if( (tmp1 & I2C_CCR_CCR) < 4 ) - { - return 4; - } - else - { - return tmp1; - } - } - else - { - /* Clock Fast Mode */ - tmp1 = I2C_CCR_FS; - - /* Duty Cylce tLow/tHigh = 2 */ - if(hi2c->Init.DutyCycle == I2C_DUTYCYCLE_2) - { - tmp1 |= (I2CClkSrcFreq/(hi2c->Init.ClockSpeed * 3)) | I2C_DUTYCYCLE_2; - } - else /* Duty Cylce tLow/tHigh = 16/9 */ - { - tmp1 |= (I2CClkSrcFreq/(hi2c->Init.ClockSpeed * 25)) | I2C_DUTYCYCLE_16_9; - } + /* Disable I2C peripheral to prevent dummy data in buffer */ + __HAL_I2C_DISABLE(hi2c); - /* The minimum allowed value set in CCR register is 0x01 for Fast Mode */ - if( (tmp1 & I2C_CCR_CCR) < 1 ) - { - return 1; - } - else - { - return tmp1; - } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + HAL_I2C_ErrorCallback(hi2c); } } -/** - * @brief DMA I2C communication error callback. - * @param hdma: DMA handle - * @retval None - */ -static void I2C_DMAError(DMA_HandleTypeDef *hdma) -{ - I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* Disable Acknowledge */ - CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - hi2c->XferCount = 0; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - HAL_I2C_ErrorCallback(hi2c); -} - /** * @brief This function handles I2C Communication Timeout. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Flag: specifies the I2C flag to check. - * @param Status: The new Flag status (SET or RESET). + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. + * @param Status The new Flag status (SET or RESET). * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait until flag is set */ - if(Status == RESET) - { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_TIMEOUT; - } - } - } - } - else + while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status) { - while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hi2c->State= HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State= HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_TIMEOUT; } } } + return HAL_OK; } /** * @brief This function handles I2C Communication Timeout for Master addressing phase. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Flag: specifies the I2C flag to check. + * the configuration information for I2C module + * @param Flag specifies the I2C flag to check. * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout) +static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) { if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) { /* Generate Stop */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); + hi2c->Instance->CR1 |= I2C_CR1_STOP; /* Clear AF Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->PreviousState = I2C_STATE_NONE; hi2c->State= HAL_I2C_STATE_READY; /* Process Unlocked */ @@ -3989,8 +5359,9 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) { + hi2c->PreviousState = I2C_STATE_NONE; hi2c->State= HAL_I2C_STATE_READY; /* Process Unlocked */ @@ -4008,12 +5379,11 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - +static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) { /* Check if a NACK is detected */ @@ -4025,9 +5395,10 @@ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->PreviousState = I2C_STATE_NONE; hi2c->State= HAL_I2C_STATE_READY; /* Process Unlocked */ @@ -4045,12 +5416,11 @@ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = HAL_GetTick(); - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) { /* Check if a NACK is detected */ @@ -4058,13 +5428,14 @@ static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { return HAL_ERROR; } - + /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->PreviousState = I2C_STATE_NONE; hi2c->State= HAL_I2C_STATE_READY; /* Process Unlocked */ @@ -4074,7 +5445,7 @@ static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, } } } - return HAL_OK; + return HAL_OK; } /** @@ -4082,13 +5453,11 @@ static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = 0x00; - tickstart = HAL_GetTick(); - while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { /* Check if a NACK is detected */ @@ -4096,11 +5465,12 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { return HAL_ERROR; } - + /* Check for the Timeout */ - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->PreviousState = I2C_STATE_NONE; hi2c->State= HAL_I2C_STATE_READY; /* Process Unlocked */ @@ -4117,13 +5487,12 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @param Timeout Timeout duration + * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout) +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) { - uint32_t tickstart = 0x00; - tickstart = HAL_GetTick(); - + while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { /* Check if a STOPF is detected */ @@ -4133,6 +5502,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->PreviousState = I2C_STATE_NONE; hi2c->State= HAL_I2C_STATE_READY; /* Process Unlocked */ @@ -4140,9 +5510,9 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, return HAL_ERROR; } - + /* Check for the Timeout */ - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) > Timeout)) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State= HAL_I2C_STATE_READY; @@ -4170,6 +5540,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); hi2c->ErrorCode = HAL_I2C_ERROR_AF; + hi2c->PreviousState = I2C_STATE_NONE; hi2c->State= HAL_I2C_STATE_READY; /* Process Unlocked */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.h index b5dd622880e..5af2067ef78 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_i2c.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -54,14 +54,13 @@ * @{ */ -/* Exported types ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ /** @defgroup I2C_Exported_Types I2C Exported Types * @{ */ - -/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + +/** * @brief I2C Configuration Structure definition - * @{ */ typedef struct { @@ -91,112 +90,146 @@ typedef struct }I2C_InitTypeDef; -/** - * @} +/** + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : Abort (Abort user request on going) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called) + * b4 (not used) + * x : Should be set to 0 + * b3 + * 0 : Ready or Busy (No Listen mode ongoing) + * 1 : Listen (IP in Address Listen Mode) + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) */ - -/** @defgroup HAL_state_structure_definition HAL state structure definition - * @brief HAL State structure definition - * @{ - */ - typedef enum { - HAL_I2C_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_I2C_STATE_READY = 0x20, /*!< Peripheral Initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x24, /*!< An internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x21, /*!< Data Transmission process is ongoing */ - HAL_I2C_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0 /*!< Error */ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ + HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ }HAL_I2C_StateTypeDef; -/** - * @} - */ - -/** @defgroup HAL_mode_structure_definition HAL mode structure definition +/** * @brief HAL Mode structure definition - * @{ + * @note HAL I2C Mode value coding follow below described bitmap : + * b7 (not used) + * x : Should be set to 0 + * b6 + * 0 : None + * 1 : Memory (HAL I2C communication is in Memory Mode) + * b5 + * 0 : None + * 1 : Slave (HAL I2C communication is in Slave Mode) + * b4 + * 0 : None + * 1 : Master (HAL I2C communication is in Master Mode) + * b3-b2-b1-b0 (not used) + * xxxx : Should be set to 0000 */ typedef enum { - HAL_I2C_MODE_NONE = 0x00, /*!< No I2C communication on going */ - HAL_I2C_MODE_MASTER = 0x10, /*!< I2C communication is in Master Mode */ - HAL_I2C_MODE_SLAVE = 0x20, /*!< I2C communication is in Slave Mode */ - HAL_I2C_MODE_MEM = 0x40 /*!< I2C communication is in Memory Mode */ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ }HAL_I2C_ModeTypeDef; -/** - * @} - */ - -/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition - * @brief I2C handle Structure definition - * @{ +/** + * @brief I2C handle Structure definition */ typedef struct { - I2C_TypeDef *Instance; /*!< I2C registers base address */ - - I2C_InitTypeDef Init; /*!< I2C communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - - uint16_t XferSize; /*!< I2C transfer size */ - - __IO uint16_t XferCount; /*!< I2C transfer counter */ - - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - - HAL_LockTypeDef Lock; /*!< I2C locking object */ - - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - - __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ - - __IO uint32_t ErrorCode; /*!< I2C Error code */ - + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C transfer options */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode + context for internal usage */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + + __IO uint32_t MemaddSize; /*!< I2C Target memory address size */ + + __IO uint32_t EventCount; /*!< I2C Event counter */ + }I2C_HandleTypeDef; + /** * @} */ -/** - * @} - */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup I2C_Exported_Constants I2C Exported Constants * @{ */ -/** @defgroup I2C_Error_Codes I2C Error Codes +/** @defgroup I2C_Error_Code I2C Error Code + * @brief I2C Error Code * @{ */ - -#define HAL_I2C_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_I2C_ERROR_BERR ((uint32_t)0x01) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO ((uint32_t)0x02) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF ((uint32_t)0x04) /*!< AF error */ -#define HAL_I2C_ERROR_OVR ((uint32_t)0x08) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x20) /*!< Timeout error */ - -/** +#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */ +#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */ +#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */ +#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */ +/** * @} */ - - -/** @defgroup I2C_duty_cycle_in_fast_mode I2C Duty Cycle +/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode * @{ */ -#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000) +#define I2C_DUTYCYCLE_2 0x00000000U #define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /** * @} @@ -205,17 +238,17 @@ typedef struct /** @defgroup I2C_addressing_mode I2C addressing mode * @{ */ -#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000) -#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000)) +#define I2C_ADDRESSINGMODE_7BIT 0x00004000U +#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) /** * @} */ -/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode +/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode * @{ */ -#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000) -#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL +#define I2C_DUALADDRESS_DISABLE 0x00000000U +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL /** * @} */ @@ -223,8 +256,8 @@ typedef struct /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode * @{ */ -#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000) -#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC +#define I2C_GENERALCALL_DISABLE 0x00000000U +#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC /** * @} */ @@ -232,8 +265,8 @@ typedef struct /** @defgroup I2C_nostretch_mode I2C nostretch mode * @{ */ -#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000) -#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +#define I2C_NOSTRETCH_DISABLE 0x00000000U +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH /** * @} */ @@ -241,8 +274,28 @@ typedef struct /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size * @{ */ -#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001) -#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010) +#define I2C_MEMADD_SIZE_8BIT 0x00000001U +#define I2C_MEMADD_SIZE_16BIT 0x00000010U +/** + * @} + */ + +/** @defgroup I2C_XferDirection_definition I2C XferDirection definition + * @{ + */ +#define I2C_DIRECTION_RECEIVE 0x00000000U +#define I2C_DIRECTION_TRANSMIT 0x00000001U +/** + * @} + */ + +/** @defgroup I2C_XferOptions_definition I2C XferOptions definition + * @{ + */ +#define I2C_FIRST_FRAME 0x00000001U +#define I2C_NEXT_FRAME 0x00000002U +#define I2C_FIRST_AND_LAST_FRAME 0x00000004U +#define I2C_LAST_FRAME 0x00000008U /** * @} */ @@ -258,199 +311,188 @@ typedef struct */ /** @defgroup I2C_Flag_definition I2C Flag definition - * @brief I2C Interrupt definition - * - 0001XXXX : Flag control mask for SR1 Register - * - 0010XXXX : Flag control mask for SR2 Register * @{ */ -#define I2C_FLAG_SMBALERT ((uint32_t)0x00018000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x00014000) -#define I2C_FLAG_PECERR ((uint32_t)0x00011000) -#define I2C_FLAG_OVR ((uint32_t)0x00010800) -#define I2C_FLAG_AF ((uint32_t)0x00010400) -#define I2C_FLAG_ARLO ((uint32_t)0x00010200) -#define I2C_FLAG_BERR ((uint32_t)0x00010100) -#define I2C_FLAG_TXE ((uint32_t)0x00010080) -#define I2C_FLAG_RXNE ((uint32_t)0x00010040) -#define I2C_FLAG_STOPF ((uint32_t)0x00010010) -#define I2C_FLAG_ADD10 ((uint32_t)0x00010008) -#define I2C_FLAG_BTF ((uint32_t)0x00010004) -#define I2C_FLAG_ADDR ((uint32_t)0x00010002) -#define I2C_FLAG_SB ((uint32_t)0x00010001) -#define I2C_FLAG_DUALF ((uint32_t)0x00100080) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00100040) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00100020) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100010) -#define I2C_FLAG_TRA ((uint32_t)0x00100004) -#define I2C_FLAG_BUSY ((uint32_t)0x00100002) -#define I2C_FLAG_MSL ((uint32_t)0x00100001) -#define I2C_FLAG_MASK ((uint32_t)0x0000FFFF) +#define I2C_FLAG_SMBALERT 0x00018000U +#define I2C_FLAG_TIMEOUT 0x00014000U +#define I2C_FLAG_PECERR 0x00011000U +#define I2C_FLAG_OVR 0x00010800U +#define I2C_FLAG_AF 0x00010400U +#define I2C_FLAG_ARLO 0x00010200U +#define I2C_FLAG_BERR 0x00010100U +#define I2C_FLAG_TXE 0x00010080U +#define I2C_FLAG_RXNE 0x00010040U +#define I2C_FLAG_STOPF 0x00010010U +#define I2C_FLAG_ADD10 0x00010008U +#define I2C_FLAG_BTF 0x00010004U +#define I2C_FLAG_ADDR 0x00010002U +#define I2C_FLAG_SB 0x00010001U +#define I2C_FLAG_DUALF 0x00100080U +#define I2C_FLAG_SMBHOST 0x00100040U +#define I2C_FLAG_SMBDEFAULT 0x00100020U +#define I2C_FLAG_GENCALL 0x00100010U +#define I2C_FLAG_TRA 0x00100004U +#define I2C_FLAG_BUSY 0x00100002U +#define I2C_FLAG_MSL 0x00100001U /** * @} */ /** * @} - */ - -/* Exported macros -----------------------------------------------------------*/ + */ +/* Exported macro ------------------------------------------------------------*/ /** @defgroup I2C_Exported_Macros I2C Exported Macros * @{ */ -/** @brief Reset I2C handle state. - * @param __HANDLE__ specifies the I2C Handle. +/** @brief Reset I2C handle state + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. * @retval None */ #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -/** @brief Enable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_BUF Buffer interrupt enable - * @arg @ref I2C_IT_EVT Event interrupt enable - * @arg @ref I2C_IT_ERR Error interrupt enable - * @retval None - */ -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))) - -/** @brief Disable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__: specifies the interrupt source to disable. +/** @brief Enable or disable the specified I2C interrupts. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. * This parameter can be one of the following values: - * @arg @ref I2C_IT_BUF Buffer interrupt enable - * @arg @ref I2C_IT_EVT Event interrupt enable - * @arg @ref I2C_IT_ERR Error interrupt enable + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable * @retval None */ -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))) +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) -/** @brief Check whether the specified I2C interrupt source is enabled or not. - * @param __HANDLE__ specifies the I2C Handle. +/** @brief Checks if the specified I2C interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. * @param __INTERRUPT__: specifies the I2C interrupt source to check. * This parameter can be one of the following values: - * @arg @ref I2C_IT_BUF Buffer interrupt enable - * @arg @ref I2C_IT_EVT Event interrupt enable - * @arg @ref I2C_IT_ERR Error interrupt enable + * @arg I2C_IT_BUF: Buffer interrupt enable + * @arg I2C_IT_EVT: Event interrupt enable + * @arg I2C_IT_ERR: Error interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) -/** @brief Check whether the specified I2C flag is set or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to check. +/** @brief Checks whether the specified I2C flag is set or not. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg @ref I2C_FLAG_SMBALERT SMBus Alert flag - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow error flag - * @arg @ref I2C_FLAG_PECERR PEC error in reception flag - * @arg @ref I2C_FLAG_OVR Overrun/Underrun flag - * @arg @ref I2C_FLAG_AF Acknowledge failure flag - * @arg @ref I2C_FLAG_ARLO Arbitration lost flag - * @arg @ref I2C_FLAG_BERR Bus error flag - * @arg @ref I2C_FLAG_TXE Data register empty flag - * @arg @ref I2C_FLAG_RXNE Data register not empty flag - * @arg @ref I2C_FLAG_STOPF Stop detection flag - * @arg @ref I2C_FLAG_ADD10 10-bit header sent flag - * @arg @ref I2C_FLAG_BTF Byte transfer finished flag - * @arg @ref I2C_FLAG_ADDR Address sent flag - * Address matched flag - * @arg @ref I2C_FLAG_SB Start bit flag - * @arg @ref I2C_FLAG_DUALF Dual flag - * @arg @ref I2C_FLAG_SMBHOST SMBus host header - * @arg @ref I2C_FLAG_SMBDEFAULT SMBus default header - * @arg @ref I2C_FLAG_GENCALL General call header flag - * @arg @ref I2C_FLAG_TRA Transmitter/Receiver flag - * @arg @ref I2C_FLAG_BUSY Bus busy flag - * @arg @ref I2C_FLAG_MSL Master/Slave flag + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag + * @arg I2C_FLAG_RXNE: Data register not empty flag + * @arg I2C_FLAG_STOPF: Stop detection flag + * @arg I2C_FLAG_ADD10: 10-bit header sent flag + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag + * Address matched flag + * @arg I2C_FLAG_SB: Start bit flag + * @arg I2C_FLAG_DUALF: Dual flag + * @arg I2C_FLAG_SMBHOST: SMBus host header + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header + * @arg I2C_FLAG_GENCALL: General call header flag + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \ ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) -/** @brief Clear the I2C pending flags which are cleared by writing 0 in a specific bit. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to clear. +/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. + * @param __FLAG__: specifies the flag to clear. * This parameter can be any combination of the following values: - * @arg @ref I2C_FLAG_SMBALERT SMBus Alert flag - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow error flag - * @arg @ref I2C_FLAG_PECERR PEC error in reception flag - * @arg @ref I2C_FLAG_OVR Overrun/Underrun flag (Slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure flag - * @arg @ref I2C_FLAG_ARLO Arbitration lost flag (Master mode) - * @arg @ref I2C_FLAG_BERR Bus error flag - * + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag * @retval None */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HANDLE__)->Instance->SR1 = (((__HANDLE__)->Instance->SR1) & (~((__FLAG__) & I2C_FLAG_MASK))) +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK)) /** @brief Clears the I2C ADDR pending flag. * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. * @retval None */ -#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR1; \ - tmpreg = (__HANDLE__)->Instance->SR2; \ - UNUSED(tmpreg); \ -}while(0) +#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + tmpreg = (__HANDLE__)->Instance->SR2; \ + UNUSED(tmpreg); \ + } while(0) /** @brief Clears the I2C STOPF pending flag. * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral. * @retval None */ -#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ -do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR1; \ - tmpreg = (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \ - UNUSED(tmpreg); \ -}while(0) - -/** @brief Enable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. +#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR1; \ + (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Enable the I2C peripheral. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. * @retval None */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) -/** @brief Disable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. +/** @brief Disable the I2C peripheral. + * @param __HANDLE__: specifies the I2C Handle. + * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral. * @retval None */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) +#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup I2C_Exported_Functions * @{ */ -/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions +/** @addtogroup I2C_Exported_Functions_Group1 * @{ */ - -/* Initialization/de-initialization functions ********************************/ +/* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); - /** * @} - */ + */ -/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions +/** @addtogroup I2C_Exported_Functions_Group2 * @{ */ - -/* IO operation functions ****************************************************/ - - /******* Blocking mode: Polling */ +/* I/O operation functions *****************************************************/ +/******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); @@ -458,29 +500,31 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); - - /******* Non-Blocking mode: Interrupt */ + +/******* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - - /******* Non-Blocking mode: DMA */ + +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); + +/******* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -/** - * @} - */ -/** @addtogroup I2C_Exported_Functions_Group4 IRQ Handler and Callbacks - * @{ - */ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); @@ -488,22 +532,23 @@ void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); - +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); /** * @} - */ + */ - -/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions +/** @addtogroup I2C_Exported_Functions_Group3 * @{ */ - -/* Peripheral State and Errors functions *************************************/ +/* Peripheral State, Mode and Errors functions *********************************/ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} @@ -511,85 +556,88 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); /** * @} - */ - + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2C_Private_Constants I2C Private Constants * @{ */ -#define I2C_STANDARD_MODE_MAX_CLK ((uint32_t)100000) /* Standard Clock Up to 100kHz */ -#define I2C_FAST_MODE_MAX_CLK ((uint32_t)400000) /* Fast Clock up to 400kHz */ +#define I2C_FLAG_MASK 0x0000FFFFU /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Macro I2C Private Macros +/** @defgroup I2C_Private_Macros I2C Private Macros + * @{ + */ + +#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) +#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) +#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) +#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3U)) : (((__PCLK__) / ((__SPEED__) * 25U)) | I2C_DUTYCYCLE_16_9)) +#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \ + ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) + +#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) +#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) + +#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) +#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U)))) +#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U)))) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters * @{ */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ + ((CYCLE) == I2C_DUTYCYCLE_16_9)) #define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \ ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT)) - #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) - #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ ((CALL) == I2C_GENERALCALL_ENABLE)) - -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) - #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ ((STRETCH) == I2C_NOSTRETCH_ENABLE)) +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U)) +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U) +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME)) +/** + * @} + */ -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0) - -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0) - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= I2C_FAST_MODE_MAX_CLK)) - -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \ - ((CYCLE) == I2C_DUTYCYCLE_16_9)) - -#define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__)/1000000) -#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= I2C_STANDARD_MODE_MAX_CLK) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1)) - -#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1))) -#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9)) -#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \ - ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \ - ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS)) - -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) - -#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) -#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) - -#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) -#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) -#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) /** * @} - */ + */ -/* Private Fonctions ---------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ /** @defgroup I2C_Private_Functions I2C Private Functions * @{ */ -/* Private functions are defined in stm32f1xx_hal_i2c.c file */ + /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ - + */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c index a73c80a3c88..2246e5e70bc 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_i2s.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.h index 00d7f5bc0dc..8b65569c1b5 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_i2s.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.c index cd45fa543cd..4773f0d51cd 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_irda.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA SIR ENDEC block (IrDA): diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.h index 326e8395053..a339d2f97a7 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_irda.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c index 23e0791a1d5..1919221a66e 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_iwdg.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.h index bfd0eda311b..4a8c682609b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_iwdg.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.c index dcd2f810f26..1896069e27b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_nand.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device. diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.h index 461ab95c8c1..0e37fb1fcfb 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_nand.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.c index 256db3b89c1..a6d9ad74ee2 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_nor.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.h index 8b54ca4aec4..fc0b0ffea6e 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_nor.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.c index 2e263f74112..558a9b0a850 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pccard.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief PCCARD HAL module driver. * This file provides a generic firmware to drive PCCARD memories mounted * as external device. diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.h index 80728f7ad4e..38a916f3cc7 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pccard.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of PCCARD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.c index 91461a39724..fe6211b1d5c 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pcd.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.h index 9489bd34b0b..87f186eafdb 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pcd.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.c index b34328a9488..b26902f2b5d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Extended PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.h index 5e13c7383d9..54d52ddada5 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of Extended PCD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.c index e178e42e243..71ab9a39955 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pwr.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief PWR HAL module driver. * * This file provides firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.h index b5f78ca7bd9..db20f8b95f5 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pwr.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.c index a8626950c16..868908a35f2 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rcc.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.h index b8930748ad3..f91c2737827 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rcc.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.c index c0cc7d15e65..d2c21ba1ee2 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.h index 4d38a3a6466..fbd5772b699 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.c index f513eb3ea03..331d428e995 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rtc.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.h index 23f5376b36a..b81c1f16117 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rtc.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.c index ce5cbc5df82..8d90e937d6b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extension peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.h index 99b0bbfdec6..25d18442595 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of RTC HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.c index 33c848a13b3..f5443003a55 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_sd.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.h index 28a3eabfa16..a57a7a384b5 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_sd.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of SD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c index 955b84cd76c..d25afce9c43 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_smartcard.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.h index d9ec888b9f1..d139575ddcd 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_smartcard.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.c index 283ee5f1aa5..6e8607150a1 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_spi.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief SPI HAL module driver. * * This file provides firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.h index aefd6f5635b..1bc59de0b60 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_spi.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi_ex.c index 69abcf30069..7659fc4c87b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_spi_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Extended SPI HAL module driver. * * This file provides firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.c index 48e79c820af..c94bf7a41ed 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_sram.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.h index 2c46ca859ad..ba2891aa6ec 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_sram.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.c index 938c948fca5..e47d6797ba5 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_tim.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief TIM HAL module driver * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.h index 70e27ef551f..91d0a07aa81 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_tim.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.c index 416dad82e19..1a0daa6696f 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.h index e26cedc8147..29380e8f6a8 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.c index 0146640b58f..b437ce83934 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_uart.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.h index 5f9a99d561c..03c2d80b532 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_uart.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of UART HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.c index ea7fda82034..5ecfcf102a3 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_usart.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief USART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.h index 18b5deed171..6ba4f6a86f9 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_usart.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of USART HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.c index 29a78a29c29..128f16f2bc7 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_wwdg.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.h index 4b2e6e93028..e4fb044b22a 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_wwdg.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_bus.h new file mode 100644 index 00000000000..d715aa491af --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_bus.h @@ -0,0 +1,1033 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_bus.h + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_BUS_H +#define __STM32F1xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +#if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST) +#define RCC_AHBRSTR_SUPPORT +#endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN +#if defined(DMA2) +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN +#endif /*DMA2*/ +#if defined(ETH) +#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN +#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN +#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN +#endif /*ETH*/ +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN +#if defined(FSMC_Bank1) +#define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN +#endif /*FSMC_Bank1*/ +#if defined(USB_OTG_FS) +#define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN +#endif /*USB_OTG_FS*/ +#if defined(SDIO) +#define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN +#endif /*SDIO*/ +#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN +#if defined(CAN1) +#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN +#endif /*CAN1*/ +#if defined(CAN2) +#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN +#endif /*CAN2*/ +#if defined(CEC) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN +#endif /*CEC*/ +#if defined(DAC) +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN +#endif /*DAC*/ +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN +#if defined(I2C2) +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN +#endif /*I2C2*/ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN +#endif /*SPI2*/ +#if defined(SPI3) +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN +#endif /*SPI3*/ +#if defined(TIM12) +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN +#endif /*TIM12*/ +#if defined(TIM13) +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN +#endif /*TIM13*/ +#if defined(TIM14) +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN +#endif /*TIM14*/ +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN +#if defined(TIM4) +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN +#endif /*TIM4*/ +#if defined(TIM5) +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN +#endif /*TIM5*/ +#if defined(TIM6) +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN +#endif /*TIM6*/ +#if defined(TIM7) +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN +#endif /*TIM7*/ +#if defined(UART4) +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN +#endif /*UART4*/ +#if defined(UART5) +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN +#endif /*UART5*/ +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN +#if defined(USART3) +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN +#endif /*USART3*/ +#if defined(USB) +#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN +#endif /*USB*/ +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN +#if defined(ADC2) +#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN +#endif /*ADC2*/ +#if defined(ADC3) +#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN +#endif /*ADC3*/ +#define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN +#define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN +#define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN +#define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN +#define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN +#if defined(GPIOE) +#define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN +#endif /*GPIOE*/ +#if defined(GPIOF) +#define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN +#endif /*GPIOF*/ +#if defined(GPIOG) +#define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN +#endif /*GPIOG*/ +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#if defined(TIM10) +#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN +#endif /*TIM10*/ +#if defined(TIM11) +#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN +#endif /*TIM11*/ +#if defined(TIM15) +#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN +#endif /*TIM15*/ +#if defined(TIM16) +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#endif /*TIM16*/ +#if defined(TIM17) +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#endif /*TIM17*/ +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#if defined(TIM8) +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#endif /*TIM8*/ +#if defined(TIM9) +#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN +#endif /*TIM9*/ +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n + * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n + * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n + * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBENR, Periphs); +} + +#if defined(RCC_AHBRSTR_SUPPORT) +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBRSTR, Periphs); +} +#endif /* RCC_AHBRSTR_SUPPORT */ + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n + * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_BKP + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_BKP + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n + * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_BKP + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_BKP + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_BKP + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n + * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n + * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_AFIO + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_AFIO + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n + * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n + * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_AFIO + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_AFIO + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_AFIO + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) + * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_BUS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_cortex.h new file mode 100644 index 00000000000..c682cb74894 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_cortex.h @@ -0,0 +1,658 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_cortex.h + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (MPU services provided only on some devices) + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_CORTEX_H +#define __STM32F1xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U) /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U) /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U) /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U) /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U) /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U) /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U) /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U) /*!< REGION Number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */ +#define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U) /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U) /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Constant number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @retval Value should be equal to 0xF for Cortex-M3 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC23 for Cortex-M3 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_CORTEX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.c new file mode 100644 index 00000000000..de4e3c24a6e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.c @@ -0,0 +1,126 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_crc.c + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief CRC LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_crc.h" +#include "stm32f1xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (CRC) + +/** @addtogroup CRC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup CRC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize CRC registers (Registers restored to their default values). + * @param CRCx CRC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: CRC registers are de-initialized + * - ERROR: CRC registers are not de-initialized + */ +ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(CRCx)); + + if (CRCx == CRC) + { + + /* Reset the CRC calculation unit */ + LL_CRC_ResetCRCCalculationUnit(CRCx); + + /* Reset IDR register */ + LL_CRC_Write_IDR(CRCx, 0x00U); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (CRC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.h new file mode 100644 index 00000000000..8155b0d1f84 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.h @@ -0,0 +1,212 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_crc.h + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief Header file of CRC LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_CRC_H +#define __STM32F1xx_LL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(CRC) + +/** @defgroup CRC_LL CRC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions + * @{ + */ + +/** + * @brief Reset the CRC calculation unit. + * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit + * @param CRCx CRC Instance + * @retval None + */ +__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx) +{ + WRITE_REG(CRCx->CR, CRC_CR_RESET); +} + +/** + * @} + */ + +/** @defgroup CRC_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Write given 32-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData32 + * @param CRCx CRC Instance + * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) +{ + WRITE_REG(CRCx->DR, InData); +} + +/** + * @brief Return current CRC calculation result. 32 bits value is returned. + * @rmtoll DR DR LL_CRC_ReadData32 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). + */ +__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->DR)); +} + +/** + * @brief Return data stored in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one byte. + * @rmtoll IDR IDR LL_CRC_Read_IDR + * @param CRCx CRC Instance + * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register). + */ +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->IDR)); +} + +/** + * @brief Store data in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one byte. + * @rmtoll IDR IDR LL_CRC_Write_IDR + * @param CRCx CRC Instance + * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) +{ + *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_CRC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.c new file mode 100644 index 00000000000..2715899a428 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.c @@ -0,0 +1,232 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_exti.c + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief EXTI LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_exti.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Private_Macros + * @{ + */ + +#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) + +#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + + +#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the EXTI registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are de-initialized + * - ERROR: not applicable + */ +uint32_t LL_EXTI_DeInit(void) +{ + /* Interrupt mask register set to default reset values */ + LL_EXTI_WriteReg(IMR, 0x00000000U); + /* Event mask register set to default reset values */ + LL_EXTI_WriteReg(EMR, 0x00000000U); + /* Rising Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(RTSR, 0x00000000U); + /* Falling Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(FTSR, 0x00000000U); + /* Software interrupt event register set to default reset values */ + LL_EXTI_WriteReg(SWIER, 0x00000000U); + /* Pending register set to default reset values */ + LL_EXTI_WriteReg(PR, 0x000FFFFFU); + + return SUCCESS; +} + +/** + * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are initialized + * - ERROR: not applicable + */ +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + ErrorStatus status = SUCCESS; + /* Check the parameters */ + assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + + /* ENABLE LineCommand */ + if (EXTI_InitStruct->LineCommand != DISABLE) + { + assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + + /* Configure EXTI Lines in range from 0 to 31 */ + if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT & Event on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + } + } + } + /* DISABLE LineCommand */ + else + { + /* De-configure EXTI Lines in range from 0 to 31 */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + } + return status; +} + +/** + * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval None + */ +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->LineCommand = DISABLE; + EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EXTI) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.h new file mode 100644 index 00000000000..5146fc04c82 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.h @@ -0,0 +1,906 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_exti.h + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_EXTI_H +#define __STM32F1xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#if defined(EXTI_IMR_IM19) +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#endif +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#if defined(EXTI_IMR_IM23) +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#endif +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.c index 221d55cc0f4..16da9a93273 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_fsmc.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief FSMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.h index 7632d8e48cf..d3c77504d8e 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_fsmc.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of FSMC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.c new file mode 100644 index 00000000000..ee061717120 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.c @@ -0,0 +1,265 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_gpio.c + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief GPIO LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_gpio.h" +#include "stm32f1xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) + +/** @addtogroup GPIO_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Private_Macros + * @{ + */ +#define IS_LL_GPIO_PIN(__VALUE__) ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) + +#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_ANALOG) ||\ + ((__VALUE__) == LL_GPIO_MODE_FLOATING) ||\ + ((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_ALTERNATE)) + +#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)) + +#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_DOWN) ||\ + ((__VALUE__) == LL_GPIO_PULL_UP)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize GPIO registers (Registers restored to their default values). + * @param GPIOx GPIO Port + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: Wrong GPIO Port + */ +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force and Release reset on clock of GPIOx Port */ + if (GPIOx == GPIOA) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOA); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOA); + } + else if (GPIOx == GPIOB) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOB); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOB); + } + else if (GPIOx == GPIOC) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOC); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOC); + } + else if (GPIOx == GPIOD) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOD); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOD); + } +#if defined(GPIOE) + else if (GPIOx == GPIOE) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOE); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOE); + } +#endif +#if defined(GPIOF) + else if (GPIOx == GPIOF) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOF); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOF); + } +#endif +#if defined(GPIOG) + else if (GPIOx == GPIOG) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOG); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOG); + } +#endif + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + * @param GPIOx GPIO Port + * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * that contains the configuration information for the specified GPIO peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t pinpos = 0x00000000U; + uint32_t currentpin = 0x00000000U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + + /* ------------------------- Configure the port pins ---------------- */ + /* Initialize pinpos on first pin set */ + pinpos = POSITION_VAL(GPIO_InitStruct->Pin); + + /* Configure the port pins */ + while ((((GPIO_InitStruct->Pin) & 0x0000FFFFU) >> pinpos) != 0x00000000U) + { + /* Get current io position */ + if(pinpos <8 ) + { + currentpin = (GPIO_InitStruct->Pin) & (0x00000101U << pinpos); + } + else + { + currentpin = (GPIO_InitStruct->Pin) & ((0x00010001U << (pinpos-8)) | 0x04000000U); + } + + if (currentpin) + { + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + + /* Pull-up Pull down resistor configuration*/ + LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_FLOATING)) + { + /* Speed mode configuration */ + LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + } + } + pinpos++; + } + + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_FLOATING)) + { + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + } + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + GPIO_InitStruct->Mode = LL_GPIO_MODE_FLOATING; + GPIO_InitStruct->Speed = 0x00000000U; + GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_OPENDRAIN; + GPIO_InitStruct->Pull = LL_GPIO_PULL_DOWN; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.h new file mode 100644 index 00000000000..91af0dac53c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.h @@ -0,0 +1,2091 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_gpio.h + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_GPIO_H +#define __STM32F1xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_LL_Private_Constants GPIO Private Constants + * @{ + */ +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ +}LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 (GPIO_BSRR_BS0 << 8) | 0x00000001U /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 (GPIO_BSRR_BS1 << 8) | 0x00000002U /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 (GPIO_BSRR_BS2 << 8) | 0x00000004U /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 (GPIO_BSRR_BS3 << 8) | 0x00000008U /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 (GPIO_BSRR_BS4 << 8) | 0x00000010U /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 (GPIO_BSRR_BS5 << 8) | 0x00000020U /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 (GPIO_BSRR_BS6 << 8) | 0x00000040U /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 (GPIO_BSRR_BS7 << 8) | 0x00000080U /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 (GPIO_BSRR_BS8 << 8) | 0x04000001U /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 (GPIO_BSRR_BS9 << 8) | 0x04000002U /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 (GPIO_BSRR_BS10 << 8) | 0x04000004U /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 (GPIO_BSRR_BS11 << 8) | 0x04000008U /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 (GPIO_BSRR_BS12 << 8) | 0x04000010U /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 (GPIO_BSRR_BS13 << 8) | 0x04000020U /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 (GPIO_BSRR_BS14 << 8) | 0x04000040U /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 (GPIO_BSRR_BS15 << 8) | 0x04000080U /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \ + LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \ + LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \ + LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \ + LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \ + LL_GPIO_PIN_15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */ +#define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */ +#define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */ +#define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */ +#define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */ +#define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */ +/** + * @} + */ + +#define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */ + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */ +#define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */ + +/** + * @} + */ + +/** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin + * @{ + */ + +#define LL_GPIO_AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ +#define LL_GPIO_AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ + +/** + * @} + */ + +/** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port + * @{ + */ + +#define LL_GPIO_AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ +#define LL_GPIO_AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ +#define LL_GPIO_AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ +#define LL_GPIO_AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ +#define LL_GPIO_AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ + +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT + * @{ + */ +#define LL_GPIO_AFIO_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */ +#define LL_GPIO_AFIO_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */ +#define LL_GPIO_AFIO_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */ +#define LL_GPIO_AFIO_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */ +#define LL_GPIO_AFIO_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */ +#define LL_GPIO_AFIO_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */ +#define LL_GPIO_AFIO_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE + * @{ + */ +#define LL_GPIO_AFIO_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_GPIO_AFIO_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_GPIO_AFIO_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_GPIO_AFIO_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_GPIO_AFIO_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_GPIO_AFIO_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_GPIO_AFIO_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_GPIO_AFIO_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_GPIO_AFIO_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_GPIO_AFIO_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_GPIO_AFIO_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_GPIO_AFIO_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_GPIO_AFIO_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_GPIO_AFIO_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_GPIO_AFIO_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_GPIO_AFIO_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, + * Alternate function Output. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll CRL CNFy LL_GPIO_SetPinMode + * @rmtoll CRL MODEy LL_GPIO_SetPinMode + * @rmtoll CRH CNFy LL_GPIO_SetPinMode + * @rmtoll CRH MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_ANALOG + * @arg @ref LL_GPIO_MODE_FLOATING + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24))); + MODIFY_REG(*pReg, ((GPIO_CRL_CNF0|GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, + * Alternate function Output. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll CRL CNFy LL_GPIO_GetPinMode + * @rmtoll CRL MODEy LL_GPIO_GetPinMode + * @rmtoll CRH CNFy LL_GPIO_GetPinMode + * @rmtoll CRH MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_ANALOG + * @arg @ref LL_GPIO_MODE_FLOATING + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24))); + return (uint32_t)(READ_BIT(*pReg, + ((GPIO_CRL_CNF0|GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium or Fast speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed + * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24))); + MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)), + (Speed << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed + * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24))); + return (uint32_t)(READ_BIT(*pReg, + (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType + * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType) +{ + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24))); + MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)), + (OutputType << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType + * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin>>24))); + return (uint32_t)(READ_BIT(*pReg, + (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); + +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll ODR ODR LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_DOWN + * @arg @ref LL_GPIO_PULL_UP + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->ODR, (Pin>>8) , Pull << (POSITION_VAL(Pin>>8))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll ODR ODR LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_DOWN + * @arg @ref LL_GPIO_PULL_UP + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->ODR, + (GPIO_ODR_ODR0 << (POSITION_VAL(Pin>>8)))) >> (POSITION_VAL(Pin>>8))); +} + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> 8) & 0x0000FFFFU)); + WRITE_REG(GPIOx->LCKR, ((PinMask >>8 ) & 0x0000FFFFU)); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask>>8) & 0x0000FFFFU)); + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCKR, ((PinMask >> 8 ) & 0x0000FFFFU)) == ((PinMask >>8 ) & 0x0000FFFFU)); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->IDR, (PinMask >> 8 ) & 0x0000FFFFU) == ((PinMask >> 8 ) & 0x0000FFFFU)); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->ODR, (PinMask >> 8 ) & 0x0000FFFFU) == ((PinMask >> 8 ) & 0x0000FFFFU)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, (PinMask >> 8) & 0x0000FFFFU); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, (PinMask >> 8 ) & 0x0000FFFFU); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> 8 ) & 0x0000FFFFU)); +} + +/** + * @} + */ + +/** @defgroup GPIO_AFIO_AF_REMAPPING Alternate Function Remapping + * @brief This section propose definition to remap the alternate function to some other port/pins. + * @{ + */ + +/** + * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. + * @rmtoll MAPR SPI1_REMAP LL_GPIO_AFIO_REMAP_SPI1_ENABLE + * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SPI1_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP); +} + +/** + * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. + * @rmtoll MAPR SPI1_REMAP LL_GPIO_AFIO_REMAP_SPI1_DISABLE + * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SPI1_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP); +} + +/** + * @brief Enable the remapping of I2C1 alternate function SCL and SDA. + * @rmtoll MAPR I2C1_REMAP LL_GPIO_AFIO_REMAP_I2C1_ENABLE + * @note ENABLE: Remap (SCL/PB8, SDA/PB9) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_I2C1_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP); +} + +/** + * @brief Disable the remapping of I2C1 alternate function SCL and SDA. + * @rmtoll MAPR I2C1_REMAP LL_GPIO_AFIO_REMAP_I2C1_DISABLE + * @note DISABLE: No remap (SCL/PB6, SDA/PB7) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_I2C1_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP); +} + +/** + * @brief Enable the remapping of USART1 alternate function TX and RX. + * @rmtoll MAPR USART1_REMAP LL_GPIO_AFIO_REMAP_USART1_ENABLE + * @note ENABLE: Remap (TX/PB6, RX/PB7) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART1_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP); +} + +/** + * @brief Disable the remapping of USART1 alternate function TX and RX. + * @rmtoll MAPR USART1_REMAP LL_GPIO_AFIO_REMAP_USART1_DISABLE + * @note DISABLE: No remap (TX/PA9, RX/PA10) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART1_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP); +} + +/** + * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. + * @rmtoll MAPR USART2_REMAP LL_GPIO_AFIO_REMAP_USART2_ENABLE + * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART2_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP); +} + +/** + * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. + * @rmtoll MAPR USART2_REMAP LL_GPIO_AFIO_REMAP_USART2_DISABLE + * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART2_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP); +} + +#if defined (AFIO_MAPR_USART3_REMAP) +/** + * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. + * @rmtoll MAPR USART3_REMAP LL_GPIO_AFIO_REMAP_USART3_ENABLE + * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART3_ENABLE(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP); +} + +/** + * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. + * @rmtoll MAPR USART3_REMAP LL_GPIO_AFIO_REMAP_USART3_PARTIAL + * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART3_PARTIAL(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_PARTIALREMAP); +} + +/** + * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. + * @rmtoll MAPR USART3_REMAP LL_GPIO_AFIO_REMAP_USART3_DISABLE + * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART3_DISABLE(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_NOREMAP); +} +#endif + +/** + * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) + * @rmtoll MAPR TIM1_REMAP LL_GPIO_AFIO_REMAP_TIM1_ENABLE + * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM1_ENABLE(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP); +} + +/** + * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) + * @rmtoll MAPR TIM1_REMAP LL_GPIO_AFIO_REMAP_TIM1_PARTIAL + * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM1_PARTIAL(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP); +} + +/** + * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) + * @rmtoll MAPR TIM1_REMAP LL_GPIO_AFIO_REMAP_TIM1_DISABLE + * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM1_DISABLE(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_NOREMAP); +} + +/** + * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) + * @rmtoll MAPR TIM2_REMAP LL_GPIO_AFIO_REMAP_TIM2_ENABLE + * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM2_ENABLE(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP); +} + +/** + * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) + * @rmtoll MAPR TIM2_REMAP LL_GPIO_AFIO_REMAP_TIM2_PARTIAL_2 + * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM2_PARTIAL_2(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2); +} + +/** + * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) + * @rmtoll MAPR TIM2_REMAP LL_GPIO_AFIO_REMAP_TIM2_PARTIAL_1 + * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM2_PARTIAL_1(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1); +} + +/** + * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) + * @rmtoll MAPR TIM2_REMAP LL_GPIO_AFIO_REMAP_TIM2_PARTIAL_1 + * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM2_DISABLE(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_NOREMAP); +} + +/** + * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 + * @rmtoll MAPR TIM3_REMAP LL_GPIO_AFIO_REMAP_TIM3_ENABLE + * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) + * @note TIM3_ETR on PE0 is not re-mapped. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM3_ENABLE(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP); +} + +/** + * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 + * @rmtoll MAPR TIM3_REMAP LL_GPIO_AFIO_REMAP_TIM3_PARTIAL + * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) + * @note TIM3_ETR on PE0 is not re-mapped. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM3_PARTIAL(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP); +} + +/** + * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 + * @rmtoll MAPR TIM3_REMAP LL_GPIO_AFIO_REMAP_TIM3_DISABLE + * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) + * @note TIM3_ETR on PE0 is not re-mapped. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM3_DISABLE(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_NOREMAP); +} + +#if defined(AFIO_MAPR_TIM4_REMAP) +/** + * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. + * @rmtoll MAPR TIM4_REMAP LL_GPIO_AFIO_REMAP_TIM4_ENABLE + * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) + * @note TIM4_ETR on PE0 is not re-mapped. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM4_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP); +} +/** + * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. + * @rmtoll MAPR TIM4_REMAP LL_GPIO_AFIO_REMAP_TIM4_DISABLE + * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) + * @note TIM4_ETR on PE0 is not re-mapped. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM4_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP); +} +#endif + +#if defined(AFIO_MAPR_CAN_REMAP_REMAP1) + +/** + * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. + * @rmtoll MAPR CAN_REMAP LL_GPIO_AFIO_REMAP_CAN1_1 + * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CAN1_1(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP1); +} + +/** + * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. + * @rmtoll MAPR CAN_REMAP LL_GPIO_AFIO_REMAP_CAN1_2 + * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CAN1_2(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP2); +} + +/** + * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. + * @rmtoll MAPR CAN_REMAP LL_GPIO_AFIO_REMAP_CAN1_3 + * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CAN1_3(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP3); +} +#endif + +/** + * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used + * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and + * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available + * on 100-pin and 144-pin packages, no need for remapping). + * @rmtoll MAPR PD01_REMAP LL_GPIO_AFIO_REMAP_PD01_ENABLE + * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_PD01_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP); +} + +/** + * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used + * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and + * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available + * on 100-pin and 144-pin packages, no need for remapping). + * @rmtoll MAPR PD01_REMAP LL_GPIO_AFIO_REMAP_PD01_DISABLE + * @note DISABLE: No remapping of PD0 and PD1 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_PD01_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP); +} + +#if defined(AFIO_MAPR_TIM5CH4_IREMAP) +/** + * @brief Enable the remapping of TIM5CH4. + * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AFIO_REMAP_TIM5CH4_ENABLE + * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. + * @note This function is available only in high density value line devices. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM5CH4_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP); +} + +/** + * @brief Disable the remapping of TIM5CH4. + * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AFIO_REMAP_TIM5CH4_DISABLE + * @note DISABLE: TIM5_CH4 is connected to PA3 + * @note This function is available only in high density value line devices. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM5CH4_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP); +} +#endif + +#if defined(AFIO_MAPR_ETH_REMAP) +/** + * @brief Enable the remapping of Ethernet MAC connections with the PHY. + * @rmtoll MAPR ETH_REMAP LL_GPIO_AFIO_REMAP_ETH_ENABLE + * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ETH_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP); +} + +/** + * @brief Disable the remapping of Ethernet MAC connections with the PHY. + * @rmtoll MAPR ETH_REMAP LL_GPIO_AFIO_REMAP_ETH_DISABLE + * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ETH_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP); +} +#endif + +#if defined(AFIO_MAPR_CAN2_REMAP) + +/** + * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. + * @rmtoll MAPR CAN2_REMAP LL_GPIO_AFIO_REMAP_CAN2_ENABLE + * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CAN2_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP); +} +/** + * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. + * @rmtoll MAPR CAN2_REMAP LL_GPIO_AFIO_REMAP_CAN2_DISABLE + * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CAN2_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP); +} +#endif + +#if defined(AFIO_MAPR_MII_RMII_SEL) +/** + * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. + * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AFIO_REMAP_ETH_RMII + * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ETH_RMII(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL); +} + +/** + * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. + * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AFIO_REMAP_ETH_MII + * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ETH_MII(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL); +} +#endif + +#if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP) +/** + * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). + * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AFIO_REMAP_ADC1_ETRGINJ_ENABLE + * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC1_ETRGINJ_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP); +} + +/** + * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). + * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AFIO_REMAP_ADC1_ETRGINJ_DISABLE + * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC1_ETRGINJ_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP); +} +#endif + +#if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP) +/** + * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). + * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AFIO_REMAP_ADC1_ETRGREG_ENABLE + * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC1_ETRGREG_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP); +} + +/** + * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). + * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AFIO_REMAP_ADC1_ETRGREG_DISABLE + * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC1_ETRGREG_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP); +} +#endif + +#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) + +/** + * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). + * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AFIO_REMAP_ADC2_ETRGINJ_ENABLE + * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC2_ETRGINJ_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP); +} + +/** + * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). + * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AFIO_REMAP_ADC2_ETRGINJ_DISABLE + * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC2_ETRGINJ_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP); +} +#endif + +#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) + +/** + * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). + * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AFIO_REMAP_ADC2_ETRGREG_ENABLE + * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC2_ETRGREG_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP); +} + +/** + * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). + * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AFIO_REMAP_ADC2_ETRGREG_DISABLE + * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC2_ETRGREG_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP); +} +#endif + +/** + * @brief Enable the Serial wire JTAG configuration + * @rmtoll MAPR SWJ_CFG LL_GPIO_AFIO_REMAP_SWJ_ENABLE + * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SWJ_ENABLE(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET); +} + +/** + * @brief Enable the Serial wire JTAG configuration + * @rmtoll MAPR SWJ_CFG LL_GPIO_AFIO_REMAP_SWJ_NONJTRST + * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SWJ_NONJTRST(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST); +} + +/** + * @brief Enable the Serial wire JTAG configuration + * @rmtoll MAPR SWJ_CFG LL_GPIO_AFIO_REMAP_SWJ_NOJTAG + * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SWJ_NOJTAG(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); +} + +/** + * @brief Disable the Serial wire JTAG configuration + * @rmtoll MAPR SWJ_CFG LL_GPIO_AFIO_REMAP_SWJ_DISABLE + * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SWJ_DISABLE(void) +{ + MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE); +} + +#if defined(AFIO_MAPR_SPI3_REMAP) + +/** + * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. + * @rmtoll MAPR SPI3_REMAP LL_GPIO_AFIO_REMAP_SPI3_ENABLE + * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SPI3_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP); +} + +/** + * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. + * @rmtoll MAPR SPI3_REMAP LL_GPIO_AFIO_REMAP_SPI3_DISABLE + * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SPI3_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP); +} +#endif + +#if defined(AFIO_MAPR_TIM2ITR1_IREMAP) + +/** + * @brief Control of TIM2_ITR1 internal mapping. + * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AFIO_TIM2ITR1_TO_USB + * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_TIM2ITR1_TO_USB(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP); +} + +/** + * @brief Control of TIM2_ITR1 internal mapping. + * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AFIO_TIM2ITR1_TO_ETH + * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_TIM2ITR1_TO_ETH(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP); +} +#endif + +#if defined(AFIO_MAPR_PTP_PPS_REMAP) + +/** + * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). + * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AFIO_ETH_PTP_PPS_ENABLE + * @note ENABLE: PTP_PPS is output on PB5 pin. + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_ETH_PTP_PPS_ENABLE(void) +{ + SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP); +} + +/** + * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). + * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AFIO_ETH_PTP_PPS_DISABLE + * @note DISABLE: PTP_PPS not output on PB5 pin. + * @note This bit is available only in connectivity line devices and is reserved otherwise. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_ETH_PTP_PPS_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_TIM9_REMAP) + +/** + * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. + * @rmtoll MAPR TIM9_REMAP LL_GPIO_AFIO_REMAP_TIM9_ENABLE + * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM9_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); +} + +/** + * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. + * @rmtoll MAPR TIM9_REMAP LL_GPIO_AFIO_REMAP_TIM9_ENABLE + * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM9_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_TIM10_REMAP) + +/** + * @brief Enable the remapping of TIM10_CH1. + * @rmtoll MAPR TIM10_REMAP LL_GPIO_AFIO_REMAP_TIM10_ENABLE + * @note ENABLE: Remap (TIM10_CH1 on PF6). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM10_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); +} + +/** + * @brief Disable the remapping of TIM10_CH1. + * @rmtoll MAPR TIM10_REMAP LL_GPIO_AFIO_REMAP_TIM10_DISABLE + * @note DISABLE: No remap (TIM10_CH1 on PB8). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM10_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_TIM11_REMAP) +/** + * @brief Enable the remapping of TIM11_CH1. + * @rmtoll MAPR TIM11_REMAP LL_GPIO_AFIO_REMAP_TIM11_ENABLE + * @note ENABLE: Remap (TIM11_CH1 on PF7). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM11_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); +} + +/** + * @brief Disable the remapping of TIM11_CH1. + * @rmtoll MAPR TIM11_REMAP LL_GPIO_AFIO_REMAP_TIM11_DISABLE + * @note DISABLE: No remap (TIM11_CH1 on PB9). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM11_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_TIM13_REMAP) + +/** + * @brief Enable the remapping of TIM13_CH1. + * @rmtoll MAPR TIM13_REMAP LL_GPIO_AFIO_REMAP_TIM13_ENABLE + * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM13_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); +} + +/** + * @brief Disable the remapping of TIM13_CH1. + * @rmtoll MAPR TIM13_REMAP LL_GPIO_AFIO_REMAP_TIM13_DISABLE + * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM13_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_TIM14_REMAP) + +/** + * @brief Enable the remapping of TIM14_CH1. + * @rmtoll MAPR TIM14_REMAP LL_GPIO_AFIO_REMAP_TIM14_ENABLE + * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM14_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); +} + +/** + * @brief Disable the remapping of TIM14_CH1. + * @rmtoll MAPR TIM14_REMAP LL_GPIO_AFIO_REMAP_TIM14_DISABLE + * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM14_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_FSMC_NADV_REMAP) + +/** + * @brief Controls the use of the optional FSMC_NADV signal. + * @rmtoll MAPR FSMC_NADV LL_GPIO_AFIO_FSMCNADV_DISCONNECTED + * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_FSMCNADV_DISCONNECTED(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); +} + +/** + * @brief Controls the use of the optional FSMC_NADV signal. + * @rmtoll MAPR FSMC_NADV LL_GPIO_AFIO_FSMCNADV_CONNECTED + * @note CONNECTED: The NADV signal is connected to the output (default). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_FSMCNADV_CONNECTED(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_TIM15_REMAP) + +/** + * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. + * @rmtoll MAPR TIM15_REMAP LL_GPIO_AFIO_REMAP_TIM15_ENABLE + * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM15_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); +} +/** + * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. + * @rmtoll MAPR TIM15_REMAP LL_GPIO_AFIO_REMAP_TIM15_DISABLE + * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM15_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_TIM16_REMAP) + +/** + * @brief Enable the remapping of TIM16_CH1. + * @rmtoll MAPR TIM16_REMAP LL_GPIO_AFIO_REMAP_TIM16_ENABLE + * @note ENABLE: Remap (TIM16_CH1 on PA6). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM16_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); +} + +/** + * @brief Disable the remapping of TIM16_CH1. + * @rmtoll MAPR TIM16_REMAP LL_GPIO_AFIO_REMAP_TIM16_DISABLE + * @note DISABLE: No remap (TIM16_CH1 on PB8). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM16_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_TIM17_REMAP) + +/** + * @brief Enable the remapping of TIM17_CH1. + * @rmtoll MAPR TIM17_REMAP LL_GPIO_AFIO_REMAP_TIM17_ENABLE + * @note ENABLE: Remap (TIM17_CH1 on PA7). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM17_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); +} + +/** + * @brief Disable the remapping of TIM17_CH1. + * @rmtoll MAPR TIM17_REMAP LL_GPIO_AFIO_REMAP_TIM17_DISABLE + * @note DISABLE: No remap (TIM17_CH1 on PB9). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM17_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_CEC_REMAP) + +/** + * @brief Enable the remapping of CEC. + * @rmtoll MAPR CEC_REMAP LL_GPIO_AFIO_REMAP_CEC_ENABLE + * @note ENABLE: Remap (CEC on PB10). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CEC_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); +} + +/** + * @brief Disable the remapping of CEC. + * @rmtoll MAPR CEC_REMAP LL_GPIO_AFIO_REMAP_CEC_DISABLE + * @note DISABLE: No remap (CEC on PB8). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CEC_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_TIM1_DMA_REMAP) + +/** + * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. + * @rmtoll MAPR TIM1_DMA_REMAP LL_GPIO_AFIO_REMAP_TIM1DMA_ENABLE + * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM1DMA_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); +} + +/** + * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. + * @rmtoll MAPR TIM1_DMA_REMAP LL_GPIO_AFIO_REMAP_TIM1DMA_DISABLE + * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM1DMA_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) + +/** + * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. + * @rmtoll MAPR TIM76_DAC_DMA_REMAP LL_GPIO_AFIO_REMAP_TIM67DACDMA_ENABLE + * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM67DACDMA_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); +} + +/** + * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. + * @rmtoll MAPR TIM76_DAC_DMA_REMAP LL_GPIO_AFIO_REMAP_TIM67DACDMA_DISABLE + * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM67DACDMA_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_TIM12_REMAP) + +/** + * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. + * @rmtoll MAPR TIM12_REMAP LL_GPIO_AFIO_REMAP_TIM12_ENABLE + * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). + * @note This bit is available only in high density value line devices. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM12_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); +} + +/** + * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. + * @rmtoll MAPR TIM12_REMAP LL_GPIO_AFIO_REMAP_TIM12_DISABLE + * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). + * @note This bit is available only in high density value line devices. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM12_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); +} +#endif + +#if defined(AFIO_MAPR2_MISC_REMAP) + +/** + * @brief Miscellaneous features remapping. + * This bit is set and cleared by software. It controls miscellaneous features. + * The DMA2 channel 5 interrupt position in the vector table. + * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). + * @rmtoll MAPR MISC_REMAP LL_GPIO_AFIO_REMAP_MISC_ENABLE + * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is + * selected as DAC Trigger 3, TIM15 triggers TIM1/3. + * @note This bit is available only in high density value line devices. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_MISC_ENABLE(void) +{ + SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); +} + +/** + * @brief Miscellaneous features remapping. + * This bit is set and cleared by software. It controls miscellaneous features. + * The DMA2 channel 5 interrupt position in the vector table. + * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). + * @rmtoll MAPR MISC_REMAP LL_GPIO_AFIO_REMAP_MISC_DISABLE + * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO + * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. + * @note This bit is available only in high density value line devices. + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_REMAP_MISC_DISABLE(void) +{ + CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); +} +#endif + +/** + * @} + */ + +/** @defgroup GPIO_AFIO_LL_EVENTOUT Output Event configuration + * @brief This section propose definition to Configure EVENTOUT Cortex feature . + * @{ + */ + +/** + * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. + * @rmtoll EVCR PORT LL_GPIO_AFIO_ConfigEventout\n + * EVCR PIN LL_GPIO_AFIO_ConfigEventout + * @param LL_GPIO_PortSource This parameter can be one of the following values: + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PORT_A + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PORT_B + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PORT_C + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PORT_D + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PORT_E + * @param LL_GPIO_PinSource This parameter can be one of the following values: + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_0 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_1 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_2 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_3 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_4 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_5 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_6 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_7 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_8 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_9 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_10 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_11 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_12 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_13 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_14 + * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_15 + * @retval None +*/ +__STATIC_INLINE void LL_GPIO_AFIO_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource) +{ + MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource)); +} + +/** + * @brief Enables the Event Output. + * @rmtoll EVCR EVOE LL_GPIO_AFIO_EnableEventout + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_EnableEventout(void) +{ + SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); +} + +/** + * @brief Disables the Event Output. + * @rmtoll EVCR EVOE LL_GPIO_AFIO_DisableEventout + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_DisableEventout(void) +{ + CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); +} + +/** + * @} + */ +/** @defgroup GPIO_AFIO_LL_EXTI EXTI external interrupt + * @brief This section Configure source input for the EXTI external interrupt . + * @{ + */ + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AFIO_SetEXTISource\n + * AFIO_EXTICR2 EXTIx LL_GPIO_AFIO_SetEXTISource\n + * AFIO_EXTICR3 EXTIx LL_GPIO_AFIO_SetEXTISource\n + * AFIO_EXTICR4 EXTIx LL_GPIO_AFIO_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_GPIO_AFIO_EXTI_PORTA + * @arg @ref LL_GPIO_AFIO_EXTI_PORTB + * @arg @ref LL_GPIO_AFIO_EXTI_PORTC + * @arg @ref LL_GPIO_AFIO_EXTI_PORTD + * @arg @ref LL_GPIO_AFIO_EXTI_PORTE + * @arg @ref LL_GPIO_AFIO_EXTI_PORTF + * @arg @ref LL_GPIO_AFIO_EXTI_PORTG + * @param Line This parameter can be one of the following values: + * @arg @ref LL_GPIO_AFIO_EXTI_LINE0 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE1 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE2 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE3 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE4 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE5 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE6 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE7 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE8 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE9 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE10 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE11 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE12 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE13 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE14 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AFIO_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16))); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AFIO_GetEXTISource\n + * AFIO_EXTICR2 EXTIx LL_GPIO_AFIO_GetEXTISource\n + * AFIO_EXTICR3 EXTIx LL_GPIO_AFIO_GetEXTISource\n + * AFIO_EXTICR4 EXTIx LL_GPIO_AFIO_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_GPIO_AFIO_EXTI_LINE0 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE1 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE2 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE3 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE4 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE5 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE6 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE7 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE8 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE9 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE10 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE11 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE12 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE13 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE14 + * @arg @ref LL_GPIO_AFIO_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AFIO_EXTI_PORTA + * @arg @ref LL_GPIO_AFIO_EXTI_PORTB + * @arg @ref LL_GPIO_AFIO_EXTI_PORTC + * @arg @ref LL_GPIO_AFIO_EXTI_PORTD + * @arg @ref LL_GPIO_AFIO_EXTI_PORTE + * @arg @ref LL_GPIO_AFIO_EXTI_PORTF + * @arg @ref LL_GPIO_AFIO_EXTI_PORTG + */ +__STATIC_INLINE uint32_t LL_GPIO_AFIO_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.c new file mode 100644 index 00000000000..af58b118cd1 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.c @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_pwr.c + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief PWR LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_pwr.h" +#include "stm32f1xx_ll_bus.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_LL_Exported_Functions + * @{ + */ + +/** @addtogroup PWR_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the PWR registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PWR registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_PWR_DeInit(void) +{ + /* Force reset of PWR clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR); + + /* Release reset of PWR clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR); + + return SUCCESS; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined(PWR) */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.h new file mode 100644 index 00000000000..4c5c3455dc2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.h @@ -0,0 +1,457 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_pwr.h + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_PWR_H +#define __STM32F1xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ +#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ +#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ +#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ +#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */ +/** + * @} + */ + + +/** @defgroup PWR_LL_EC_MODE_PWR Mode Power + * @{ + */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (ith low power regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + * @{ + */ +#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */ +#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */ +#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */ +#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */ +#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */ +/** + * @} + */ +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable access to the backup domain + * @rmtoll CR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); +} + +/** + * @brief Set voltage regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); +} + +/** + * @brief Get voltage regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); +} + +/** + * @brief Set power down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_SetPowerMode\n + * @rmtoll CR LPDS LL_PWR_SetPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode); +} + +/** + * @brief Get power down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_GetPowerMode\n + * @rmtoll CR LPDS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS))); +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); +} + + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Wake-up Flag + * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); +} + +/** + * @brief Get Standby Flag + * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); +} + +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); +} + +/** + * @brief Clear Standby Flag + * @rmtoll CR CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + SET_BIT(PWR->CR, PWR_CR_CSBF); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll CR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + SET_BIT(PWR->CR, PWR_CR_CWUF); +} +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.c new file mode 100644 index 00000000000..e13376a66f9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.c @@ -0,0 +1,511 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_rcc.c + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief RCC LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_rcc.h" +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Macros + * @{ + */ +#if defined(RCC_PLLI2S_SUPPORT) +#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE)) +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(USB) || defined(USB_OTG_FS) +#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) +#endif /* USB */ + +#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_LL_Private_Functions RCC Private functions + * @{ + */ +uint32_t RCC_GetSystemClockFreq(void); +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_PLL_GetFreqDomain_SYS(void); +#if defined(RCC_PLLI2S_SUPPORT) +uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void); +#endif /* RCC_PLLI2S_SUPPORT */ +#if defined(RCC_PLL2_SUPPORT) +uint32_t RCC_PLL2_GetFreqClockFreq(void); +#endif /* RCC_PLL2_SUPPORT */ +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_LL_EF_Init + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE PLL, PLL2, PLL3 OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RCC registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RCC_DeInit(void) +{ + uint32_t vl_mask = 0U; + + /* Set HSION bit */ + LL_RCC_HSI_Enable(); + + /* Reset SW, HPRE, PPRE, MCOSEL, PLLXTPRE, PLLSRC and ADCPRE bits */ + vl_mask = 0xFFFFFFFFU; + CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCOSEL |\ + RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_ADCPRE)); + +#if defined(USB) + /* Reset USBPRE bit */ + CLEAR_BIT(vl_mask, RCC_CFGR_USBPRE); +#elif defined(USB_OTG_FS) + /* Reset OTGFSPRE bit */ + CLEAR_BIT(vl_mask, RCC_CFGR_OTGFSPRE); +#endif /* USB */ + +#if defined(RCC_CFGR_PLLMULL2) + /* Set PLL multiplication factor to 2 */ + vl_mask |= RCC_CFGR_PLLMULL2; +#else + /* Set PLL multiplication factor to 4 */ + vl_mask |= RCC_CFGR_PLLMULL4; +#endif /* RCC_CFGR_PLLMULL2 */ + + LL_RCC_WriteReg(CFGR, vl_mask); + + /* Reset HSEON, HSEBYP, CSSON, PLLON bits */ + vl_mask = 0xFFFFFFFFU; + CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP)); + +#if defined(RCC_CR_PLL2ON) + /* Reset PLL2ON bit */ + CLEAR_BIT(vl_mask, RCC_CR_PLL2ON); +#endif /* RCC_CR_PLL2ON */ + +#if defined(RCC_CR_PLL3ON) + /* Reset PLL3ON bit */ + CLEAR_BIT(vl_mask, RCC_CR_PLL3ON); +#endif /* RCC_CR_PLL3ON */ + + LL_RCC_WriteReg(CR, vl_mask); + + /* Set HSITRIM bits to the reset value */ + LL_RCC_HSI_SetCalibTrimming(0x10U); + +#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT) + /* Reset CFGR2 register */ + vl_mask = 0x00000000U; + +#if defined(RCC_PLL2_SUPPORT) + /* Set PLL2 multiplication factor to 8 */ + vl_mask |= RCC_CFGR2_PLL2MUL8; +#endif /* RCC_PLL2_SUPPORT */ + +#if defined(RCC_PLLI2S_SUPPORT) + /* Set PLL3 multiplication factor to 8 */ + vl_mask |= RCC_CFGR2_PLL3MUL8; +#endif /* RCC_PLLI2S_SUPPORT */ + + LL_RCC_WriteReg(CFGR2, vl_mask); +#endif /* RCC_PREDIV1_DIV_2_16_SUPPORT */ + + /* Disable all interrupts */ + LL_RCC_WriteReg(CIR, 0x00000000U); + + return SUCCESS; +} + +/** + * @} + */ + +/** @addtogroup RCC_LL_EF_Get_Freq + * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks + * and different peripheral clocks available on the device. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (**) HSI_VALUE is a defined constant but the real value may vary + * depending on the variations in voltage and temperature. + * @note (***) HSE_VALUE is a defined constant, user has to ensure that + * HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * @note The result of this function could be incorrect when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * @{ + */ + +/** + * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks + * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function + * must be called to update structure fields. Otherwise, any + * configuration based on this function will be incorrect. + * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies + * @retval None + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) +{ + /* Get SYSCLK frequency */ + RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); + + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); +} + +#if defined(RCC_CFGR2_I2S2SRC) +/** + * @brief Return I2Sx clock frequency + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S2_CLKSOURCE + * @arg @ref LL_RCC_I2S3_CLKSOURCE + * @retval I2S clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */ +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) +{ + uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); + + /* I2S1CLK clock frequency */ + switch (LL_RCC_GetI2SClockSource(I2SxSource)) + { + case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */ + case LL_RCC_I2S3_CLKSOURCE_SYSCLK: + i2s_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */ + case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO: + default: + i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2; + break; + } + + return i2s_frequency; +} +#endif /* RCC_CFGR2_I2S2SRC */ +#if defined(USB) || defined(USB_OTG_FS) +/** + * @brief Return USBx clock frequency + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval USB clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) +{ + uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); + + /* USBCLK clock frequency */ + switch (LL_RCC_GetUSBClockSource(USBxSource)) + { +#if defined(RCC_CFGR_USBPRE) + case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + if (LL_RCC_PLL_IsReady()) + { + usb_frequency = RCC_PLL_GetFreqDomain_SYS(); + } + break; + + case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */ + default: + if (LL_RCC_PLL_IsReady()) + { + usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3) / 2; + } + break; +#endif /* RCC_CFGR_USBPRE */ +#if defined(RCC_CFGR_OTGFSPRE) + /* USBCLK = PLLVCO/2 + = (2 x PLLCLK) / 2 + = PLLCLK */ + case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */ + if (LL_RCC_PLL_IsReady()) + { + usb_frequency = RCC_PLL_GetFreqDomain_SYS(); + } + break; + + /* USBCLK = PLLVCO/3 + = (2 x PLLCLK) / 3 */ + case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 1.5 used as USB clock source */ + default: + if (LL_RCC_PLL_IsReady()) + { + usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2) / 3; + } + break; +#endif /* RCC_CFGR_OTGFSPRE */ + } + + return usb_frequency; +} +#endif /* USB */ + +/** + * @brief Return ADCx clock frequency + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval ADC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready + */ +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) +{ + uint32_t adc_prescaler = 0U; + uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource)); + + /* Get ADC prescaler */ + adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource); + + /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */ + adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())) + / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U); + + return adc_frequency; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_LL_Private_Functions + * @{ + */ + +/** + * @brief Return SYSTEM clock frequency + * @retval SYSTEM clock frequency (in Hz) + */ +uint32_t RCC_GetSystemClockFreq(void) +{ + uint32_t frequency = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + frequency = HSI_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ + frequency = RCC_PLL_GetFreqDomain_SYS(); + break; + + default: + frequency = HSI_VALUE; + break; + } + + return frequency; +} + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} + +/** + * @brief Return PCLK2 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK2 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK2 clock frequency */ + return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); +} + +/** + * @brief Return PLL clock frequency used for system domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_SYS(void) +{ + uint32_t pllinputfreq = 0U, pllsource = 0U; + + /* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */ + + /* Get PLL source */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE / 2; + break; + + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1); + break; + +#if defined(RCC_PLL2_SUPPORT) + case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */ + pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1); + break; +#endif /* RCC_PLL2_SUPPORT */ + + default: + pllinputfreq = HSI_VALUE / 2; + break; + } + return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator()); +} + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Return PLL clock frequency used for system domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL2_GetFreqClockFreq(void) +{ + return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2()); +} +#endif /* RCC_PLL2_SUPPORT */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Return PLL clock frequency used for system domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void) +{ + return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2()); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h new file mode 100644 index 00000000000..de79141d041 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h @@ -0,0 +1,2356 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_rcc.h + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_RCC_H +#define __STM32F1xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ +/* Define used for feature activation */ +#if defined(RCC_CFGR2_PREDIV2) +#define RCC_PREDIV2_SUPPORT +#endif /* RCC_CFGR2_PREDIV2 */ + +#if defined(RCC_CR_PLL3ON) +#define RCC_PLLI2S_SUPPORT +#endif /* RCC_CR_PLL3ON */ + +#if defined(RCC_CR_PLL2ON) +#define RCC_PLL2_SUPPORT +#endif /* RCC_CR_PLL2ON */ + +#if defined(RCC_CFGR2_PREDIV1SRC) +#define RCC_SRC_PREDIV1_SUPPORT +#endif /* RCC_CFGR2_PREDIV1SRC */ + +#if defined(RCC_CFGR2_PREDIV1) +#define RCC_PREDIV1_DIV_2_16_SUPPORT +#endif /* RCC_CFGR2_PREDIV1 */ + + +/* Defines used for the bit position in the register and perform offsets*/ +#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /*!< field position in register RCC_CR */ +#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /*!< field position in register RCC_CR */ +#define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMULL) /*!< field position in register RCC_CFGR */ +#define RCC_POSITION_I2S2SRC 17U /*!< field position in register RCC_CFGR2 */ +#define RCC_POSITION_I2S3SRC 18U /*!< field position in register RCC_CFGR2 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE ((uint32_t)8000000U) /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE ((uint32_t)32000U) /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Clear */ +#define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */ +#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */ +#define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ +#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */ +#define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */ +/** + * @} + */ + +#if defined(RCC_PREDIV2_SUPPORT) +/** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor + * @{ + */ +#define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */ +#define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */ +#define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */ +#define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */ +#define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */ +#define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */ +#define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */ +#define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */ +#define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */ +#define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */ +#define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */ +#define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */ +#define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */ +#define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */ +#define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */ +#define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */ +/** + * @} + */ + +#endif /* RCC_PREDIV2_SUPPORT */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ +#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/ +#if defined(RCC_CFGR_MCOSEL_PLL2CLK) +#define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCOSEL_PLL2 /*!< PLL2 clock selected as MCO source*/ +#endif /* RCC_CFGR_MCOSEL_PLL2CLK */ +#if defined(RCC_CFGR_MCOSEL_PLL3CLK_DIV2) +#define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCOSEL_PLL3_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/ +#endif /* RCC_CFGR_MCOSEL_PLL3CLK_DIV2 */ +#if defined(RCC_CFGR_MCOSEL_EXT_HSE) +#define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCOSEL_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ +#endif /* RCC_CFGR_MCOSEL_EXT_HSE */ +#if defined(RCC_CFGR_MCOSEL_PLL3CLK) +#define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCOSEL_PLL3CLK /*!< PLLI2S clock selected as MCO source */ +#endif /* RCC_CFGR_MCOSEL_PLL3CLK */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +#if defined(RCC_CFGR2_I2S2SRC) +/** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#define LL_RCC_I2S2_CLKSOURCE_SYSCLK (uint32_t)(RCC_CFGR2_I2S2SRC | (0x00000000 >> 16)) /*!< System clock (SYSCLK) selected as I2S2 clock entry */ +#define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */ +#define LL_RCC_I2S3_CLKSOURCE_SYSCLK (uint32_t)(RCC_CFGR2_I2S3SRC | (0x00000000 >> 16)) /*!< System clock (SYSCLK) selected as I2S3 clock entry */ +#define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */ +/** + * @} + */ + +#endif /* RCC_CFGR2_I2S2SRC */ + +#if defined(USB_OTG_FS) || defined(USB) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#if defined(RCC_CFGR_USBPRE) +#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */ +#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 ((uint32_t)0x00000000) /*!< PLL clock is divided by 1.5 */ +#endif /*RCC_CFGR_USBPRE*/ +#if defined(RCC_CFGR_OTGFSPRE) +#define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */ +#define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 ((uint32_t)0x00000000) /*!< PLL clock is divided by 3 */ +#endif /*RCC_CFGR_OTGFSPRE*/ +/** + * @} + */ + +#endif /* USB_OTG_FS || USB */ + +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection + * @{ + */ +#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/ +#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/ +#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/ +#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/ +/** + * @} + */ + +#if defined(RCC_CFGR2_I2S2SRC) +/** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source + * @{ + */ +#define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection */ +#define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection */ +/** + * @} + */ + +#endif /* RCC_CFGR2_I2S2SRC */ + +#if defined(USB_OTG_FS) || defined(USB) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE ((uint32_t)0x00400000) /*!< USB Clock source selection */ +/** + * @} + */ + +#endif /* USB_OTG_FS || USB */ + +/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + * @{ + */ +#if defined(RCC_CFGR_PLLMULL2) +#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */ +#endif /*RCC_CFGR_PLLMULL2*/ +#if defined(RCC_CFGR_PLLMULL3) +#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */ +#endif /*RCC_CFGR_PLLMULL3*/ +#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */ +#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */ +#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */ +#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */ +#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */ +#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */ +#if defined(RCC_CFGR_PLLMULL6_5) +#define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */ +#else +#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */ +#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */ +#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */ +#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */ +#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */ +#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */ +#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */ +#endif /*RCC_CFGR_PLLMULL6_5*/ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI_DIV_2 ((uint32_t)0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */ +#if defined(RCC_SRC_PREDIV1_SUPPORT) +#define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */ +#endif /*RCC_SRC_PREDIV1_SUPPORT*/ + +#define LL_RCC_PLLSOURCE_HSE_DIV_1 RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ +#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT) +#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ +#if defined(RCC_SRC_PREDIV1_SUPPORT) +#define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/2 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/3 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/4 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/5 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/6 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/7 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/8 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/9 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/10 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/11 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/12 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/13 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/14 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/15 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/16 clock selected as PLL entry clock source */ +#endif /*RCC_SRC_PREDIV1_SUPPORT*/ +#else +#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */ +#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor + * @{ + */ +#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT) +#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */ +#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */ +#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */ +#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divided by 4 */ +#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divided by 5 */ +#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divided by 6 */ +#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divided by 7 */ +#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divided by 8 */ +#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divided by 9 */ +#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divided by 10 */ +#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divided by 11 */ +#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divided by 12 */ +#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divided by 13 */ +#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divided by 14 */ +#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */ +#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */ +#else +#define LL_RCC_PREDIV_DIV_1 ((uint32_t)0x00000000U) /*!< HSE divider clock clock not divided */ +#define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */ +#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/ +/** + * @} + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL + * @{ + */ +#define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */ +#define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */ +#define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */ +#define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */ +#define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */ +#define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */ +#define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */ +#define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */ +#define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */ +/** + * @} + */ + +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL + * @{ + */ +#define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */ +#define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */ +#define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */ +#define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */ +#define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */ +#define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */ +#define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */ +#define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */ +#define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */ +/** + * @} + */ + +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +#if defined(RCC_CFGR_PLLMULL6_5) +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1) + * @param __PLLMUL__: This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_6_5 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ + (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \ + ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_POSITION_PLLMUL) + 2U)) :\ + (((__INPUTFREQ__) * 13U) / 2U)) + +#else +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2) + * @param __PLLMUL__: This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_10 + * @arg @ref LL_RCC_PLL_MUL_11 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_13 + * @arg @ref LL_RCC_PLL_MUL_14 + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_POSITION_PLLMUL) + 2U)) +#endif /* RCC_CFGR_PLLMULL6_5 */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Helper macro to calculate the PLLI2S frequency + * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ()); + * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value) + * @param __PLLI2SMUL__: This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2S_MUL_8 + * @arg @ref LL_RCC_PLLI2S_MUL_9 + * @arg @ref LL_RCC_PLLI2S_MUL_10 + * @arg @ref LL_RCC_PLLI2S_MUL_11 + * @arg @ref LL_RCC_PLLI2S_MUL_12 + * @arg @ref LL_RCC_PLLI2S_MUL_13 + * @arg @ref LL_RCC_PLLI2S_MUL_14 + * @arg @ref LL_RCC_PLLI2S_MUL_16 + * @arg @ref LL_RCC_PLLI2S_MUL_20 + * @param __PLLI2SDIV__: This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2U)) / (((__PLLI2SDIV__) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1U)) +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Helper macro to calculate the PLL2 frequency + * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ()); + * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value) + * @param __PLL2MUL__: This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL2_MUL_8 + * @arg @ref LL_RCC_PLL2_MUL_9 + * @arg @ref LL_RCC_PLL2_MUL_10 + * @arg @ref LL_RCC_PLL2_MUL_11 + * @arg @ref LL_RCC_PLL2_MUL_12 + * @arg @ref LL_RCC_PLL2_MUL_13 + * @arg @ref LL_RCC_PLL2_MUL_14 + * @arg @ref LL_RCC_PLL2_MUL_16 + * @arg @ref LL_RCC_PLL2_MUL_20 + * @param __PLL2DIV__: This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 + * @retval PLL2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2U)) / (((__PLL2DIV__) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1U)) +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @brief Helper macro to calculate the HCLK frequency + * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__: This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__: This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1]) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler + * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__: This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2]) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); +} + +#if defined(RCC_PREDIV2_SUPPORT) +/** + * @brief Get PREDIV2 division factor + * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)); +} +#endif /* RCC_PREDIV2_SUPPORT */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_POSITION_HSICAL); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_POSITION_HSITRIM); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_POSITION_HSITRIM); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 + * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*) + * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*) + * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +#if defined(RCC_CFGR2_I2S2SRC) +/** + * @brief Configure I2Sx clock source + * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n + * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource + * @param I2SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO + * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource) +{ + MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U)); +} +#endif /* RCC_CFGR2_I2S2SRC */ + +#if defined(USB_OTG_FS) || defined(USB) +/** + * @brief Configure USB clock source + * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n + * CFGR USBPRE LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ +#if defined(RCC_CFGR_USBPRE) + MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource); +#else /*RCC_CFGR_OTGFSPRE*/ + MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource); +#endif /*RCC_CFGR_USBPRE*/ +} +#endif /* USB_OTG_FS || USB */ + +/** + * @brief Configure ADC clock source + * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource); +} + +#if defined(RCC_CFGR2_I2S2SRC) +/** + * @brief Get I2Sx clock source + * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n + * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S2_CLKSOURCE + * @arg @ref LL_RCC_I2S3_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO + * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16 | I2Sx); +} +#endif /* RCC_CFGR2_I2S2SRC */ + +#if defined(USB_OTG_FS) || defined(USB) +/** + * @brief Get USBx clock source + * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n + * CFGR USBPRE LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*) + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, USBx)); +} +#endif /* USB_OTG_FS || USB */ + +/** + * @brief Get ADCx clock source + * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource + * @param ADCx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 + * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, ADCx)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed any more unless + * the Backup domain is reset. The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); +} + +/** + * @brief Configure PLL used for SYSCLK Domain + * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1 + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*) + * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*) + * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*) + * + * (*) value not defined in all devices + * @param PLLMul This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 (*) + * @arg @ref LL_RCC_PLL_MUL_3 (*) + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_6_5 (*) + * @arg @ref LL_RCC_PLL_MUL_10 (*) + * @arg @ref LL_RCC_PLL_MUL_11 (*) + * @arg @ref LL_RCC_PLL_MUL_12 (*) + * @arg @ref LL_RCC_PLL_MUL_13 (*) + * @arg @ref LL_RCC_PLL_MUL_14 (*) + * @arg @ref LL_RCC_PLL_MUL_15 (*) + * @arg @ref LL_RCC_PLL_MUL_16 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL, + (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul); +#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT) +#if defined(RCC_SRC_PREDIV1_SUPPORT) + MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC), + (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4)) >> 4)); +#else + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1)); +#endif /*RCC_SRC_PREDIV1_SUPPORT*/ +#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/ +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n + * CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ +#if defined(RCC_SRC_PREDIV1_SUPPORT) + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC) | (READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4)); +#else + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); +#endif /*RCC_SRC_PREDIV1_SUPPORT*/ +} + +/** + * @brief Get PLL multiplication Factor + * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_2 (*) + * @arg @ref LL_RCC_PLL_MUL_3 (*) + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_5 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_7 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_9 + * @arg @ref LL_RCC_PLL_MUL_6_5 (*) + * @arg @ref LL_RCC_PLL_MUL_10 (*) + * @arg @ref LL_RCC_PLL_MUL_11 (*) + * @arg @ref LL_RCC_PLL_MUL_12 (*) + * @arg @ref LL_RCC_PLL_MUL_13 (*) + * @arg @ref LL_RCC_PLL_MUL_14 (*) + * @arg @ref LL_RCC_PLL_MUL_15 (*) + * @arg @ref LL_RCC_PLL_MUL_16 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL)); +} + +/** + * @brief Get PREDIV1 division factor for the main PLL + * @note They can be written only when the PLL is disabled + * @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n + * CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PREDIV_DIV_1 + * @arg @ref LL_RCC_PREDIV_DIV_2 + * @arg @ref LL_RCC_PREDIV_DIV_3 (*) + * @arg @ref LL_RCC_PREDIV_DIV_4 (*) + * @arg @ref LL_RCC_PREDIV_DIV_5 (*) + * @arg @ref LL_RCC_PREDIV_DIV_6 (*) + * @arg @ref LL_RCC_PREDIV_DIV_7 (*) + * @arg @ref LL_RCC_PREDIV_DIV_8 (*) + * @arg @ref LL_RCC_PREDIV_DIV_9 (*) + * @arg @ref LL_RCC_PREDIV_DIV_10 (*) + * @arg @ref LL_RCC_PREDIV_DIV_11 (*) + * @arg @ref LL_RCC_PREDIV_DIV_12 (*) + * @arg @ref LL_RCC_PREDIV_DIV_13 (*) + * @arg @ref LL_RCC_PREDIV_DIV_14 (*) + * @arg @ref LL_RCC_PREDIV_DIV_15 (*) + * @arg @ref LL_RCC_PREDIV_DIV_16 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) +{ +#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT) + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)); +#else + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)); +#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/ +} + +/** + * @} + */ + +#if defined(RCC_PLLI2S_SUPPORT) +/** @defgroup RCC_LL_EF_PLLI2S PLLI2S + * @{ + */ + +/** + * @brief Enable PLLI2S + * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Disable PLLI2S + * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); +} + +/** + * @brief Check if PLLI2S Ready + * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)); +} + +/** + * @brief Configure PLLI2S used for I2S Domain + * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n + * CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 + * @param Multiplicator This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2S_MUL_8 + * @arg @ref LL_RCC_PLLI2S_MUL_9 + * @arg @ref LL_RCC_PLLI2S_MUL_10 + * @arg @ref LL_RCC_PLLI2S_MUL_11 + * @arg @ref LL_RCC_PLLI2S_MUL_12 + * @arg @ref LL_RCC_PLLI2S_MUL_13 + * @arg @ref LL_RCC_PLLI2S_MUL_14 + * @arg @ref LL_RCC_PLLI2S_MUL_16 + * @arg @ref LL_RCC_PLLI2S_MUL_20 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator); +} + +/** + * @brief Get PLLI2S Multiplication Factor + * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2S_MUL_8 + * @arg @ref LL_RCC_PLLI2S_MUL_9 + * @arg @ref LL_RCC_PLLI2S_MUL_10 + * @arg @ref LL_RCC_PLLI2S_MUL_11 + * @arg @ref LL_RCC_PLLI2S_MUL_12 + * @arg @ref LL_RCC_PLLI2S_MUL_13 + * @arg @ref LL_RCC_PLLI2S_MUL_14 + * @arg @ref LL_RCC_PLLI2S_MUL_16 + * @arg @ref LL_RCC_PLLI2S_MUL_20 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL)); +} + +/** + * @} + */ +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** @defgroup RCC_LL_EF_PLL2 PLL2 + * @{ + */ + +/** + * @brief Enable PLL2 + * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Disable PLL2 + * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL2_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); +} + +/** + * @brief Check if PLL2 Ready + * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)); +} + +/** + * @brief Configure PLL2 used for PLL2 Domain + * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n + * CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2 + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15 + * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 + * @param Multiplicator This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL2_MUL_8 + * @arg @ref LL_RCC_PLL2_MUL_9 + * @arg @ref LL_RCC_PLL2_MUL_10 + * @arg @ref LL_RCC_PLL2_MUL_11 + * @arg @ref LL_RCC_PLL2_MUL_12 + * @arg @ref LL_RCC_PLL2_MUL_13 + * @arg @ref LL_RCC_PLL2_MUL_14 + * @arg @ref LL_RCC_PLL2_MUL_16 + * @arg @ref LL_RCC_PLL2_MUL_20 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator); +} + +/** + * @brief Get PLL2 Multiplication Factor + * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL2_MUL_8 + * @arg @ref LL_RCC_PLL2_MUL_9 + * @arg @ref LL_RCC_PLL2_MUL_10 + * @arg @ref LL_RCC_PLL2_MUL_11 + * @arg @ref LL_RCC_PLL2_MUL_12 + * @arg @ref LL_RCC_PLL2_MUL_13 + * @arg @ref LL_RCC_PLL2_MUL_14 + * @arg @ref LL_RCC_PLL2_MUL_16 + * @arg @ref LL_RCC_PLL2_MUL_20 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL)); +} + +/** + * @} + */ +#endif /* RCC_PLL2_SUPPORT */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Clear PLLI2S ready interrupt flag + * @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Clear PLL2 ready interrupt flag + * @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC); +} +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_CSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Check if PLLI2S ready interrupt occurred or not + * @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF)); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Check if PLL2 ready interrupt occurred or not + * @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF)); +} +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Enable PLLI2S ready interrupt + * @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Enable PLL2 ready interrupt + * @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE); +} +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Disable PLLI2S ready interrupt + * @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Disable PLL2 ready interrupt + * @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE); +} +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); +} + +#if defined(RCC_PLLI2S_SUPPORT) +/** + * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. + * @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE)); +} +#endif /* RCC_PLLI2S_SUPPORT */ + +#if defined(RCC_PLL2_SUPPORT) +/** + * @brief Checks if PLL2 ready interrupt source is enabled or disabled. + * @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE)); +} +#endif /* RCC_PLL2_SUPPORT */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +#if defined(RCC_CFGR2_I2S2SRC) +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +#endif /* RCC_CFGR2_I2S2SRC */ +#if defined(USB_OTG_FS) || defined(USB) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_OTG_FS || USB */ +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.c index 788c73a7ec7..d3eccbf236b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.h index a3dec1d799a..22009d814ce 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of low layer SDMMC HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_system.h new file mode 100644 index 00000000000..3f86e375bc0 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_system.h @@ -0,0 +1,595 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_system.h + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief Header file of SYSTEM LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_SYSTEM_H +#define __STM32F1xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/* Defines used for position in the register */ +#define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + + + +/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment + * @{ + */ +#define LL_DBGMCU_TRACE_NONE (uint32_t)0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ +#if defined(DBGMCU_CR_DBG_TIM5_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM5_STOP */ +#if defined(DBGMCU_CR_DBG_TIM6_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM6_STOP */ +#if defined(DBGMCU_CR_DBG_TIM7_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM7_STOP */ +#if defined(DBGMCU_CR_DBG_TIM12_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM12_STOP */ +#if defined(DBGMCU_CR_DBG_TIM13_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM13_STOP */ +#if defined(DBGMCU_CR_DBG_TIM14_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM14_STOP */ +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_CR_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_STOP /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#if defined(DBGMCU_CR_DBG_CAN1_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ +#endif /* DBGMCU_CR_DBG_CAN1_STOP */ +#if defined(DBGMCU_CR_DBG_CAN2_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ +#endif /* DBGMCU_CR_DBG_CAN2_STOP */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ +#if defined(DBGMCU_CR_DBG_TIM8_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_CAN1_STOP */ +#if defined(DBGMCU_CR_DBG_TIM9_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM9_STOP */ +#if defined(DBGMCU_CR_DBG_TIM10_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM10_STOP */ +#if defined(DBGMCU_CR_DBG_TIM11_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM11_STOP */ +#if defined(DBGMCU_CR_DBG_TIM15_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM15_STOP */ +#if defined(DBGMCU_CR_DBG_TIM16_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM16_STOP */ +#if defined(DBGMCU_CR_DBG_TIM17_STOP) +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ +#endif /* DBGMCU_CR_DBG_TIM17_STOP */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#if defined(FLASH_ACR_LATENCY) +#define LL_FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ +#else +#endif /* FLASH_ACR_LATENCY */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + + + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @note For Low Density devices, the device ID is 0x412 + * @note For Medium Density devices, the device ID is 0x410 + * @note For High Density devices, the device ID is 0x414 + * @note For XL Density devices, the device ID is 0x430 + * @note For Connectivity Line devices, the device ID is 0x418 + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as revA -> 0x1000,for Low Density devices + For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices + For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices + For example, it is read as revA or 1 -> 0x1003,for XL Density devices + For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Set Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment + * @param PinAssignment This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); +} + +/** + * @brief Get Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->CR, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->CR, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->CR, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->CR, Periphs); +} +/** + * @} + */ + +#if defined(FLASH_ACR_LATENCY) +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); +} + +#endif /* FLASH_ACR_LATENCY */ +/** + * @brief Enable Flash Half Cycle Access + * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); +} + +/** + * @brief Disable Flash Half Cycle Access + * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); +} + +/** + * @brief Check if Flash Half Cycle Access is enabled or not + * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA)); +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_SYSTEM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.c index 24f343d9fb5..a698106e451 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_usb.c * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.h index d9d59f5cea5..03adbeae2ae 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_usb.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.0.5 + * @date 06-December-2016 * @brief Header file of USB Low Layer HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.c new file mode 100644 index 00000000000..9d68c2df4ad --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.c @@ -0,0 +1,619 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_utils.c + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief UTILS LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_rcc.h" +#include "stm32f1xx_ll_utils.h" +#include "stm32f1xx_ll_system.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +/** @addtogroup UTILS_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Constants + * @{ + */ + +/* Defines used for PLL range */ +#define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /*!< Frequency max for PLL output, in Hz */ + +/* Defines used for HSE range */ +#define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /*!< Frequency min for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /*!< Frequency max for HSE frequency, in Hz */ + +/* Defines used for FLASH latency according to HCLK Frequency */ +#if defined(FLASH_ACR_LATENCY) +#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */ +#define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */ +#else + /*!< No Latency Configuration in this device */ +#endif +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Macros + * @{ + */ +#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + +#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + +#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_16)) + +#if defined(RCC_CFGR_PLLMULL6_5) +#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_5) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_7) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_9) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_6_5)) +#else +#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_3) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_4) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_5) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_7) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_9) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_10) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_11) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_12) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_13) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_14) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_15) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_16)) +#endif /* RCC_CFGR_PLLMULL6_5 */ + +#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT) +#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \ + ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16)) +#else +#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2)) +#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/ + +#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX) + + +#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ + || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + +#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Functions UTILS Private functions + * @{ + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +#if defined(FLASH_ACR_LATENCY) +static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency); +#endif /* FLASH_ACR_LATENCY */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +static ErrorStatus UTILS_PLL_IsBusy(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UTILS_LL_EF_DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +void LL_Init1msTick(uint32_t HCLKFrequency) +{ + /* Use frequency provided in argument */ + LL_InitTick(HCLKFrequency, 1000U); +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on SysTick counter flag + * @note When a RTOS is used, it is recommended to avoid using blocking delay + * and use rather osDelay service. + * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + * will configure Systick to 1ms + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +void LL_mDelay(uint32_t Delay) +{ + __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + /* Add this code to indicate that local variable is not used */ + ((void)tmp); + + /* Add a period to guaranty minimum wait */ + if (Delay < LL_MAX_DELAY) + { + Delay++; + } + + while (Delay) + { + if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + { + Delay--; + } + } +} + +/** + * @} + */ + +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AHB and APB buses clocks configuration + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz. + @endverbatim + @internal + Depending on the SYSCLK frequency, the flash latency should be adapted accordingly: + (++) +-----------------------------------------------+ + (++) | Latency | SYSCLK clock frequency (MHz) | + (++) |---------------|-------------------------------| + (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + (++) |---------------|-------------------------------| + (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + (++) |---------------|-------------------------------| + (++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | + (++) +-----------------------------------------------+ + @endinternal + * @{ + */ + +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @retval None + */ +void LL_SetSystemCoreClock(uint32_t HCLKFrequency) +{ + /* HCLK clock frequency */ + SystemCoreClock = HCLKFrequency; +} + +/** + * @brief This function configures system clock with HSI as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL) + * - PREDIV: Set to 2 for few devices + * - PLLMUL: The application software must set correctly the PLL multiplication factor to + * not exceed 72MHz + * @note FLASH latency can be modified through this function. + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + /* Check PREDIV value */ + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); +#else + /* Force PREDIV value to 2 */ + UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); + + /* Enable HSI if not enabled */ + if (LL_RCC_HSI_IsReady() != 1U) + { + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + { + /* Wait for HSI ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief This function configures system clock with HSE as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL) + * - PREDIV: Set to 2 for few devices + * - PLLMUL: The application software must set correctly the PLL multiplication factor to + * not exceed @ref UTILS_PLL_OUTPUT_MAX + * @note FLASH latency can be modified through this function. + * @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX + * @param HSEBypass This parameter can be one of the following values: + * @arg @ref LL_UTILS_HSEBYPASS_ON + * @arg @ref LL_UTILS_HSEBYPASS_OFF + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv)); + + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + + /* Enable HSE if not enabled */ + if (LL_RCC_HSE_IsReady() != 1U) + { + /* Check if need to enable HSE bypass feature or not */ + if (HSEBypass == LL_UTILS_HSEBYPASS_ON) + { + LL_RCC_HSE_EnableBypass(); + } + else + { + LL_RCC_HSE_DisableBypass(); + } + + /* Enable HSE */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1U) + { + /* Wait for HSE ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UTILS_LL_Private_Functions + * @{ + */ +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param Frequency SYSCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +#if defined(FLASH_ACR_LATENCY) +static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) +{ + ErrorStatus status = SUCCESS; + + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + + /* Frequency cannot be equal to 0 */ + if (Frequency == 0U) + { + status = ERROR; + } + else + { + if (Frequency > UTILS_LATENCY2_FREQ) + { + /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if (Frequency > UTILS_LATENCY1_FREQ) + { + /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ + } + + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (LL_FLASH_GetLatency() != latency) + { + status = ERROR; + } + } + return status; +} +#endif /* FLASH_ACR_LATENCY */ + +/** + * @brief Function to check that PLL can be modified + * @param PLL_InputFrequency PLL input frequency (in Hz) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @retval PLL output frequency (in Hz) + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +{ + uint32_t pllfreq = 0U; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); + + /* Check different PLL parameters according to RM */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#elif defined (RCC_PREDIV1_DIV_2_16_SUPPORT) + pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul); +#else + pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + + return pllfreq; +} + +/** + * @brief Function to check that PLL can be modified + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PLL modification can be done + * - ERROR: PLL is busy + */ +static ErrorStatus UTILS_PLL_IsBusy(void) +{ + ErrorStatus status = SUCCESS; + + /* Check if PLL is busy*/ + if (LL_RCC_PLL_IsReady() != 0U) + { + /* PLL configuration cannot be modified */ + status = ERROR; + } +#if defined(RCC_PLL2_SUPPORT) + /* Check if PLL2 is busy*/ + if (LL_RCC_PLL2_IsReady() != 0U) + { + /* PLL2 configuration cannot be modified */ + status = ERROR; + } +#endif /* RCC_PLL2_SUPPORT */ + +#if defined(RCC_PLL3_SUPPORT) + /* Check if PLL3 is busy*/ + if (LL_RCC_PLL3_IsReady() != 0U) + { + /* PLL3 configuration cannot be modified */ + status = ERROR; + } +#endif /* RCC_PLL3_SUPPORT */ + + return status; +} + +/** + * @brief Function to enable PLL and switch system clock to PLL + * @param SYSCLK_Frequency SYSCLK frequency + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: No problem to switch system to PLL + * - ERROR: Problem to switch system to PLL + */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t sysclk_frequency_current = 0U; + + assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); + + /* Calculate current SYSCLK frequency */ + sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]); + + /* Increasing the number of wait states because of higher CPU frequency */ +#if defined (FLASH_ACR_LATENCY) + if (sysclk_frequency_current < SYSCLK_Frequency) + { + /* Set FLASH latency to highest latency */ + status = UTILS_SetFlashLatency(SYSCLK_Frequency); + } +#endif /* FLASH_ACR_LATENCY */ + + /* Update system clock configuration */ + if (status == SUCCESS) + { +#if defined(RCC_PLL2_SUPPORT) + /* Enable PLL2 */ + LL_RCC_PLL2_Enable(); + while (LL_RCC_PLL2_IsReady() != 1U) + { + /* Wait for PLL2 ready */ + } + +#endif /* RCC_PLL2_SUPPORT */ + /* Enable PLL */ + LL_RCC_PLL_Enable(); + while (LL_RCC_PLL_IsReady() != 1U) + { + /* Wait for PLL ready */ + } + + /* Sysclk activation on the main PLL */ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + /* Wait for system clock switch to PLL */ + } + + /* Set APB1 & APB2 prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); + } + + /* Decreasing the number of wait states because of lower CPU frequency */ +#if defined (FLASH_ACR_LATENCY) + if (sysclk_frequency_current > SYSCLK_Frequency) + { + /* Set FLASH latency to lowest latency */ + status = UTILS_SetFlashLatency(SYSCLK_Frequency); + } +#endif /* FLASH_ACR_LATENCY */ + + /* Update SystemCoreClock variable */ + if (status == SUCCESS) + { + LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider)); + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.h new file mode 100644 index 00000000000..c9a65233a7e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.h @@ -0,0 +1,284 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_utils.h + * @author MCD Application Team + * @version $VERSION$ + * @date $DATE$ + * @brief Header file of UTILS LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_UTILS_H +#define __STM32F1xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLL_MUL + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source. + This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS))); +} + + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_UTILS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/i2c_api_stm32f1.c b/targets/TARGET_STM/TARGET_STM32F1/i2c_api_stm32f1.c deleted file mode 100644 index 31c49b0e8f5..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F1/i2c_api_stm32f1.c +++ /dev/null @@ -1,468 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralPins.h" - -/* Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. */ -#define FLAG_TIMEOUT ((int)0x1000) -#define LONG_TIMEOUT ((int)0x8000) - -I2C_HandleTypeDef I2cHandle; - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - static int i2c1_inited = 0; - static int i2c2_inited = 0; - - // Determine the I2C to use - I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); - I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); - - obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl); - MBED_ASSERT(obj->i2c != (I2CName)NC); - - // Check if I2C peripherals are already configured - if ((obj->i2c == I2C_1) && i2c1_inited) return; - if ((obj->i2c == I2C_2) && i2c2_inited) return; - - // Set I2C clock - if (obj->i2c == I2C_1) { - i2c1_inited = 1; - __I2C1_CLK_ENABLE(); - } - - if (obj->i2c == I2C_2) { - i2c2_inited = 1; - __I2C2_CLK_ENABLE(); - } - - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrain); - pin_mode(scl, OpenDrain); - - // Reset to clear pending flags if any - i2c_reset(obj); - - // I2C configuration - i2c_frequency(obj, 100000); // 100 kHz per default - - // I2C master by default - obj->slave = 0; -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - MBED_ASSERT((hz != 0) && (hz <= 400000)); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - - // wait before init - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - // I2C configuration - I2cHandle.Init.ClockSpeed = hz; - I2cHandle.Init.DutyCycle = I2C_DUTYCYCLE_2; - I2cHandle.Init.OwnAddress1 = 0; - I2cHandle.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; - I2cHandle.Init.OwnAddress2 = 0; - I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; - I2cHandle.Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; - HAL_I2C_Init(&I2cHandle); - - if (obj->slave) { - // Enable Address Acknowledge - I2cHandle.Instance->CR1 |= I2C_CR1_ACK; - } -} - -inline int i2c_start(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - // Clear Acknowledge failure flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - - // Wait the STOP condition has been previously correctly sent - // This timeout can be avoid in some specific cases by simply clearing the STOP bit - timeout = FLAG_TIMEOUT; - while ((i2c->CR1 & I2C_CR1_STOP) == I2C_CR1_STOP) { - if ((timeout--) == 0) { - return 1; - } - } - - // Generate the START condition - i2c->CR1 |= I2C_CR1_START; - - // Wait the START condition has been correctly sent - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) { - if ((timeout--) == 0) { - return 1; - } - } - - return 0; -} - -inline int i2c_stop(i2c_t *obj) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - - // Generate the STOP condition - i2c->CR1 |= I2C_CR1_STOP; - - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - int value; - - // Generate start condition - i2c_start(obj); - - // Send address for read - i2c->DR = __HAL_I2C_7BIT_ADD_READ(address); - - // Wait address is acknowledged - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle); - - // Read all bytes except last one - for (count = 0; count < (length - 1); count++) { - value = i2c_byte_read(obj, 0); - data[count] = (char)value; - } - - // If not repeated start, send stop. - // Warning: must be done BEFORE the data is read. - if (stop) { - i2c_stop(obj); - } - - // Read the last byte - value = i2c_byte_read(obj, 1); - data[count] = (char)value; - - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int timeout; - int count; - - // Generate start condition - i2c_start(obj); - - // Send address for write - i2c->DR = __HAL_I2C_7BIT_ADD_WRITE(address); - - // Wait address is acknowledged - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) { - timeout--; - if (timeout == 0) { - return -1; - } - } - __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle); - - // Write all bytes - for (count = 0; count < length; count++) { - if (i2c_byte_write(obj, data[count]) != 1) { - i2c_stop(obj); - return -1; - } - } - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); - } - - return count; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - if (last) { - // Don't acknowledge the last byte - i2c->CR1 &= ~I2C_CR1_ACK; - } else { - // Acknowledge the byte - i2c->CR1 |= I2C_CR1_ACK; - } - - // Wait until the byte is received - timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { - if ((timeout--) == 0) { - return -1; - } - } - - return (int)i2c->DR; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - int timeout; - - i2c->DR = (uint8_t)data; - - // Wait until the byte is transmitted - timeout = FLAG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) && - (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == RESET)) { - if ((timeout--) == 0) { - return 0; - } - } - - return 1; -} - -void i2c_reset(i2c_t *obj) -{ - int timeout; - - // Wait before reset - timeout = LONG_TIMEOUT; - while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0)); - - if (obj->i2c == I2C_1) { - __I2C1_FORCE_RESET(); - __I2C1_RELEASE_RESET(); - } - - if (obj->i2c == I2C_2) { - __I2C2_FORCE_RESET(); - __I2C2_RELEASE_RESET(); - } -} - -#if DEVICE_I2CSLAVE - -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) -{ - I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c); - uint16_t tmpreg = 0; - - // Get the old register value - tmpreg = i2c->OAR1; - // Reset address bits - tmpreg &= 0xFC00; - // Set new address - tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits - // Store the new register value - i2c->OAR1 = tmpreg; -} - -void i2c_slave_mode(i2c_t *obj, int enable_slave) -{ - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - if (enable_slave) { - obj->slave = 1; - /* Enable Address Acknowledge */ - I2cHandle.Instance->CR1 |= I2C_CR1_ACK; - } -} - -// See I2CSlave.h -#define NoData 0 // the slave has not been addressed -#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) -#define WriteGeneral 2 // the master is writing to all slave -#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) - -int i2c_slave_receive(i2c_t *obj) -{ - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - int retValue = NoData; - - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) { - if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TRA) == 1) { - retValue = ReadAddressed; - } else { - retValue = WriteAddressed; - } - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR); - } - } - - return (retValue); -} - -int i2c_slave_read(i2c_t *obj, char *data, int length) -{ - uint32_t Timeout; - int size = 0; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - while (length > 0) { - // Wait until RXNE flag is set - // Wait until the byte is received - Timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) { - Timeout--; - if (Timeout == 0) { - return -1; - } - } - - // Read data - (*data++) = I2cHandle.Instance->DR; - length--; - size++; - - if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) { - // Read data - (*data++) = I2cHandle.Instance->DR; - length--; - size++; - } - } - - // Wait until STOP flag is set - Timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) { - Timeout--; - if (Timeout == 0) { - return -1; - } - } - - // Clear STOP flag - __HAL_I2C_CLEAR_STOPFLAG(&I2cHandle); - - // Wait until BUSY flag is reset - Timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) { - Timeout--; - if (Timeout == 0) { - return -1; - } - } - - return size; -} - -int i2c_slave_write(i2c_t *obj, const char *data, int length) -{ - uint32_t Timeout; - int size = 0; - - I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c); - - while (length > 0) { - // Wait until TXE flag is set - Timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) { - Timeout--; - if (Timeout == 0) { - return -1; - } - } - - // Write data - I2cHandle.Instance->DR = (*data++); - length--; - size++; - - if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) { - // Write data to DR - I2cHandle.Instance->DR = (*data++); - length--; - size++; - } - } - - // Wait until AF flag is set - Timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_AF) == RESET) { - Timeout--; - if (Timeout == 0) { - return -1; - } - } - - // Clear AF flag - __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF); - - // Wait until BUSY flag is reset - Timeout = FLAG_TIMEOUT; - while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) { - Timeout--; - if (Timeout == 0) { - return -1; - } - } - - return size; -} - - -#endif // DEVICE_I2CSLAVE - -#endif // DEVICE_I2C diff --git a/targets/TARGET_STM/TARGET_STM32F1/i2c_device.h b/targets/TARGET_STM/TARGET_STM32F1/i2c_device.h new file mode 100644 index 00000000000..50d48118c95 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/i2c_device.h @@ -0,0 +1,48 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_I2C_DEVICE_H +#define MBED_I2C_DEVICE_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef DEVICE_I2C + +/* Define IP version */ +#define I2C_IP_VERSION_V1 + +#define I2C_IT_ALL (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR) + +#endif // DEVICE_I2C + +#endif diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c index 2c2dbb59510..916179163e9 100644 --- a/targets/TARGET_STM/i2c_api.c +++ b/targets/TARGET_STM/i2c_api.c @@ -38,8 +38,6 @@ #include "cmsis.h" #include "pinmap.h" #include "PeripheralPins.h" -/* F1 HAL not ready to move to I2C common code - this is ongoing */ -#if !defined(__STM32F1xx_HAL_H) #include "i2c_device.h" // family specific defines #ifndef DEBUG_STDIO @@ -1016,6 +1014,4 @@ void i2c_abort_asynch(i2c_t *obj) { #endif // DEVICE_I2C_ASYNCH -#endif // STM32F1 - #endif // DEVICE_I2C diff --git a/targets/targets.json b/targets/targets.json index e9913959723..d57eec87bfb 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -722,7 +722,7 @@ "inherits": ["Target"], "detect_code": ["0700"], "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"], - "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "CAN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"], "release_versions": ["2", "5"], "device_name": "STM32F103RB" },