From 41d21537822d09e9d799c29d218b7026f11c728c Mon Sep 17 00:00:00 2001 From: pradeep-gr Date: Tue, 29 Nov 2016 20:11:59 +0530 Subject: [PATCH 1/3] flash A and B merged. add_fib.py will merge flash banks A and B in the binary output file when more than 316K binary is generated. Need updated daplink bootloader to flash >316K binary file by drag n drop.Refer pull request generated for flashalgo and daplink repo for more info.IAR lnker script modified for flash merge-640K and format changed as per IAR requirement. --- .../device/TOOLCHAIN_IAR/NCS36510.icf | 94 ++++++++++++------- tools/add_fib.py | 23 +++++ 2 files changed, 82 insertions(+), 35 deletions(-) diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf index 0c090199972..ae7224ea760 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf @@ -1,49 +1,73 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_1.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00003000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00003000; /* FLASHA program start*/ +define symbol __ICFEDIT_region_IROM1_end__ = 0x00051FFF; /* 316K = 320K - 4K(FIB table), FLASHA end */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x00102000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x00151FFF; /* 320K */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; -/* The memory space denoting the maximum possible amount of addressable memory */ -define memory Mem with size = 4G; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x3FFFC000; /* RAMA start */ +define symbol __ICFEDIT_region_IRAM1_end__ = 0x3FFFFFFF; /* RAMA end */ +define symbol __ICFEDIT_region_IRAM2_start__ = 0x3FFF8000; /* RAMB start */ +define symbol __ICFEDIT_region_IRAM2_end__ = 0x3FFFBFFF; /* RAMB end */ +define symbol __ICFEDIT_region_IRAM3_start__ = 0x3FFF4000; /* RAMC start */ +define symbol __ICFEDIT_region_IRAM3_end__ = 0x3FFF7FFF; /* RAMC end */ +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; -/* Memory regions in an address space */ -define region FLASHA = Mem:[from 0x00003000 size 0x4D000]; /* 308K = 320K - 4K(FIB table) - 8K(Persistent) */ -define region FLASHB = Mem:[from 0x00100000 size 0x50000]; -define region RAMA = Mem:[from 0x3FFFC000 size 0x4000]; -define region RAMB = Mem:[from 0x3FFF8000 size 0x4000]; -/* G2H ZPRO requires RAMC to be enabled */ -define region RAMC = Mem:[from 0x3FFF4000 size 0x4000]; -define region RAM_ALL = Mem:[from 0x3FFF4000 size 0xC000]; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_heap__ = 0x4000; +/**** End of ICF editor section. ###ICF###*/ -/* Create a stack */ -define block CSTACK with size = 0x200, alignment = 8 { }; -/* No Heap is created for C library, all memory management should be handled by the application */ - define block HEAP with alignment = 8, size = 0x4000 { }; +define memory mem with size = 4G; +define region FLASH_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; -/* Handle initialization */ -do not initialize { section .noinit }; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__] + | mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_end__]; + + +/* Define overlays for MIB's, ths allows view of one MIB from a application level while + * MAC and PHY only know about their own MIB */ +define overlay MIBOVERLAY { section MIBSTARTSECTION }; +define overlay MIBOVERLAY { section MIBSECTION }; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -/* Initialize RW sections, exclude zero-initialized sections */ -initialize by copy with packing = none { readwrite }; +initialize by copy { readwrite }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + // Required in a multi-threaded application + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} /* Initialize the code in RAM, copied over from FLASH */ initialize by copy with packing = none { readonly code section EXECINRAM }; -/*keep { readonly code section .EXECINRAM* } except { readonly code section EXECINRAM };*/ - -/* Place startup code at a fixed address */ -place at start of FLASHA { readonly section .intvec, readonly section SWVERSION,readonly section FIBTABLE,readonly section .cstartup }; -/* Place code and data */ +/*initialize by copy { readwrite };*/ +do not initialize { section .noinit }; -/* Place constants and initializers in FLASHA: .rodata and .data_init */ -place in FLASHA { readonly }; -/* Place .data, .bss, and .noinit */ -/* and STACK */ -/* The relocatable exception table needs to be aligned at 0x0 or multiple of 0x100, - * hence, place it as first block in RAM. - */ -place at start of RAM_ALL { section RAM_VECTORS }; -place in RAM_ALL { readonly code section EXECINRAM }; -place at end of RAM_ALL { block CSTACK }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec, readonly section SWVERSION, readonly section FIBTABLE }; +place in FLASH_region { readonly section .cstartup, readonly }; -place in RAM_ALL { readwrite }; -place in RAM_ALL { block HEAP }; +place in RAM_region { readwrite, block HEAP, section XHEAP, readonly code section EXECINRAM, overlay MIBOVERLAY, readwrite section MIBENDSECTION, block CSTACK}; \ No newline at end of file diff --git a/tools/add_fib.py b/tools/add_fib.py index f884a118c5f..20fb32f5706 100644 --- a/tools/add_fib.py +++ b/tools/add_fib.py @@ -16,6 +16,7 @@ import binascii import intelhex from tools.config import Config +import sys FIB_BASE = 0x2000 FLASH_BASE = 0x3000 @@ -29,6 +30,24 @@ def ranges(i): def add_fib_at_start(arginput): + import os +# Take binary file back up to '_orig.bin' + filesize = os.path.getsize(arginput + ".bin") + if filesize > 0x4F000: +# Remove gap between Flash A and B + origfile = open(arginput + ".bin", "rb") + newfile = open(arginput + "_new.bin", "wb") + FlashA = origfile.read(0x4F000) + newfile.write(FlashA) + origfile.seek(0xFF000) + FlashB = origfile.read(filesize) + newfile.write(FlashB) + newfile.close() + origfile.close() + Origfile = arginput + ".bin" + Newfile = arginput + "_new.bin" + os.remove(Origfile) + os.rename(Newfile, Origfile) input_file = arginput + ".bin" file_name_hex = arginput + "_fib.hex" file_name_bin = arginput + ".bin" @@ -213,3 +232,7 @@ def add_fib_at_start(arginput): # Write out file(s) output_hex_file.tofile(file_name_hex, 'hex') output_hex_file.tofile(file_name_bin, 'bin') + +if __name__ == '__main__': + arginput = sys.argv[1] + add_fib_at_start(arginput) From 079aedf2531e23a504b5f1ca761ec87033792f0f Mon Sep 17 00:00:00 2001 From: pradeep-gr Date: Tue, 20 Dec 2016 18:02:42 +0530 Subject: [PATCH 2/3] GCC linker script changes to enable both flash banks A and B in NCS36510. Linker places feature specific and application code in Flash B while the rest of the mbed-os including rtos is placed in Flash A. --- .../device/TOOLCHAIN_GCC_ARM/NCS36510.ld | 103 +++++------------- 1 file changed, 27 insertions(+), 76 deletions(-) diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld index 6076d11859d..fd4a467f30e 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld @@ -4,8 +4,9 @@ MEMORY { VECTORS (rx) : ORIGIN = 0x00003000, LENGTH = 0x00000090 - FLASH (rx) : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90 - RAM (rwx) : ORIGIN = 0x3FFF4000, LENGTH = 48K + FLASHA (rx) : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90 + FLASHB (rx) : ORIGIN = 0x00102000, LENGTH = 320K + RAM (rwx) : ORIGIN = 0x3FFF4000, LENGTH = 48K } /* Linker script to place sections and symbol values. Should be used together @@ -37,47 +38,24 @@ MEMORY { ENTRY(Reset_Handler) SECTIONS { -.isr_vector : + .isr_vector : { __vector_table = .; KEEP(*(.vector_table)) . = ALIGN(4); } > VECTORS - /* ensure that uvisor bss is at the beginning of memory */ - .uvisor.bss (NOLOAD): + mbed_rtos_start = .; + .text_mbed_rtos : /* Place mbed-os and HAL code in FlashA */ { - . = ALIGN(32); - __uvisor_bss_start = .; - - /* protected uvisor main bss */ - . = ALIGN(32); - __uvisor_bss_main_start = .; - KEEP(*(.keep.uvisor.bss.main)) - . = ALIGN(32); - __uvisor_bss_main_end = .; - - /* protected uvisor secure boxes bss */ - . = ALIGN(32); - __uvisor_bss_boxes_start = .; - KEEP(*(.keep.uvisor.bss.boxes)) - . = ALIGN(32); - __uvisor_bss_boxes_end = .; - - . = ALIGN(32); - __uvisor_bss_end = .; - } > RAM - -.text : - { - /* uVisor code and data */ - . = ALIGN(4); - __uvisor_main_start = .; - *(.uvisor.main) - __uvisor_main_end = .; - - *(.text*) - + + *drivers/*.o(.text* .rodata*) + *events/*.o(.text* .rodata*) + *hal/*.o(.text* .rodata*) + *platform/*.o(.text* .rodata*) + *rtos/*.o(.text* .rodata*) + *targets/*.o(.text* .rodata*) + KEEP(*(.init)) KEEP(*(.fini)) @@ -95,22 +73,29 @@ MEMORY { *(SORT(.dtors.*)) *(.dtors) - *(.rodata*) - KEEP(*(.eh_frame*)) - } > FLASH + + } > FLASHA + mbed_rtos_end = .; + size_of_mbed_rtos = mbed_rtos_end - mbed_rtos_start; .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH + } > FLASHA .ARM.exidx : { __exidx_start = .; *(.ARM.exidx* .gnu.linkonce.armexidx.*) __exidx_end = .; - } > FLASH + } > FLASHA + +.text : /* Place the remaining application and feature specific code in FlashB */ + { + *(.text*) + *(.rodata*) + } > FLASHB .data : { @@ -144,41 +129,7 @@ MEMORY { . = ALIGN(32); __data_end__ = .; - } >RAM AT>FLASH - - /* uvisor configuration data */ -.uvisor.secure : - { - . = ALIGN(32); - __uvisor_secure_start = .; - - /* uvisor secure boxes configuration tables */ - . = ALIGN(32); - __uvisor_cfgtbl_start = .; - KEEP(*(.keep.uvisor.cfgtbl)) - . = ALIGN(32); - __uvisor_cfgtbl_end = .; - - /* pointers to uvisor secure boxes configuration tables */ - /* note: no further alignment here, we need to have the exact list of pointers */ - __uvisor_cfgtbl_ptr_start = .; - KEEP(*(.keep.uvisor.cfgtbl_ptr_first)) - KEEP(*(.keep.uvisor.cfgtbl_ptr)) - __uvisor_cfgtbl_ptr_end = .; - - /* the following symbols are kept for backward compatibility and will be soon - * deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED) - * will need to use uVisor 0.8.x or above, or the security assetions will halt the - * system */ - /************************/ - __uvisor_data_src = .; - __uvisor_data_start = .; - __uvisor_data_end = .; - /************************/ - - . = ALIGN(32); - __uvisor_secure_end = .; - } >FLASH + } >RAM AT>FLASHB .uninitialized (NOLOAD): { From 7b84bf1bec555f4771280ee4c3bcd7ebdc15ad4a Mon Sep 17 00:00:00 2001 From: pradeep-gr Date: Tue, 17 Jan 2017 18:33:28 +0530 Subject: [PATCH 3/3] I2C fix added. SPI slave fix added and SPISLAVE enabled --- targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h | 12 +++-- .../TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c | 7 ++- .../TARGET_NCS36510/ncs36510_i2c.c | 53 +++++++++++-------- .../TARGET_ONSEMI/TARGET_NCS36510/spi_api.c | 16 +++--- targets/targets.json | 2 +- 5 files changed, 53 insertions(+), 37 deletions(-) diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h index 15abc34edd2..b5a1e873299 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h @@ -83,14 +83,18 @@ #define I2C_APB_CLK_DIVIDER_VAL_MASK 0x1FE0 /* Error check */ -#define I2C_UFL_CHECK (d->membase->STATUS.WORD & 0x80) -#define FIFO_OFL_CHECK (d->membase->STATUS.WORD & 0x10) -#define I2C_BUS_ERR_CHECK (d->membase->STATUS.WORD & 0x04) -#define RD_DATA_READY (d->membase->STATUS.WORD & 0x02) +#define I2C_UFL_CHECK (obj->membase->STATUS.WORD & 0x80) +#define I2C_FIFO_FULL (obj->membase->STATUS.WORD & 0x20) +#define FIFO_OFL_CHECK (obj->membase->STATUS.WORD & 0x10) +#define I2C_BUS_ERR_CHECK (obj->membase->STATUS.WORD & 0x04) +#define RD_DATA_READY (obj->membase->STATUS.WORD & 0x02) +#define I2C_FIFO_EMPTY (obj->membase->STATUS.WORD & 0x01) #define I2C_API_STATUS_SUCCESS 0 #define PAD_REG_ADRS_BYTE_SIZE 4 +#define SEND_COMMAND(cmd) while(!I2C_FIFO_EMPTY); wait_us(1); obj->membase->CMD_REG = cmd; + /** Init I2C device. * @details * Sets the necessary registers. The baud rate is set default to 100K diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c index 8b254c8c907..6e19e925882 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c @@ -31,6 +31,7 @@ #include "i2c.h" #include "i2c_api.h" +#include "wait_api.h" #define I2C_READ_WRITE_BIT_MASK 0xFE @@ -151,10 +152,10 @@ int i2c_byte_read(i2c_t *obj, int last) /* TODO return size can be uint8_t */ } if(last) { /* ACK */ - obj->membase->CMD_REG = I2C_CMD_WDAT0; + SEND_COMMAND(I2C_CMD_WDAT0); } else { /* No ACK */ - obj->membase->CMD_REG = I2C_CMD_WDAT1; + SEND_COMMAND(I2C_CMD_WDAT1); } return data; } @@ -168,8 +169,6 @@ int i2c_byte_write(i2c_t *obj, int data) return Count; } - obj->membase->CMD_REG = I2C_CMD_VRFY_ACK; /* Verify ACK */ - while(obj->membase->STATUS.WORD & I2C_STATUS_CMD_FIFO_OFL_BIT); /* Wait till command overflow ends */ if(obj->membase->STATUS.WORD & I2C_STATUS_BUS_ERR_BIT) { diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c index 784ea31bc1c..37235965d66 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c @@ -60,6 +60,7 @@ */ #if DEVICE_I2C #include "i2c.h" +#include "wait_api.h" /* See i2c.h for details */ void fI2cInit(i2c_t *obj,PinName sda,PinName scl) @@ -135,7 +136,7 @@ void fI2cFrequency(i2c_t *obj, uint32_t hz) int32_t fI2cStart(i2c_t *obj) { /* Send start bit */ - obj->membase->CMD_REG = I2C_CMD_START; + SEND_COMMAND(I2C_CMD_START) return I2C_API_STATUS_SUCCESS; } @@ -143,7 +144,7 @@ int32_t fI2cStart(i2c_t *obj) int32_t fI2cStop(i2c_t *obj) { /* Send stop bit */ - obj->membase->CMD_REG = I2C_CMD_STOP; + SEND_COMMAND(I2C_CMD_STOP); if (obj->membase->STATUS.WORD & (I2C_STATUS_CMD_FIFO_FULL_BIT | I2C_STATUS_CMD_FIFO_OFL_BIT | I2C_STATUS_BUS_ERR_BIT)) { @@ -154,23 +155,26 @@ int32_t fI2cStop(i2c_t *obj) } /* See i2c.h for details */ -int32_t fI2cReadB(i2c_t *d, char *buf, int len) +int32_t fI2cReadB(i2c_t *obj, char *buf, int len) { int32_t read = 0; while (read < len) { /* Send read command */ - d->membase->CMD_REG = I2C_CMD_RDAT8; + SEND_COMMAND(I2C_CMD_RDAT8); while(!RD_DATA_READY) { if (I2C_BUS_ERR_CHECK) { /* Bus error occured */ return I2C_ERROR_BUS_BUSY; } } - buf[read++] = d->membase->RD_FIFO_REG; /**< Reading 'read FIFO register' will clear status register */ + buf[read++] = obj->membase->RD_FIFO_REG; /**< Reading 'read FIFO register' will clear status register */ if(!(read>=len)) { /* No ACK will be generated for the last read, upper level I2C protocol should generate */ - d->membase->CMD_REG=I2C_CMD_WDAT0; /* TODO based on requirement generate ACK or NACK Based on the requirement. */ + SEND_COMMAND(I2C_CMD_WDAT0); /* TODO based on requirement generate ACK or NACK Based on the requirement. */ + } else { + /* No ack */ + SEND_COMMAND(I2C_CMD_WDAT1); } /* check for FIFO underflow */ @@ -187,39 +191,46 @@ int32_t fI2cReadB(i2c_t *d, char *buf, int len) } /* See i2c.h for details */ -int32_t fI2cWriteB(i2c_t *d, const char *buf, int len) +int32_t fI2cWriteB(i2c_t *obj, const char *buf, int len) { int32_t write = 0; while (write < len) { /* Send write command */ - d->membase->CMD_REG = I2C_CMD_WDAT8; + SEND_COMMAND(I2C_CMD_WDAT8); + if(buf[write] == I2C_CMD_RDAT8) { /* SW work around to counter FSM issue. If the only command in the CMD FIFO is the WDAT8 command (data of 0x13) then as the command is read out (i.e. the FIFO goes empty), the WDAT8 command will be misinterpreted as a RDAT8 command by the data FSM; resulting in an I2C bus error (NACK instead of an ACK). */ /* Send 0x13 bit wise */ - d->membase->CMD_REG = I2C_CMD_WDAT0; - d->membase->CMD_REG = I2C_CMD_WDAT0; - d->membase->CMD_REG = I2C_CMD_WDAT0; - d->membase->CMD_REG = I2C_CMD_WDAT1; - - d->membase->CMD_REG = I2C_CMD_WDAT0; - d->membase->CMD_REG = I2C_CMD_WDAT0; - d->membase->CMD_REG = I2C_CMD_WDAT1; - d->membase->CMD_REG = I2C_CMD_WDAT1; + SEND_COMMAND(I2C_CMD_WDAT0); + + SEND_COMMAND(I2C_CMD_WDAT0); + + SEND_COMMAND(I2C_CMD_WDAT0); + + SEND_COMMAND(I2C_CMD_WDAT1); + + SEND_COMMAND(I2C_CMD_WDAT0); + + SEND_COMMAND(I2C_CMD_WDAT0); + + SEND_COMMAND(I2C_CMD_WDAT1); + + SEND_COMMAND(I2C_CMD_WDAT1); } else { /* Send data */ - d->membase->CMD_REG = buf[write++]; + SEND_COMMAND(buf[write++]); } - d->membase->CMD_REG = I2C_CMD_VRFY_ACK; /* TODO Verify ACK based on requirement, Do we need? */ - - while(FIFO_OFL_CHECK); /* Wait till command overflow ends */ + SEND_COMMAND(I2C_CMD_VRFY_ACK); /* TODO Verify ACK based on requirement, Do we need? */ if (I2C_BUS_ERR_CHECK) { /* Bus error */ return I2C_ERROR_BUS_BUSY; } + + while(FIFO_OFL_CHECK); /* Wait till command overflow ends */ } return write; diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c index 2d96ec0be90..0ddbde820b8 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c @@ -57,14 +57,16 @@ void spi_free(spi_t *obj) void spi_format(spi_t *obj, int bits, int mode, int slave) { /* Clear word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */ - obj->membase->CONTROL.WORD &= ~(uint32_t)((True >> SPI_WORD_WIDTH_BIT_POS) | - (True >> SPI_SLAVE_MASTER_BIT_POS) | - (True >> SPI_CPOL_BIT_POS) | - (True >> SPI_CPHA_BIT_POS)); + obj->membase->CONTROL.WORD &= ~(uint32_t)((True << SPI_WORD_WIDTH_BIT_POS) | + (True << SPI_SLAVE_MASTER_BIT_POS) | + (True << SPI_CPOL_BIT_POS) | + (True << SPI_CPHA_BIT_POS)); /* Configure word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */ - obj->membase->CONTROL.WORD |= (uint32_t)(((bits >> 0x4) >> 6) | (!slave >> 5) | - ((mode >> 0x1) >> 4) | ((mode & 0x1) >> 3)); + obj->membase->CONTROL.WORD |= (uint32_t)(((bits >> 0x4) << SPI_WORD_WIDTH_BIT_POS) | + (!slave << SPI_SLAVE_MASTER_BIT_POS) | + ((mode >> 0x1) << SPI_CPOL_BIT_POS) | + ((mode & 0x1) << SPI_CPHA_BIT_POS)); } void spi_frequency(spi_t *obj, int hz) @@ -210,4 +212,4 @@ void spi_abort_asynch(spi_t *obj) } #endif /* DEVICE_SPI_ASYNCH */ -#endif /* DEVICE_SPI */ \ No newline at end of file +#endif /* DEVICE_SPI */ diff --git a/targets/targets.json b/targets/targets.json index aef822ea6e6..7808585e4a3 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2560,7 +2560,7 @@ "post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"}, "macros": ["CM3", "CPU_NCS36510", "TARGET_NCS36510", "LOAD_ADDRESS=0x3000"], "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], - "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "LOWPOWERTIMER", "TRNG"], + "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "LOWPOWERTIMER", "TRNG", "SPISLAVE"], "device_name": "NCS36510", "release_versions": ["2", "5"] },