diff --git a/TESTS/events/timing/main.cpp b/TESTS/events/timing/main.cpp index aa361d8dd28..6a7e0fcf6f6 100644 --- a/TESTS/events/timing/main.cpp +++ b/TESTS/events/timing/main.cpp @@ -104,7 +104,7 @@ void semaphore_timing_test() { // Test setup utest::v1::status_t test_setup(const size_t number_of_cases) { - GREENTEA_SETUP((number_of_cases+1)*TEST_EVENTS_TIMING_TIME, "default_auto"); + GREENTEA_SETUP((number_of_cases+1)*TEST_EVENTS_TIMING_TIME/1000, "default_auto"); return verbose_test_setup_handler(number_of_cases); } diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp index 1274151d0d4..811e7152544 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp @@ -24,7 +24,6 @@ #include "ble_conn_params.h" #include "btle_gap.h" -#include "btle_advertising.h" #include "custom/custom_helper.h" #include "ble/GapEvents.h" @@ -165,6 +164,10 @@ error_t btle_init(void) return ERROR_INVALID_PARAM; } + // Peer Manger must been initialised prior any other call to its API (this file and btle_security_pm.cpp) + pm_init(); + +#if (NRF_SD_BLE_API_VERSION <= 2) ble_gap_addr_t addr; if (sd_ble_gap_address_get(&addr) != NRF_SUCCESS) { return ERROR_INVALID_PARAM; @@ -172,6 +175,11 @@ error_t btle_init(void) if (sd_ble_gap_address_set(BLE_GAP_ADDR_CYCLE_MODE_NONE, &addr) != NRF_SUCCESS) { return ERROR_INVALID_PARAM; } +#else + ble_gap_privacy_params_t privacy_params = {0}; + privacy_params.privacy_mode = BLE_GAP_PRIVACY_MODE_OFF; + pm_privacy_set(&privacy_params); +#endif ASSERT_STATUS( softdevice_ble_evt_handler_set(btle_handler)); ASSERT_STATUS( softdevice_sys_evt_handler_set(sys_evt_dispatch)); @@ -219,12 +227,25 @@ static void btle_handler(ble_evt_t *p_ble_evt) gap.setConnectionHandle(handle); const Gap::ConnectionParams_t *params = reinterpret_cast(&(p_ble_evt->evt.gap_evt.params.connected.conn_params)); const ble_gap_addr_t *peer = &p_ble_evt->evt.gap_evt.params.connected.peer_addr; +#if (NRF_SD_BLE_API_VERSION <= 2) const ble_gap_addr_t *own = &p_ble_evt->evt.gap_evt.params.connected.own_addr; + gap.processConnectionEvent(handle, - role, - static_cast(peer->addr_type), peer->addr, - static_cast(own->addr_type), own->addr, - params); + role, + static_cast(peer->addr_type), peer->addr, + static_cast(own->addr_type), own->addr, + params); +#else + Gap::AddressType_t addr_type; + Gap::Address_t own_address; + gap.getAddress(&addr_type, own_address); + + gap.processConnectionEvent(handle, + role, + static_cast(peer->addr_type), peer->addr, + addr_type, own_address, + params); +#endif break; } diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h index 2e6fe3d9f7d..021dd50513b 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h @@ -24,7 +24,7 @@ extern "C" { #include "common/common.h" #include "ble_srv_common.h" -#include "nrf_ble.h" +#include "headers/nrf_ble.h" error_t btle_init(void); diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_advertising.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_advertising.cpp deleted file mode 100644 index cdaf6a4a49c..00000000000 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_advertising.cpp +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "common/common.h" - -#include "ble_advdata.h" -#include "btle.h" - -/**************************************************************************/ -/*! - @brief Starts the advertising process - - @returns -*/ -/**************************************************************************/ -error_t btle_advertising_start(void) -{ - ble_gap_adv_params_t adv_para = {0}; - - /* Set the default advertising parameters */ - adv_para.type = BLE_GAP_ADV_TYPE_ADV_IND; - adv_para.p_peer_addr = NULL; /* Undirected advertising */ - adv_para.fp = BLE_GAP_ADV_FP_ANY; - adv_para.p_whitelist = NULL; - adv_para.interval = (CFG_GAP_ADV_INTERVAL_MS * 8) / 5; /* Advertising - * interval in - * units of 0.625 - * ms */ - adv_para.timeout = CFG_GAP_ADV_TIMEOUT_S; - - ASSERT_STATUS( sd_ble_gap_adv_start(&adv_para)); - - return ERROR_NONE; -} diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp index 0b6b1d6a9cc..99059f6623a 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp @@ -57,7 +57,7 @@ void bleGattcEventHandler(const ble_evt_t *p_ble_evt) case BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP: if (sdSingleton.isActive()) { - sdSingleton.processDiscoverUUIDResponse(&p_ble_evt->evt.gattc_evt.params.char_val_by_uuid_read_rsp); + sdSingleton.processDiscoverUUIDResponse(&p_ble_evt->evt.gattc_evt); } break; diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_gap.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_gap.cpp index 5dbc372135f..8bc8600d7b1 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_gap.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_gap.cpp @@ -15,7 +15,7 @@ */ #include "common/common.h" -#include "nrf_ble_gap.h" +#include "headers/nrf_ble_gap.h" #include "ble_conn_params.h" static inline uint32_t msec_to_1_25msec(uint32_t interval_ms) ATTR_ALWAYS_INLINE ATTR_CONST; diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security.h index 4f863975ab3..3197e838818 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security.h @@ -84,6 +84,7 @@ ble_error_t btle_setLinkSecurity(Gap::Handle_t connectionHandle, SecurityManager */ ble_error_t btle_purgeAllBondingState(void); +#if (NRF_SD_BLE_API_VERSION <= 2) /** * Query the SoftDevice bond table to extract a whitelist containing the BLE * addresses and IRKs of bonded devices. @@ -98,6 +99,7 @@ ble_error_t btle_purgeAllBondingState(void); * @return BLE_ERROR_NONE Or appropriate error code indicating reason for failure. */ ble_error_t btle_createWhitelistFromBondTable(ble_gap_whitelist_t *p_whitelist); +#endif /** * Function to test whether a BLE address is generated using an IRK. diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security_pm.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security_pm.cpp index e29002d07ab..8b0c16175e1 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security_pm.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security_pm.cpp @@ -14,7 +14,7 @@ * limitations under the License. */ -#if defined(S130) || defined(S132) +#if defined(S130) || defined(S132) || defined(S140) #include "btle.h" #include "nRF5xn.h" @@ -94,10 +94,6 @@ btle_initializeSecurity(bool enableBonding, } } - if (pm_init() != NRF_SUCCESS) { - return BLE_ERROR_UNSPECIFIED; - } - // update default security parameters with function call parameters securityParameters.bond = enableBonding; securityParameters.mitm = requireMITM; @@ -393,6 +389,7 @@ void pm_handler(pm_evt_t const *p_event) } } +#if (NRF_SD_BLE_API_VERSION <= 2) ble_error_t btle_createWhitelistFromBondTable(ble_gap_whitelist_t *p_whitelist) { @@ -408,7 +405,7 @@ btle_createWhitelistFromBondTable(ble_gap_whitelist_t *p_whitelist) return BLE_ERROR_INVALID_STATE; } } - +#endif bool btle_matchAddressAndIrk(ble_gap_addr_t const * p_addr, ble_gap_irk_t const * p_irk) diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h index 22a32907c1b..af47fb98527 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h @@ -18,7 +18,7 @@ #define _CUSTOM_HELPER_H_ #include "common/common.h" -#include "nrf_ble.h" +#include "headers/nrf_ble.h" #include "ble/UUID.h" #include "ble/GattCharacteristic.h" diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp index a06de22ffd1..0dee44efbfc 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp @@ -14,7 +14,7 @@ * limitations under the License. */ #include "nRF5xCharacteristicDescriptorDiscoverer.h" -#include "nrf_ble_err.h" +#include "headers/nrf_ble_err.h" #include "ble/DiscoveredCharacteristicDescriptor.h" nRF5xCharacteristicDescriptorDiscoverer::nRF5xCharacteristicDescriptorDiscoverer() : @@ -136,6 +136,7 @@ void nRF5xCharacteristicDescriptorDiscoverer::processAttributeInformation( return; } +#if (NRF_SD_BLE_API_VERSION <= 2) // for all UUIDS found, process the discovery for (uint16_t i = 0; i < infos.count; ++i) { bool use_16bits_uuids = infos.format == BLE_GATTC_ATTR_INFO_FORMAT_16BIT; @@ -146,6 +147,27 @@ void nRF5xCharacteristicDescriptorDiscoverer::processAttributeInformation( // prepare the next round of descriptors discovery uint16_t startHandle = infos.attr_info[infos.count - 1].handle + 1; +#else + uint16_t startHandle; + // for all UUIDS found, process the discovery + if (infos.format == BLE_GATTC_ATTR_INFO_FORMAT_16BIT) { + for (uint16_t i = 0; i < infos.count; ++i) { + UUID uuid = UUID(infos.info.attr_info16[i].uuid.uuid); + discovery->process(infos.info.attr_info16[i].handle, uuid); + } + + // prepare the next round of descriptors discovery + startHandle = infos.info.attr_info16[infos.count - 1].handle + 1; + } else { + for (uint16_t i = 0; i < infos.count; ++i) { + UUID uuid = UUID(infos.info.attr_info128[i].uuid.uuid128, UUID::LSB); + discovery->process(infos.info.attr_info128[i].handle, uuid); + } + + // prepare the next round of descriptors discovery + startHandle = infos.info.attr_info128[infos.count - 1].handle + 1; + } +#endif uint16_t endHandle = discovery->getCharacteristic().getLastHandle(); if(startHandle > endHandle) { diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h index 285a4a12885..753e368f0fe 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h @@ -21,7 +21,7 @@ #include "ble/DiscoveredCharacteristic.h" #include "ble/CharacteristicDescriptorDiscovery.h" #include "ble/GattClient.h" -#include "nrf_ble_gattc.h" +#include "headers/nrf_ble_gattc.h" /** * @brief Manage the discovery of Characteristic descriptors diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp index a228a624d2b..f7d6996f4d8 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp @@ -16,7 +16,7 @@ #include "nRF5xDiscoveredCharacteristic.h" #include "nRF5xGattClient.h" -#include "nrf_ble_gatt.h" +#include "headers/nrf_ble_gatt.h" void nRF5xDiscoveredCharacteristic::setup(nRF5xGattClient *gattcIn, diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h index 7b4bfc82c7c..87ebbbf7679 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h @@ -18,7 +18,7 @@ #define __NRF_DISCOVERED_CHARACTERISTIC_H__ #include "ble/DiscoveredCharacteristic.h" -#include "nrf_ble_gatt.h" +#include "headers/nrf_ble_gatt.h" class nRF5xGattClient; /* forward declaration */ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.cpp index f874bfefe52..56c9218feeb 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.cpp @@ -24,7 +24,13 @@ #include "common/common.h" #include "ble_advdata.h" -#include "nrf_ble_hci.h" +#include "headers/nrf_ble_hci.h" + +#if (NRF_SD_BLE_API_VERSION >= 3) + #include "peer_manager.h" + #include "peer_data_storage.h" +#endif + void radioNotificationStaticCallback(bool param) { nRF5xGap &gap = (nRF5xGap &) nRF5xn::Instance(BLE::DEFAULT_INSTANCE).getGap(); @@ -135,6 +141,9 @@ ble_error_t nRF5xGap::setAdvertisingData(const GapAdvertisingData &advData, cons /**************************************************************************/ ble_error_t nRF5xGap::startAdvertising(const GapAdvertisingParams ¶ms) { + uint32_t err; + ble_gap_adv_params_t adv_para = {0}; + /* Make sure we support the advertising type */ if (params.getAdvertisingType() == GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) { /* ToDo: This requires a propery security implementation, etc. */ @@ -168,6 +177,7 @@ ble_error_t nRF5xGap::startAdvertising(const GapAdvertisingParams ¶ms) return BLE_ERROR_PARAM_OUT_OF_RANGE; } +#if (NRF_SD_BLE_API_VERSION <= 2) /* Allocate the stack's whitelist statically */ ble_gap_whitelist_t whitelist; ble_gap_addr_t *whitelistAddressPtrs[YOTTA_CFG_WHITELIST_MAX_SIZE]; @@ -185,18 +195,22 @@ ble_error_t nRF5xGap::startAdvertising(const GapAdvertisingParams ¶ms) return error; } } - + + adv_para.p_whitelist = &whitelist; +#endif + /* For NRF_SD_BLE_API_VERSION >= 3 nRF5xGap::setWhitelist setups the whitelist. */ + /* Start Advertising */ - ble_gap_adv_params_t adv_para = {0}; + adv_para.type = params.getAdvertisingType(); adv_para.p_peer_addr = NULL; // Undirected advertisement adv_para.fp = advertisingPolicyMode; - adv_para.p_whitelist = &whitelist; adv_para.interval = params.getIntervalInADVUnits(); // advertising interval (in units of 0.625 ms) adv_para.timeout = params.getTimeout(); + - uint32_t err = sd_ble_gap_adv_start(&adv_para); + err = sd_ble_gap_adv_start(&adv_para); switch(err) { case ERROR_NONE: return BLE_ERROR_NONE; @@ -211,6 +225,10 @@ ble_error_t nRF5xGap::startAdvertising(const GapAdvertisingParams ¶ms) #if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110) ble_error_t nRF5xGap::startRadioScan(const GapScanningParams &scanningParams) { + + ble_gap_scan_params_t scanParams; + +#if (NRF_SD_BLE_API_VERSION <= 2) /* Allocate the stack's whitelist statically */ ble_gap_whitelist_t whitelist; ble_gap_addr_t *whitelistAddressPtrs[YOTTA_CFG_WHITELIST_MAX_SIZE]; @@ -229,11 +247,17 @@ ble_error_t nRF5xGap::startRadioScan(const GapScanningParams &scanningParams) } } - ble_gap_scan_params_t scanParams; - - scanParams.active = scanningParams.getActiveScanning(); /**< If 1, perform active scanning (scan requests). */ scanParams.selective = scanningPolicyMode; /**< If 1, ignore unknown devices (non whitelisted). */ scanParams.p_whitelist = &whitelist; /**< Pointer to whitelist, NULL if none is given. */ +#else + /* For NRF_SD_BLE_API_VERSION >= 3 nRF5xGap::setWhitelist setups the whitelist. */ + + scanParams.use_whitelist = scanningPolicyMode; + scanParams.adv_dir_report = 0; +#endif + + scanParams.active = scanningParams.getActiveScanning(); /**< If 1, perform active scanning (scan requests). */ + scanParams.interval = scanningParams.getInterval(); /**< Scan interval between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */ scanParams.window = scanningParams.getWindow(); /**< Scan window between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */ scanParams.timeout = scanningParams.getTimeout(); /**< Scan timeout between 0x0001 and 0xFFFF in seconds, 0x0000 disables timeout. */ @@ -302,6 +326,9 @@ ble_error_t nRF5xGap::connect(const Address_t peerAddr, connParams.conn_sup_timeout = 600; } + ble_gap_scan_params_t scanParams ={0}; + +#if (NRF_SD_BLE_API_VERSION <= 2) /* Allocate the stack's whitelist statically */ ble_gap_whitelist_t whitelist; ble_gap_addr_t *whitelistAddressPtrs[YOTTA_CFG_WHITELIST_MAX_SIZE]; @@ -319,10 +346,28 @@ ble_error_t nRF5xGap::connect(const Address_t peerAddr, return error; } } - - ble_gap_scan_params_t scanParams; + scanParams.selective = scanningPolicyMode; /**< If 1, ignore unknown devices (non whitelisted). */ scanParams.p_whitelist = &whitelist; /**< Pointer to whitelist, NULL if none is given. */ +#else + /* For NRF_SD_BLE_API_VERSION >= 3 nRF5xGap::setWhitelist setups the whitelist. */ + + scanParams.use_whitelist = (whitelistAddressesSize) ? 1 : 0; + + if ((addr.addr_type == BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE) + || (addr.addr_type == BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE)) { + /* If a device is using Resolvable Private Addresses Section 1.3.2.2 (Core spec v4.2 volume 6 part B), + it shall also have an Identity Address that is either a Public or Random Static address type.” + To establish a connection, a static address must be provided by the application to the SoftDevice. + The SoftDevice resolves the address and connects to the right device if it is available. */ + addr.addr_id_peer = 1; + addr.addr_type = BLE_GAP_ADDR_TYPE_PUBLIC; + } else { + addr.addr_id_peer = 0; + } + +#endif + if (scanParamsIn != NULL) { scanParams.active = scanParamsIn->getActiveScanning(); /**< If 1, perform active scanning (scan requests). */ scanParams.interval = scanParamsIn->getInterval(); /**< Scan interval between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */ @@ -447,6 +492,7 @@ ble_error_t nRF5xGap::reset(void) /* Clear the internal whitelist */ whitelistAddressesSize = 0; + return BLE_ERROR_NONE; } @@ -489,7 +535,13 @@ uint16_t nRF5xGap::getConnectionHandle(void) /**************************************************************************/ ble_error_t nRF5xGap::setAddress(AddressType_t type, const Address_t address) { +#if (NRF_SD_BLE_API_VERSION <= 2) uint8_t cycle_mode; +#else + ble_gap_privacy_params_t privacy_params = {0}; +#endif + + ble_gap_addr_t dev_addr; /* When using Public or Static addresses, the cycle mode must be None. @@ -498,12 +550,27 @@ ble_error_t nRF5xGap::setAddress(AddressType_t type, const Address_t address) */ if ((type == BLEProtocol::AddressType::PUBLIC) || (type == BLEProtocol::AddressType::RANDOM_STATIC)) { + memcpy(dev_addr.addr, address, ADDR_LEN); +#if (NRF_SD_BLE_API_VERSION <= 2) cycle_mode = BLE_GAP_ADDR_CYCLE_MODE_NONE; - memcpy(dev_addr.addr, address, ADDR_LEN); +#else + privacy_params.privacy_mode = BLE_GAP_PRIVACY_MODE_OFF; + dev_addr.addr_type = type; + + ASSERT_INT(ERROR_NONE, pm_id_addr_set(&dev_addr), BLE_ERROR_PARAM_OUT_OF_RANGE); + ASSERT_INT(ERROR_NONE, pm_privacy_set(&privacy_params), BLE_ERROR_PARAM_OUT_OF_RANGE); +#endif } else if ((type == BLEProtocol::AddressType::RANDOM_PRIVATE_RESOLVABLE) || (type == BLEProtocol::AddressType::RANDOM_PRIVATE_NON_RESOLVABLE)) { +#if (NRF_SD_BLE_API_VERSION <= 2) cycle_mode = BLE_GAP_ADDR_CYCLE_MODE_AUTO; +#else + privacy_params.privacy_mode = BLE_GAP_PRIVACY_MODE_DEVICE_PRIVACY; + privacy_params.private_addr_type = type; + + ASSERT_INT(ERROR_NONE, pm_privacy_set(&privacy_params), BLE_ERROR_PARAM_OUT_OF_RANGE); +#endif // address is ignored when in auto mode } else @@ -511,8 +578,10 @@ ble_error_t nRF5xGap::setAddress(AddressType_t type, const Address_t address) return BLE_ERROR_PARAM_OUT_OF_RANGE; } +#if (NRF_SD_BLE_API_VERSION <= 2) dev_addr.addr_type = type; ASSERT_INT(ERROR_NONE, sd_ble_gap_address_set(cycle_mode, &dev_addr), BLE_ERROR_PARAM_OUT_OF_RANGE); +#endif return BLE_ERROR_NONE; } @@ -520,7 +589,11 @@ ble_error_t nRF5xGap::setAddress(AddressType_t type, const Address_t address) ble_error_t nRF5xGap::getAddress(AddressType_t *typeP, Address_t address) { ble_gap_addr_t dev_addr; +#if (NRF_SD_BLE_API_VERSION <= 2) if (sd_ble_gap_address_get(&dev_addr) != NRF_SUCCESS) { +#else + if (sd_ble_gap_addr_get(&dev_addr) != NRF_SUCCESS) { +#endif return BLE_ERROR_PARAM_OUT_OF_RANGE; } @@ -599,6 +672,10 @@ void nRF5xGap::getPermittedTxPowerValues(const int8_t **valueArrayPP, size_t *co static const int8_t permittedTxValues[] = { -40, -20, -16, -12, -8, -4, 0, 4 }; +#elif defined(NRF52840_XXAA) + static const int8_t permittedTxValues[] = { + -40, -20, -16, -12, -8, -4, 0, 2, 3, 4, 5, 6, 7, 8, 9 + }; #else #error permitted TX power values unknown for this SOC #endif @@ -648,9 +725,12 @@ uint8_t nRF5xGap::getMaxWhitelistSize(void) const /**************************************************************************/ ble_error_t nRF5xGap::getWhitelist(Gap::Whitelist_t &whitelistOut) const { - uint8_t i; + uint32_t i; for (i = 0; i < whitelistAddressesSize && i < whitelistOut.capacity; ++i) { - memcpy(&whitelistOut.addresses[i], &whitelistAddresses[i], sizeof(BLEProtocol::Address_t)); + memcpy( &whitelistOut.addresses[i].address, &whitelistAddresses[i].addr, sizeof(whitelistOut.addresses[0].address)); + whitelistOut.addresses[i].type = static_cast (whitelistAddresses[i].addr_type); + + } whitelistOut.size = i; @@ -694,19 +774,24 @@ ble_error_t nRF5xGap::setWhitelist(const Gap::Whitelist_t &whitelistIn) } /* Test for invalid parameters before we change the internal state */ - for (uint8_t i = 0; i < whitelistIn.size; ++i) { + for (uint32_t i = 0; i < whitelistIn.size; ++i) { if (whitelistIn.addresses[i].type == BLEProtocol::AddressType::RANDOM_PRIVATE_NON_RESOLVABLE) { /* This is not allowed because it is completely meaningless */ return BLE_ERROR_INVALID_PARAM; } } - whitelistAddressesSize = 0; - for (uint8_t i = 0; i < whitelistIn.size; ++i) { - memcpy(&whitelistAddresses[whitelistAddressesSize], &whitelistIn.addresses[i], sizeof(BLEProtocol::Address_t)); - whitelistAddressesSize++; + whitelistAddressesSize = whitelistIn.size; + + for (uint32_t i = 0; i < whitelistIn.size; ++i) { + memcpy(&whitelistAddresses[i].addr , &whitelistIn.addresses[i].address , sizeof(whitelistAddresses[0].addr)); + whitelistAddresses[i].addr_type = static_cast (whitelistIn.addresses[i].type); } +#if (NRF_SD_BLE_API_VERSION >= 3) + updateWhiteAndIdentityListInStack(); +#endif + return BLE_ERROR_NONE; } @@ -846,6 +931,7 @@ Gap::InitiatorPolicyMode_t nRF5xGap::getInitiatorPolicyMode(void) const return Gap::INIT_POLICY_IGNORE_WHITELIST; } +#if (NRF_SD_BLE_API_VERSION <= 2) /**************************************************************************/ /*! @brief Helper function used to populate the ble_gap_whitelist_t that @@ -945,3 +1031,167 @@ ble_error_t nRF5xGap::generateStackWhitelist(ble_gap_whitelist_t &whitelist) return BLE_ERROR_NONE; } +#endif + +#if (NRF_SD_BLE_API_VERSION >= 3) + +/** + * Function for preparing settings of the whitelist feature and the identity-resolving feature (privacy) for the SoftDevice. + * + * Gap::setWhitelist provides the base for preparation of these settings. + * This function matches resolvable addresses (passed by Gap::setWhitelist) to IRK data in bonds table. + * Therefore resolvable addresses instead of being passed to the whitelist (intended to be passed to the Softdevice) + * are passed to the identities list (intended to be passed to the Softdevice). + * + * @param[out] gapAdrHelper Reference to the struct for storing settings. + */ + +ble_error_t nRF5xGap::getStackWhiteIdentityList(GapWhiteAndIdentityList_t &gapAdrHelper) +{ + pm_peer_id_t peer_id; + + ret_code_t ret; + + pm_peer_data_bonding_t bond_data; + + uint8_t irk_found[YOTTA_CFG_WHITELIST_MAX_SIZE]; + + memset(irk_found, 0x00, sizeof(irk_found)); + + + gapAdrHelper.identities_cnt = 0; + + + peer_id = pm_next_peer_id_get(PM_PEER_ID_INVALID); + + nRF5xSecurityManager& securityManager = (nRF5xSecurityManager&) nRF5xn::Instance(0).getSecurityManager(); + + /** + * Build identities list: + * For every private resolvable address in the bond table check if + * there is maching address in th provided whitelist. + */ + while (peer_id != PM_PEER_ID_INVALID) + { + memset(&bond_data, 0x00, sizeof(bond_data)); + + // Read peer data from flash. + ret = pm_peer_data_bonding_load(peer_id, &bond_data); + + + if ((ret == NRF_ERROR_NOT_FOUND) || (ret == NRF_ERROR_INVALID_PARAM)) + { + // Peer data could not be found in flash or peer ID is not valid. + return BLE_ERROR_UNSPECIFIED; + } + + if ( bond_data.peer_ble_id.id_addr_info.addr_type == BLEProtocol::AddressType::RANDOM_PRIVATE_RESOLVABLE) + { + for (uint8_t i = 0; i < whitelistAddressesSize; ++i) + { + if (!irk_found[i]) + { + if (whitelistAddresses[i].addr_type == BLEProtocol::AddressType::RANDOM_PRIVATE_RESOLVABLE) + { + + //ble_gap_irk_t *p_dfg = &bond_data.peer_ble_id.id_info; + if (securityManager.matchAddressAndIrk(&whitelistAddresses[i], &bond_data.peer_ble_id.id_info)) + { + // Copy data to the buffer. + memcpy(&gapAdrHelper.identities[i], &bond_data.peer_ble_id, sizeof(ble_gap_id_key_t)); + gapAdrHelper.identities_cnt++; + + irk_found[i] = 1; // don't look at this address again + } + } + } + } + } + + // get next peer id + peer_id = pm_next_peer_id_get(peer_id); + } + + gapAdrHelper.addrs_cnt = 0; + + /** + * Build whitelist from the rest of addresses (explicit addresses) + */ + for (uint8_t i = 0; i < whitelistAddressesSize; ++i) + { + if (!irk_found[i]) + { + memcpy(&gapAdrHelper.addrs[i], &whitelistAddresses[i], sizeof(ble_gap_addr_t)); + gapAdrHelper.addrs[i].addr_id_peer = 0; + gapAdrHelper.addrs_cnt++; + } + } + + return BLE_ERROR_NONE; +} + +ble_error_t nRF5xGap::applyWhiteIdentityList(GapWhiteAndIdentityList_t &gapAdrHelper) +{ + uint32_t retc; + + if (gapAdrHelper.identities_cnt == 0) { + retc = sd_ble_gap_device_identities_set(NULL, NULL, 0); + } else { + ble_gap_id_key_t * pp_identities[YOTTA_CFG_IRK_TABLE_MAX_SIZE]; + + for (uint32_t i = 0; i < gapAdrHelper.identities_cnt; ++i) + { + pp_identities[i] = &gapAdrHelper.identities[i]; + } + + retc = sd_ble_gap_device_identities_set(pp_identities, NULL /* Don't use local IRKs*/,gapAdrHelper.identities_cnt); + } + + if (retc == NRF_SUCCESS) { + if (gapAdrHelper.addrs_cnt == 0) { + retc = sd_ble_gap_whitelist_set(NULL, 0); + } else { + ble_gap_addr_t * pp_addrs[YOTTA_CFG_IRK_TABLE_MAX_SIZE]; + + for (uint32_t i = 0; i < gapAdrHelper.addrs_cnt; ++i) + { + pp_addrs[i] = &gapAdrHelper.addrs[i]; + } + + retc = sd_ble_gap_whitelist_set(pp_addrs, gapAdrHelper.addrs_cnt); + } + } + + switch(retc) { + case NRF_SUCCESS: + return BLE_ERROR_NONE; + + case BLE_ERROR_GAP_WHITELIST_IN_USE: //The whitelist is in use by a BLE role and cannot be set or cleared. + case BLE_ERROR_GAP_DEVICE_IDENTITIES_IN_USE: //The device identity list is in use and cannot be set or cleared. + return BLE_ERROR_ALREADY_INITIALIZED; + + case NRF_ERROR_INVALID_ADDR: + case BLE_ERROR_GAP_INVALID_BLE_ADDR: //Invalid address type is supplied. + case NRF_ERROR_DATA_SIZE: + case BLE_ERROR_GAP_DEVICE_IDENTITIES_DUPLICATE: //The device identity list contains multiple entries with the same identity address. + return BLE_ERROR_INVALID_PARAM; + + default: + return BLE_ERROR_UNSPECIFIED; + } +} + +ble_error_t nRF5xGap::updateWhiteAndIdentityListInStack() +{ + GapWhiteAndIdentityList_t whiteAndIdentityList; + uint32_t err; + + err = getStackWhiteIdentityList(whiteAndIdentityList); + + if (err != BLE_ERROR_NONE) { + return (ble_error_t)err; + } + + return applyWhiteIdentityList(whiteAndIdentityList); +} +#endif diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.h index cdcd9fa8fea..922260954a5 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.h @@ -29,13 +29,17 @@ #define YOTTA_CFG_WHITELIST_MAX_SIZE BLE_GAP_WHITELIST_ADDR_MAX_COUNT #endif #ifndef YOTTA_CFG_IRK_TABLE_MAX_SIZE - #define YOTTA_CFG_IRK_TABLE_MAX_SIZE BLE_GAP_WHITELIST_IRK_MAX_COUNT + #if (NRF_SD_BLE_API_VERSION >= 3) + #define YOTTA_CFG_IRK_TABLE_MAX_SIZE BLE_GAP_DEVICE_IDENTITIES_MAX_COUNT + #else + #define YOTTA_CFG_IRK_TABLE_MAX_SIZE BLE_GAP_WHITELIST_IRK_MAX_COUNT + #endif #elif YOTTA_CFG_IRK_TABLE_MAX_SIZE > BLE_GAP_WHITELIST_IRK_MAX_COUNT #undef YOTTA_CFG_IRK_TABLE_MAX_SIZE #define YOTTA_CFG_IRK_TABLE_MAX_SIZE BLE_GAP_WHITELIST_IRK_MAX_COUNT #endif #include "ble/blecommon.h" -#include "nrf_ble.h" +#include "headers/nrf_ble.h" #include "ble/GapAdvertisingParams.h" #include "ble/GapAdvertisingData.h" #include "ble/Gap.h" @@ -135,6 +139,7 @@ class nRF5xGap : public Gap uint8_t whitelistAddressesSize; ble_gap_addr_t whitelistAddresses[YOTTA_CFG_WHITELIST_MAX_SIZE]; +#if (NRF_SD_BLE_API_VERSION <= 2) /* * An internal function used to populate the ble_gap_whitelist_t that will be used by * the SoftDevice for filtering requests. This function is needed because for the BLE @@ -142,6 +147,30 @@ class nRF5xGap : public Gap * the IRK table. */ ble_error_t generateStackWhitelist(ble_gap_whitelist_t &whitelist); +#endif + +#if (NRF_SD_BLE_API_VERSION >= 3) + /* internal type for passing a whitelist and a identities list. */ + typedef struct + { + ble_gap_addr_t addrs[YOTTA_CFG_WHITELIST_MAX_SIZE]; + uint32_t addrs_cnt; + + ble_gap_id_key_t identities[YOTTA_CFG_IRK_TABLE_MAX_SIZE]; + uint32_t identities_cnt; + } GapWhiteAndIdentityList_t; + + /* Function for preparing setting of the whitelist feature and the identity-resolving feature (privacy).*/ + ble_error_t getStackWhiteIdentityList(GapWhiteAndIdentityList_t &whiteAndIdentityList); + + /* Function for applying setting of the whitelist feature and identity-resolving feature (privacy).*/ + ble_error_t applyWhiteIdentityList(GapWhiteAndIdentityList_t &whiteAndIdentityList); + + /* Function for introducing whitelist feature and the identity-resolving feature setting into SoftDevice. + * + * This function incorporates getStackWhiteIdentityList and applyWhiteIdentityList together. */ + ble_error_t updateWhiteAndIdentityListInStack(void); +#endif private: bool radioNotificationCallbackParam; /* parameter to be passed into the Timeout-generated radio notification callback. */ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.h index dc40f8b3619..77bfd26d908 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.h @@ -20,7 +20,7 @@ #include #include "ble/blecommon.h" -#include "nrf_ble.h" /* nordic ble */ +#include "headers/nrf_ble.h" /* nordic ble */ #include "ble/Gap.h" #include "ble/GattServer.h" diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xSecurityManager.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xSecurityManager.h index 2fa7b05511e..1b675806d93 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xSecurityManager.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xSecurityManager.h @@ -45,7 +45,7 @@ class nRF5xSecurityManager : public SecurityManager virtual ble_error_t purgeAllBondingState(void) { return btle_purgeAllBondingState(); } - +#if (NRF_SD_BLE_API_VERSION <= 2) /** * @brief Returns a list of addresses from peers in the stacks bond table. * @@ -57,6 +57,8 @@ class nRF5xSecurityManager : public SecurityManager * * @return * BLE_ERROR_NONE if successful. + * + * @todo check whether remove this function (because it is never called) */ virtual ble_error_t getAddressesFromBondTable(Gap::Whitelist_t &addresses) const { uint8_t i; @@ -112,7 +114,7 @@ class nRF5xSecurityManager : public SecurityManager return BLE_ERROR_NONE; } - +#endif /** * @brief Clear nRF5xSecurityManager's state. * @@ -146,6 +148,7 @@ class nRF5xSecurityManager : public SecurityManager nRF5xSecurityManager(const nRF5xSecurityManager &); const nRF5xSecurityManager& operator=(const nRF5xSecurityManager &); +#if (NRF_SD_BLE_API_VERSION <= 2) /* * Expose an interface that allows us to query the SoftDevice bond table * and extract a whitelist. @@ -153,7 +156,7 @@ class nRF5xSecurityManager : public SecurityManager ble_error_t createWhitelistFromBondTable(ble_gap_whitelist_t &whitelistFromBondTable) const { return btle_createWhitelistFromBondTable(&whitelistFromBondTable); } - +#endif /* * Given a BLE address and a IRK this function check whether the address * can be generated from the IRK. To do so, this function uses the hash diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp index 4bd0da6dd7b..87ac20c8ff0 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp @@ -281,12 +281,22 @@ nRF5xServiceDiscovery::CharUUIDDiscoveryQueue::triggerFirst(void) } void -nRF5xServiceDiscovery::processDiscoverUUIDResponse(const ble_gattc_evt_char_val_by_uuid_read_rsp_t *response) +nRF5xServiceDiscovery::processDiscoverUUIDResponse(const ble_gattc_evt_t *p_gattc_evt) { + const ble_gattc_evt_char_val_by_uuid_read_rsp_t * response = &p_gattc_evt->params.char_val_by_uuid_read_rsp; + if (state == DISCOVER_SERVICE_UUIDS) { if ((response->count == 1) && (response->value_len == UUID::LENGTH_OF_LONG_UUID)) { UUID::LongUUIDBytes_t uuid; - memcpy(uuid, response->handle_value[0].p_value, UUID::LENGTH_OF_LONG_UUID); + +#if (NRF_SD_BLE_API_VERSION >= 3) + ble_gattc_handle_value_t iter; + memset(&iter, 0, sizeof(ble_gattc_handle_value_t)); + (void) sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(const_cast(p_gattc_evt), &iter); + memcpy(uuid, iter.p_value, UUID::LENGTH_OF_LONG_UUID); +#else + memcpy(uuid, &(response->handle_value[0].p_value[0]), UUID::LENGTH_OF_LONG_UUID); +#endif unsigned serviceIndex = serviceUUIDDiscoveryQueue.dequeue(); services[serviceIndex].setupLongUUID(uuid, UUID::LSB); @@ -298,9 +308,16 @@ nRF5xServiceDiscovery::processDiscoverUUIDResponse(const ble_gattc_evt_char_val_ } else if (state == DISCOVER_CHARACTERISTIC_UUIDS) { if ((response->count == 1) && (response->value_len == UUID::LENGTH_OF_LONG_UUID + 1 /* props */ + 2 /* value handle */)) { UUID::LongUUIDBytes_t uuid; - + +#if (NRF_SD_BLE_API_VERSION >= 3) + ble_gattc_handle_value_t iter; + memset(&iter, 0, sizeof(ble_gattc_handle_value_t)); + (void) sd_ble_gattc_evt_char_val_by_uuid_read_rsp_iter(const_cast(p_gattc_evt), &iter); + memcpy(uuid, &(iter.p_value[3]), UUID::LENGTH_OF_LONG_UUID); +#else memcpy(uuid, &(response->handle_value[0].p_value[3]), UUID::LENGTH_OF_LONG_UUID); - +#endif + unsigned charIndex = charUUIDDiscoveryQueue.dequeue(); characteristics[charIndex].setupLongUUID(uuid, UUID::LSB); diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h index 20bf505936e..9fb28f1d798 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h @@ -21,8 +21,8 @@ #include "ble/DiscoveredService.h" #include "nRF5xDiscoveredCharacteristic.h" -#include "nrf_ble.h" -#include "nrf_ble_gattc.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gattc.h" class nRF5xGattClient; /* forward declaration */ @@ -139,7 +139,7 @@ class nRF5xServiceDiscovery : public ServiceDiscovery void setupDiscoveredCharacteristics(const ble_gattc_evt_char_disc_rsp_t *response); void triggerServiceUUIDDiscovery(void); - void processDiscoverUUIDResponse(const ble_gattc_evt_char_val_by_uuid_read_rsp_t *response); + void processDiscoverUUIDResponse(const ble_gattc_evt_t *p_gattc_evt); void removeFirstServiceNeedingUUIDDiscovery(void); void terminateServiceDiscovery(void) { diff --git a/features/FEATURE_LWIP/lwip-interface/emac_lwip.c b/features/FEATURE_LWIP/lwip-interface/emac_lwip.c index f79be5d4717..f189bb2a988 100644 --- a/features/FEATURE_LWIP/lwip-interface/emac_lwip.c +++ b/features/FEATURE_LWIP/lwip-interface/emac_lwip.c @@ -63,10 +63,13 @@ err_t emac_lwip_if_init(struct netif *netif) mac->ops.set_link_input_cb(mac, emac_lwip_input, netif); mac->ops.set_link_state_cb(mac, emac_lwip_state_change, netif); - netif->hwaddr_len = mac->ops.get_hwaddr_size(mac); - mac->ops.get_hwaddr(mac, netif->hwaddr); + if (!mac->ops.power_up(mac)) { + err = ERR_IF; + } netif->mtu = mac->ops.get_mtu_size(mac); + netif->hwaddr_len = mac->ops.get_hwaddr_size(mac); + mac->ops.get_hwaddr(mac, netif->hwaddr); /* Interface capabilities */ netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP; @@ -79,10 +82,6 @@ err_t emac_lwip_if_init(struct netif *netif) netif->linkoutput = emac_lwip_low_level_output; - if (!mac->ops.power_up(mac)) { - err = ERR_IF; - } - return err; } diff --git a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c index dffc1610fb7..8717ec4caf1 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c @@ -393,8 +393,6 @@ nsapi_error_t mbed_lwip_init(emac_interface_t *emac) // Check if we've already brought up lwip if (!mbed_lwip_get_mac_address()) { // Set up network - mbed_lwip_set_mac_address(); - sys_sem_new(&lwip_tcpip_inited, 0); sys_sem_new(&lwip_netif_linked, 0); sys_sem_new(&lwip_netif_has_addr, 0); @@ -411,6 +409,7 @@ nsapi_error_t mbed_lwip_init(emac_interface_t *emac) return NSAPI_ERROR_DEVICE_ERROR; } + mbed_lwip_set_mac_address(); netif_set_default(&lwip_netif); netif_set_link_callback(&lwip_netif, mbed_lwip_netif_link_irq); diff --git a/mbed.h b/mbed.h index fc2e09c1b6e..3f1c0e52be2 100644 --- a/mbed.h +++ b/mbed.h @@ -16,13 +16,13 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 142 +#define MBED_LIBRARY_VERSION 143 #if MBED_CONF_RTOS_PRESENT // RTOS present, this is valid only for mbed OS 5 #define MBED_MAJOR_VERSION 5 #define MBED_MINOR_VERSION 4 -#define MBED_PATCH_VERSION 5 +#define MBED_PATCH_VERSION 6 #else // mbed 2 diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/PeripheralNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/PeripheralNames.h new file mode 100644 index 00000000000..752684c7e98 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/PeripheralNames.h @@ -0,0 +1,137 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 1, +} RTCName; + +typedef enum { + UART_0 = 0, + UART_1 = 1, + UART_2 = 2, + UART_3 = 3, + UART_4 = 4, +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, + I2C_2 = 2, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 + PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 + PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 + PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 + PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 + PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 + PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 + PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 + PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 + PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 + PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 + PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 + PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 +typedef enum { + ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8, + ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9, + ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12, + ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13, + ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14, + ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15, + ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16, + ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17, + ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18, + ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21, + ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22, + ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23, + ADC1_SE4a = (1 << ADC_INSTANCE_SHIFT) | 4, + ADC1_SE5a = (1 << ADC_INSTANCE_SHIFT) | 5, + ADC1_SE6a = (1 << ADC_INSTANCE_SHIFT) | 6, + ADC1_SE7a = (1 << ADC_INSTANCE_SHIFT) | 7, + ADC1_SE4b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4, + ADC1_SE5b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5, + ADC1_SE6b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6, + ADC1_SE7b = (1 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7, + ADC1_SE8 = (1 << ADC_INSTANCE_SHIFT) | 8, + ADC1_SE9 = (1 << ADC_INSTANCE_SHIFT) | 9, + ADC1_SE12 = (1 << ADC_INSTANCE_SHIFT) | 12, + ADC1_SE13 = (1 << ADC_INSTANCE_SHIFT) | 13, + ADC1_SE14 = (1 << ADC_INSTANCE_SHIFT) | 14, + ADC1_SE15 = (1 << ADC_INSTANCE_SHIFT) | 15, + ADC1_SE16 = (1 << ADC_INSTANCE_SHIFT) | 16, + ADC1_SE17 = (1 << ADC_INSTANCE_SHIFT) | 17, + ADC1_SE18 = (1 << ADC_INSTANCE_SHIFT) | 18, + ADC1_SE23 = (1 << ADC_INSTANCE_SHIFT) | 23, +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, + SPI_2 = 2, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/PeripheralPins.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/PeripheralPins.c new file mode 100644 index 00000000000..c28829cd108 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/PeripheralPins.c @@ -0,0 +1,242 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {PTA17, ADC1_SE17, 0}, + {PTB0 , ADC0_SE8 , 0}, + {PTB1 , ADC0_SE9 , 0}, + {PTB2 , ADC0_SE12, 0}, + {PTB3 , ADC0_SE13, 0}, + {PTB6 , ADC1_SE12, 0}, + {PTB7 , ADC1_SE13, 0}, + {PTB10, ADC1_SE14, 0}, + {PTB11, ADC1_SE15, 0}, + {PTC0 , ADC0_SE14, 0}, + {PTC1 , ADC0_SE15, 0}, + {PTC2, ADC0_SE4b, 0}, + {PTC8, ADC1_SE4b, 0}, + {PTC9, ADC1_SE5b, 0}, + {PTC10, ADC1_SE6b, 0}, + {PTC11, ADC1_SE7b, 0}, + {PTD1, ADC0_SE5b, 0}, + {PTD5, ADC0_SE6b, 0}, + {PTD6, ADC0_SE7b, 0}, + {PTE0, ADC1_SE4a, 0}, + {PTE1, ADC1_SE5a, 0}, + {PTE2, ADC1_SE6a, 0}, + {PTE3, ADC1_SE7a, 0}, + //{PTE24, ADC0_SE17, 0}, //I2C pull up + //{PTE25, ADC0_SE18, 0}, //I2C pull up + {NC , NC , 0} +}; + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {DAC0_OUT, DAC_0, 0}, + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {PTE25, I2C_0, 5}, + {PTB1 , I2C_0, 2}, + {PTB3 , I2C_0, 2}, + {PTC11, I2C_1, 2}, + {PTA13, I2C_2, 5}, + {PTD3 , I2C_0, 7}, + {PTE0 , I2C_1, 6}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PTE24, I2C_0, 5}, + {PTB0 , I2C_0, 2}, + {PTB2 , I2C_0, 2}, + {PTC10, I2C_1, 2}, + {PTA12, I2C_2, 5}, + {PTA14, I2C_2, 5}, + {PTD2 , I2C_0, 7}, + {PTE1 , I2C_1, 6}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {PTB17, UART_0, 3}, + {PTC17, UART_3, 3}, + {PTD7 , UART_0, 3}, + {PTD3 , UART_2, 3}, + {PTC4 , UART_1, 3}, + {PTC15, UART_4, 3}, + {PTB11, UART_3, 3}, + {PTA14, UART_0, 3}, + {PTE24, UART_4, 3}, + {PTE4 , UART_3, 3}, + {PTE0, UART_1, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PTB16, UART_0, 3}, + {PTE1 , UART_1, 3}, + {PTE5 , UART_3, 3}, + {PTE25, UART_4, 3}, + {PTA15, UART_0, 3}, + {PTC16, UART_3, 3}, + {PTB10, UART_3, 3}, + {PTC3 , UART_1, 3}, + {PTC14, UART_4, 3}, + {PTD2 , UART_2, 3}, + {PTD6 , UART_0, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PTB13, UART_3, 2}, + {PTE2 , UART_1, 3}, + {PTE6 , UART_3, 3}, + {PTE26, UART_4, 3}, + {PTA0 , UART_0, 2}, + {PTA16, UART_0, 3}, + {PTB3 , UART_0, 3}, + {PTB9 , UART_3, 3}, + {PTC2 , UART_1, 3}, + {PTC13, UART_4, 3}, + {PTC19, UART_3, 3}, + {PTD1 , UART_2, 3}, + {PTD5 , UART_0, 3}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PTB12, UART_3, 2}, + {PTE3 , UART_1, 3}, + {PTE7 , UART_3, 3}, + {PTE27, UART_4, 3}, + {PTA17, UART_0, 3}, + {PTB8 , UART_3, 3}, + {PTC1 , UART_1, 3}, + {PTC12, UART_4, 3}, + {PTC18, UART_3, 3}, + {PTD0 , UART_2, 3}, + {PTD4 , UART_0, 3}, + {PTA3 , UART_0, 2}, + {PTB2 , UART_0, 3}, + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {PTD1 , SPI_0, 2}, + {PTE2 , SPI_1, 2}, + {PTA15, SPI_0, 2}, + {PTB11, SPI_1, 2}, + {PTB21, SPI_2, 2}, + {PTC5 , SPI_0, 2}, + {PTD5 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {PTD2 , SPI_0, 2}, + {PTE1 , SPI_1, 2}, + {PTE3 , SPI_1, 7}, + {PTA16, SPI_0, 2}, + {PTB16, SPI_1, 2}, + {PTB22, SPI_2, 2}, + {PTC6 , SPI_0, 2}, + {PTD6 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PTD3 , SPI_0, 2}, + {PTE1 , SPI_1, 7}, + {PTE3 , SPI_1, 2}, + {PTA17, SPI_0, 2}, + {PTB17, SPI_1, 2}, + {PTB23, SPI_2, 2}, + {PTC7 , SPI_0, 2}, + {PTD7 , SPI_1, 7}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PTD0 , SPI_0, 2}, + {PTE4 , SPI_1, 2}, + {PTA14, SPI_0, 2}, + {PTB10, SPI_1, 2}, + {PTB20, SPI_2, 2}, + {PTC4 , SPI_0, 2}, + {PTD4 , SPI_1, 7}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {PTA0 , PWM_6 , 3}, + {PTA1 , PWM_7 , 3}, + {PTA2 , PWM_8 , 3}, + {PTA3 , PWM_1 , 3}, + {PTA4 , PWM_2 , 3}, + {PTA5 , PWM_3 , 3}, + {PTA6 , PWM_4 , 3}, + {PTA7 , PWM_5 , 3}, + {PTA8 , PWM_9 , 3}, + {PTA9 , PWM_10, 3}, + {PTA10, PWM_17, 3}, + {PTA11, PWM_18, 3}, + {PTA12, PWM_9 , 3}, + {PTA13, PWM_10, 3}, + + {PTB0 , PWM_9 , 3}, + {PTB1 , PWM_10, 3}, + {PTB18, PWM_17, 3}, + {PTB19, PWM_18, 3}, + + {PTC1 , PWM_1 , 4}, + {PTC2 , PWM_2 , 4}, + {PTC3 , PWM_3 , 4}, + {PTC4 , PWM_4 , 4}, + {PTC5 , PWM_3 , 7}, + {PTC8 , PWM_29, 3}, + {PTC9 , PWM_30, 3}, + {PTC10, PWM_31, 3}, + {PTC11, PWM_32, 3}, + + {PTD0 , PWM_25, 4}, + {PTD1 , PWM_26, 4}, + {PTD2 , PWM_27, 4}, + {PTD3 , PWM_28, 4}, + {PTD4 , PWM_5 , 4}, + {PTD5 , PWM_6 , 4}, + {PTD6 , PWM_7 , 4}, + {PTD4 , PWM_5 , 4}, + {PTD7 , PWM_8 , 4}, + + {PTE5 , PWM_25, 6}, + {PTE6 , PWM_26, 6}, + + {NC , NC , 0} +}; diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/PinNames.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/PinNames.h new file mode 100644 index 00000000000..e1d7a2b6fa0 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/PinNames.h @@ -0,0 +1,259 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define GPIO_PORT_SHIFT 12 + +typedef enum { + PTA0 = (0 << GPIO_PORT_SHIFT | 0 ), + PTA1 = (0 << GPIO_PORT_SHIFT | 1 ), + PTA2 = (0 << GPIO_PORT_SHIFT | 2 ), + PTA3 = (0 << GPIO_PORT_SHIFT | 3 ), + PTA4 = (0 << GPIO_PORT_SHIFT | 4 ), + PTA5 = (0 << GPIO_PORT_SHIFT | 5 ), + PTA6 = (0 << GPIO_PORT_SHIFT | 6 ), + PTA7 = (0 << GPIO_PORT_SHIFT | 7 ), + PTA8 = (0 << GPIO_PORT_SHIFT | 8 ), + PTA9 = (0 << GPIO_PORT_SHIFT | 9 ), + PTA10 = (0 << GPIO_PORT_SHIFT | 10), + PTA11 = (0 << GPIO_PORT_SHIFT | 11), + PTA12 = (0 << GPIO_PORT_SHIFT | 12), + PTA13 = (0 << GPIO_PORT_SHIFT | 13), + PTA14 = (0 << GPIO_PORT_SHIFT | 14), + PTA15 = (0 << GPIO_PORT_SHIFT | 15), + PTA16 = (0 << GPIO_PORT_SHIFT | 16), + PTA17 = (0 << GPIO_PORT_SHIFT | 17), + PTA18 = (0 << GPIO_PORT_SHIFT | 18), + PTA19 = (0 << GPIO_PORT_SHIFT | 19), + PTA20 = (0 << GPIO_PORT_SHIFT | 20), + PTA21 = (0 << GPIO_PORT_SHIFT | 21), + PTA22 = (0 << GPIO_PORT_SHIFT | 22), + PTA23 = (0 << GPIO_PORT_SHIFT | 23), + PTA24 = (0 << GPIO_PORT_SHIFT | 24), + PTA25 = (0 << GPIO_PORT_SHIFT | 25), + PTA26 = (0 << GPIO_PORT_SHIFT | 26), + PTA27 = (0 << GPIO_PORT_SHIFT | 27), + PTA28 = (0 << GPIO_PORT_SHIFT | 28), + PTA29 = (0 << GPIO_PORT_SHIFT | 29), + PTA30 = (0 << GPIO_PORT_SHIFT | 30), + PTA31 = (0 << GPIO_PORT_SHIFT | 31), + PTB0 = (1 << GPIO_PORT_SHIFT | 0 ), + PTB1 = (1 << GPIO_PORT_SHIFT | 1 ), + PTB2 = (1 << GPIO_PORT_SHIFT | 2 ), + PTB3 = (1 << GPIO_PORT_SHIFT | 3 ), + PTB4 = (1 << GPIO_PORT_SHIFT | 4 ), + PTB5 = (1 << GPIO_PORT_SHIFT | 5 ), + PTB6 = (1 << GPIO_PORT_SHIFT | 6 ), + PTB7 = (1 << GPIO_PORT_SHIFT | 7 ), + PTB8 = (1 << GPIO_PORT_SHIFT | 8 ), + PTB9 = (1 << GPIO_PORT_SHIFT | 9 ), + PTB10 = (1 << GPIO_PORT_SHIFT | 10), + PTB11 = (1 << GPIO_PORT_SHIFT | 11), + PTB12 = (1 << GPIO_PORT_SHIFT | 12), + PTB13 = (1 << GPIO_PORT_SHIFT | 13), + PTB14 = (1 << GPIO_PORT_SHIFT | 14), + PTB15 = (1 << GPIO_PORT_SHIFT | 15), + PTB16 = (1 << GPIO_PORT_SHIFT | 16), + PTB17 = (1 << GPIO_PORT_SHIFT | 17), + PTB18 = (1 << GPIO_PORT_SHIFT | 18), + PTB19 = (1 << GPIO_PORT_SHIFT | 19), + PTB20 = (1 << GPIO_PORT_SHIFT | 20), + PTB21 = (1 << GPIO_PORT_SHIFT | 21), + PTB22 = (1 << GPIO_PORT_SHIFT | 22), + PTB23 = (1 << GPIO_PORT_SHIFT | 23), + PTB24 = (1 << GPIO_PORT_SHIFT | 24), + PTB25 = (1 << GPIO_PORT_SHIFT | 25), + PTB26 = (1 << GPIO_PORT_SHIFT | 26), + PTB27 = (1 << GPIO_PORT_SHIFT | 27), + PTB28 = (1 << GPIO_PORT_SHIFT | 28), + PTB29 = (1 << GPIO_PORT_SHIFT | 29), + PTB30 = (1 << GPIO_PORT_SHIFT | 30), + PTB31 = (1 << GPIO_PORT_SHIFT | 31), + PTC0 = (2 << GPIO_PORT_SHIFT | 0 ), + PTC1 = (2 << GPIO_PORT_SHIFT | 1 ), + PTC2 = (2 << GPIO_PORT_SHIFT | 2 ), + PTC3 = (2 << GPIO_PORT_SHIFT | 3 ), + PTC4 = (2 << GPIO_PORT_SHIFT | 4 ), + PTC5 = (2 << GPIO_PORT_SHIFT | 5 ), + PTC6 = (2 << GPIO_PORT_SHIFT | 6 ), + PTC7 = (2 << GPIO_PORT_SHIFT | 7 ), + PTC8 = (2 << GPIO_PORT_SHIFT | 8 ), + PTC9 = (2 << GPIO_PORT_SHIFT | 9 ), + PTC10 = (2 << GPIO_PORT_SHIFT | 10), + PTC11 = (2 << GPIO_PORT_SHIFT | 11), + PTC12 = (2 << GPIO_PORT_SHIFT | 12), + PTC13 = (2 << GPIO_PORT_SHIFT | 13), + PTC14 = (2 << GPIO_PORT_SHIFT | 14), + PTC15 = (2 << GPIO_PORT_SHIFT | 15), + PTC16 = (2 << GPIO_PORT_SHIFT | 16), + PTC17 = (2 << GPIO_PORT_SHIFT | 17), + PTC18 = (2 << GPIO_PORT_SHIFT | 18), + PTC19 = (2 << GPIO_PORT_SHIFT | 19), + PTC20 = (2 << GPIO_PORT_SHIFT | 20), + PTC21 = (2 << GPIO_PORT_SHIFT | 21), + PTC22 = (2 << GPIO_PORT_SHIFT | 22), + PTC23 = (2 << GPIO_PORT_SHIFT | 23), + PTC24 = (2 << GPIO_PORT_SHIFT | 24), + PTC25 = (2 << GPIO_PORT_SHIFT | 25), + PTC26 = (2 << GPIO_PORT_SHIFT | 26), + PTC27 = (2 << GPIO_PORT_SHIFT | 27), + PTC28 = (2 << GPIO_PORT_SHIFT | 28), + PTC29 = (2 << GPIO_PORT_SHIFT | 29), + PTC30 = (2 << GPIO_PORT_SHIFT | 30), + PTC31 = (2 << GPIO_PORT_SHIFT | 31), + PTD0 = (3 << GPIO_PORT_SHIFT | 0 ), + PTD1 = (3 << GPIO_PORT_SHIFT | 1 ), + PTD2 = (3 << GPIO_PORT_SHIFT | 2 ), + PTD3 = (3 << GPIO_PORT_SHIFT | 3 ), + PTD4 = (3 << GPIO_PORT_SHIFT | 4 ), + PTD5 = (3 << GPIO_PORT_SHIFT | 5 ), + PTD6 = (3 << GPIO_PORT_SHIFT | 6 ), + PTD7 = (3 << GPIO_PORT_SHIFT | 7 ), + PTD8 = (3 << GPIO_PORT_SHIFT | 8 ), + PTD9 = (3 << GPIO_PORT_SHIFT | 9 ), + PTD10 = (3 << GPIO_PORT_SHIFT | 10), + PTD11 = (3 << GPIO_PORT_SHIFT | 11), + PTD12 = (3 << GPIO_PORT_SHIFT | 12), + PTD13 = (3 << GPIO_PORT_SHIFT | 13), + PTD14 = (3 << GPIO_PORT_SHIFT | 14), + PTD15 = (3 << GPIO_PORT_SHIFT | 15), + PTD16 = (3 << GPIO_PORT_SHIFT | 16), + PTD17 = (3 << GPIO_PORT_SHIFT | 17), + PTD18 = (3 << GPIO_PORT_SHIFT | 18), + PTD19 = (3 << GPIO_PORT_SHIFT | 19), + PTD20 = (3 << GPIO_PORT_SHIFT | 20), + PTD21 = (3 << GPIO_PORT_SHIFT | 21), + PTD22 = (3 << GPIO_PORT_SHIFT | 22), + PTD23 = (3 << GPIO_PORT_SHIFT | 23), + PTD24 = (3 << GPIO_PORT_SHIFT | 24), + PTD25 = (3 << GPIO_PORT_SHIFT | 25), + PTD26 = (3 << GPIO_PORT_SHIFT | 26), + PTD27 = (3 << GPIO_PORT_SHIFT | 27), + PTD28 = (3 << GPIO_PORT_SHIFT | 28), + PTD29 = (3 << GPIO_PORT_SHIFT | 29), + PTD30 = (3 << GPIO_PORT_SHIFT | 30), + PTD31 = (3 << GPIO_PORT_SHIFT | 31), + PTE0 = (4 << GPIO_PORT_SHIFT | 0 ), + PTE1 = (4 << GPIO_PORT_SHIFT | 1 ), + PTE2 = (4 << GPIO_PORT_SHIFT | 2 ), + PTE3 = (4 << GPIO_PORT_SHIFT | 3 ), + PTE4 = (4 << GPIO_PORT_SHIFT | 4 ), + PTE5 = (4 << GPIO_PORT_SHIFT | 5 ), + PTE6 = (4 << GPIO_PORT_SHIFT | 6 ), + PTE7 = (4 << GPIO_PORT_SHIFT | 7 ), + PTE8 = (4 << GPIO_PORT_SHIFT | 8 ), + PTE9 = (4 << GPIO_PORT_SHIFT | 9 ), + PTE10 = (4 << GPIO_PORT_SHIFT | 10), + PTE11 = (4 << GPIO_PORT_SHIFT | 11), + PTE12 = (4 << GPIO_PORT_SHIFT | 12), + PTE13 = (4 << GPIO_PORT_SHIFT | 13), + PTE14 = (4 << GPIO_PORT_SHIFT | 14), + PTE15 = (4 << GPIO_PORT_SHIFT | 15), + PTE16 = (4 << GPIO_PORT_SHIFT | 16), + PTE17 = (4 << GPIO_PORT_SHIFT | 17), + PTE18 = (4 << GPIO_PORT_SHIFT | 18), + PTE19 = (4 << GPIO_PORT_SHIFT | 19), + PTE20 = (4 << GPIO_PORT_SHIFT | 20), + PTE21 = (4 << GPIO_PORT_SHIFT | 21), + PTE22 = (4 << GPIO_PORT_SHIFT | 22), + PTE23 = (4 << GPIO_PORT_SHIFT | 23), + PTE24 = (4 << GPIO_PORT_SHIFT | 24), + PTE25 = (4 << GPIO_PORT_SHIFT | 25), + PTE26 = (4 << GPIO_PORT_SHIFT | 26), + PTE27 = (4 << GPIO_PORT_SHIFT | 27), + PTE28 = (4 << GPIO_PORT_SHIFT | 28), + PTE29 = (4 << GPIO_PORT_SHIFT | 29), + PTE30 = (4 << GPIO_PORT_SHIFT | 30), + PTE31 = (4 << GPIO_PORT_SHIFT | 31), + + LED_RED = PTB22, + LED_GREEN = PTE26, + LED_BLUE = PTB2, // GPIO2 + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_RED, + + // USB Pins + USBTX = PTA14, + USBRX = PTA15, + + // Module Pins + MODTX = PTC4, + MODRX = PTC3, + + // Arduino Headers + D0 = PTC14, + D1 = PTC15, + D2 = PTA1, + D3 = PTA2, + D4 = PTA5, + D5 = PTC12, + D6 = PTC13, + D7 = PTB20, + + D8 = PTB18, + D9 = PTB19, + D10 = PTB10, + D11 = PTB16, + D12 = PTB17, + D13 = PTB11, + D14 = PTA13, + D15 = PTA12, + + I2C_SCL = D15, + I2C_SDA = D14, + + A0 = PTA16, + A1 = PTA17, + A2 = PTE26, + A3 = PTB2, + A4 = PTB1, + A5 = PTB0, + + DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/crc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/crc.c new file mode 100644 index 00000000000..7e2d7e7c516 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/crc.c @@ -0,0 +1,234 @@ +/********************************************************************** + * + * Filename: crc.c + * + * Description: Slow and fast implementations of the CRC standards. + * + * Notes: The parameters for each supported CRC standard are + * defined in the header file crc.h. The implementations + * here should stand up to further additions to that list. + * + * + * Copyright (c) 2000 by Michael Barr. This software is placed into + * the public domain and may be used for any purpose. However, this + * notice must not be changed or removed and no warranty is either + * expressed or implied by its publication or distribution. + **********************************************************************/ + +#include "crc.h" + + +/* + * Derive parameters from the standard-specific parameters in crc.h. + */ +#define WIDTH (8 * sizeof(crc)) +#define TOPBIT (1 << (WIDTH - 1)) + +#if (REFLECT_DATA == TRUE) +#undef REFLECT_DATA +#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8)) +#else +#undef REFLECT_DATA +#define REFLECT_DATA(X) (X) +#endif + +#if (REFLECT_REMAINDER == TRUE) +#undef REFLECT_REMAINDER +#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH)) +#else +#undef REFLECT_REMAINDER +#define REFLECT_REMAINDER(X) (X) +#endif + + +/********************************************************************* + * + * Function: reflect() + * + * Description: Reorder the bits of a binary sequence, by reflecting + * them about the middle position. + * + * Notes: No checking is done that nBits <= 32. + * + * Returns: The reflection of the original data. + * + *********************************************************************/ +static unsigned long +reflect(unsigned long data, unsigned char nBits) +{ + unsigned long reflection = 0x00000000; + unsigned char bit; + + /* + * Reflect the data about the center bit. + */ + for (bit = 0; bit < nBits; ++bit) + { + /* + * If the LSB bit is set, set the reflection of it. + */ + if (data & 0x01) + { + reflection |= (1 << ((nBits - 1) - bit)); + } + + data = (data >> 1); + } + + return (reflection); + +} /* reflect() */ + + +/********************************************************************* + * + * Function: crcSlow() + * + * Description: Compute the CRC of a given message. + * + * Notes: + * + * Returns: The CRC of the message. + * + *********************************************************************/ +crc +crcSlow(unsigned char const message[], int nBytes) +{ + crc remainder = INITIAL_REMAINDER; + int byte; + unsigned char bit; + + + /* + * Perform modulo-2 division, a byte at a time. + */ + for (byte = 0; byte < nBytes; ++byte) + { + /* + * Bring the next byte into the remainder. + */ + remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8)); + + /* + * Perform modulo-2 division, a bit at a time. + */ + for (bit = 8; bit > 0; --bit) + { + /* + * Try to divide the current data bit. + */ + if (remainder & TOPBIT) + { + remainder = (remainder << 1) ^ POLYNOMIAL; + } + else + { + remainder = (remainder << 1); + } + } + } + + /* + * The final remainder is the CRC result. + */ + return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE); + +} /* crcSlow() */ + + +crc crcTable[256]; + + +/********************************************************************* + * + * Function: crcInit() + * + * Description: Populate the partial CRC lookup table. + * + * Notes: This function must be rerun any time the CRC standard + * is changed. If desired, it can be run "offline" and + * the table results stored in an embedded system's ROM. + * + * Returns: None defined. + * + *********************************************************************/ +void +crcInit(void) +{ + crc remainder; + int dividend; + unsigned char bit; + + + /* + * Compute the remainder of each possible dividend. + */ + for (dividend = 0; dividend < 256; ++dividend) + { + /* + * Start with the dividend followed by zeros. + */ + remainder = dividend << (WIDTH - 8); + + /* + * Perform modulo-2 division, a bit at a time. + */ + for (bit = 8; bit > 0; --bit) + { + /* + * Try to divide the current data bit. + */ + if (remainder & TOPBIT) + { + remainder = (remainder << 1) ^ POLYNOMIAL; + } + else + { + remainder = (remainder << 1); + } + } + + /* + * Store the result into the table. + */ + crcTable[dividend] = remainder; + } + +} /* crcInit() */ + + +/********************************************************************* + * + * Function: crcFast() + * + * Description: Compute the CRC of a given message. + * + * Notes: crcInit() must be called first. + * + * Returns: The CRC of the message. + * + *********************************************************************/ +crc +crcFast(unsigned char const message[], int nBytes) +{ + crc remainder = INITIAL_REMAINDER; + unsigned char data; + int byte; + + + /* + * Divide the message by the polynomial, a byte at a time. + */ + for (byte = 0; byte < nBytes; ++byte) + { + data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8)); + remainder = crcTable[data] ^ (remainder << 8); + } + + /* + * The final remainder is the CRC. + */ + return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE); + +} /* crcFast() */ + diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/crc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/crc.h new file mode 100644 index 00000000000..fae66ae4bcc --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/crc.h @@ -0,0 +1,77 @@ +/********************************************************************** + * + * Filename: crc.h + * + * Description: A header file describing the various CRC standards. + * + * Notes: + * + * + * Copyright (c) 2000 by Michael Barr. This software is placed into + * the public domain and may be used for any purpose. However, this + * notice must not be changed or removed and no warranty is either + * expressed or implied by its publication or distribution. + **********************************************************************/ + +#ifndef _crc_h +#define _crc_h + + +#define FALSE 0 +#define TRUE !FALSE + +/* + * Select the CRC standard from the list that follows. + */ +#define CRC16 + + +#if defined(CRC_CCITT) + +typedef unsigned short crc; + +#define CRC_NAME "CRC-CCITT" +#define POLYNOMIAL 0x1021 +#define INITIAL_REMAINDER 0xFFFF +#define FINAL_XOR_VALUE 0x0000 +#define REFLECT_DATA FALSE +#define REFLECT_REMAINDER FALSE +#define CHECK_VALUE 0x29B1 + +#elif defined(CRC16) + +typedef unsigned short crc; + +#define CRC_NAME "CRC-16" +#define POLYNOMIAL 0x8005 +#define INITIAL_REMAINDER 0x0000 +#define FINAL_XOR_VALUE 0x0000 +#define REFLECT_DATA TRUE +#define REFLECT_REMAINDER TRUE +#define CHECK_VALUE 0xBB3D + +#elif defined(CRC32) + +typedef unsigned long crc; + +#define CRC_NAME "CRC-32" +#define POLYNOMIAL 0x04C11DB7 +#define INITIAL_REMAINDER 0xFFFFFFFF +#define FINAL_XOR_VALUE 0xFFFFFFFF +#define REFLECT_DATA TRUE +#define REFLECT_REMAINDER TRUE +#define CHECK_VALUE 0xCBF43926 + +#else + +#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd." + +#endif + + +void crcInit(void); +crc crcSlow(unsigned char const message[], int nBytes); +crc crcFast(unsigned char const message[], int nBytes); + + +#endif /* _crc_h */ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_advertising.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/device.h similarity index 62% rename from features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_advertising.h rename to targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/device.h index a215153ab5e..976726a94a8 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_advertising.h +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/device.h @@ -1,5 +1,7 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. /* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited + * Copyright (c) 2006-2017 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,12 +15,25 @@ * See the License for the specific language governing permissions and * limitations under the License. */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H -#ifndef _BTLE_ADVERTISING_H_ -#define _BTLE_ADVERTISING_H_ -#include "common/common.h" -error_t btle_advertising_start(void); -#endif // ifndef _BTLE_ADVERTISING_H_ + + + + + + + +#define DEVICE_ID_LENGTH 24 + + + + + +#include "objects.h" + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/fsl_clock_config.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/fsl_clock_config.c new file mode 100644 index 00000000000..a3398b49fcf --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/fsl_clock_config.c @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +#include "fsl_smc.h" +#include "fsl_rtc.h" +#include "fsl_clock_config.h" + +#define MCG_IRCLK_DISABLE 0U /*!< MCGIRCLK disabled */ +#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */ +#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */ +#define RTC_OSC_CAP_LOAD_0PF 0x0U /*!< RTC oscillator capacity load: 0pF */ +#define RTC_RTC32KCLK_PERIPHERALS_ENABLED 1U /*!< RTC32KCLK to other peripherals: enabled */ +#define SIM_CLKOUT_SEL_FLEXBUS_CLK 0U /*!< CLKOUT pin clock select: FlexBus clock */ +#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ +#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */ + +static void CLOCK_CONFIG_SetRtcClock(uint32_t capLoad, uint8_t enableOutPeriph) +{ + /* RTC clock gate enable */ + CLOCK_EnableClock(kCLOCK_Rtc0); + if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the Rtc oscillator is not already enabled */ + /* Set the specified capacitor configuration for the RTC oscillator */ + RTC_SetOscCapLoad(RTC, capLoad); + /* Enable the RTC 32KHz oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; + } + /* Output to other peripherals */ + if (enableOutPeriph) { + RTC->CR &= ~RTC_CR_CLKO_MASK; + } + else { + RTC->CR |= RTC_CR_CLKO_MASK; + } + /* Set the XTAL32/RTC_CLKIN frequency based on board setting. */ + CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ); + /* Set RTC_TSR if there is fault value in RTC */ + if (RTC->SR & RTC_SR_TIF_MASK) { + RTC -> TSR = RTC -> TSR; + } + /* RTC clock gate disable */ + CLOCK_DisableClock(kCLOCK_Rtc0); +} + +static void CLOCK_CONFIG_EnableIrc48MOsc() +{ + /* USB clock gate enable */ + CLOCK_EnableClock(kCLOCK_Usbfs0); + /* IRC48M oscillator enable */ + USB0->CLK_RECOVER_IRC_EN = USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK | USB_CLK_RECOVER_IRC_EN_REG_EN_MASK; + /* USB clock gate disable */ + CLOCK_DisableClock(kCLOCK_Usbfs0); +} + +static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) +{ + MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); +} + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock configuration structure. */ +typedef struct _clock_config +{ + mcg_config_t mcgConfig; /*!< MCG configuration. */ + sim_clock_config_t simConfig; /*!< SIM configuration. */ + osc_config_t oscConfig; /*!< OSC configuration. */ + uint32_t coreClock; /*!< core clock frequency. */ +} clock_config_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/* Configuration for enter VLPR mode. Core clock = 4MHz. */ +const clock_config_t g_defaultClockConfigVlpr = { + .mcgConfig = + { + .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */ + .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */ + .ircs = kMCG_IrcFast, /* Select IRC4M. */ + .fcrdiv = 0U, /* FCRDIV is 0. */ + + .frdiv = 0U, + .drs = kMCG_DrsLow, /* Low frequency range. */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */ + .oscsel = kMCG_OscselOsc, /* Select OSC. */ + + .pll0Config = + { + .enableMode = 0U, /* Don't eanble PLL. */ + .prdiv = 0U, + .vdiv = 0U, + }, + }, + .simConfig = + { + .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */ + .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */ + .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */ + }, + .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ, + .capLoad = 0, + .workMode = kOSC_ModeExt, + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, +#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) + .erclkDiv = 0U, +#endif + }}, + .coreClock = 4000000U, /* Core clock frequency */ +}; + +/* Configuration for enter RUN mode. Core clock = 95.977472 MHz. */ +const clock_config_t g_defaultClockConfigRun = { + .mcgConfig = + { + .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ + .irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */ + .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */ + .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ + .frdiv = 0x2U, /* FLL reference clock divider: divided by 4 */ + .drs = kMCG_DrsLow, /* Low frequency range */ + .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */ + .oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */ + .pll0Config = + { + .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */ + .prdiv = 0xbU, /* PLL Reference divider: divided by 12 */ + .vdiv = 0x0U, /* VCO divider: multiplied by 24 */ + }, + }, + .simConfig = //OK + { + .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */ + .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */ + .clkdiv1 = 0x1240000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /5 */ + }, + .oscConfig = + { + .freq = 0U, /* Oscillator frequency: 0Hz */ + .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */ + .workMode = kOSC_ModeExt, /* Use external clock */ + .oscerConfig = + { + .enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */ + + } + }, + .coreClock = 96000000U, /* Core clock frequency */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock + * and flash clock are in allowed range during clock mode switch. + * + * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. + * + * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and + * internal reference clock(MCGIRCLK). Follow the steps to setup: + * + * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. + * + * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured + * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig + * explicitly to setup MCGIRCLK. + * + * 3). Don't need to configure FLL explicitly, because if target mode is FLL + * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, + * if the target mode is not FLL mode, the FLL is disabled. + * + * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been + * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could + * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. + * + * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. + */ + +static void fllStableDelay(void) +{ + /* + Should wait at least 1ms. Because in these modes, the core clock is 100MHz + at most, so this function could obtain the 1ms delay. + */ + volatile uint32_t i = 30000U; + while (i--) + { + __NOP(); + } +} + +void BOARD_BootClockVLPR(void) +{ + CLOCK_SetSimSafeDivs(); + + CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs, + g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode); + + CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig); + + SystemCoreClock = g_defaultClockConfigVlpr.coreClock; + + SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); + SMC_SetPowerModeVlpr(SMC, false); + while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr) + { + } +} + +void BOARD_BootClockRUN(void) +{ + /* Set the system clock dividers in SIM to safe value. */ + CLOCK_SetSimSafeDivs(); + /* Configure RTC clock including enabling RTC oscillator. */ + CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_0PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED); + /* Enable IRC48M oscillator for K24 as workaround because there is not enabled the oscillator automatically. */ + CLOCK_CONFIG_EnableIrc48MOsc(); + /* Configure FLL external reference divider (FRDIV). */ + CLOCK_CONFIG_SetFllExtRefDiv(g_defaultClockConfigRun.mcgConfig.frdiv); + /* Set MCG to PEE mode. */ + CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, + kMCG_PllClkSelPll0, + &g_defaultClockConfigRun.mcgConfig.pll0Config); + /* Set the clock configuration in SIM module. */ + CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig); + /* Set SystemCoreClock variable. */ + SystemCoreClock = g_defaultClockConfigRun.coreClock; + /* Set CLKOUT source. */ + CLOCK_SetClkOutClock(SIM_CLKOUT_SEL_FLEXBUS_CLK); +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/fsl_clock_config.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/fsl_clock_config.h new file mode 100644 index 00000000000..050c3ab79b0 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/fsl_clock_config.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +/******************************************************************************* + * DEFINITION + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 50000000U +#define BOARD_XTAL32K_CLK_HZ 32768U + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +void BOARD_BootClockVLPR(void); +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/mbed_overrides.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/mbed_overrides.c new file mode 100644 index 00000000000..0fa409f8c75 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/TARGET_RO359B/mbed_overrides.c @@ -0,0 +1,43 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" + +#define CRC16 +#include "crc.h" +#include "fsl_clock_config.h" + +// called before main +void mbed_sdk_init() +{ + BOARD_BootClockRUN(); +} + +// Change the NMI pin to an input. This allows NMI pin to +// be used as a low power mode wakeup. The application will +// need to change the pin back to NMI_b or wakeup only occurs once! +void NMI_Handler(void) +{ + gpio_t gpio; + gpio_init_in(&gpio, PTA4); +} + +// Enable the RTC oscillator if available on the board +void rtc_setup_oscillator(RTC_Type *base) +{ + /* Enable the RTC oscillator */ + RTC->CR |= RTC_CR_OSCE_MASK; +} + diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/MK24F12.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/MK24F12.h new file mode 100644 index 00000000000..a057d576175 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/MK24F12.h @@ -0,0 +1,11819 @@ +/* +** ################################################################### +** Processors: MK24FN1M0CAJ12 +** MK24FN1M0VDC12 +** MK24FN1M0VLL12 +** MK24FN1M0VLQ12 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: K24P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.8, 2016-03-21 +** Build: b170112 +** +** Abstract: +** CMSIS Peripheral Access Layer for MK24F12 +** +** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. +** Copyright 2016 - 2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2013-08-12) +** Initial version. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** MCG - registers updated. +** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-09) +** DMA - EARS register removed. +** AIPS0, AIPS1 - MPRA register updated. +** - rev. 2.3 (2014-01-24) +** Update according to reference manual rev. 2 +** ENET, MCG, MCM, SIM, USB - registers updated +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK24F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** - rev. 2.5 (2014-08-28) +** Update of system files - default clock configuration changed. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 2.6 (2014-10-14) +** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. +** - rev. 2.7 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** - rev. 2.8 (2016-03-21) +** Added MK24FN1M0CAJ12 part. +** GPIO - renamed port instances: PTx -> GPIOx. +** +** ################################################################### +*/ + +/*! + * @file MK24F12.h + * @version 2.8 + * @date 2016-03-21 + * @brief CMSIS Peripheral Access Layer for MK24F12 + * + * CMSIS Peripheral Access Layer for MK24F12 + */ + +#ifndef _MK24F12_H_ +#define _MK24F12_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0200U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0008U + +/** + * @brief Macro to calculate address of an aliased word in the peripheral + * bitband area for a peripheral register and bit (bit band region 0x40000000 to + * 0x400FFFFF). + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Address of the aliased word in the peripheral bitband area. + */ +#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 32bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) +#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 16bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) +/** + * @brief Macro to access a single bit of a peripheral register (bit band region + * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can + * be used for peripherals with 8bit access allowed. + * @param Reg Register to access. + * @param Bit Bit number to access. + * @return Value of the targeted bit in the bit band region. + */ +#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit))))) + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ + DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ + DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ + DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ + DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ + DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ + DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ + DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ + DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ + DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ + DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ + DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ + DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ + DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ + DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ + DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ + DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ + MCM_IRQn = 17, /**< Normal Interrupt */ + FTFE_IRQn = 18, /**< FTFE Command complete interrupt */ + Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ + LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ + LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */ + WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */ + RNG_IRQn = 23, /**< RNG Interrupt */ + I2C0_IRQn = 24, /**< I2C0 interrupt */ + I2C1_IRQn = 25, /**< I2C1 interrupt */ + SPI0_IRQn = 26, /**< SPI0 Interrupt */ + SPI1_IRQn = 27, /**< SPI1 Interrupt */ + I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ + I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ + UART0_LON_IRQn = 30, /**< UART0 LON interrupt */ + UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ + UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ + UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ + UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ + UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ + UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ + UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */ + UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */ + ADC0_IRQn = 39, /**< ADC0 interrupt */ + CMP0_IRQn = 40, /**< CMP0 interrupt */ + CMP1_IRQn = 41, /**< CMP1 interrupt */ + FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ + FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ + FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ + CMT_IRQn = 45, /**< CMT interrupt */ + RTC_IRQn = 46, /**< RTC interrupt */ + RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ + PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ + PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ + PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ + PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ + PDB0_IRQn = 52, /**< PDB0 Interrupt */ + USB0_IRQn = 53, /**< USB0 interrupt */ + USBDCD_IRQn = 54, /**< USBDCD Interrupt */ + Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ + DAC0_IRQn = 56, /**< DAC0 interrupt */ + MCG_IRQn = 57, /**< MCG Interrupt */ + LPTMR0_IRQn = 58, /**< LPTimer interrupt */ + PORTA_IRQn = 59, /**< Port A interrupt */ + PORTB_IRQn = 60, /**< Port B interrupt */ + PORTC_IRQn = 61, /**< Port C interrupt */ + PORTD_IRQn = 62, /**< Port D interrupt */ + PORTE_IRQn = 63, /**< Port E interrupt */ + SWI_IRQn = 64, /**< Software interrupt */ + SPI2_IRQn = 65, /**< SPI2 Interrupt */ + UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */ + UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */ + UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */ + UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */ + CMP2_IRQn = 70, /**< CMP2 interrupt */ + FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ + DAC1_IRQn = 72, /**< DAC1 interrupt */ + ADC1_IRQn = 73, /**< ADC1 interrupt */ + I2C2_IRQn = 74, /**< I2C2 interrupt */ + CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */ + CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */ + CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */ + CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */ + CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */ + CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */ + SDHC_IRQn = 81, /**< SDHC interrupt */ + Reserved98_IRQn = 82, /**< Reserved interrupt 98 */ + Reserved99_IRQn = 83, /**< Reserved interrupt 99 */ + Reserved100_IRQn = 84, /**< Reserved interrupt 100 */ + Reserved101_IRQn = 85 /**< Reserved interrupt 101 */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ +#include "system_MK24F12.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ + kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */ + kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */ + kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */ + kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */ + kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */ + kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */ + kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */ + kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */ + kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */ + kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */ + kDmaRequestMux0UART5 = 11|0x100U, /**< UART5 Transmit or Receive. */ + kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */ + kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */ + kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */ + kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */ + kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */ + kDmaRequestMux0SPI2 = 17|0x100U, /**< SPI2 Transmit or Receive. */ + kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */ + kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ + kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */ + kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */ + kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */ + kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */ + kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */ + kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */ + kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */ + kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */ + kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */ + kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */ + kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */ + kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */ + kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */ + kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */ + kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */ + kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */ + kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */ + kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */ + kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */ + kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */ + kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */ + kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */ + kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */ + kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */ + kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */ + kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */ + kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2. */ + kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */ + kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */ + kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */ + kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */ + kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */ + kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */ + kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */ + kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */ + kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */ + kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */ + kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */ + kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */ + kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */ + kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ + kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ + __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ + __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ + __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ + __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ + __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ + __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ + __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ + __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ + __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ + __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ + __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ + __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ + __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ + __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ + __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ + __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ + __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ + uint8_t RESERVED_0[4]; + __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ + __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ + __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ + __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ + __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ + __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ + __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name SC1 - ADC Status and Control Registers 1 */ +#define ADC_SC1_ADCH_MASK (0x1FU) +#define ADC_SC1_ADCH_SHIFT (0U) +#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) +#define ADC_SC1_DIFF_MASK (0x20U) +#define ADC_SC1_DIFF_SHIFT (5U) +#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) +#define ADC_SC1_AIEN_MASK (0x40U) +#define ADC_SC1_AIEN_SHIFT (6U) +#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) +#define ADC_SC1_COCO_MASK (0x80U) +#define ADC_SC1_COCO_SHIFT (7U) +#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) + +/* The count of ADC_SC1 */ +#define ADC_SC1_COUNT (2U) + +/*! @name CFG1 - ADC Configuration Register 1 */ +#define ADC_CFG1_ADICLK_MASK (0x3U) +#define ADC_CFG1_ADICLK_SHIFT (0U) +#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) +#define ADC_CFG1_MODE_MASK (0xCU) +#define ADC_CFG1_MODE_SHIFT (2U) +#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) +#define ADC_CFG1_ADLSMP_MASK (0x10U) +#define ADC_CFG1_ADLSMP_SHIFT (4U) +#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) +#define ADC_CFG1_ADIV_MASK (0x60U) +#define ADC_CFG1_ADIV_SHIFT (5U) +#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) +#define ADC_CFG1_ADLPC_MASK (0x80U) +#define ADC_CFG1_ADLPC_SHIFT (7U) +#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) + +/*! @name CFG2 - ADC Configuration Register 2 */ +#define ADC_CFG2_ADLSTS_MASK (0x3U) +#define ADC_CFG2_ADLSTS_SHIFT (0U) +#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) +#define ADC_CFG2_ADHSC_MASK (0x4U) +#define ADC_CFG2_ADHSC_SHIFT (2U) +#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) +#define ADC_CFG2_ADACKEN_MASK (0x8U) +#define ADC_CFG2_ADACKEN_SHIFT (3U) +#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) +#define ADC_CFG2_MUXSEL_MASK (0x10U) +#define ADC_CFG2_MUXSEL_SHIFT (4U) +#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) + +/*! @name R - ADC Data Result Register */ +#define ADC_R_D_MASK (0xFFFFU) +#define ADC_R_D_SHIFT (0U) +#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) + +/* The count of ADC_R */ +#define ADC_R_COUNT (2U) + +/*! @name CV1 - Compare Value Registers */ +#define ADC_CV1_CV_MASK (0xFFFFU) +#define ADC_CV1_CV_SHIFT (0U) +#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) + +/*! @name CV2 - Compare Value Registers */ +#define ADC_CV2_CV_MASK (0xFFFFU) +#define ADC_CV2_CV_SHIFT (0U) +#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) + +/*! @name SC2 - Status and Control Register 2 */ +#define ADC_SC2_REFSEL_MASK (0x3U) +#define ADC_SC2_REFSEL_SHIFT (0U) +#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) +#define ADC_SC2_DMAEN_MASK (0x4U) +#define ADC_SC2_DMAEN_SHIFT (2U) +#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) +#define ADC_SC2_ACREN_MASK (0x8U) +#define ADC_SC2_ACREN_SHIFT (3U) +#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) +#define ADC_SC2_ACFGT_MASK (0x10U) +#define ADC_SC2_ACFGT_SHIFT (4U) +#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) +#define ADC_SC2_ACFE_MASK (0x20U) +#define ADC_SC2_ACFE_SHIFT (5U) +#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) +#define ADC_SC2_ADTRG_MASK (0x40U) +#define ADC_SC2_ADTRG_SHIFT (6U) +#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) +#define ADC_SC2_ADACT_MASK (0x80U) +#define ADC_SC2_ADACT_SHIFT (7U) +#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) + +/*! @name SC3 - Status and Control Register 3 */ +#define ADC_SC3_AVGS_MASK (0x3U) +#define ADC_SC3_AVGS_SHIFT (0U) +#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) +#define ADC_SC3_AVGE_MASK (0x4U) +#define ADC_SC3_AVGE_SHIFT (2U) +#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) +#define ADC_SC3_ADCO_MASK (0x8U) +#define ADC_SC3_ADCO_SHIFT (3U) +#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) +#define ADC_SC3_CALF_MASK (0x40U) +#define ADC_SC3_CALF_SHIFT (6U) +#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) +#define ADC_SC3_CAL_MASK (0x80U) +#define ADC_SC3_CAL_SHIFT (7U) +#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) + +/*! @name OFS - ADC Offset Correction Register */ +#define ADC_OFS_OFS_MASK (0xFFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) + +/*! @name PG - ADC Plus-Side Gain Register */ +#define ADC_PG_PG_MASK (0xFFFFU) +#define ADC_PG_PG_SHIFT (0U) +#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) + +/*! @name MG - ADC Minus-Side Gain Register */ +#define ADC_MG_MG_MASK (0xFFFFU) +#define ADC_MG_MG_SHIFT (0U) +#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) + +/*! @name CLPD - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLPD_CLPD_MASK (0x3FU) +#define ADC_CLPD_CLPD_SHIFT (0U) +#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) + +/*! @name CLPS - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLPS_CLPS_MASK (0x3FU) +#define ADC_CLPS_CLPS_SHIFT (0U) +#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) + +/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP4_CLP4_MASK (0x3FFU) +#define ADC_CLP4_CLP4_SHIFT (0U) +#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) + +/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP3_CLP3_MASK (0x1FFU) +#define ADC_CLP3_CLP3_SHIFT (0U) +#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) + +/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP2_CLP2_MASK (0xFFU) +#define ADC_CLP2_CLP2_SHIFT (0U) +#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) + +/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP1_CLP1_MASK (0x7FU) +#define ADC_CLP1_CLP1_SHIFT (0U) +#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) + +/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ +#define ADC_CLP0_CLP0_MASK (0x3FU) +#define ADC_CLP0_CLP0_SHIFT (0U) +#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) + +/*! @name CLMD - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLMD_CLMD_MASK (0x3FU) +#define ADC_CLMD_CLMD_SHIFT (0U) +#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) + +/*! @name CLMS - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLMS_CLMS_MASK (0x3FU) +#define ADC_CLMS_CLMS_SHIFT (0U) +#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) + +/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM4_CLM4_MASK (0x3FFU) +#define ADC_CLM4_CLM4_SHIFT (0U) +#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) + +/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM3_CLM3_MASK (0x1FFU) +#define ADC_CLM3_CLM3_SHIFT (0U) +#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) + +/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM2_CLM2_MASK (0xFFU) +#define ADC_CLM2_CLM2_SHIFT (0U) +#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) + +/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM1_CLM1_MASK (0x7FU) +#define ADC_CLM1_CLM1_SHIFT (0U) +#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) + +/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ +#define ADC_CLM0_CLM0_MASK (0x3FU) +#define ADC_CLM0_CLM0_SHIFT (0U) +#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x4003B000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400BB000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AIPS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer + * @{ + */ + +/** AIPS - Register Layout Typedef */ +typedef struct { + __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */ + __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */ + __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */ + __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */ + __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */ + __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */ + __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */ + __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */ + __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */ + __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */ + __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */ + __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */ + __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */ + __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */ + __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */ + uint8_t RESERVED_2[16]; + __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */ +} AIPS_Type; + +/* ---------------------------------------------------------------------------- + -- AIPS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPS_Register_Masks AIPS Register Masks + * @{ + */ + +/*! @name MPRA - Master Privilege Register A */ +#define AIPS_MPRA_MPL5_MASK (0x100U) +#define AIPS_MPRA_MPL5_SHIFT (8U) +#define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK) +#define AIPS_MPRA_MTW5_MASK (0x200U) +#define AIPS_MPRA_MTW5_SHIFT (9U) +#define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK) +#define AIPS_MPRA_MTR5_MASK (0x400U) +#define AIPS_MPRA_MTR5_SHIFT (10U) +#define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK) +#define AIPS_MPRA_MPL4_MASK (0x1000U) +#define AIPS_MPRA_MPL4_SHIFT (12U) +#define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK) +#define AIPS_MPRA_MTW4_MASK (0x2000U) +#define AIPS_MPRA_MTW4_SHIFT (13U) +#define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK) +#define AIPS_MPRA_MTR4_MASK (0x4000U) +#define AIPS_MPRA_MTR4_SHIFT (14U) +#define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK) +#define AIPS_MPRA_MPL3_MASK (0x10000U) +#define AIPS_MPRA_MPL3_SHIFT (16U) +#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK) +#define AIPS_MPRA_MTW3_MASK (0x20000U) +#define AIPS_MPRA_MTW3_SHIFT (17U) +#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK) +#define AIPS_MPRA_MTR3_MASK (0x40000U) +#define AIPS_MPRA_MTR3_SHIFT (18U) +#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK) +#define AIPS_MPRA_MPL2_MASK (0x100000U) +#define AIPS_MPRA_MPL2_SHIFT (20U) +#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK) +#define AIPS_MPRA_MTW2_MASK (0x200000U) +#define AIPS_MPRA_MTW2_SHIFT (21U) +#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK) +#define AIPS_MPRA_MTR2_MASK (0x400000U) +#define AIPS_MPRA_MTR2_SHIFT (22U) +#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK) +#define AIPS_MPRA_MPL1_MASK (0x1000000U) +#define AIPS_MPRA_MPL1_SHIFT (24U) +#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK) +#define AIPS_MPRA_MTW1_MASK (0x2000000U) +#define AIPS_MPRA_MTW1_SHIFT (25U) +#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK) +#define AIPS_MPRA_MTR1_MASK (0x4000000U) +#define AIPS_MPRA_MTR1_SHIFT (26U) +#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK) +#define AIPS_MPRA_MPL0_MASK (0x10000000U) +#define AIPS_MPRA_MPL0_SHIFT (28U) +#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK) +#define AIPS_MPRA_MTW0_MASK (0x20000000U) +#define AIPS_MPRA_MTW0_SHIFT (29U) +#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK) +#define AIPS_MPRA_MTR0_MASK (0x40000000U) +#define AIPS_MPRA_MTR0_SHIFT (30U) +#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK) + +/*! @name PACRA - Peripheral Access Control Register */ +#define AIPS_PACRA_TP7_MASK (0x1U) +#define AIPS_PACRA_TP7_SHIFT (0U) +#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK) +#define AIPS_PACRA_WP7_MASK (0x2U) +#define AIPS_PACRA_WP7_SHIFT (1U) +#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK) +#define AIPS_PACRA_SP7_MASK (0x4U) +#define AIPS_PACRA_SP7_SHIFT (2U) +#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK) +#define AIPS_PACRA_TP6_MASK (0x10U) +#define AIPS_PACRA_TP6_SHIFT (4U) +#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK) +#define AIPS_PACRA_WP6_MASK (0x20U) +#define AIPS_PACRA_WP6_SHIFT (5U) +#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK) +#define AIPS_PACRA_SP6_MASK (0x40U) +#define AIPS_PACRA_SP6_SHIFT (6U) +#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK) +#define AIPS_PACRA_TP5_MASK (0x100U) +#define AIPS_PACRA_TP5_SHIFT (8U) +#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK) +#define AIPS_PACRA_WP5_MASK (0x200U) +#define AIPS_PACRA_WP5_SHIFT (9U) +#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK) +#define AIPS_PACRA_SP5_MASK (0x400U) +#define AIPS_PACRA_SP5_SHIFT (10U) +#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK) +#define AIPS_PACRA_TP4_MASK (0x1000U) +#define AIPS_PACRA_TP4_SHIFT (12U) +#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK) +#define AIPS_PACRA_WP4_MASK (0x2000U) +#define AIPS_PACRA_WP4_SHIFT (13U) +#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK) +#define AIPS_PACRA_SP4_MASK (0x4000U) +#define AIPS_PACRA_SP4_SHIFT (14U) +#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK) +#define AIPS_PACRA_TP3_MASK (0x10000U) +#define AIPS_PACRA_TP3_SHIFT (16U) +#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK) +#define AIPS_PACRA_WP3_MASK (0x20000U) +#define AIPS_PACRA_WP3_SHIFT (17U) +#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK) +#define AIPS_PACRA_SP3_MASK (0x40000U) +#define AIPS_PACRA_SP3_SHIFT (18U) +#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK) +#define AIPS_PACRA_TP2_MASK (0x100000U) +#define AIPS_PACRA_TP2_SHIFT (20U) +#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK) +#define AIPS_PACRA_WP2_MASK (0x200000U) +#define AIPS_PACRA_WP2_SHIFT (21U) +#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK) +#define AIPS_PACRA_SP2_MASK (0x400000U) +#define AIPS_PACRA_SP2_SHIFT (22U) +#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK) +#define AIPS_PACRA_TP1_MASK (0x1000000U) +#define AIPS_PACRA_TP1_SHIFT (24U) +#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK) +#define AIPS_PACRA_WP1_MASK (0x2000000U) +#define AIPS_PACRA_WP1_SHIFT (25U) +#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK) +#define AIPS_PACRA_SP1_MASK (0x4000000U) +#define AIPS_PACRA_SP1_SHIFT (26U) +#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK) +#define AIPS_PACRA_TP0_MASK (0x10000000U) +#define AIPS_PACRA_TP0_SHIFT (28U) +#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK) +#define AIPS_PACRA_WP0_MASK (0x20000000U) +#define AIPS_PACRA_WP0_SHIFT (29U) +#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK) +#define AIPS_PACRA_SP0_MASK (0x40000000U) +#define AIPS_PACRA_SP0_SHIFT (30U) +#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK) + +/*! @name PACRB - Peripheral Access Control Register */ +#define AIPS_PACRB_TP7_MASK (0x1U) +#define AIPS_PACRB_TP7_SHIFT (0U) +#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK) +#define AIPS_PACRB_WP7_MASK (0x2U) +#define AIPS_PACRB_WP7_SHIFT (1U) +#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK) +#define AIPS_PACRB_SP7_MASK (0x4U) +#define AIPS_PACRB_SP7_SHIFT (2U) +#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK) +#define AIPS_PACRB_TP6_MASK (0x10U) +#define AIPS_PACRB_TP6_SHIFT (4U) +#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK) +#define AIPS_PACRB_WP6_MASK (0x20U) +#define AIPS_PACRB_WP6_SHIFT (5U) +#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK) +#define AIPS_PACRB_SP6_MASK (0x40U) +#define AIPS_PACRB_SP6_SHIFT (6U) +#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK) +#define AIPS_PACRB_TP5_MASK (0x100U) +#define AIPS_PACRB_TP5_SHIFT (8U) +#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK) +#define AIPS_PACRB_WP5_MASK (0x200U) +#define AIPS_PACRB_WP5_SHIFT (9U) +#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK) +#define AIPS_PACRB_SP5_MASK (0x400U) +#define AIPS_PACRB_SP5_SHIFT (10U) +#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK) +#define AIPS_PACRB_TP4_MASK (0x1000U) +#define AIPS_PACRB_TP4_SHIFT (12U) +#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK) +#define AIPS_PACRB_WP4_MASK (0x2000U) +#define AIPS_PACRB_WP4_SHIFT (13U) +#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK) +#define AIPS_PACRB_SP4_MASK (0x4000U) +#define AIPS_PACRB_SP4_SHIFT (14U) +#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK) +#define AIPS_PACRB_TP3_MASK (0x10000U) +#define AIPS_PACRB_TP3_SHIFT (16U) +#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK) +#define AIPS_PACRB_WP3_MASK (0x20000U) +#define AIPS_PACRB_WP3_SHIFT (17U) +#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK) +#define AIPS_PACRB_SP3_MASK (0x40000U) +#define AIPS_PACRB_SP3_SHIFT (18U) +#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK) +#define AIPS_PACRB_TP2_MASK (0x100000U) +#define AIPS_PACRB_TP2_SHIFT (20U) +#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK) +#define AIPS_PACRB_WP2_MASK (0x200000U) +#define AIPS_PACRB_WP2_SHIFT (21U) +#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK) +#define AIPS_PACRB_SP2_MASK (0x400000U) +#define AIPS_PACRB_SP2_SHIFT (22U) +#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK) +#define AIPS_PACRB_TP1_MASK (0x1000000U) +#define AIPS_PACRB_TP1_SHIFT (24U) +#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK) +#define AIPS_PACRB_WP1_MASK (0x2000000U) +#define AIPS_PACRB_WP1_SHIFT (25U) +#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK) +#define AIPS_PACRB_SP1_MASK (0x4000000U) +#define AIPS_PACRB_SP1_SHIFT (26U) +#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK) +#define AIPS_PACRB_TP0_MASK (0x10000000U) +#define AIPS_PACRB_TP0_SHIFT (28U) +#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK) +#define AIPS_PACRB_WP0_MASK (0x20000000U) +#define AIPS_PACRB_WP0_SHIFT (29U) +#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK) +#define AIPS_PACRB_SP0_MASK (0x40000000U) +#define AIPS_PACRB_SP0_SHIFT (30U) +#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK) + +/*! @name PACRC - Peripheral Access Control Register */ +#define AIPS_PACRC_TP7_MASK (0x1U) +#define AIPS_PACRC_TP7_SHIFT (0U) +#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK) +#define AIPS_PACRC_WP7_MASK (0x2U) +#define AIPS_PACRC_WP7_SHIFT (1U) +#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK) +#define AIPS_PACRC_SP7_MASK (0x4U) +#define AIPS_PACRC_SP7_SHIFT (2U) +#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK) +#define AIPS_PACRC_TP6_MASK (0x10U) +#define AIPS_PACRC_TP6_SHIFT (4U) +#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK) +#define AIPS_PACRC_WP6_MASK (0x20U) +#define AIPS_PACRC_WP6_SHIFT (5U) +#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK) +#define AIPS_PACRC_SP6_MASK (0x40U) +#define AIPS_PACRC_SP6_SHIFT (6U) +#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK) +#define AIPS_PACRC_TP5_MASK (0x100U) +#define AIPS_PACRC_TP5_SHIFT (8U) +#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK) +#define AIPS_PACRC_WP5_MASK (0x200U) +#define AIPS_PACRC_WP5_SHIFT (9U) +#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK) +#define AIPS_PACRC_SP5_MASK (0x400U) +#define AIPS_PACRC_SP5_SHIFT (10U) +#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK) +#define AIPS_PACRC_TP4_MASK (0x1000U) +#define AIPS_PACRC_TP4_SHIFT (12U) +#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK) +#define AIPS_PACRC_WP4_MASK (0x2000U) +#define AIPS_PACRC_WP4_SHIFT (13U) +#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK) +#define AIPS_PACRC_SP4_MASK (0x4000U) +#define AIPS_PACRC_SP4_SHIFT (14U) +#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK) +#define AIPS_PACRC_TP3_MASK (0x10000U) +#define AIPS_PACRC_TP3_SHIFT (16U) +#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK) +#define AIPS_PACRC_WP3_MASK (0x20000U) +#define AIPS_PACRC_WP3_SHIFT (17U) +#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK) +#define AIPS_PACRC_SP3_MASK (0x40000U) +#define AIPS_PACRC_SP3_SHIFT (18U) +#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK) +#define AIPS_PACRC_TP2_MASK (0x100000U) +#define AIPS_PACRC_TP2_SHIFT (20U) +#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK) +#define AIPS_PACRC_WP2_MASK (0x200000U) +#define AIPS_PACRC_WP2_SHIFT (21U) +#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK) +#define AIPS_PACRC_SP2_MASK (0x400000U) +#define AIPS_PACRC_SP2_SHIFT (22U) +#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK) +#define AIPS_PACRC_TP1_MASK (0x1000000U) +#define AIPS_PACRC_TP1_SHIFT (24U) +#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK) +#define AIPS_PACRC_WP1_MASK (0x2000000U) +#define AIPS_PACRC_WP1_SHIFT (25U) +#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK) +#define AIPS_PACRC_SP1_MASK (0x4000000U) +#define AIPS_PACRC_SP1_SHIFT (26U) +#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK) +#define AIPS_PACRC_TP0_MASK (0x10000000U) +#define AIPS_PACRC_TP0_SHIFT (28U) +#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK) +#define AIPS_PACRC_WP0_MASK (0x20000000U) +#define AIPS_PACRC_WP0_SHIFT (29U) +#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK) +#define AIPS_PACRC_SP0_MASK (0x40000000U) +#define AIPS_PACRC_SP0_SHIFT (30U) +#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK) + +/*! @name PACRD - Peripheral Access Control Register */ +#define AIPS_PACRD_TP7_MASK (0x1U) +#define AIPS_PACRD_TP7_SHIFT (0U) +#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK) +#define AIPS_PACRD_WP7_MASK (0x2U) +#define AIPS_PACRD_WP7_SHIFT (1U) +#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK) +#define AIPS_PACRD_SP7_MASK (0x4U) +#define AIPS_PACRD_SP7_SHIFT (2U) +#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK) +#define AIPS_PACRD_TP6_MASK (0x10U) +#define AIPS_PACRD_TP6_SHIFT (4U) +#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK) +#define AIPS_PACRD_WP6_MASK (0x20U) +#define AIPS_PACRD_WP6_SHIFT (5U) +#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK) +#define AIPS_PACRD_SP6_MASK (0x40U) +#define AIPS_PACRD_SP6_SHIFT (6U) +#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK) +#define AIPS_PACRD_TP5_MASK (0x100U) +#define AIPS_PACRD_TP5_SHIFT (8U) +#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK) +#define AIPS_PACRD_WP5_MASK (0x200U) +#define AIPS_PACRD_WP5_SHIFT (9U) +#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK) +#define AIPS_PACRD_SP5_MASK (0x400U) +#define AIPS_PACRD_SP5_SHIFT (10U) +#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK) +#define AIPS_PACRD_TP4_MASK (0x1000U) +#define AIPS_PACRD_TP4_SHIFT (12U) +#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK) +#define AIPS_PACRD_WP4_MASK (0x2000U) +#define AIPS_PACRD_WP4_SHIFT (13U) +#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK) +#define AIPS_PACRD_SP4_MASK (0x4000U) +#define AIPS_PACRD_SP4_SHIFT (14U) +#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK) +#define AIPS_PACRD_TP3_MASK (0x10000U) +#define AIPS_PACRD_TP3_SHIFT (16U) +#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK) +#define AIPS_PACRD_WP3_MASK (0x20000U) +#define AIPS_PACRD_WP3_SHIFT (17U) +#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK) +#define AIPS_PACRD_SP3_MASK (0x40000U) +#define AIPS_PACRD_SP3_SHIFT (18U) +#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK) +#define AIPS_PACRD_TP2_MASK (0x100000U) +#define AIPS_PACRD_TP2_SHIFT (20U) +#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK) +#define AIPS_PACRD_WP2_MASK (0x200000U) +#define AIPS_PACRD_WP2_SHIFT (21U) +#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK) +#define AIPS_PACRD_SP2_MASK (0x400000U) +#define AIPS_PACRD_SP2_SHIFT (22U) +#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK) +#define AIPS_PACRD_TP1_MASK (0x1000000U) +#define AIPS_PACRD_TP1_SHIFT (24U) +#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK) +#define AIPS_PACRD_WP1_MASK (0x2000000U) +#define AIPS_PACRD_WP1_SHIFT (25U) +#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK) +#define AIPS_PACRD_SP1_MASK (0x4000000U) +#define AIPS_PACRD_SP1_SHIFT (26U) +#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK) +#define AIPS_PACRD_TP0_MASK (0x10000000U) +#define AIPS_PACRD_TP0_SHIFT (28U) +#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK) +#define AIPS_PACRD_WP0_MASK (0x20000000U) +#define AIPS_PACRD_WP0_SHIFT (29U) +#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK) +#define AIPS_PACRD_SP0_MASK (0x40000000U) +#define AIPS_PACRD_SP0_SHIFT (30U) +#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK) + +/*! @name PACRE - Peripheral Access Control Register */ +#define AIPS_PACRE_TP7_MASK (0x1U) +#define AIPS_PACRE_TP7_SHIFT (0U) +#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK) +#define AIPS_PACRE_WP7_MASK (0x2U) +#define AIPS_PACRE_WP7_SHIFT (1U) +#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK) +#define AIPS_PACRE_SP7_MASK (0x4U) +#define AIPS_PACRE_SP7_SHIFT (2U) +#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK) +#define AIPS_PACRE_TP6_MASK (0x10U) +#define AIPS_PACRE_TP6_SHIFT (4U) +#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK) +#define AIPS_PACRE_WP6_MASK (0x20U) +#define AIPS_PACRE_WP6_SHIFT (5U) +#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK) +#define AIPS_PACRE_SP6_MASK (0x40U) +#define AIPS_PACRE_SP6_SHIFT (6U) +#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK) +#define AIPS_PACRE_TP5_MASK (0x100U) +#define AIPS_PACRE_TP5_SHIFT (8U) +#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK) +#define AIPS_PACRE_WP5_MASK (0x200U) +#define AIPS_PACRE_WP5_SHIFT (9U) +#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK) +#define AIPS_PACRE_SP5_MASK (0x400U) +#define AIPS_PACRE_SP5_SHIFT (10U) +#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK) +#define AIPS_PACRE_TP4_MASK (0x1000U) +#define AIPS_PACRE_TP4_SHIFT (12U) +#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK) +#define AIPS_PACRE_WP4_MASK (0x2000U) +#define AIPS_PACRE_WP4_SHIFT (13U) +#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK) +#define AIPS_PACRE_SP4_MASK (0x4000U) +#define AIPS_PACRE_SP4_SHIFT (14U) +#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK) +#define AIPS_PACRE_TP3_MASK (0x10000U) +#define AIPS_PACRE_TP3_SHIFT (16U) +#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK) +#define AIPS_PACRE_WP3_MASK (0x20000U) +#define AIPS_PACRE_WP3_SHIFT (17U) +#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK) +#define AIPS_PACRE_SP3_MASK (0x40000U) +#define AIPS_PACRE_SP3_SHIFT (18U) +#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK) +#define AIPS_PACRE_TP2_MASK (0x100000U) +#define AIPS_PACRE_TP2_SHIFT (20U) +#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK) +#define AIPS_PACRE_WP2_MASK (0x200000U) +#define AIPS_PACRE_WP2_SHIFT (21U) +#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK) +#define AIPS_PACRE_SP2_MASK (0x400000U) +#define AIPS_PACRE_SP2_SHIFT (22U) +#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK) +#define AIPS_PACRE_TP1_MASK (0x1000000U) +#define AIPS_PACRE_TP1_SHIFT (24U) +#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK) +#define AIPS_PACRE_WP1_MASK (0x2000000U) +#define AIPS_PACRE_WP1_SHIFT (25U) +#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK) +#define AIPS_PACRE_SP1_MASK (0x4000000U) +#define AIPS_PACRE_SP1_SHIFT (26U) +#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK) +#define AIPS_PACRE_TP0_MASK (0x10000000U) +#define AIPS_PACRE_TP0_SHIFT (28U) +#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK) +#define AIPS_PACRE_WP0_MASK (0x20000000U) +#define AIPS_PACRE_WP0_SHIFT (29U) +#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK) +#define AIPS_PACRE_SP0_MASK (0x40000000U) +#define AIPS_PACRE_SP0_SHIFT (30U) +#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK) + +/*! @name PACRF - Peripheral Access Control Register */ +#define AIPS_PACRF_TP7_MASK (0x1U) +#define AIPS_PACRF_TP7_SHIFT (0U) +#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK) +#define AIPS_PACRF_WP7_MASK (0x2U) +#define AIPS_PACRF_WP7_SHIFT (1U) +#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK) +#define AIPS_PACRF_SP7_MASK (0x4U) +#define AIPS_PACRF_SP7_SHIFT (2U) +#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK) +#define AIPS_PACRF_TP6_MASK (0x10U) +#define AIPS_PACRF_TP6_SHIFT (4U) +#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK) +#define AIPS_PACRF_WP6_MASK (0x20U) +#define AIPS_PACRF_WP6_SHIFT (5U) +#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK) +#define AIPS_PACRF_SP6_MASK (0x40U) +#define AIPS_PACRF_SP6_SHIFT (6U) +#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK) +#define AIPS_PACRF_TP5_MASK (0x100U) +#define AIPS_PACRF_TP5_SHIFT (8U) +#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK) +#define AIPS_PACRF_WP5_MASK (0x200U) +#define AIPS_PACRF_WP5_SHIFT (9U) +#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK) +#define AIPS_PACRF_SP5_MASK (0x400U) +#define AIPS_PACRF_SP5_SHIFT (10U) +#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK) +#define AIPS_PACRF_TP4_MASK (0x1000U) +#define AIPS_PACRF_TP4_SHIFT (12U) +#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK) +#define AIPS_PACRF_WP4_MASK (0x2000U) +#define AIPS_PACRF_WP4_SHIFT (13U) +#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK) +#define AIPS_PACRF_SP4_MASK (0x4000U) +#define AIPS_PACRF_SP4_SHIFT (14U) +#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK) +#define AIPS_PACRF_TP3_MASK (0x10000U) +#define AIPS_PACRF_TP3_SHIFT (16U) +#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK) +#define AIPS_PACRF_WP3_MASK (0x20000U) +#define AIPS_PACRF_WP3_SHIFT (17U) +#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK) +#define AIPS_PACRF_SP3_MASK (0x40000U) +#define AIPS_PACRF_SP3_SHIFT (18U) +#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK) +#define AIPS_PACRF_TP2_MASK (0x100000U) +#define AIPS_PACRF_TP2_SHIFT (20U) +#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK) +#define AIPS_PACRF_WP2_MASK (0x200000U) +#define AIPS_PACRF_WP2_SHIFT (21U) +#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK) +#define AIPS_PACRF_SP2_MASK (0x400000U) +#define AIPS_PACRF_SP2_SHIFT (22U) +#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK) +#define AIPS_PACRF_TP1_MASK (0x1000000U) +#define AIPS_PACRF_TP1_SHIFT (24U) +#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK) +#define AIPS_PACRF_WP1_MASK (0x2000000U) +#define AIPS_PACRF_WP1_SHIFT (25U) +#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK) +#define AIPS_PACRF_SP1_MASK (0x4000000U) +#define AIPS_PACRF_SP1_SHIFT (26U) +#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK) +#define AIPS_PACRF_TP0_MASK (0x10000000U) +#define AIPS_PACRF_TP0_SHIFT (28U) +#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK) +#define AIPS_PACRF_WP0_MASK (0x20000000U) +#define AIPS_PACRF_WP0_SHIFT (29U) +#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK) +#define AIPS_PACRF_SP0_MASK (0x40000000U) +#define AIPS_PACRF_SP0_SHIFT (30U) +#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK) + +/*! @name PACRG - Peripheral Access Control Register */ +#define AIPS_PACRG_TP7_MASK (0x1U) +#define AIPS_PACRG_TP7_SHIFT (0U) +#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK) +#define AIPS_PACRG_WP7_MASK (0x2U) +#define AIPS_PACRG_WP7_SHIFT (1U) +#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK) +#define AIPS_PACRG_SP7_MASK (0x4U) +#define AIPS_PACRG_SP7_SHIFT (2U) +#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK) +#define AIPS_PACRG_TP6_MASK (0x10U) +#define AIPS_PACRG_TP6_SHIFT (4U) +#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK) +#define AIPS_PACRG_WP6_MASK (0x20U) +#define AIPS_PACRG_WP6_SHIFT (5U) +#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK) +#define AIPS_PACRG_SP6_MASK (0x40U) +#define AIPS_PACRG_SP6_SHIFT (6U) +#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK) +#define AIPS_PACRG_TP5_MASK (0x100U) +#define AIPS_PACRG_TP5_SHIFT (8U) +#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK) +#define AIPS_PACRG_WP5_MASK (0x200U) +#define AIPS_PACRG_WP5_SHIFT (9U) +#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK) +#define AIPS_PACRG_SP5_MASK (0x400U) +#define AIPS_PACRG_SP5_SHIFT (10U) +#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK) +#define AIPS_PACRG_TP4_MASK (0x1000U) +#define AIPS_PACRG_TP4_SHIFT (12U) +#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK) +#define AIPS_PACRG_WP4_MASK (0x2000U) +#define AIPS_PACRG_WP4_SHIFT (13U) +#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK) +#define AIPS_PACRG_SP4_MASK (0x4000U) +#define AIPS_PACRG_SP4_SHIFT (14U) +#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK) +#define AIPS_PACRG_TP3_MASK (0x10000U) +#define AIPS_PACRG_TP3_SHIFT (16U) +#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK) +#define AIPS_PACRG_WP3_MASK (0x20000U) +#define AIPS_PACRG_WP3_SHIFT (17U) +#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK) +#define AIPS_PACRG_SP3_MASK (0x40000U) +#define AIPS_PACRG_SP3_SHIFT (18U) +#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK) +#define AIPS_PACRG_TP2_MASK (0x100000U) +#define AIPS_PACRG_TP2_SHIFT (20U) +#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK) +#define AIPS_PACRG_WP2_MASK (0x200000U) +#define AIPS_PACRG_WP2_SHIFT (21U) +#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK) +#define AIPS_PACRG_SP2_MASK (0x400000U) +#define AIPS_PACRG_SP2_SHIFT (22U) +#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK) +#define AIPS_PACRG_TP1_MASK (0x1000000U) +#define AIPS_PACRG_TP1_SHIFT (24U) +#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK) +#define AIPS_PACRG_WP1_MASK (0x2000000U) +#define AIPS_PACRG_WP1_SHIFT (25U) +#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK) +#define AIPS_PACRG_SP1_MASK (0x4000000U) +#define AIPS_PACRG_SP1_SHIFT (26U) +#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK) +#define AIPS_PACRG_TP0_MASK (0x10000000U) +#define AIPS_PACRG_TP0_SHIFT (28U) +#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK) +#define AIPS_PACRG_WP0_MASK (0x20000000U) +#define AIPS_PACRG_WP0_SHIFT (29U) +#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK) +#define AIPS_PACRG_SP0_MASK (0x40000000U) +#define AIPS_PACRG_SP0_SHIFT (30U) +#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK) + +/*! @name PACRH - Peripheral Access Control Register */ +#define AIPS_PACRH_TP7_MASK (0x1U) +#define AIPS_PACRH_TP7_SHIFT (0U) +#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK) +#define AIPS_PACRH_WP7_MASK (0x2U) +#define AIPS_PACRH_WP7_SHIFT (1U) +#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK) +#define AIPS_PACRH_SP7_MASK (0x4U) +#define AIPS_PACRH_SP7_SHIFT (2U) +#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK) +#define AIPS_PACRH_TP6_MASK (0x10U) +#define AIPS_PACRH_TP6_SHIFT (4U) +#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK) +#define AIPS_PACRH_WP6_MASK (0x20U) +#define AIPS_PACRH_WP6_SHIFT (5U) +#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK) +#define AIPS_PACRH_SP6_MASK (0x40U) +#define AIPS_PACRH_SP6_SHIFT (6U) +#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK) +#define AIPS_PACRH_TP5_MASK (0x100U) +#define AIPS_PACRH_TP5_SHIFT (8U) +#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK) +#define AIPS_PACRH_WP5_MASK (0x200U) +#define AIPS_PACRH_WP5_SHIFT (9U) +#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK) +#define AIPS_PACRH_SP5_MASK (0x400U) +#define AIPS_PACRH_SP5_SHIFT (10U) +#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK) +#define AIPS_PACRH_TP4_MASK (0x1000U) +#define AIPS_PACRH_TP4_SHIFT (12U) +#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK) +#define AIPS_PACRH_WP4_MASK (0x2000U) +#define AIPS_PACRH_WP4_SHIFT (13U) +#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK) +#define AIPS_PACRH_SP4_MASK (0x4000U) +#define AIPS_PACRH_SP4_SHIFT (14U) +#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK) +#define AIPS_PACRH_TP3_MASK (0x10000U) +#define AIPS_PACRH_TP3_SHIFT (16U) +#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK) +#define AIPS_PACRH_WP3_MASK (0x20000U) +#define AIPS_PACRH_WP3_SHIFT (17U) +#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK) +#define AIPS_PACRH_SP3_MASK (0x40000U) +#define AIPS_PACRH_SP3_SHIFT (18U) +#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK) +#define AIPS_PACRH_TP2_MASK (0x100000U) +#define AIPS_PACRH_TP2_SHIFT (20U) +#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK) +#define AIPS_PACRH_WP2_MASK (0x200000U) +#define AIPS_PACRH_WP2_SHIFT (21U) +#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK) +#define AIPS_PACRH_SP2_MASK (0x400000U) +#define AIPS_PACRH_SP2_SHIFT (22U) +#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK) +#define AIPS_PACRH_TP1_MASK (0x1000000U) +#define AIPS_PACRH_TP1_SHIFT (24U) +#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK) +#define AIPS_PACRH_WP1_MASK (0x2000000U) +#define AIPS_PACRH_WP1_SHIFT (25U) +#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK) +#define AIPS_PACRH_SP1_MASK (0x4000000U) +#define AIPS_PACRH_SP1_SHIFT (26U) +#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK) +#define AIPS_PACRH_TP0_MASK (0x10000000U) +#define AIPS_PACRH_TP0_SHIFT (28U) +#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK) +#define AIPS_PACRH_WP0_MASK (0x20000000U) +#define AIPS_PACRH_WP0_SHIFT (29U) +#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK) +#define AIPS_PACRH_SP0_MASK (0x40000000U) +#define AIPS_PACRH_SP0_SHIFT (30U) +#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK) + +/*! @name PACRI - Peripheral Access Control Register */ +#define AIPS_PACRI_TP7_MASK (0x1U) +#define AIPS_PACRI_TP7_SHIFT (0U) +#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK) +#define AIPS_PACRI_WP7_MASK (0x2U) +#define AIPS_PACRI_WP7_SHIFT (1U) +#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK) +#define AIPS_PACRI_SP7_MASK (0x4U) +#define AIPS_PACRI_SP7_SHIFT (2U) +#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK) +#define AIPS_PACRI_TP6_MASK (0x10U) +#define AIPS_PACRI_TP6_SHIFT (4U) +#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK) +#define AIPS_PACRI_WP6_MASK (0x20U) +#define AIPS_PACRI_WP6_SHIFT (5U) +#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK) +#define AIPS_PACRI_SP6_MASK (0x40U) +#define AIPS_PACRI_SP6_SHIFT (6U) +#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK) +#define AIPS_PACRI_TP5_MASK (0x100U) +#define AIPS_PACRI_TP5_SHIFT (8U) +#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK) +#define AIPS_PACRI_WP5_MASK (0x200U) +#define AIPS_PACRI_WP5_SHIFT (9U) +#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK) +#define AIPS_PACRI_SP5_MASK (0x400U) +#define AIPS_PACRI_SP5_SHIFT (10U) +#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK) +#define AIPS_PACRI_TP4_MASK (0x1000U) +#define AIPS_PACRI_TP4_SHIFT (12U) +#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK) +#define AIPS_PACRI_WP4_MASK (0x2000U) +#define AIPS_PACRI_WP4_SHIFT (13U) +#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK) +#define AIPS_PACRI_SP4_MASK (0x4000U) +#define AIPS_PACRI_SP4_SHIFT (14U) +#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK) +#define AIPS_PACRI_TP3_MASK (0x10000U) +#define AIPS_PACRI_TP3_SHIFT (16U) +#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK) +#define AIPS_PACRI_WP3_MASK (0x20000U) +#define AIPS_PACRI_WP3_SHIFT (17U) +#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK) +#define AIPS_PACRI_SP3_MASK (0x40000U) +#define AIPS_PACRI_SP3_SHIFT (18U) +#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK) +#define AIPS_PACRI_TP2_MASK (0x100000U) +#define AIPS_PACRI_TP2_SHIFT (20U) +#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK) +#define AIPS_PACRI_WP2_MASK (0x200000U) +#define AIPS_PACRI_WP2_SHIFT (21U) +#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK) +#define AIPS_PACRI_SP2_MASK (0x400000U) +#define AIPS_PACRI_SP2_SHIFT (22U) +#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK) +#define AIPS_PACRI_TP1_MASK (0x1000000U) +#define AIPS_PACRI_TP1_SHIFT (24U) +#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK) +#define AIPS_PACRI_WP1_MASK (0x2000000U) +#define AIPS_PACRI_WP1_SHIFT (25U) +#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK) +#define AIPS_PACRI_SP1_MASK (0x4000000U) +#define AIPS_PACRI_SP1_SHIFT (26U) +#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK) +#define AIPS_PACRI_TP0_MASK (0x10000000U) +#define AIPS_PACRI_TP0_SHIFT (28U) +#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK) +#define AIPS_PACRI_WP0_MASK (0x20000000U) +#define AIPS_PACRI_WP0_SHIFT (29U) +#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK) +#define AIPS_PACRI_SP0_MASK (0x40000000U) +#define AIPS_PACRI_SP0_SHIFT (30U) +#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK) + +/*! @name PACRJ - Peripheral Access Control Register */ +#define AIPS_PACRJ_TP7_MASK (0x1U) +#define AIPS_PACRJ_TP7_SHIFT (0U) +#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK) +#define AIPS_PACRJ_WP7_MASK (0x2U) +#define AIPS_PACRJ_WP7_SHIFT (1U) +#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK) +#define AIPS_PACRJ_SP7_MASK (0x4U) +#define AIPS_PACRJ_SP7_SHIFT (2U) +#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK) +#define AIPS_PACRJ_TP6_MASK (0x10U) +#define AIPS_PACRJ_TP6_SHIFT (4U) +#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK) +#define AIPS_PACRJ_WP6_MASK (0x20U) +#define AIPS_PACRJ_WP6_SHIFT (5U) +#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK) +#define AIPS_PACRJ_SP6_MASK (0x40U) +#define AIPS_PACRJ_SP6_SHIFT (6U) +#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK) +#define AIPS_PACRJ_TP5_MASK (0x100U) +#define AIPS_PACRJ_TP5_SHIFT (8U) +#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK) +#define AIPS_PACRJ_WP5_MASK (0x200U) +#define AIPS_PACRJ_WP5_SHIFT (9U) +#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK) +#define AIPS_PACRJ_SP5_MASK (0x400U) +#define AIPS_PACRJ_SP5_SHIFT (10U) +#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK) +#define AIPS_PACRJ_TP4_MASK (0x1000U) +#define AIPS_PACRJ_TP4_SHIFT (12U) +#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK) +#define AIPS_PACRJ_WP4_MASK (0x2000U) +#define AIPS_PACRJ_WP4_SHIFT (13U) +#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK) +#define AIPS_PACRJ_SP4_MASK (0x4000U) +#define AIPS_PACRJ_SP4_SHIFT (14U) +#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK) +#define AIPS_PACRJ_TP3_MASK (0x10000U) +#define AIPS_PACRJ_TP3_SHIFT (16U) +#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK) +#define AIPS_PACRJ_WP3_MASK (0x20000U) +#define AIPS_PACRJ_WP3_SHIFT (17U) +#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK) +#define AIPS_PACRJ_SP3_MASK (0x40000U) +#define AIPS_PACRJ_SP3_SHIFT (18U) +#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK) +#define AIPS_PACRJ_TP2_MASK (0x100000U) +#define AIPS_PACRJ_TP2_SHIFT (20U) +#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK) +#define AIPS_PACRJ_WP2_MASK (0x200000U) +#define AIPS_PACRJ_WP2_SHIFT (21U) +#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK) +#define AIPS_PACRJ_SP2_MASK (0x400000U) +#define AIPS_PACRJ_SP2_SHIFT (22U) +#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK) +#define AIPS_PACRJ_TP1_MASK (0x1000000U) +#define AIPS_PACRJ_TP1_SHIFT (24U) +#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK) +#define AIPS_PACRJ_WP1_MASK (0x2000000U) +#define AIPS_PACRJ_WP1_SHIFT (25U) +#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK) +#define AIPS_PACRJ_SP1_MASK (0x4000000U) +#define AIPS_PACRJ_SP1_SHIFT (26U) +#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK) +#define AIPS_PACRJ_TP0_MASK (0x10000000U) +#define AIPS_PACRJ_TP0_SHIFT (28U) +#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK) +#define AIPS_PACRJ_WP0_MASK (0x20000000U) +#define AIPS_PACRJ_WP0_SHIFT (29U) +#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK) +#define AIPS_PACRJ_SP0_MASK (0x40000000U) +#define AIPS_PACRJ_SP0_SHIFT (30U) +#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK) + +/*! @name PACRK - Peripheral Access Control Register */ +#define AIPS_PACRK_TP7_MASK (0x1U) +#define AIPS_PACRK_TP7_SHIFT (0U) +#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK) +#define AIPS_PACRK_WP7_MASK (0x2U) +#define AIPS_PACRK_WP7_SHIFT (1U) +#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK) +#define AIPS_PACRK_SP7_MASK (0x4U) +#define AIPS_PACRK_SP7_SHIFT (2U) +#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK) +#define AIPS_PACRK_TP6_MASK (0x10U) +#define AIPS_PACRK_TP6_SHIFT (4U) +#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK) +#define AIPS_PACRK_WP6_MASK (0x20U) +#define AIPS_PACRK_WP6_SHIFT (5U) +#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK) +#define AIPS_PACRK_SP6_MASK (0x40U) +#define AIPS_PACRK_SP6_SHIFT (6U) +#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK) +#define AIPS_PACRK_TP5_MASK (0x100U) +#define AIPS_PACRK_TP5_SHIFT (8U) +#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK) +#define AIPS_PACRK_WP5_MASK (0x200U) +#define AIPS_PACRK_WP5_SHIFT (9U) +#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK) +#define AIPS_PACRK_SP5_MASK (0x400U) +#define AIPS_PACRK_SP5_SHIFT (10U) +#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK) +#define AIPS_PACRK_TP4_MASK (0x1000U) +#define AIPS_PACRK_TP4_SHIFT (12U) +#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK) +#define AIPS_PACRK_WP4_MASK (0x2000U) +#define AIPS_PACRK_WP4_SHIFT (13U) +#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK) +#define AIPS_PACRK_SP4_MASK (0x4000U) +#define AIPS_PACRK_SP4_SHIFT (14U) +#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK) +#define AIPS_PACRK_TP3_MASK (0x10000U) +#define AIPS_PACRK_TP3_SHIFT (16U) +#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK) +#define AIPS_PACRK_WP3_MASK (0x20000U) +#define AIPS_PACRK_WP3_SHIFT (17U) +#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK) +#define AIPS_PACRK_SP3_MASK (0x40000U) +#define AIPS_PACRK_SP3_SHIFT (18U) +#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK) +#define AIPS_PACRK_TP2_MASK (0x100000U) +#define AIPS_PACRK_TP2_SHIFT (20U) +#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK) +#define AIPS_PACRK_WP2_MASK (0x200000U) +#define AIPS_PACRK_WP2_SHIFT (21U) +#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK) +#define AIPS_PACRK_SP2_MASK (0x400000U) +#define AIPS_PACRK_SP2_SHIFT (22U) +#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK) +#define AIPS_PACRK_TP1_MASK (0x1000000U) +#define AIPS_PACRK_TP1_SHIFT (24U) +#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK) +#define AIPS_PACRK_WP1_MASK (0x2000000U) +#define AIPS_PACRK_WP1_SHIFT (25U) +#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK) +#define AIPS_PACRK_SP1_MASK (0x4000000U) +#define AIPS_PACRK_SP1_SHIFT (26U) +#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK) +#define AIPS_PACRK_TP0_MASK (0x10000000U) +#define AIPS_PACRK_TP0_SHIFT (28U) +#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK) +#define AIPS_PACRK_WP0_MASK (0x20000000U) +#define AIPS_PACRK_WP0_SHIFT (29U) +#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK) +#define AIPS_PACRK_SP0_MASK (0x40000000U) +#define AIPS_PACRK_SP0_SHIFT (30U) +#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK) + +/*! @name PACRL - Peripheral Access Control Register */ +#define AIPS_PACRL_TP7_MASK (0x1U) +#define AIPS_PACRL_TP7_SHIFT (0U) +#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK) +#define AIPS_PACRL_WP7_MASK (0x2U) +#define AIPS_PACRL_WP7_SHIFT (1U) +#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK) +#define AIPS_PACRL_SP7_MASK (0x4U) +#define AIPS_PACRL_SP7_SHIFT (2U) +#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK) +#define AIPS_PACRL_TP6_MASK (0x10U) +#define AIPS_PACRL_TP6_SHIFT (4U) +#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK) +#define AIPS_PACRL_WP6_MASK (0x20U) +#define AIPS_PACRL_WP6_SHIFT (5U) +#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK) +#define AIPS_PACRL_SP6_MASK (0x40U) +#define AIPS_PACRL_SP6_SHIFT (6U) +#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK) +#define AIPS_PACRL_TP5_MASK (0x100U) +#define AIPS_PACRL_TP5_SHIFT (8U) +#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK) +#define AIPS_PACRL_WP5_MASK (0x200U) +#define AIPS_PACRL_WP5_SHIFT (9U) +#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK) +#define AIPS_PACRL_SP5_MASK (0x400U) +#define AIPS_PACRL_SP5_SHIFT (10U) +#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK) +#define AIPS_PACRL_TP4_MASK (0x1000U) +#define AIPS_PACRL_TP4_SHIFT (12U) +#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK) +#define AIPS_PACRL_WP4_MASK (0x2000U) +#define AIPS_PACRL_WP4_SHIFT (13U) +#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK) +#define AIPS_PACRL_SP4_MASK (0x4000U) +#define AIPS_PACRL_SP4_SHIFT (14U) +#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK) +#define AIPS_PACRL_TP3_MASK (0x10000U) +#define AIPS_PACRL_TP3_SHIFT (16U) +#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK) +#define AIPS_PACRL_WP3_MASK (0x20000U) +#define AIPS_PACRL_WP3_SHIFT (17U) +#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK) +#define AIPS_PACRL_SP3_MASK (0x40000U) +#define AIPS_PACRL_SP3_SHIFT (18U) +#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK) +#define AIPS_PACRL_TP2_MASK (0x100000U) +#define AIPS_PACRL_TP2_SHIFT (20U) +#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK) +#define AIPS_PACRL_WP2_MASK (0x200000U) +#define AIPS_PACRL_WP2_SHIFT (21U) +#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK) +#define AIPS_PACRL_SP2_MASK (0x400000U) +#define AIPS_PACRL_SP2_SHIFT (22U) +#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK) +#define AIPS_PACRL_TP1_MASK (0x1000000U) +#define AIPS_PACRL_TP1_SHIFT (24U) +#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK) +#define AIPS_PACRL_WP1_MASK (0x2000000U) +#define AIPS_PACRL_WP1_SHIFT (25U) +#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK) +#define AIPS_PACRL_SP1_MASK (0x4000000U) +#define AIPS_PACRL_SP1_SHIFT (26U) +#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK) +#define AIPS_PACRL_TP0_MASK (0x10000000U) +#define AIPS_PACRL_TP0_SHIFT (28U) +#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK) +#define AIPS_PACRL_WP0_MASK (0x20000000U) +#define AIPS_PACRL_WP0_SHIFT (29U) +#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK) +#define AIPS_PACRL_SP0_MASK (0x40000000U) +#define AIPS_PACRL_SP0_SHIFT (30U) +#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK) + +/*! @name PACRM - Peripheral Access Control Register */ +#define AIPS_PACRM_TP7_MASK (0x1U) +#define AIPS_PACRM_TP7_SHIFT (0U) +#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK) +#define AIPS_PACRM_WP7_MASK (0x2U) +#define AIPS_PACRM_WP7_SHIFT (1U) +#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK) +#define AIPS_PACRM_SP7_MASK (0x4U) +#define AIPS_PACRM_SP7_SHIFT (2U) +#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK) +#define AIPS_PACRM_TP6_MASK (0x10U) +#define AIPS_PACRM_TP6_SHIFT (4U) +#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK) +#define AIPS_PACRM_WP6_MASK (0x20U) +#define AIPS_PACRM_WP6_SHIFT (5U) +#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK) +#define AIPS_PACRM_SP6_MASK (0x40U) +#define AIPS_PACRM_SP6_SHIFT (6U) +#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK) +#define AIPS_PACRM_TP5_MASK (0x100U) +#define AIPS_PACRM_TP5_SHIFT (8U) +#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK) +#define AIPS_PACRM_WP5_MASK (0x200U) +#define AIPS_PACRM_WP5_SHIFT (9U) +#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK) +#define AIPS_PACRM_SP5_MASK (0x400U) +#define AIPS_PACRM_SP5_SHIFT (10U) +#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK) +#define AIPS_PACRM_TP4_MASK (0x1000U) +#define AIPS_PACRM_TP4_SHIFT (12U) +#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK) +#define AIPS_PACRM_WP4_MASK (0x2000U) +#define AIPS_PACRM_WP4_SHIFT (13U) +#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK) +#define AIPS_PACRM_SP4_MASK (0x4000U) +#define AIPS_PACRM_SP4_SHIFT (14U) +#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK) +#define AIPS_PACRM_TP3_MASK (0x10000U) +#define AIPS_PACRM_TP3_SHIFT (16U) +#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK) +#define AIPS_PACRM_WP3_MASK (0x20000U) +#define AIPS_PACRM_WP3_SHIFT (17U) +#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK) +#define AIPS_PACRM_SP3_MASK (0x40000U) +#define AIPS_PACRM_SP3_SHIFT (18U) +#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK) +#define AIPS_PACRM_TP2_MASK (0x100000U) +#define AIPS_PACRM_TP2_SHIFT (20U) +#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK) +#define AIPS_PACRM_WP2_MASK (0x200000U) +#define AIPS_PACRM_WP2_SHIFT (21U) +#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK) +#define AIPS_PACRM_SP2_MASK (0x400000U) +#define AIPS_PACRM_SP2_SHIFT (22U) +#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK) +#define AIPS_PACRM_TP1_MASK (0x1000000U) +#define AIPS_PACRM_TP1_SHIFT (24U) +#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK) +#define AIPS_PACRM_WP1_MASK (0x2000000U) +#define AIPS_PACRM_WP1_SHIFT (25U) +#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK) +#define AIPS_PACRM_SP1_MASK (0x4000000U) +#define AIPS_PACRM_SP1_SHIFT (26U) +#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK) +#define AIPS_PACRM_TP0_MASK (0x10000000U) +#define AIPS_PACRM_TP0_SHIFT (28U) +#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK) +#define AIPS_PACRM_WP0_MASK (0x20000000U) +#define AIPS_PACRM_WP0_SHIFT (29U) +#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK) +#define AIPS_PACRM_SP0_MASK (0x40000000U) +#define AIPS_PACRM_SP0_SHIFT (30U) +#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK) + +/*! @name PACRN - Peripheral Access Control Register */ +#define AIPS_PACRN_TP7_MASK (0x1U) +#define AIPS_PACRN_TP7_SHIFT (0U) +#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK) +#define AIPS_PACRN_WP7_MASK (0x2U) +#define AIPS_PACRN_WP7_SHIFT (1U) +#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK) +#define AIPS_PACRN_SP7_MASK (0x4U) +#define AIPS_PACRN_SP7_SHIFT (2U) +#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK) +#define AIPS_PACRN_TP6_MASK (0x10U) +#define AIPS_PACRN_TP6_SHIFT (4U) +#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK) +#define AIPS_PACRN_WP6_MASK (0x20U) +#define AIPS_PACRN_WP6_SHIFT (5U) +#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK) +#define AIPS_PACRN_SP6_MASK (0x40U) +#define AIPS_PACRN_SP6_SHIFT (6U) +#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK) +#define AIPS_PACRN_TP5_MASK (0x100U) +#define AIPS_PACRN_TP5_SHIFT (8U) +#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK) +#define AIPS_PACRN_WP5_MASK (0x200U) +#define AIPS_PACRN_WP5_SHIFT (9U) +#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK) +#define AIPS_PACRN_SP5_MASK (0x400U) +#define AIPS_PACRN_SP5_SHIFT (10U) +#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK) +#define AIPS_PACRN_TP4_MASK (0x1000U) +#define AIPS_PACRN_TP4_SHIFT (12U) +#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK) +#define AIPS_PACRN_WP4_MASK (0x2000U) +#define AIPS_PACRN_WP4_SHIFT (13U) +#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK) +#define AIPS_PACRN_SP4_MASK (0x4000U) +#define AIPS_PACRN_SP4_SHIFT (14U) +#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK) +#define AIPS_PACRN_TP3_MASK (0x10000U) +#define AIPS_PACRN_TP3_SHIFT (16U) +#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK) +#define AIPS_PACRN_WP3_MASK (0x20000U) +#define AIPS_PACRN_WP3_SHIFT (17U) +#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK) +#define AIPS_PACRN_SP3_MASK (0x40000U) +#define AIPS_PACRN_SP3_SHIFT (18U) +#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK) +#define AIPS_PACRN_TP2_MASK (0x100000U) +#define AIPS_PACRN_TP2_SHIFT (20U) +#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK) +#define AIPS_PACRN_WP2_MASK (0x200000U) +#define AIPS_PACRN_WP2_SHIFT (21U) +#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK) +#define AIPS_PACRN_SP2_MASK (0x400000U) +#define AIPS_PACRN_SP2_SHIFT (22U) +#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK) +#define AIPS_PACRN_TP1_MASK (0x1000000U) +#define AIPS_PACRN_TP1_SHIFT (24U) +#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK) +#define AIPS_PACRN_WP1_MASK (0x2000000U) +#define AIPS_PACRN_WP1_SHIFT (25U) +#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK) +#define AIPS_PACRN_SP1_MASK (0x4000000U) +#define AIPS_PACRN_SP1_SHIFT (26U) +#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK) +#define AIPS_PACRN_TP0_MASK (0x10000000U) +#define AIPS_PACRN_TP0_SHIFT (28U) +#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK) +#define AIPS_PACRN_WP0_MASK (0x20000000U) +#define AIPS_PACRN_WP0_SHIFT (29U) +#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK) +#define AIPS_PACRN_SP0_MASK (0x40000000U) +#define AIPS_PACRN_SP0_SHIFT (30U) +#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK) + +/*! @name PACRO - Peripheral Access Control Register */ +#define AIPS_PACRO_TP7_MASK (0x1U) +#define AIPS_PACRO_TP7_SHIFT (0U) +#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK) +#define AIPS_PACRO_WP7_MASK (0x2U) +#define AIPS_PACRO_WP7_SHIFT (1U) +#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK) +#define AIPS_PACRO_SP7_MASK (0x4U) +#define AIPS_PACRO_SP7_SHIFT (2U) +#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK) +#define AIPS_PACRO_TP6_MASK (0x10U) +#define AIPS_PACRO_TP6_SHIFT (4U) +#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK) +#define AIPS_PACRO_WP6_MASK (0x20U) +#define AIPS_PACRO_WP6_SHIFT (5U) +#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK) +#define AIPS_PACRO_SP6_MASK (0x40U) +#define AIPS_PACRO_SP6_SHIFT (6U) +#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK) +#define AIPS_PACRO_TP5_MASK (0x100U) +#define AIPS_PACRO_TP5_SHIFT (8U) +#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK) +#define AIPS_PACRO_WP5_MASK (0x200U) +#define AIPS_PACRO_WP5_SHIFT (9U) +#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK) +#define AIPS_PACRO_SP5_MASK (0x400U) +#define AIPS_PACRO_SP5_SHIFT (10U) +#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK) +#define AIPS_PACRO_TP4_MASK (0x1000U) +#define AIPS_PACRO_TP4_SHIFT (12U) +#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK) +#define AIPS_PACRO_WP4_MASK (0x2000U) +#define AIPS_PACRO_WP4_SHIFT (13U) +#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK) +#define AIPS_PACRO_SP4_MASK (0x4000U) +#define AIPS_PACRO_SP4_SHIFT (14U) +#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK) +#define AIPS_PACRO_TP3_MASK (0x10000U) +#define AIPS_PACRO_TP3_SHIFT (16U) +#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK) +#define AIPS_PACRO_WP3_MASK (0x20000U) +#define AIPS_PACRO_WP3_SHIFT (17U) +#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK) +#define AIPS_PACRO_SP3_MASK (0x40000U) +#define AIPS_PACRO_SP3_SHIFT (18U) +#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK) +#define AIPS_PACRO_TP2_MASK (0x100000U) +#define AIPS_PACRO_TP2_SHIFT (20U) +#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK) +#define AIPS_PACRO_WP2_MASK (0x200000U) +#define AIPS_PACRO_WP2_SHIFT (21U) +#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK) +#define AIPS_PACRO_SP2_MASK (0x400000U) +#define AIPS_PACRO_SP2_SHIFT (22U) +#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK) +#define AIPS_PACRO_TP1_MASK (0x1000000U) +#define AIPS_PACRO_TP1_SHIFT (24U) +#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK) +#define AIPS_PACRO_WP1_MASK (0x2000000U) +#define AIPS_PACRO_WP1_SHIFT (25U) +#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK) +#define AIPS_PACRO_SP1_MASK (0x4000000U) +#define AIPS_PACRO_SP1_SHIFT (26U) +#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK) +#define AIPS_PACRO_TP0_MASK (0x10000000U) +#define AIPS_PACRO_TP0_SHIFT (28U) +#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK) +#define AIPS_PACRO_WP0_MASK (0x20000000U) +#define AIPS_PACRO_WP0_SHIFT (29U) +#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK) +#define AIPS_PACRO_SP0_MASK (0x40000000U) +#define AIPS_PACRO_SP0_SHIFT (30U) +#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK) + +/*! @name PACRP - Peripheral Access Control Register */ +#define AIPS_PACRP_TP7_MASK (0x1U) +#define AIPS_PACRP_TP7_SHIFT (0U) +#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK) +#define AIPS_PACRP_WP7_MASK (0x2U) +#define AIPS_PACRP_WP7_SHIFT (1U) +#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK) +#define AIPS_PACRP_SP7_MASK (0x4U) +#define AIPS_PACRP_SP7_SHIFT (2U) +#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK) +#define AIPS_PACRP_TP6_MASK (0x10U) +#define AIPS_PACRP_TP6_SHIFT (4U) +#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK) +#define AIPS_PACRP_WP6_MASK (0x20U) +#define AIPS_PACRP_WP6_SHIFT (5U) +#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK) +#define AIPS_PACRP_SP6_MASK (0x40U) +#define AIPS_PACRP_SP6_SHIFT (6U) +#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK) +#define AIPS_PACRP_TP5_MASK (0x100U) +#define AIPS_PACRP_TP5_SHIFT (8U) +#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK) +#define AIPS_PACRP_WP5_MASK (0x200U) +#define AIPS_PACRP_WP5_SHIFT (9U) +#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK) +#define AIPS_PACRP_SP5_MASK (0x400U) +#define AIPS_PACRP_SP5_SHIFT (10U) +#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK) +#define AIPS_PACRP_TP4_MASK (0x1000U) +#define AIPS_PACRP_TP4_SHIFT (12U) +#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK) +#define AIPS_PACRP_WP4_MASK (0x2000U) +#define AIPS_PACRP_WP4_SHIFT (13U) +#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK) +#define AIPS_PACRP_SP4_MASK (0x4000U) +#define AIPS_PACRP_SP4_SHIFT (14U) +#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK) +#define AIPS_PACRP_TP3_MASK (0x10000U) +#define AIPS_PACRP_TP3_SHIFT (16U) +#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK) +#define AIPS_PACRP_WP3_MASK (0x20000U) +#define AIPS_PACRP_WP3_SHIFT (17U) +#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK) +#define AIPS_PACRP_SP3_MASK (0x40000U) +#define AIPS_PACRP_SP3_SHIFT (18U) +#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK) +#define AIPS_PACRP_TP2_MASK (0x100000U) +#define AIPS_PACRP_TP2_SHIFT (20U) +#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK) +#define AIPS_PACRP_WP2_MASK (0x200000U) +#define AIPS_PACRP_WP2_SHIFT (21U) +#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK) +#define AIPS_PACRP_SP2_MASK (0x400000U) +#define AIPS_PACRP_SP2_SHIFT (22U) +#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK) +#define AIPS_PACRP_TP1_MASK (0x1000000U) +#define AIPS_PACRP_TP1_SHIFT (24U) +#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK) +#define AIPS_PACRP_WP1_MASK (0x2000000U) +#define AIPS_PACRP_WP1_SHIFT (25U) +#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK) +#define AIPS_PACRP_SP1_MASK (0x4000000U) +#define AIPS_PACRP_SP1_SHIFT (26U) +#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK) +#define AIPS_PACRP_TP0_MASK (0x10000000U) +#define AIPS_PACRP_TP0_SHIFT (28U) +#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK) +#define AIPS_PACRP_WP0_MASK (0x20000000U) +#define AIPS_PACRP_WP0_SHIFT (29U) +#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK) +#define AIPS_PACRP_SP0_MASK (0x40000000U) +#define AIPS_PACRP_SP0_SHIFT (30U) +#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK) + +/*! @name PACRU - Peripheral Access Control Register */ +#define AIPS_PACRU_TP1_MASK (0x1000000U) +#define AIPS_PACRU_TP1_SHIFT (24U) +#define AIPS_PACRU_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP1_SHIFT)) & AIPS_PACRU_TP1_MASK) +#define AIPS_PACRU_WP1_MASK (0x2000000U) +#define AIPS_PACRU_WP1_SHIFT (25U) +#define AIPS_PACRU_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP1_SHIFT)) & AIPS_PACRU_WP1_MASK) +#define AIPS_PACRU_SP1_MASK (0x4000000U) +#define AIPS_PACRU_SP1_SHIFT (26U) +#define AIPS_PACRU_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP1_SHIFT)) & AIPS_PACRU_SP1_MASK) +#define AIPS_PACRU_TP0_MASK (0x10000000U) +#define AIPS_PACRU_TP0_SHIFT (28U) +#define AIPS_PACRU_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP0_SHIFT)) & AIPS_PACRU_TP0_MASK) +#define AIPS_PACRU_WP0_MASK (0x20000000U) +#define AIPS_PACRU_WP0_SHIFT (29U) +#define AIPS_PACRU_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP0_SHIFT)) & AIPS_PACRU_WP0_MASK) +#define AIPS_PACRU_SP0_MASK (0x40000000U) +#define AIPS_PACRU_SP0_SHIFT (30U) +#define AIPS_PACRU_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP0_SHIFT)) & AIPS_PACRU_SP0_MASK) + + +/*! + * @} + */ /* end of group AIPS_Register_Masks */ + + +/* AIPS - Peripheral instance base addresses */ +/** Peripheral AIPS0 base address */ +#define AIPS0_BASE (0x40000000u) +/** Peripheral AIPS0 base pointer */ +#define AIPS0 ((AIPS_Type *)AIPS0_BASE) +/** Peripheral AIPS1 base address */ +#define AIPS1_BASE (0x40080000u) +/** Peripheral AIPS1 base pointer */ +#define AIPS1 ((AIPS_Type *)AIPS1_BASE) +/** Array initializer of AIPS peripheral base addresses */ +#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } +/** Array initializer of AIPS peripheral base pointers */ +#define AIPS_BASE_PTRS { AIPS0, AIPS1 } + +/*! + * @} + */ /* end of group AIPS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AXBS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer + * @{ + */ + +/** AXBS - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x100 */ + __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ + uint8_t RESERVED_1[236]; + } SLAVE[5]; + uint8_t RESERVED_0[768]; + __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ + uint8_t RESERVED_1[252]; + __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ + uint8_t RESERVED_2[252]; + __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ + uint8_t RESERVED_3[508]; + __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ + uint8_t RESERVED_4[252]; + __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ +} AXBS_Type; + +/* ---------------------------------------------------------------------------- + -- AXBS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AXBS_Register_Masks AXBS Register Masks + * @{ + */ + +/*! @name PRS - Priority Registers Slave */ +#define AXBS_PRS_M0_MASK (0x7U) +#define AXBS_PRS_M0_SHIFT (0U) +#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK) +#define AXBS_PRS_M1_MASK (0x70U) +#define AXBS_PRS_M1_SHIFT (4U) +#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK) +#define AXBS_PRS_M2_MASK (0x700U) +#define AXBS_PRS_M2_SHIFT (8U) +#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK) +#define AXBS_PRS_M4_MASK (0x70000U) +#define AXBS_PRS_M4_SHIFT (16U) +#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK) +#define AXBS_PRS_M5_MASK (0x700000U) +#define AXBS_PRS_M5_SHIFT (20U) +#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK) + +/* The count of AXBS_PRS */ +#define AXBS_PRS_COUNT (5U) + +/*! @name CRS - Control Register */ +#define AXBS_CRS_PARK_MASK (0x7U) +#define AXBS_CRS_PARK_SHIFT (0U) +#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK) +#define AXBS_CRS_PCTL_MASK (0x30U) +#define AXBS_CRS_PCTL_SHIFT (4U) +#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK) +#define AXBS_CRS_ARB_MASK (0x300U) +#define AXBS_CRS_ARB_SHIFT (8U) +#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK) +#define AXBS_CRS_HLP_MASK (0x40000000U) +#define AXBS_CRS_HLP_SHIFT (30U) +#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK) +#define AXBS_CRS_RO_MASK (0x80000000U) +#define AXBS_CRS_RO_SHIFT (31U) +#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK) + +/* The count of AXBS_CRS */ +#define AXBS_CRS_COUNT (5U) + +/*! @name MGPCR0 - Master General Purpose Control Register */ +#define AXBS_MGPCR0_AULB_MASK (0x7U) +#define AXBS_MGPCR0_AULB_SHIFT (0U) +#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) + +/*! @name MGPCR1 - Master General Purpose Control Register */ +#define AXBS_MGPCR1_AULB_MASK (0x7U) +#define AXBS_MGPCR1_AULB_SHIFT (0U) +#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) + +/*! @name MGPCR2 - Master General Purpose Control Register */ +#define AXBS_MGPCR2_AULB_MASK (0x7U) +#define AXBS_MGPCR2_AULB_SHIFT (0U) +#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) + +/*! @name MGPCR4 - Master General Purpose Control Register */ +#define AXBS_MGPCR4_AULB_MASK (0x7U) +#define AXBS_MGPCR4_AULB_SHIFT (0U) +#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) + +/*! @name MGPCR5 - Master General Purpose Control Register */ +#define AXBS_MGPCR5_AULB_MASK (0x7U) +#define AXBS_MGPCR5_AULB_SHIFT (0U) +#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK) + + +/*! + * @} + */ /* end of group AXBS_Register_Masks */ + + +/* AXBS - Peripheral instance base addresses */ +/** Peripheral AXBS base address */ +#define AXBS_BASE (0x40004000u) +/** Peripheral AXBS base pointer */ +#define AXBS ((AXBS_Type *)AXBS_BASE) +/** Array initializer of AXBS peripheral base addresses */ +#define AXBS_BASE_ADDRS { AXBS_BASE } +/** Array initializer of AXBS peripheral base pointers */ +#define AXBS_BASE_PTRS { AXBS } + +/*! + * @} + */ /* end of group AXBS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */ + uint8_t RESERVED_3[8]; + __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */ + __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ + uint8_t RESERVED_4[48]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[16]; + uint8_t RESERVED_5[1792]; + __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) + +/*! @name CTRL1 - Control 1 register */ +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) +#define CAN_CTRL1_CLKSRC_MASK (0x2000U) +#define CAN_CTRL1_CLKSRC_SHIFT (13U) +#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) + +/*! @name TIMER - Free Running Timer */ +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) + +/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) + +/*! @name RX14MASK - Rx 14 Mask register */ +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) + +/*! @name RX15MASK - Rx 15 Mask register */ +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) + +/*! @name ECR - Error Counter */ +#define CAN_ECR_TXERRCNT_MASK (0xFFU) +#define CAN_ECR_TXERRCNT_SHIFT (0U) +#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) +#define CAN_ECR_RXERRCNT_MASK (0xFF00U) +#define CAN_ECR_RXERRCNT_SHIFT (8U) +#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) + +/*! @name ESR1 - Error and Status 1 register */ +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +/*! @name IMASK1 - Interrupt Masks 1 register */ +#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUFLM_SHIFT (0U) +#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) + +/*! @name IFLAG1 - Interrupt Flags 1 register */ +#define CAN_IFLAG1_BUF0I_MASK (0x1U) +#define CAN_IFLAG1_BUF0I_SHIFT (0U) +#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) +#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) +#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) +#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) + +/*! @name CTRL2 - Control 2 register */ +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) +#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) +#define CAN_CTRL2_WRMFRZ_SHIFT (28U) +#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) + +/*! @name ESR2 - Error and Status 2 register */ +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) + +/*! @name CRCR - CRC Register */ +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) + +/*! @name RXFGMASK - Rx FIFO Global Mask register */ +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) + +/*! @name RXFIR - Rx FIFO Information Register */ +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */ +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (16U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */ +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (16U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */ +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (16U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */ +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (16U) + +/*! @name RXIMR - Rx Individual Mask Registers */ +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (16U) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x40024000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn } +#define CAN_Error_IRQS { CAN0_Error_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer + * @{ + */ + +/** CAU - Register Layout Typedef */ +typedef struct { + __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[2048]; + __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */ + __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */ + __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */ + uint8_t RESERVED_1[20]; + __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */ + __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */ + __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */ + uint8_t RESERVED_2[20]; + __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */ + __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */ + __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */ + uint8_t RESERVED_3[20]; + __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */ + __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */ + __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */ + uint8_t RESERVED_4[84]; + __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */ + __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */ + __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */ + uint8_t RESERVED_5[20]; + __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */ + __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */ + __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */ + uint8_t RESERVED_6[276]; + __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */ + __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */ + __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */ + uint8_t RESERVED_7[20]; + __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */ + __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */ + __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */ +} CAU_Type; + +/* ---------------------------------------------------------------------------- + -- CAU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAU_Register_Masks CAU Register Masks + * @{ + */ + +/*! @name DIRECT - Direct access register 0..Direct access register 15 */ +#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK) +#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK) +#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK) +#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK) +#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK) +#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK) +#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK) +#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK) +#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK) +#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK) +#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK) +#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK) +#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK) +#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK) +#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK) +#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU) +#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U) +#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK) + +/* The count of CAU_DIRECT */ +#define CAU_DIRECT_COUNT (16U) + +/*! @name LDR_CASR - Status register - Load Register command */ +#define CAU_LDR_CASR_IC_MASK (0x1U) +#define CAU_LDR_CASR_IC_SHIFT (0U) +#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK) +#define CAU_LDR_CASR_DPE_MASK (0x2U) +#define CAU_LDR_CASR_DPE_SHIFT (1U) +#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK) +#define CAU_LDR_CASR_VER_MASK (0xF0000000U) +#define CAU_LDR_CASR_VER_SHIFT (28U) +#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK) + +/*! @name LDR_CAA - Accumulator register - Load Register command */ +#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_LDR_CAA_ACC_SHIFT (0U) +#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK) + +/*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */ +#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA0_SHIFT (0U) +#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK) +#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA1_SHIFT (0U) +#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK) +#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA2_SHIFT (0U) +#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK) +#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA3_SHIFT (0U) +#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK) +#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA4_SHIFT (0U) +#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK) +#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA5_SHIFT (0U) +#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK) +#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA6_SHIFT (0U) +#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK) +#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA7_SHIFT (0U) +#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK) +#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_LDR_CA_CA8_SHIFT (0U) +#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK) + +/* The count of CAU_LDR_CA */ +#define CAU_LDR_CA_COUNT (9U) + +/*! @name STR_CASR - Status register - Store Register command */ +#define CAU_STR_CASR_IC_MASK (0x1U) +#define CAU_STR_CASR_IC_SHIFT (0U) +#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK) +#define CAU_STR_CASR_DPE_MASK (0x2U) +#define CAU_STR_CASR_DPE_SHIFT (1U) +#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK) +#define CAU_STR_CASR_VER_MASK (0xF0000000U) +#define CAU_STR_CASR_VER_SHIFT (28U) +#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK) + +/*! @name STR_CAA - Accumulator register - Store Register command */ +#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_STR_CAA_ACC_SHIFT (0U) +#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK) + +/*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */ +#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA0_SHIFT (0U) +#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK) +#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA1_SHIFT (0U) +#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK) +#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA2_SHIFT (0U) +#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK) +#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA3_SHIFT (0U) +#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK) +#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA4_SHIFT (0U) +#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK) +#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA5_SHIFT (0U) +#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK) +#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA6_SHIFT (0U) +#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK) +#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA7_SHIFT (0U) +#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK) +#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_STR_CA_CA8_SHIFT (0U) +#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK) + +/* The count of CAU_STR_CA */ +#define CAU_STR_CA_COUNT (9U) + +/*! @name ADR_CASR - Status register - Add Register command */ +#define CAU_ADR_CASR_IC_MASK (0x1U) +#define CAU_ADR_CASR_IC_SHIFT (0U) +#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK) +#define CAU_ADR_CASR_DPE_MASK (0x2U) +#define CAU_ADR_CASR_DPE_SHIFT (1U) +#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK) +#define CAU_ADR_CASR_VER_MASK (0xF0000000U) +#define CAU_ADR_CASR_VER_SHIFT (28U) +#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK) + +/*! @name ADR_CAA - Accumulator register - Add to register command */ +#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_ADR_CAA_ACC_SHIFT (0U) +#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK) + +/*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */ +#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA0_SHIFT (0U) +#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK) +#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA1_SHIFT (0U) +#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK) +#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA2_SHIFT (0U) +#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK) +#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA3_SHIFT (0U) +#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK) +#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA4_SHIFT (0U) +#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK) +#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA5_SHIFT (0U) +#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK) +#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA6_SHIFT (0U) +#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK) +#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA7_SHIFT (0U) +#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK) +#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_ADR_CA_CA8_SHIFT (0U) +#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK) + +/* The count of CAU_ADR_CA */ +#define CAU_ADR_CA_COUNT (9U) + +/*! @name RADR_CASR - Status register - Reverse and Add to Register command */ +#define CAU_RADR_CASR_IC_MASK (0x1U) +#define CAU_RADR_CASR_IC_SHIFT (0U) +#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK) +#define CAU_RADR_CASR_DPE_MASK (0x2U) +#define CAU_RADR_CASR_DPE_SHIFT (1U) +#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK) +#define CAU_RADR_CASR_VER_MASK (0xF0000000U) +#define CAU_RADR_CASR_VER_SHIFT (28U) +#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK) + +/*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */ +#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_RADR_CAA_ACC_SHIFT (0U) +#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK) + +/*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */ +#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA0_SHIFT (0U) +#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK) +#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA1_SHIFT (0U) +#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK) +#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA2_SHIFT (0U) +#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK) +#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA3_SHIFT (0U) +#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK) +#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA4_SHIFT (0U) +#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK) +#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA5_SHIFT (0U) +#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK) +#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA6_SHIFT (0U) +#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK) +#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA7_SHIFT (0U) +#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK) +#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_RADR_CA_CA8_SHIFT (0U) +#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK) + +/* The count of CAU_RADR_CA */ +#define CAU_RADR_CA_COUNT (9U) + +/*! @name XOR_CASR - Status register - Exclusive Or command */ +#define CAU_XOR_CASR_IC_MASK (0x1U) +#define CAU_XOR_CASR_IC_SHIFT (0U) +#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK) +#define CAU_XOR_CASR_DPE_MASK (0x2U) +#define CAU_XOR_CASR_DPE_SHIFT (1U) +#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK) +#define CAU_XOR_CASR_VER_MASK (0xF0000000U) +#define CAU_XOR_CASR_VER_SHIFT (28U) +#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK) + +/*! @name XOR_CAA - Accumulator register - Exclusive Or command */ +#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_XOR_CAA_ACC_SHIFT (0U) +#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK) + +/*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */ +#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA0_SHIFT (0U) +#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK) +#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA1_SHIFT (0U) +#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK) +#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA2_SHIFT (0U) +#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK) +#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA3_SHIFT (0U) +#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK) +#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA4_SHIFT (0U) +#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK) +#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA5_SHIFT (0U) +#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK) +#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA6_SHIFT (0U) +#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK) +#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA7_SHIFT (0U) +#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK) +#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_XOR_CA_CA8_SHIFT (0U) +#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK) + +/* The count of CAU_XOR_CA */ +#define CAU_XOR_CA_COUNT (9U) + +/*! @name ROTL_CASR - Status register - Rotate Left command */ +#define CAU_ROTL_CASR_IC_MASK (0x1U) +#define CAU_ROTL_CASR_IC_SHIFT (0U) +#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK) +#define CAU_ROTL_CASR_DPE_MASK (0x2U) +#define CAU_ROTL_CASR_DPE_SHIFT (1U) +#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK) +#define CAU_ROTL_CASR_VER_MASK (0xF0000000U) +#define CAU_ROTL_CASR_VER_SHIFT (28U) +#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK) + +/*! @name ROTL_CAA - Accumulator register - Rotate Left command */ +#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CAA_ACC_SHIFT (0U) +#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK) + +/*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */ +#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA0_SHIFT (0U) +#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK) +#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA1_SHIFT (0U) +#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK) +#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA2_SHIFT (0U) +#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK) +#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA3_SHIFT (0U) +#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK) +#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA4_SHIFT (0U) +#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK) +#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA5_SHIFT (0U) +#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK) +#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA6_SHIFT (0U) +#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK) +#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA7_SHIFT (0U) +#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK) +#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_ROTL_CA_CA8_SHIFT (0U) +#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK) + +/* The count of CAU_ROTL_CA */ +#define CAU_ROTL_CA_COUNT (9U) + +/*! @name AESC_CASR - Status register - AES Column Operation command */ +#define CAU_AESC_CASR_IC_MASK (0x1U) +#define CAU_AESC_CASR_IC_SHIFT (0U) +#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK) +#define CAU_AESC_CASR_DPE_MASK (0x2U) +#define CAU_AESC_CASR_DPE_SHIFT (1U) +#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK) +#define CAU_AESC_CASR_VER_MASK (0xF0000000U) +#define CAU_AESC_CASR_VER_SHIFT (28U) +#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK) + +/*! @name AESC_CAA - Accumulator register - AES Column Operation command */ +#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_AESC_CAA_ACC_SHIFT (0U) +#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK) + +/*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */ +#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA0_SHIFT (0U) +#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK) +#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA1_SHIFT (0U) +#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK) +#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA2_SHIFT (0U) +#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK) +#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA3_SHIFT (0U) +#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK) +#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA4_SHIFT (0U) +#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK) +#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA5_SHIFT (0U) +#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK) +#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA6_SHIFT (0U) +#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK) +#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA7_SHIFT (0U) +#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK) +#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_AESC_CA_CA8_SHIFT (0U) +#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK) + +/* The count of CAU_AESC_CA */ +#define CAU_AESC_CA_COUNT (9U) + +/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */ +#define CAU_AESIC_CASR_IC_MASK (0x1U) +#define CAU_AESIC_CASR_IC_SHIFT (0U) +#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK) +#define CAU_AESIC_CASR_DPE_MASK (0x2U) +#define CAU_AESIC_CASR_DPE_SHIFT (1U) +#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK) +#define CAU_AESIC_CASR_VER_MASK (0xF0000000U) +#define CAU_AESIC_CASR_VER_SHIFT (28U) +#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK) + +/*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */ +#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CAA_ACC_SHIFT (0U) +#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK) + +/*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */ +#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA0_SHIFT (0U) +#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK) +#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA1_SHIFT (0U) +#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK) +#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA2_SHIFT (0U) +#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK) +#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA3_SHIFT (0U) +#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK) +#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA4_SHIFT (0U) +#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK) +#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA5_SHIFT (0U) +#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK) +#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA6_SHIFT (0U) +#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK) +#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA7_SHIFT (0U) +#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK) +#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU) +#define CAU_AESIC_CA_CA8_SHIFT (0U) +#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK) + +/* The count of CAU_AESIC_CA */ +#define CAU_AESIC_CA_COUNT (9U) + + +/*! + * @} + */ /* end of group CAU_Register_Masks */ + + +/* CAU - Peripheral instance base addresses */ +/** Peripheral CAU base address */ +#define CAU_BASE (0xE0081000u) +/** Peripheral CAU base pointer */ +#define CAU ((CAU_Type *)CAU_BASE) +/** Array initializer of CAU peripheral base addresses */ +#define CAU_BASE_ADDRS { CAU_BASE } +/** Array initializer of CAU peripheral base pointers */ +#define CAU_BASE_PTRS { CAU } + +/*! + * @} + */ /* end of group CAU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer + * @{ + */ + +/** CMP - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ + __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ + __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ + __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ + __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ + __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ +} CMP_Type; + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/*! @name CR0 - CMP Control Register 0 */ +#define CMP_CR0_HYSTCTR_MASK (0x3U) +#define CMP_CR0_HYSTCTR_SHIFT (0U) +#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) +#define CMP_CR0_FILTER_CNT_MASK (0x70U) +#define CMP_CR0_FILTER_CNT_SHIFT (4U) +#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) + +/*! @name CR1 - CMP Control Register 1 */ +#define CMP_CR1_EN_MASK (0x1U) +#define CMP_CR1_EN_SHIFT (0U) +#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) +#define CMP_CR1_OPE_MASK (0x2U) +#define CMP_CR1_OPE_SHIFT (1U) +#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) +#define CMP_CR1_COS_MASK (0x4U) +#define CMP_CR1_COS_SHIFT (2U) +#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) +#define CMP_CR1_INV_MASK (0x8U) +#define CMP_CR1_INV_SHIFT (3U) +#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) +#define CMP_CR1_PMODE_MASK (0x10U) +#define CMP_CR1_PMODE_SHIFT (4U) +#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) +#define CMP_CR1_WE_MASK (0x40U) +#define CMP_CR1_WE_SHIFT (6U) +#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) +#define CMP_CR1_SE_MASK (0x80U) +#define CMP_CR1_SE_SHIFT (7U) +#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) + +/*! @name FPR - CMP Filter Period Register */ +#define CMP_FPR_FILT_PER_MASK (0xFFU) +#define CMP_FPR_FILT_PER_SHIFT (0U) +#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) + +/*! @name SCR - CMP Status and Control Register */ +#define CMP_SCR_COUT_MASK (0x1U) +#define CMP_SCR_COUT_SHIFT (0U) +#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) +#define CMP_SCR_CFF_MASK (0x2U) +#define CMP_SCR_CFF_SHIFT (1U) +#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) +#define CMP_SCR_CFR_MASK (0x4U) +#define CMP_SCR_CFR_SHIFT (2U) +#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) +#define CMP_SCR_IEF_MASK (0x8U) +#define CMP_SCR_IEF_SHIFT (3U) +#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) +#define CMP_SCR_IER_MASK (0x10U) +#define CMP_SCR_IER_SHIFT (4U) +#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) +#define CMP_SCR_DMAEN_MASK (0x40U) +#define CMP_SCR_DMAEN_SHIFT (6U) +#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) + +/*! @name DACCR - DAC Control Register */ +#define CMP_DACCR_VOSEL_MASK (0x3FU) +#define CMP_DACCR_VOSEL_SHIFT (0U) +#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) +#define CMP_DACCR_VRSEL_MASK (0x40U) +#define CMP_DACCR_VRSEL_SHIFT (6U) +#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) +#define CMP_DACCR_DACEN_MASK (0x80U) +#define CMP_DACCR_DACEN_SHIFT (7U) +#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) + +/*! @name MUXCR - MUX Control Register */ +#define CMP_MUXCR_MSEL_MASK (0x7U) +#define CMP_MUXCR_MSEL_SHIFT (0U) +#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) +#define CMP_MUXCR_PSEL_MASK (0x38U) +#define CMP_MUXCR_PSEL_SHIFT (3U) +#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) +#define CMP_MUXCR_PSTM_MASK (0x80U) +#define CMP_MUXCR_PSTM_SHIFT (7U) +#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK) + + +/*! + * @} + */ /* end of group CMP_Register_Masks */ + + +/* CMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x40073000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((CMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x40073008u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((CMP_Type *)CMP1_BASE) +/** Peripheral CMP2 base address */ +#define CMP2_BASE (0x40073010u) +/** Peripheral CMP2 base pointer */ +#define CMP2 ((CMP_Type *)CMP2_BASE) +/** Array initializer of CMP peripheral base addresses */ +#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE } +/** Array initializer of CMP peripheral base pointers */ +#define CMP_BASE_PTRS { CMP0, CMP1, CMP2 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn } + +/*! + * @} + */ /* end of group CMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer + * @{ + */ + +/** CMT - Register Layout Typedef */ +typedef struct { + __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */ + __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */ + __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */ + __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */ + __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */ + __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */ + __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */ + __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */ + __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */ + __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */ + __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */ + __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */ +} CMT_Type; + +/* ---------------------------------------------------------------------------- + -- CMT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMT_Register_Masks CMT Register Masks + * @{ + */ + +/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */ +#define CMT_CGH1_PH_MASK (0xFFU) +#define CMT_CGH1_PH_SHIFT (0U) +#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK) + +/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */ +#define CMT_CGL1_PL_MASK (0xFFU) +#define CMT_CGL1_PL_SHIFT (0U) +#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK) + +/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */ +#define CMT_CGH2_SH_MASK (0xFFU) +#define CMT_CGH2_SH_SHIFT (0U) +#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK) + +/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */ +#define CMT_CGL2_SL_MASK (0xFFU) +#define CMT_CGL2_SL_SHIFT (0U) +#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK) + +/*! @name OC - CMT Output Control Register */ +#define CMT_OC_IROPEN_MASK (0x20U) +#define CMT_OC_IROPEN_SHIFT (5U) +#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK) +#define CMT_OC_CMTPOL_MASK (0x40U) +#define CMT_OC_CMTPOL_SHIFT (6U) +#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK) +#define CMT_OC_IROL_MASK (0x80U) +#define CMT_OC_IROL_SHIFT (7U) +#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK) + +/*! @name MSC - CMT Modulator Status and Control Register */ +#define CMT_MSC_MCGEN_MASK (0x1U) +#define CMT_MSC_MCGEN_SHIFT (0U) +#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK) +#define CMT_MSC_EOCIE_MASK (0x2U) +#define CMT_MSC_EOCIE_SHIFT (1U) +#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK) +#define CMT_MSC_FSK_MASK (0x4U) +#define CMT_MSC_FSK_SHIFT (2U) +#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK) +#define CMT_MSC_BASE_MASK (0x8U) +#define CMT_MSC_BASE_SHIFT (3U) +#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK) +#define CMT_MSC_EXSPC_MASK (0x10U) +#define CMT_MSC_EXSPC_SHIFT (4U) +#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK) +#define CMT_MSC_CMTDIV_MASK (0x60U) +#define CMT_MSC_CMTDIV_SHIFT (5U) +#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK) +#define CMT_MSC_EOCF_MASK (0x80U) +#define CMT_MSC_EOCF_SHIFT (7U) +#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK) + +/*! @name CMD1 - CMT Modulator Data Register Mark High */ +#define CMT_CMD1_MB_MASK (0xFFU) +#define CMT_CMD1_MB_SHIFT (0U) +#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK) + +/*! @name CMD2 - CMT Modulator Data Register Mark Low */ +#define CMT_CMD2_MB_MASK (0xFFU) +#define CMT_CMD2_MB_SHIFT (0U) +#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK) + +/*! @name CMD3 - CMT Modulator Data Register Space High */ +#define CMT_CMD3_SB_MASK (0xFFU) +#define CMT_CMD3_SB_SHIFT (0U) +#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK) + +/*! @name CMD4 - CMT Modulator Data Register Space Low */ +#define CMT_CMD4_SB_MASK (0xFFU) +#define CMT_CMD4_SB_SHIFT (0U) +#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK) + +/*! @name PPS - CMT Primary Prescaler Register */ +#define CMT_PPS_PPSDIV_MASK (0xFU) +#define CMT_PPS_PPSDIV_SHIFT (0U) +#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK) + +/*! @name DMA - CMT Direct Memory Access Register */ +#define CMT_DMA_DMA_MASK (0x1U) +#define CMT_DMA_DMA_SHIFT (0U) +#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK) + + +/*! + * @} + */ /* end of group CMT_Register_Masks */ + + +/* CMT - Peripheral instance base addresses */ +/** Peripheral CMT base address */ +#define CMT_BASE (0x40062000u) +/** Peripheral CMT base pointer */ +#define CMT ((CMT_Type *)CMT_BASE) +/** Array initializer of CMT peripheral base addresses */ +#define CMT_BASE_ADDRS { CMT_BASE } +/** Array initializer of CMT peripheral base pointers */ +#define CMT_BASE_PTRS { CMT } +/** Interrupt vectors for the CMT peripheral type */ +#define CMT_IRQS { CMT_IRQn } + +/*! + * @} + */ /* end of group CMT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ + __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ + __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ + __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ + __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ + } ACCESS8BIT; + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ + } GPOLY_ACCESS8BIT; + }; + union { /* offset: 0x8 */ + __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ + } CTRL_ACCESS8BIT; + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name DATAL - CRC_DATAL register. */ +#define CRC_DATAL_DATAL_MASK (0xFFFFU) +#define CRC_DATAL_DATAL_SHIFT (0U) +#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) + +/*! @name DATAH - CRC_DATAH register. */ +#define CRC_DATAH_DATAH_MASK (0xFFFFU) +#define CRC_DATAH_DATAH_SHIFT (0U) +#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) + +/*! @name DATA - CRC Data register */ +#define CRC_DATA_LL_MASK (0xFFU) +#define CRC_DATA_LL_SHIFT (0U) +#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) +#define CRC_DATA_LU_MASK (0xFF00U) +#define CRC_DATA_LU_SHIFT (8U) +#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) +#define CRC_DATA_HL_MASK (0xFF0000U) +#define CRC_DATA_HL_SHIFT (16U) +#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) +#define CRC_DATA_HU_MASK (0xFF000000U) +#define CRC_DATA_HU_SHIFT (24U) +#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) + +/*! @name DATALL - CRC_DATALL register. */ +#define CRC_DATALL_DATALL_MASK (0xFFU) +#define CRC_DATALL_DATALL_SHIFT (0U) +#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) + +/*! @name DATALU - CRC_DATALU register. */ +#define CRC_DATALU_DATALU_MASK (0xFFU) +#define CRC_DATALU_DATALU_SHIFT (0U) +#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) + +/*! @name DATAHL - CRC_DATAHL register. */ +#define CRC_DATAHL_DATAHL_MASK (0xFFU) +#define CRC_DATAHL_DATAHL_SHIFT (0U) +#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) + +/*! @name DATAHU - CRC_DATAHU register. */ +#define CRC_DATAHU_DATAHU_MASK (0xFFU) +#define CRC_DATAHU_DATAHU_SHIFT (0U) +#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) + +/*! @name GPOLYL - CRC_GPOLYL register. */ +#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) +#define CRC_GPOLYL_GPOLYL_SHIFT (0U) +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) + +/*! @name GPOLYH - CRC_GPOLYH register. */ +#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) +#define CRC_GPOLYH_GPOLYH_SHIFT (0U) +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) + +/*! @name GPOLY - CRC Polynomial register */ +#define CRC_GPOLY_LOW_MASK (0xFFFFU) +#define CRC_GPOLY_LOW_SHIFT (0U) +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) +#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) +#define CRC_GPOLY_HIGH_SHIFT (16U) +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) + +/*! @name GPOLYLL - CRC_GPOLYLL register. */ +#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) +#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) + +/*! @name GPOLYLU - CRC_GPOLYLU register. */ +#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) +#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) + +/*! @name GPOLYHL - CRC_GPOLYHL register. */ +#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) +#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) + +/*! @name GPOLYHU - CRC_GPOLYHU register. */ +#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) +#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) + +/*! @name CTRL - CRC Control register */ +#define CRC_CTRL_TCRC_MASK (0x1000000U) +#define CRC_CTRL_TCRC_SHIFT (24U) +#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) +#define CRC_CTRL_WAS_MASK (0x2000000U) +#define CRC_CTRL_WAS_SHIFT (25U) +#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) +#define CRC_CTRL_FXOR_MASK (0x4000000U) +#define CRC_CTRL_FXOR_SHIFT (26U) +#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) +#define CRC_CTRL_TOTR_MASK (0x30000000U) +#define CRC_CTRL_TOTR_SHIFT (28U) +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) +#define CRC_CTRL_TOT_MASK (0xC0000000U) +#define CRC_CTRL_TOT_SHIFT (30U) +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) + +/*! @name CTRLHU - CRC_CTRLHU register. */ +#define CRC_CTRLHU_TCRC_MASK (0x1U) +#define CRC_CTRLHU_TCRC_SHIFT (0U) +#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) +#define CRC_CTRLHU_WAS_MASK (0x2U) +#define CRC_CTRLHU_WAS_SHIFT (1U) +#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) +#define CRC_CTRLHU_FXOR_MASK (0x4U) +#define CRC_CTRLHU_FXOR_SHIFT (2U) +#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) +#define CRC_CTRLHU_TOTR_MASK (0x30U) +#define CRC_CTRLHU_TOTR_SHIFT (4U) +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) +#define CRC_CTRLHU_TOT_MASK (0xC0U) +#define CRC_CTRLHU_TOT_SHIFT (6U) +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC base address */ +#define CRC_BASE (0x40032000u) +/** Peripheral CRC base pointer */ +#define CRC0 ((CRC_Type *)CRC_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DAC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer + * @{ + */ + +/** DAC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x2 */ + __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ + __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ + } DAT[16]; + __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ + __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ + __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ + __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ +} DAC_Type; + +/* ---------------------------------------------------------------------------- + -- DAC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DAC_Register_Masks DAC Register Masks + * @{ + */ + +/*! @name DATL - DAC Data Low Register */ +#define DAC_DATL_DATA0_MASK (0xFFU) +#define DAC_DATL_DATA0_SHIFT (0U) +#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) + +/* The count of DAC_DATL */ +#define DAC_DATL_COUNT (16U) + +/*! @name DATH - DAC Data High Register */ +#define DAC_DATH_DATA1_MASK (0xFU) +#define DAC_DATH_DATA1_SHIFT (0U) +#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) + +/* The count of DAC_DATH */ +#define DAC_DATH_COUNT (16U) + +/*! @name SR - DAC Status Register */ +#define DAC_SR_DACBFRPBF_MASK (0x1U) +#define DAC_SR_DACBFRPBF_SHIFT (0U) +#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) +#define DAC_SR_DACBFRPTF_MASK (0x2U) +#define DAC_SR_DACBFRPTF_SHIFT (1U) +#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) +#define DAC_SR_DACBFWMF_MASK (0x4U) +#define DAC_SR_DACBFWMF_SHIFT (2U) +#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK) + +/*! @name C0 - DAC Control Register */ +#define DAC_C0_DACBBIEN_MASK (0x1U) +#define DAC_C0_DACBBIEN_SHIFT (0U) +#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) +#define DAC_C0_DACBTIEN_MASK (0x2U) +#define DAC_C0_DACBTIEN_SHIFT (1U) +#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) +#define DAC_C0_DACBWIEN_MASK (0x4U) +#define DAC_C0_DACBWIEN_SHIFT (2U) +#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK) +#define DAC_C0_LPEN_MASK (0x8U) +#define DAC_C0_LPEN_SHIFT (3U) +#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) +#define DAC_C0_DACSWTRG_MASK (0x10U) +#define DAC_C0_DACSWTRG_SHIFT (4U) +#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) +#define DAC_C0_DACTRGSEL_MASK (0x20U) +#define DAC_C0_DACTRGSEL_SHIFT (5U) +#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) +#define DAC_C0_DACRFS_MASK (0x40U) +#define DAC_C0_DACRFS_SHIFT (6U) +#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) +#define DAC_C0_DACEN_MASK (0x80U) +#define DAC_C0_DACEN_SHIFT (7U) +#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) + +/*! @name C1 - DAC Control Register 1 */ +#define DAC_C1_DACBFEN_MASK (0x1U) +#define DAC_C1_DACBFEN_SHIFT (0U) +#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) +#define DAC_C1_DACBFMD_MASK (0x6U) +#define DAC_C1_DACBFMD_SHIFT (1U) +#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) +#define DAC_C1_DACBFWM_MASK (0x18U) +#define DAC_C1_DACBFWM_SHIFT (3U) +#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK) +#define DAC_C1_DMAEN_MASK (0x80U) +#define DAC_C1_DMAEN_SHIFT (7U) +#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) + +/*! @name C2 - DAC Control Register 2 */ +#define DAC_C2_DACBFUP_MASK (0xFU) +#define DAC_C2_DACBFUP_SHIFT (0U) +#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) +#define DAC_C2_DACBFRP_MASK (0xF0U) +#define DAC_C2_DACBFRP_SHIFT (4U) +#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) + + +/*! + * @} + */ /* end of group DAC_Register_Masks */ + + +/* DAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400CC000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((DAC_Type *)DAC0_BASE) +/** Peripheral DAC1 base address */ +#define DAC1_BASE (0x400CD000u) +/** Peripheral DAC1 base pointer */ +#define DAC1 ((DAC_Type *)DAC1_BASE) +/** Array initializer of DAC peripheral base addresses */ +#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE } +/** Array initializer of DAC peripheral base pointers */ +#define DAC_BASE_PTRS { DAC0, DAC1 } +/** Interrupt vectors for the DAC peripheral type */ +#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn } + +/*! + * @} + */ /* end of group DAC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control Register, offset: 0x0 */ + __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ + __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ + __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ + __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ + __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ + __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ + __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ + __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ + __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ + uint8_t RESERVED_2[4]; + __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ + uint8_t RESERVED_4[4]; + __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ + uint8_t RESERVED_5[200]; + __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ + __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ + __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ + __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ + __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ + __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ + __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ + __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ + __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ + __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ + __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ + __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ + __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ + __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ + __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ + __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ + uint8_t RESERVED_6[3824]; + struct { /* offset: 0x1000, array step: 0x20 */ + __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ + union { /* offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */ + }; + __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ + __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ + union { /* offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ + }; + __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ + __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ + union { /* offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ + }; + } TCD[16]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CR - Control Register */ +#define DMA_CR_EDBG_MASK (0x2U) +#define DMA_CR_EDBG_SHIFT (1U) +#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) +#define DMA_CR_ERCA_MASK (0x4U) +#define DMA_CR_ERCA_SHIFT (2U) +#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) +#define DMA_CR_HOE_MASK (0x10U) +#define DMA_CR_HOE_SHIFT (4U) +#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) +#define DMA_CR_HALT_MASK (0x20U) +#define DMA_CR_HALT_SHIFT (5U) +#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) +#define DMA_CR_CLM_MASK (0x40U) +#define DMA_CR_CLM_SHIFT (6U) +#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) +#define DMA_CR_EMLM_MASK (0x80U) +#define DMA_CR_EMLM_SHIFT (7U) +#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) +#define DMA_CR_ECX_MASK (0x10000U) +#define DMA_CR_ECX_SHIFT (16U) +#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) +#define DMA_CR_CX_MASK (0x20000U) +#define DMA_CR_CX_SHIFT (17U) +#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) + +/*! @name ES - Error Status Register */ +#define DMA_ES_DBE_MASK (0x1U) +#define DMA_ES_DBE_SHIFT (0U) +#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) +#define DMA_ES_SBE_MASK (0x2U) +#define DMA_ES_SBE_SHIFT (1U) +#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) +#define DMA_ES_SGE_MASK (0x4U) +#define DMA_ES_SGE_SHIFT (2U) +#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) +#define DMA_ES_NCE_MASK (0x8U) +#define DMA_ES_NCE_SHIFT (3U) +#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) +#define DMA_ES_DOE_MASK (0x10U) +#define DMA_ES_DOE_SHIFT (4U) +#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) +#define DMA_ES_DAE_MASK (0x20U) +#define DMA_ES_DAE_SHIFT (5U) +#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) +#define DMA_ES_SOE_MASK (0x40U) +#define DMA_ES_SOE_SHIFT (6U) +#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) +#define DMA_ES_SAE_MASK (0x80U) +#define DMA_ES_SAE_SHIFT (7U) +#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) +#define DMA_ES_ERRCHN_MASK (0xF00U) +#define DMA_ES_ERRCHN_SHIFT (8U) +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) +#define DMA_ES_CPE_MASK (0x4000U) +#define DMA_ES_CPE_SHIFT (14U) +#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) +#define DMA_ES_ECX_MASK (0x10000U) +#define DMA_ES_ECX_SHIFT (16U) +#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) +#define DMA_ES_VLD_MASK (0x80000000U) +#define DMA_ES_VLD_SHIFT (31U) +#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) + +/*! @name ERQ - Enable Request Register */ +#define DMA_ERQ_ERQ0_MASK (0x1U) +#define DMA_ERQ_ERQ0_SHIFT (0U) +#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) +#define DMA_ERQ_ERQ1_MASK (0x2U) +#define DMA_ERQ_ERQ1_SHIFT (1U) +#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) +#define DMA_ERQ_ERQ2_MASK (0x4U) +#define DMA_ERQ_ERQ2_SHIFT (2U) +#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) +#define DMA_ERQ_ERQ3_MASK (0x8U) +#define DMA_ERQ_ERQ3_SHIFT (3U) +#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) +#define DMA_ERQ_ERQ4_MASK (0x10U) +#define DMA_ERQ_ERQ4_SHIFT (4U) +#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) +#define DMA_ERQ_ERQ5_MASK (0x20U) +#define DMA_ERQ_ERQ5_SHIFT (5U) +#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) +#define DMA_ERQ_ERQ6_MASK (0x40U) +#define DMA_ERQ_ERQ6_SHIFT (6U) +#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) +#define DMA_ERQ_ERQ7_MASK (0x80U) +#define DMA_ERQ_ERQ7_SHIFT (7U) +#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) +#define DMA_ERQ_ERQ8_MASK (0x100U) +#define DMA_ERQ_ERQ8_SHIFT (8U) +#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) +#define DMA_ERQ_ERQ9_MASK (0x200U) +#define DMA_ERQ_ERQ9_SHIFT (9U) +#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) +#define DMA_ERQ_ERQ10_MASK (0x400U) +#define DMA_ERQ_ERQ10_SHIFT (10U) +#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) +#define DMA_ERQ_ERQ11_MASK (0x800U) +#define DMA_ERQ_ERQ11_SHIFT (11U) +#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) +#define DMA_ERQ_ERQ12_MASK (0x1000U) +#define DMA_ERQ_ERQ12_SHIFT (12U) +#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) +#define DMA_ERQ_ERQ13_MASK (0x2000U) +#define DMA_ERQ_ERQ13_SHIFT (13U) +#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) +#define DMA_ERQ_ERQ14_MASK (0x4000U) +#define DMA_ERQ_ERQ14_SHIFT (14U) +#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) +#define DMA_ERQ_ERQ15_MASK (0x8000U) +#define DMA_ERQ_ERQ15_SHIFT (15U) +#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) + +/*! @name EEI - Enable Error Interrupt Register */ +#define DMA_EEI_EEI0_MASK (0x1U) +#define DMA_EEI_EEI0_SHIFT (0U) +#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) +#define DMA_EEI_EEI1_MASK (0x2U) +#define DMA_EEI_EEI1_SHIFT (1U) +#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) +#define DMA_EEI_EEI2_MASK (0x4U) +#define DMA_EEI_EEI2_SHIFT (2U) +#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) +#define DMA_EEI_EEI3_MASK (0x8U) +#define DMA_EEI_EEI3_SHIFT (3U) +#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) +#define DMA_EEI_EEI4_MASK (0x10U) +#define DMA_EEI_EEI4_SHIFT (4U) +#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) +#define DMA_EEI_EEI5_MASK (0x20U) +#define DMA_EEI_EEI5_SHIFT (5U) +#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) +#define DMA_EEI_EEI6_MASK (0x40U) +#define DMA_EEI_EEI6_SHIFT (6U) +#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) +#define DMA_EEI_EEI7_MASK (0x80U) +#define DMA_EEI_EEI7_SHIFT (7U) +#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) +#define DMA_EEI_EEI8_MASK (0x100U) +#define DMA_EEI_EEI8_SHIFT (8U) +#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) +#define DMA_EEI_EEI9_MASK (0x200U) +#define DMA_EEI_EEI9_SHIFT (9U) +#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) +#define DMA_EEI_EEI10_MASK (0x400U) +#define DMA_EEI_EEI10_SHIFT (10U) +#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) +#define DMA_EEI_EEI11_MASK (0x800U) +#define DMA_EEI_EEI11_SHIFT (11U) +#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) +#define DMA_EEI_EEI12_MASK (0x1000U) +#define DMA_EEI_EEI12_SHIFT (12U) +#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) +#define DMA_EEI_EEI13_MASK (0x2000U) +#define DMA_EEI_EEI13_SHIFT (13U) +#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) +#define DMA_EEI_EEI14_MASK (0x4000U) +#define DMA_EEI_EEI14_SHIFT (14U) +#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) +#define DMA_EEI_EEI15_MASK (0x8000U) +#define DMA_EEI_EEI15_SHIFT (15U) +#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) + +/*! @name CEEI - Clear Enable Error Interrupt Register */ +#define DMA_CEEI_CEEI_MASK (0xFU) +#define DMA_CEEI_CEEI_SHIFT (0U) +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) +#define DMA_CEEI_CAEE_MASK (0x40U) +#define DMA_CEEI_CAEE_SHIFT (6U) +#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) +#define DMA_CEEI_NOP_MASK (0x80U) +#define DMA_CEEI_NOP_SHIFT (7U) +#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) + +/*! @name SEEI - Set Enable Error Interrupt Register */ +#define DMA_SEEI_SEEI_MASK (0xFU) +#define DMA_SEEI_SEEI_SHIFT (0U) +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) +#define DMA_SEEI_SAEE_MASK (0x40U) +#define DMA_SEEI_SAEE_SHIFT (6U) +#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) +#define DMA_SEEI_NOP_MASK (0x80U) +#define DMA_SEEI_NOP_SHIFT (7U) +#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) + +/*! @name CERQ - Clear Enable Request Register */ +#define DMA_CERQ_CERQ_MASK (0xFU) +#define DMA_CERQ_CERQ_SHIFT (0U) +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) +#define DMA_CERQ_CAER_MASK (0x40U) +#define DMA_CERQ_CAER_SHIFT (6U) +#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) +#define DMA_CERQ_NOP_MASK (0x80U) +#define DMA_CERQ_NOP_SHIFT (7U) +#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) + +/*! @name SERQ - Set Enable Request Register */ +#define DMA_SERQ_SERQ_MASK (0xFU) +#define DMA_SERQ_SERQ_SHIFT (0U) +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) +#define DMA_SERQ_SAER_MASK (0x40U) +#define DMA_SERQ_SAER_SHIFT (6U) +#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) +#define DMA_SERQ_NOP_MASK (0x80U) +#define DMA_SERQ_NOP_SHIFT (7U) +#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) + +/*! @name CDNE - Clear DONE Status Bit Register */ +#define DMA_CDNE_CDNE_MASK (0xFU) +#define DMA_CDNE_CDNE_SHIFT (0U) +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) +#define DMA_CDNE_CADN_MASK (0x40U) +#define DMA_CDNE_CADN_SHIFT (6U) +#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) +#define DMA_CDNE_NOP_MASK (0x80U) +#define DMA_CDNE_NOP_SHIFT (7U) +#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) + +/*! @name SSRT - Set START Bit Register */ +#define DMA_SSRT_SSRT_MASK (0xFU) +#define DMA_SSRT_SSRT_SHIFT (0U) +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) +#define DMA_SSRT_SAST_MASK (0x40U) +#define DMA_SSRT_SAST_SHIFT (6U) +#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) +#define DMA_SSRT_NOP_MASK (0x80U) +#define DMA_SSRT_NOP_SHIFT (7U) +#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) + +/*! @name CERR - Clear Error Register */ +#define DMA_CERR_CERR_MASK (0xFU) +#define DMA_CERR_CERR_SHIFT (0U) +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) +#define DMA_CERR_CAEI_MASK (0x40U) +#define DMA_CERR_CAEI_SHIFT (6U) +#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) +#define DMA_CERR_NOP_MASK (0x80U) +#define DMA_CERR_NOP_SHIFT (7U) +#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) + +/*! @name CINT - Clear Interrupt Request Register */ +#define DMA_CINT_CINT_MASK (0xFU) +#define DMA_CINT_CINT_SHIFT (0U) +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) +#define DMA_CINT_CAIR_MASK (0x40U) +#define DMA_CINT_CAIR_SHIFT (6U) +#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) +#define DMA_CINT_NOP_MASK (0x80U) +#define DMA_CINT_NOP_SHIFT (7U) +#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) + +/*! @name INT - Interrupt Request Register */ +#define DMA_INT_INT0_MASK (0x1U) +#define DMA_INT_INT0_SHIFT (0U) +#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) +#define DMA_INT_INT1_MASK (0x2U) +#define DMA_INT_INT1_SHIFT (1U) +#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) +#define DMA_INT_INT2_MASK (0x4U) +#define DMA_INT_INT2_SHIFT (2U) +#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) +#define DMA_INT_INT3_MASK (0x8U) +#define DMA_INT_INT3_SHIFT (3U) +#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) +#define DMA_INT_INT4_MASK (0x10U) +#define DMA_INT_INT4_SHIFT (4U) +#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) +#define DMA_INT_INT5_MASK (0x20U) +#define DMA_INT_INT5_SHIFT (5U) +#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) +#define DMA_INT_INT6_MASK (0x40U) +#define DMA_INT_INT6_SHIFT (6U) +#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) +#define DMA_INT_INT7_MASK (0x80U) +#define DMA_INT_INT7_SHIFT (7U) +#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) +#define DMA_INT_INT8_MASK (0x100U) +#define DMA_INT_INT8_SHIFT (8U) +#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) +#define DMA_INT_INT9_MASK (0x200U) +#define DMA_INT_INT9_SHIFT (9U) +#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) +#define DMA_INT_INT10_MASK (0x400U) +#define DMA_INT_INT10_SHIFT (10U) +#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) +#define DMA_INT_INT11_MASK (0x800U) +#define DMA_INT_INT11_SHIFT (11U) +#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) +#define DMA_INT_INT12_MASK (0x1000U) +#define DMA_INT_INT12_SHIFT (12U) +#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) +#define DMA_INT_INT13_MASK (0x2000U) +#define DMA_INT_INT13_SHIFT (13U) +#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) +#define DMA_INT_INT14_MASK (0x4000U) +#define DMA_INT_INT14_SHIFT (14U) +#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) +#define DMA_INT_INT15_MASK (0x8000U) +#define DMA_INT_INT15_SHIFT (15U) +#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) + +/*! @name ERR - Error Register */ +#define DMA_ERR_ERR0_MASK (0x1U) +#define DMA_ERR_ERR0_SHIFT (0U) +#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) +#define DMA_ERR_ERR1_MASK (0x2U) +#define DMA_ERR_ERR1_SHIFT (1U) +#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) +#define DMA_ERR_ERR2_MASK (0x4U) +#define DMA_ERR_ERR2_SHIFT (2U) +#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) +#define DMA_ERR_ERR3_MASK (0x8U) +#define DMA_ERR_ERR3_SHIFT (3U) +#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) +#define DMA_ERR_ERR4_MASK (0x10U) +#define DMA_ERR_ERR4_SHIFT (4U) +#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) +#define DMA_ERR_ERR5_MASK (0x20U) +#define DMA_ERR_ERR5_SHIFT (5U) +#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) +#define DMA_ERR_ERR6_MASK (0x40U) +#define DMA_ERR_ERR6_SHIFT (6U) +#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) +#define DMA_ERR_ERR7_MASK (0x80U) +#define DMA_ERR_ERR7_SHIFT (7U) +#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) +#define DMA_ERR_ERR8_MASK (0x100U) +#define DMA_ERR_ERR8_SHIFT (8U) +#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) +#define DMA_ERR_ERR9_MASK (0x200U) +#define DMA_ERR_ERR9_SHIFT (9U) +#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) +#define DMA_ERR_ERR10_MASK (0x400U) +#define DMA_ERR_ERR10_SHIFT (10U) +#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) +#define DMA_ERR_ERR11_MASK (0x800U) +#define DMA_ERR_ERR11_SHIFT (11U) +#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) +#define DMA_ERR_ERR12_MASK (0x1000U) +#define DMA_ERR_ERR12_SHIFT (12U) +#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) +#define DMA_ERR_ERR13_MASK (0x2000U) +#define DMA_ERR_ERR13_SHIFT (13U) +#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) +#define DMA_ERR_ERR14_MASK (0x4000U) +#define DMA_ERR_ERR14_SHIFT (14U) +#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) +#define DMA_ERR_ERR15_MASK (0x8000U) +#define DMA_ERR_ERR15_SHIFT (15U) +#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) + +/*! @name HRS - Hardware Request Status Register */ +#define DMA_HRS_HRS0_MASK (0x1U) +#define DMA_HRS_HRS0_SHIFT (0U) +#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) +#define DMA_HRS_HRS1_MASK (0x2U) +#define DMA_HRS_HRS1_SHIFT (1U) +#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) +#define DMA_HRS_HRS2_MASK (0x4U) +#define DMA_HRS_HRS2_SHIFT (2U) +#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) +#define DMA_HRS_HRS3_MASK (0x8U) +#define DMA_HRS_HRS3_SHIFT (3U) +#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) +#define DMA_HRS_HRS4_MASK (0x10U) +#define DMA_HRS_HRS4_SHIFT (4U) +#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) +#define DMA_HRS_HRS5_MASK (0x20U) +#define DMA_HRS_HRS5_SHIFT (5U) +#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) +#define DMA_HRS_HRS6_MASK (0x40U) +#define DMA_HRS_HRS6_SHIFT (6U) +#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) +#define DMA_HRS_HRS7_MASK (0x80U) +#define DMA_HRS_HRS7_SHIFT (7U) +#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) +#define DMA_HRS_HRS8_MASK (0x100U) +#define DMA_HRS_HRS8_SHIFT (8U) +#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) +#define DMA_HRS_HRS9_MASK (0x200U) +#define DMA_HRS_HRS9_SHIFT (9U) +#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) +#define DMA_HRS_HRS10_MASK (0x400U) +#define DMA_HRS_HRS10_SHIFT (10U) +#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) +#define DMA_HRS_HRS11_MASK (0x800U) +#define DMA_HRS_HRS11_SHIFT (11U) +#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) +#define DMA_HRS_HRS12_MASK (0x1000U) +#define DMA_HRS_HRS12_SHIFT (12U) +#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) +#define DMA_HRS_HRS13_MASK (0x2000U) +#define DMA_HRS_HRS13_SHIFT (13U) +#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) +#define DMA_HRS_HRS14_MASK (0x4000U) +#define DMA_HRS_HRS14_SHIFT (14U) +#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) +#define DMA_HRS_HRS15_MASK (0x8000U) +#define DMA_HRS_HRS15_SHIFT (15U) +#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) + +/*! @name DCHPRI3 - Channel n Priority Register */ +#define DMA_DCHPRI3_CHPRI_MASK (0xFU) +#define DMA_DCHPRI3_CHPRI_SHIFT (0U) +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) +#define DMA_DCHPRI3_DPA_MASK (0x40U) +#define DMA_DCHPRI3_DPA_SHIFT (6U) +#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) +#define DMA_DCHPRI3_ECP_MASK (0x80U) +#define DMA_DCHPRI3_ECP_SHIFT (7U) +#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) + +/*! @name DCHPRI2 - Channel n Priority Register */ +#define DMA_DCHPRI2_CHPRI_MASK (0xFU) +#define DMA_DCHPRI2_CHPRI_SHIFT (0U) +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) +#define DMA_DCHPRI2_DPA_MASK (0x40U) +#define DMA_DCHPRI2_DPA_SHIFT (6U) +#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) +#define DMA_DCHPRI2_ECP_MASK (0x80U) +#define DMA_DCHPRI2_ECP_SHIFT (7U) +#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) + +/*! @name DCHPRI1 - Channel n Priority Register */ +#define DMA_DCHPRI1_CHPRI_MASK (0xFU) +#define DMA_DCHPRI1_CHPRI_SHIFT (0U) +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) +#define DMA_DCHPRI1_DPA_MASK (0x40U) +#define DMA_DCHPRI1_DPA_SHIFT (6U) +#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) +#define DMA_DCHPRI1_ECP_MASK (0x80U) +#define DMA_DCHPRI1_ECP_SHIFT (7U) +#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) + +/*! @name DCHPRI0 - Channel n Priority Register */ +#define DMA_DCHPRI0_CHPRI_MASK (0xFU) +#define DMA_DCHPRI0_CHPRI_SHIFT (0U) +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) +#define DMA_DCHPRI0_DPA_MASK (0x40U) +#define DMA_DCHPRI0_DPA_SHIFT (6U) +#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) +#define DMA_DCHPRI0_ECP_MASK (0x80U) +#define DMA_DCHPRI0_ECP_SHIFT (7U) +#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) + +/*! @name DCHPRI7 - Channel n Priority Register */ +#define DMA_DCHPRI7_CHPRI_MASK (0xFU) +#define DMA_DCHPRI7_CHPRI_SHIFT (0U) +#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) +#define DMA_DCHPRI7_DPA_MASK (0x40U) +#define DMA_DCHPRI7_DPA_SHIFT (6U) +#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) +#define DMA_DCHPRI7_ECP_MASK (0x80U) +#define DMA_DCHPRI7_ECP_SHIFT (7U) +#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) + +/*! @name DCHPRI6 - Channel n Priority Register */ +#define DMA_DCHPRI6_CHPRI_MASK (0xFU) +#define DMA_DCHPRI6_CHPRI_SHIFT (0U) +#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) +#define DMA_DCHPRI6_DPA_MASK (0x40U) +#define DMA_DCHPRI6_DPA_SHIFT (6U) +#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) +#define DMA_DCHPRI6_ECP_MASK (0x80U) +#define DMA_DCHPRI6_ECP_SHIFT (7U) +#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) + +/*! @name DCHPRI5 - Channel n Priority Register */ +#define DMA_DCHPRI5_CHPRI_MASK (0xFU) +#define DMA_DCHPRI5_CHPRI_SHIFT (0U) +#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) +#define DMA_DCHPRI5_DPA_MASK (0x40U) +#define DMA_DCHPRI5_DPA_SHIFT (6U) +#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) +#define DMA_DCHPRI5_ECP_MASK (0x80U) +#define DMA_DCHPRI5_ECP_SHIFT (7U) +#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) + +/*! @name DCHPRI4 - Channel n Priority Register */ +#define DMA_DCHPRI4_CHPRI_MASK (0xFU) +#define DMA_DCHPRI4_CHPRI_SHIFT (0U) +#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) +#define DMA_DCHPRI4_DPA_MASK (0x40U) +#define DMA_DCHPRI4_DPA_SHIFT (6U) +#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) +#define DMA_DCHPRI4_ECP_MASK (0x80U) +#define DMA_DCHPRI4_ECP_SHIFT (7U) +#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) + +/*! @name DCHPRI11 - Channel n Priority Register */ +#define DMA_DCHPRI11_CHPRI_MASK (0xFU) +#define DMA_DCHPRI11_CHPRI_SHIFT (0U) +#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) +#define DMA_DCHPRI11_DPA_MASK (0x40U) +#define DMA_DCHPRI11_DPA_SHIFT (6U) +#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) +#define DMA_DCHPRI11_ECP_MASK (0x80U) +#define DMA_DCHPRI11_ECP_SHIFT (7U) +#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) + +/*! @name DCHPRI10 - Channel n Priority Register */ +#define DMA_DCHPRI10_CHPRI_MASK (0xFU) +#define DMA_DCHPRI10_CHPRI_SHIFT (0U) +#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) +#define DMA_DCHPRI10_DPA_MASK (0x40U) +#define DMA_DCHPRI10_DPA_SHIFT (6U) +#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) +#define DMA_DCHPRI10_ECP_MASK (0x80U) +#define DMA_DCHPRI10_ECP_SHIFT (7U) +#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) + +/*! @name DCHPRI9 - Channel n Priority Register */ +#define DMA_DCHPRI9_CHPRI_MASK (0xFU) +#define DMA_DCHPRI9_CHPRI_SHIFT (0U) +#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) +#define DMA_DCHPRI9_DPA_MASK (0x40U) +#define DMA_DCHPRI9_DPA_SHIFT (6U) +#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) +#define DMA_DCHPRI9_ECP_MASK (0x80U) +#define DMA_DCHPRI9_ECP_SHIFT (7U) +#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) + +/*! @name DCHPRI8 - Channel n Priority Register */ +#define DMA_DCHPRI8_CHPRI_MASK (0xFU) +#define DMA_DCHPRI8_CHPRI_SHIFT (0U) +#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) +#define DMA_DCHPRI8_DPA_MASK (0x40U) +#define DMA_DCHPRI8_DPA_SHIFT (6U) +#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) +#define DMA_DCHPRI8_ECP_MASK (0x80U) +#define DMA_DCHPRI8_ECP_SHIFT (7U) +#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) + +/*! @name DCHPRI15 - Channel n Priority Register */ +#define DMA_DCHPRI15_CHPRI_MASK (0xFU) +#define DMA_DCHPRI15_CHPRI_SHIFT (0U) +#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) +#define DMA_DCHPRI15_DPA_MASK (0x40U) +#define DMA_DCHPRI15_DPA_SHIFT (6U) +#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) +#define DMA_DCHPRI15_ECP_MASK (0x80U) +#define DMA_DCHPRI15_ECP_SHIFT (7U) +#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) + +/*! @name DCHPRI14 - Channel n Priority Register */ +#define DMA_DCHPRI14_CHPRI_MASK (0xFU) +#define DMA_DCHPRI14_CHPRI_SHIFT (0U) +#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) +#define DMA_DCHPRI14_DPA_MASK (0x40U) +#define DMA_DCHPRI14_DPA_SHIFT (6U) +#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) +#define DMA_DCHPRI14_ECP_MASK (0x80U) +#define DMA_DCHPRI14_ECP_SHIFT (7U) +#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) + +/*! @name DCHPRI13 - Channel n Priority Register */ +#define DMA_DCHPRI13_CHPRI_MASK (0xFU) +#define DMA_DCHPRI13_CHPRI_SHIFT (0U) +#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) +#define DMA_DCHPRI13_DPA_MASK (0x40U) +#define DMA_DCHPRI13_DPA_SHIFT (6U) +#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) +#define DMA_DCHPRI13_ECP_MASK (0x80U) +#define DMA_DCHPRI13_ECP_SHIFT (7U) +#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) + +/*! @name DCHPRI12 - Channel n Priority Register */ +#define DMA_DCHPRI12_CHPRI_MASK (0xFU) +#define DMA_DCHPRI12_CHPRI_SHIFT (0U) +#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) +#define DMA_DCHPRI12_DPA_MASK (0x40U) +#define DMA_DCHPRI12_DPA_SHIFT (6U) +#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) +#define DMA_DCHPRI12_ECP_MASK (0x80U) +#define DMA_DCHPRI12_ECP_SHIFT (7U) +#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) + +/*! @name SADDR - TCD Source Address */ +#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_SADDR_SADDR_SHIFT (0U) +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) + +/* The count of DMA_SADDR */ +#define DMA_SADDR_COUNT (16U) + +/*! @name SOFF - TCD Signed Source Address Offset */ +#define DMA_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_SOFF_SOFF_SHIFT (0U) +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) + +/* The count of DMA_SOFF */ +#define DMA_SOFF_COUNT (16U) + +/*! @name ATTR - TCD Transfer Attributes */ +#define DMA_ATTR_DSIZE_MASK (0x7U) +#define DMA_ATTR_DSIZE_SHIFT (0U) +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) +#define DMA_ATTR_DMOD_MASK (0xF8U) +#define DMA_ATTR_DMOD_SHIFT (3U) +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) +#define DMA_ATTR_SSIZE_MASK (0x700U) +#define DMA_ATTR_SSIZE_SHIFT (8U) +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) +#define DMA_ATTR_SMOD_MASK (0xF800U) +#define DMA_ATTR_SMOD_SHIFT (11U) +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) + +/* The count of DMA_ATTR */ +#define DMA_ATTR_COUNT (16U) + +/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */ +#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) +#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) + +/* The count of DMA_NBYTES_MLNO */ +#define DMA_NBYTES_MLNO_COUNT (16U) + +/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) + +/* The count of DMA_NBYTES_MLOFFNO */ +#define DMA_NBYTES_MLOFFNO_COUNT (16U) + +/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) + +/* The count of DMA_NBYTES_MLOFFYES */ +#define DMA_NBYTES_MLOFFYES_COUNT (16U) + +/*! @name SLAST - TCD Last Source Address Adjustment */ +#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) +#define DMA_SLAST_SLAST_SHIFT (0U) +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) + +/* The count of DMA_SLAST */ +#define DMA_SLAST_COUNT (16U) + +/*! @name DADDR - TCD Destination Address */ +#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_DADDR_DADDR_SHIFT (0U) +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) + +/* The count of DMA_DADDR */ +#define DMA_DADDR_COUNT (16U) + +/*! @name DOFF - TCD Signed Destination Address Offset */ +#define DMA_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_DOFF_DOFF_SHIFT (0U) +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) + +/* The count of DMA_DOFF */ +#define DMA_DOFF_COUNT (16U) + +/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) +#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) +#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) + +/* The count of DMA_CITER_ELINKNO */ +#define DMA_CITER_ELINKNO_COUNT (16U) + +/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) +#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U) +#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) +#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) +#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) + +/* The count of DMA_CITER_ELINKYES */ +#define DMA_CITER_ELINKYES_COUNT (16U) + +/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) +#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) + +/* The count of DMA_DLAST_SGA */ +#define DMA_DLAST_SGA_COUNT (16U) + +/*! @name CSR - TCD Control and Status */ +#define DMA_CSR_START_MASK (0x1U) +#define DMA_CSR_START_SHIFT (0U) +#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) +#define DMA_CSR_INTMAJOR_MASK (0x2U) +#define DMA_CSR_INTMAJOR_SHIFT (1U) +#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) +#define DMA_CSR_INTHALF_MASK (0x4U) +#define DMA_CSR_INTHALF_SHIFT (2U) +#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) +#define DMA_CSR_DREQ_MASK (0x8U) +#define DMA_CSR_DREQ_SHIFT (3U) +#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) +#define DMA_CSR_ESG_MASK (0x10U) +#define DMA_CSR_ESG_SHIFT (4U) +#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) +#define DMA_CSR_MAJORELINK_MASK (0x20U) +#define DMA_CSR_MAJORELINK_SHIFT (5U) +#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) +#define DMA_CSR_ACTIVE_MASK (0x40U) +#define DMA_CSR_ACTIVE_SHIFT (6U) +#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) +#define DMA_CSR_DONE_MASK (0x80U) +#define DMA_CSR_DONE_SHIFT (7U) +#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) +#define DMA_CSR_MAJORLINKCH_MASK (0xF00U) +#define DMA_CSR_MAJORLINKCH_SHIFT (8U) +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) +#define DMA_CSR_BWC_MASK (0xC000U) +#define DMA_CSR_BWC_SHIFT (14U) +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) + +/* The count of DMA_CSR */ +#define DMA_CSR_COUNT (16U) + +/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) +#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) +#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) + +/* The count of DMA_BITER_ELINKNO */ +#define DMA_BITER_ELINKNO_COUNT (16U) + +/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) +#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U) +#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) +#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) +#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) + +/* The count of DMA_BITER_ELINKYES */ +#define DMA_BITER_ELINKYES_COUNT (16U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA base address */ +#define DMA_BASE (0x40008000u) +/** Peripheral DMA base pointer */ +#define DMA0 ((DMA_Type *)DMA_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } } +#define DMA_ERROR_IRQS { DMA_Error_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @{ + */ + +/** DMAMUX - Register Layout Typedef */ +typedef struct { + __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ +} DMAMUX_Type; + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/*! @name CHCFG - Channel Configuration register */ +#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) +#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) +#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) +#define DMAMUX_CHCFG_TRIG_MASK (0x40U) +#define DMAMUX_CHCFG_TRIG_SHIFT (6U) +#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) +#define DMAMUX_CHCFG_ENBL_MASK (0x80U) +#define DMAMUX_CHCFG_ENBL_SHIFT (7U) +#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) + +/* The count of DMAMUX_CHCFG */ +#define DMAMUX_CHCFG_COUNT (16U) + + +/*! + * @} + */ /* end of group DMAMUX_Register_Masks */ + + +/* DMAMUX - Peripheral instance base addresses */ +/** Peripheral DMAMUX base address */ +#define DMAMUX_BASE (0x40021000u) +/** Peripheral DMAMUX base pointer */ +#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) +/** Array initializer of DMAMUX peripheral base addresses */ +#define DMAMUX_BASE_ADDRS { DMAMUX_BASE } +/** Array initializer of DMAMUX peripheral base pointers */ +#define DMAMUX_BASE_PTRS { DMAMUX } + +/*! + * @} + */ /* end of group DMAMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ + __O uint8_t SERV; /**< Service Register, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +#define EWM_CTRL_EWMEN_MASK (0x1U) +#define EWM_CTRL_EWMEN_SHIFT (0U) +#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) +#define EWM_CTRL_ASSIN_MASK (0x2U) +#define EWM_CTRL_ASSIN_SHIFT (1U) +#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) +#define EWM_CTRL_INEN_MASK (0x4U) +#define EWM_CTRL_INEN_SHIFT (2U) +#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) +#define EWM_CTRL_INTEN_MASK (0x8U) +#define EWM_CTRL_INTEN_SHIFT (3U) +#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) + +/*! @name SERV - Service Register */ +#define EWM_SERV_SERVICE_MASK (0xFFU) +#define EWM_SERV_SERVICE_SHIFT (0U) +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) + +/*! @name CMPL - Compare Low Register */ +#define EWM_CMPL_COMPAREL_MASK (0xFFU) +#define EWM_CMPL_COMPAREL_SHIFT (0U) +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) + +/*! @name CMPH - Compare High Register */ +#define EWM_CMPH_COMPAREH_MASK (0xFFU) +#define EWM_CMPH_COMPAREH_SHIFT (0U) +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) + + +/*! + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +/** Peripheral EWM base address */ +#define EWM_BASE (0x40061000u) +/** Peripheral EWM base pointer */ +#define EWM ((EWM_Type *)EWM_BASE) +/** Array initializer of EWM peripheral base addresses */ +#define EWM_BASE_ADDRS { EWM_BASE } +/** Array initializer of EWM peripheral base pointers */ +#define EWM_BASE_PTRS { EWM } +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { WDOG_EWM_IRQn } + +/*! + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer + * @{ + */ + +/** FB - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0xC */ + __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */ + __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */ + __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */ + } CS[6]; + uint8_t RESERVED_0[24]; + __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */ +} FB_Type; + +/* ---------------------------------------------------------------------------- + -- FB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FB_Register_Masks FB Register Masks + * @{ + */ + +/*! @name CSAR - Chip Select Address Register */ +#define FB_CSAR_BA_MASK (0xFFFF0000U) +#define FB_CSAR_BA_SHIFT (16U) +#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK) + +/* The count of FB_CSAR */ +#define FB_CSAR_COUNT (6U) + +/*! @name CSMR - Chip Select Mask Register */ +#define FB_CSMR_V_MASK (0x1U) +#define FB_CSMR_V_SHIFT (0U) +#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK) +#define FB_CSMR_WP_MASK (0x100U) +#define FB_CSMR_WP_SHIFT (8U) +#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK) +#define FB_CSMR_BAM_MASK (0xFFFF0000U) +#define FB_CSMR_BAM_SHIFT (16U) +#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK) + +/* The count of FB_CSMR */ +#define FB_CSMR_COUNT (6U) + +/*! @name CSCR - Chip Select Control Register */ +#define FB_CSCR_BSTW_MASK (0x8U) +#define FB_CSCR_BSTW_SHIFT (3U) +#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK) +#define FB_CSCR_BSTR_MASK (0x10U) +#define FB_CSCR_BSTR_SHIFT (4U) +#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK) +#define FB_CSCR_BEM_MASK (0x20U) +#define FB_CSCR_BEM_SHIFT (5U) +#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK) +#define FB_CSCR_PS_MASK (0xC0U) +#define FB_CSCR_PS_SHIFT (6U) +#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK) +#define FB_CSCR_AA_MASK (0x100U) +#define FB_CSCR_AA_SHIFT (8U) +#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK) +#define FB_CSCR_BLS_MASK (0x200U) +#define FB_CSCR_BLS_SHIFT (9U) +#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK) +#define FB_CSCR_WS_MASK (0xFC00U) +#define FB_CSCR_WS_SHIFT (10U) +#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK) +#define FB_CSCR_WRAH_MASK (0x30000U) +#define FB_CSCR_WRAH_SHIFT (16U) +#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK) +#define FB_CSCR_RDAH_MASK (0xC0000U) +#define FB_CSCR_RDAH_SHIFT (18U) +#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK) +#define FB_CSCR_ASET_MASK (0x300000U) +#define FB_CSCR_ASET_SHIFT (20U) +#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK) +#define FB_CSCR_EXTS_MASK (0x400000U) +#define FB_CSCR_EXTS_SHIFT (22U) +#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK) +#define FB_CSCR_SWSEN_MASK (0x800000U) +#define FB_CSCR_SWSEN_SHIFT (23U) +#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK) +#define FB_CSCR_SWS_MASK (0xFC000000U) +#define FB_CSCR_SWS_SHIFT (26U) +#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK) + +/* The count of FB_CSCR */ +#define FB_CSCR_COUNT (6U) + +/*! @name CSPMCR - Chip Select port Multiplexing Control Register */ +#define FB_CSPMCR_GROUP5_MASK (0xF000U) +#define FB_CSPMCR_GROUP5_SHIFT (12U) +#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK) +#define FB_CSPMCR_GROUP4_MASK (0xF0000U) +#define FB_CSPMCR_GROUP4_SHIFT (16U) +#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK) +#define FB_CSPMCR_GROUP3_MASK (0xF00000U) +#define FB_CSPMCR_GROUP3_SHIFT (20U) +#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK) +#define FB_CSPMCR_GROUP2_MASK (0xF000000U) +#define FB_CSPMCR_GROUP2_SHIFT (24U) +#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK) +#define FB_CSPMCR_GROUP1_MASK (0xF0000000U) +#define FB_CSPMCR_GROUP1_SHIFT (28U) +#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK) + + +/*! + * @} + */ /* end of group FB_Register_Masks */ + + +/* FB - Peripheral instance base addresses */ +/** Peripheral FB base address */ +#define FB_BASE (0x4000C000u) +/** Peripheral FB base pointer */ +#define FB ((FB_Type *)FB_BASE) +/** Array initializer of FB peripheral base addresses */ +#define FB_BASE_ADDRS { FB_BASE } +/** Array initializer of FB peripheral base pointers */ +#define FB_BASE_PTRS { FB } + +/*! + * @} + */ /* end of group FB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer + * @{ + */ + +/** FMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */ + __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */ + __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */ + uint8_t RESERVED_0[244]; + __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */ + __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */ + __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */ + __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */ + uint8_t RESERVED_1[192]; + struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */ + __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */ + __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */ + } SET[4][4]; +} FMC_Type; + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/*! @name PFAPR - Flash Access Protection Register */ +#define FMC_PFAPR_M0AP_MASK (0x3U) +#define FMC_PFAPR_M0AP_SHIFT (0U) +#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK) +#define FMC_PFAPR_M1AP_MASK (0xCU) +#define FMC_PFAPR_M1AP_SHIFT (2U) +#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK) +#define FMC_PFAPR_M2AP_MASK (0x30U) +#define FMC_PFAPR_M2AP_SHIFT (4U) +#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK) +#define FMC_PFAPR_M3AP_MASK (0xC0U) +#define FMC_PFAPR_M3AP_SHIFT (6U) +#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK) +#define FMC_PFAPR_M4AP_MASK (0x300U) +#define FMC_PFAPR_M4AP_SHIFT (8U) +#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK) +#define FMC_PFAPR_M5AP_MASK (0xC00U) +#define FMC_PFAPR_M5AP_SHIFT (10U) +#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK) +#define FMC_PFAPR_M6AP_MASK (0x3000U) +#define FMC_PFAPR_M6AP_SHIFT (12U) +#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK) +#define FMC_PFAPR_M7AP_MASK (0xC000U) +#define FMC_PFAPR_M7AP_SHIFT (14U) +#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK) +#define FMC_PFAPR_M0PFD_MASK (0x10000U) +#define FMC_PFAPR_M0PFD_SHIFT (16U) +#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK) +#define FMC_PFAPR_M1PFD_MASK (0x20000U) +#define FMC_PFAPR_M1PFD_SHIFT (17U) +#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK) +#define FMC_PFAPR_M2PFD_MASK (0x40000U) +#define FMC_PFAPR_M2PFD_SHIFT (18U) +#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK) +#define FMC_PFAPR_M3PFD_MASK (0x80000U) +#define FMC_PFAPR_M3PFD_SHIFT (19U) +#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK) +#define FMC_PFAPR_M4PFD_MASK (0x100000U) +#define FMC_PFAPR_M4PFD_SHIFT (20U) +#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK) +#define FMC_PFAPR_M5PFD_MASK (0x200000U) +#define FMC_PFAPR_M5PFD_SHIFT (21U) +#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK) +#define FMC_PFAPR_M6PFD_MASK (0x400000U) +#define FMC_PFAPR_M6PFD_SHIFT (22U) +#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK) +#define FMC_PFAPR_M7PFD_MASK (0x800000U) +#define FMC_PFAPR_M7PFD_SHIFT (23U) +#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK) + +/*! @name PFB0CR - Flash Bank 0 Control Register */ +#define FMC_PFB0CR_B0SEBE_MASK (0x1U) +#define FMC_PFB0CR_B0SEBE_SHIFT (0U) +#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK) +#define FMC_PFB0CR_B0IPE_MASK (0x2U) +#define FMC_PFB0CR_B0IPE_SHIFT (1U) +#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK) +#define FMC_PFB0CR_B0DPE_MASK (0x4U) +#define FMC_PFB0CR_B0DPE_SHIFT (2U) +#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK) +#define FMC_PFB0CR_B0ICE_MASK (0x8U) +#define FMC_PFB0CR_B0ICE_SHIFT (3U) +#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK) +#define FMC_PFB0CR_B0DCE_MASK (0x10U) +#define FMC_PFB0CR_B0DCE_SHIFT (4U) +#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK) +#define FMC_PFB0CR_CRC_MASK (0xE0U) +#define FMC_PFB0CR_CRC_SHIFT (5U) +#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK) +#define FMC_PFB0CR_B0MW_MASK (0x60000U) +#define FMC_PFB0CR_B0MW_SHIFT (17U) +#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK) +#define FMC_PFB0CR_S_B_INV_MASK (0x80000U) +#define FMC_PFB0CR_S_B_INV_SHIFT (19U) +#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK) +#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U) +#define FMC_PFB0CR_CINV_WAY_SHIFT (20U) +#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK) +#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U) +#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U) +#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK) +#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U) +#define FMC_PFB0CR_B0RWSC_SHIFT (28U) +#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK) + +/*! @name PFB1CR - Flash Bank 1 Control Register */ +#define FMC_PFB1CR_B1SEBE_MASK (0x1U) +#define FMC_PFB1CR_B1SEBE_SHIFT (0U) +#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK) +#define FMC_PFB1CR_B1IPE_MASK (0x2U) +#define FMC_PFB1CR_B1IPE_SHIFT (1U) +#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK) +#define FMC_PFB1CR_B1DPE_MASK (0x4U) +#define FMC_PFB1CR_B1DPE_SHIFT (2U) +#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK) +#define FMC_PFB1CR_B1ICE_MASK (0x8U) +#define FMC_PFB1CR_B1ICE_SHIFT (3U) +#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK) +#define FMC_PFB1CR_B1DCE_MASK (0x10U) +#define FMC_PFB1CR_B1DCE_SHIFT (4U) +#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK) +#define FMC_PFB1CR_B1MW_MASK (0x60000U) +#define FMC_PFB1CR_B1MW_SHIFT (17U) +#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK) +#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U) +#define FMC_PFB1CR_B1RWSC_SHIFT (28U) +#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK) + +/*! @name TAGVDW0S - Cache Tag Storage */ +#define FMC_TAGVDW0S_valid_MASK (0x1U) +#define FMC_TAGVDW0S_valid_SHIFT (0U) +#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK) +#define FMC_TAGVDW0S_tag_MASK (0x7FFE0U) +#define FMC_TAGVDW0S_tag_SHIFT (5U) +#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK) + +/* The count of FMC_TAGVDW0S */ +#define FMC_TAGVDW0S_COUNT (4U) + +/*! @name TAGVDW1S - Cache Tag Storage */ +#define FMC_TAGVDW1S_valid_MASK (0x1U) +#define FMC_TAGVDW1S_valid_SHIFT (0U) +#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK) +#define FMC_TAGVDW1S_tag_MASK (0x7FFE0U) +#define FMC_TAGVDW1S_tag_SHIFT (5U) +#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK) + +/* The count of FMC_TAGVDW1S */ +#define FMC_TAGVDW1S_COUNT (4U) + +/*! @name TAGVDW2S - Cache Tag Storage */ +#define FMC_TAGVDW2S_valid_MASK (0x1U) +#define FMC_TAGVDW2S_valid_SHIFT (0U) +#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK) +#define FMC_TAGVDW2S_tag_MASK (0x7FFE0U) +#define FMC_TAGVDW2S_tag_SHIFT (5U) +#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK) + +/* The count of FMC_TAGVDW2S */ +#define FMC_TAGVDW2S_COUNT (4U) + +/*! @name TAGVDW3S - Cache Tag Storage */ +#define FMC_TAGVDW3S_valid_MASK (0x1U) +#define FMC_TAGVDW3S_valid_SHIFT (0U) +#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK) +#define FMC_TAGVDW3S_tag_MASK (0x7FFE0U) +#define FMC_TAGVDW3S_tag_SHIFT (5U) +#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK) + +/* The count of FMC_TAGVDW3S */ +#define FMC_TAGVDW3S_COUNT (4U) + +/*! @name DATA_U - Cache Data Storage (upper word) */ +#define FMC_DATA_U_data_MASK (0xFFFFFFFFU) +#define FMC_DATA_U_data_SHIFT (0U) +#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK) + +/* The count of FMC_DATA_U */ +#define FMC_DATA_U_COUNT (4U) + +/* The count of FMC_DATA_U */ +#define FMC_DATA_U_COUNT2 (4U) + +/*! @name DATA_L - Cache Data Storage (lower word) */ +#define FMC_DATA_L_data_MASK (0xFFFFFFFFU) +#define FMC_DATA_L_data_SHIFT (0U) +#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK) + +/* The count of FMC_DATA_L */ +#define FMC_DATA_L_COUNT (4U) + +/* The count of FMC_DATA_L */ +#define FMC_DATA_L_COUNT2 (4U) + + +/*! + * @} + */ /* end of group FMC_Register_Masks */ + + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC base address */ +#define FMC_BASE (0x4001F000u) +/** Peripheral FMC base pointer */ +#define FMC ((FMC_Type *)FMC_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC } + +/*! + * @} + */ /* end of group FMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FTFE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer + * @{ + */ + +/** FTFE - Register Layout Typedef */ +typedef struct { + __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ + __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ + __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ + __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ + __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ + __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ + __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ + __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ + __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ + __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ + __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ + __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ + __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ + __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ + __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ + __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ + __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ + __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ + __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ +} FTFE_Type; + +/* ---------------------------------------------------------------------------- + -- FTFE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTFE_Register_Masks FTFE Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +#define FTFE_FSTAT_MGSTAT0_MASK (0x1U) +#define FTFE_FSTAT_MGSTAT0_SHIFT (0U) +#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK) +#define FTFE_FSTAT_FPVIOL_MASK (0x10U) +#define FTFE_FSTAT_FPVIOL_SHIFT (4U) +#define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK) +#define FTFE_FSTAT_ACCERR_MASK (0x20U) +#define FTFE_FSTAT_ACCERR_SHIFT (5U) +#define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK) +#define FTFE_FSTAT_RDCOLERR_MASK (0x40U) +#define FTFE_FSTAT_RDCOLERR_SHIFT (6U) +#define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK) +#define FTFE_FSTAT_CCIF_MASK (0x80U) +#define FTFE_FSTAT_CCIF_SHIFT (7U) +#define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK) + +/*! @name FCNFG - Flash Configuration Register */ +#define FTFE_FCNFG_EEERDY_MASK (0x1U) +#define FTFE_FCNFG_EEERDY_SHIFT (0U) +#define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK) +#define FTFE_FCNFG_RAMRDY_MASK (0x2U) +#define FTFE_FCNFG_RAMRDY_SHIFT (1U) +#define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK) +#define FTFE_FCNFG_PFLSH_MASK (0x4U) +#define FTFE_FCNFG_PFLSH_SHIFT (2U) +#define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK) +#define FTFE_FCNFG_SWAP_MASK (0x8U) +#define FTFE_FCNFG_SWAP_SHIFT (3U) +#define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK) +#define FTFE_FCNFG_ERSSUSP_MASK (0x10U) +#define FTFE_FCNFG_ERSSUSP_SHIFT (4U) +#define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK) +#define FTFE_FCNFG_ERSAREQ_MASK (0x20U) +#define FTFE_FCNFG_ERSAREQ_SHIFT (5U) +#define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK) +#define FTFE_FCNFG_RDCOLLIE_MASK (0x40U) +#define FTFE_FCNFG_RDCOLLIE_SHIFT (6U) +#define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK) +#define FTFE_FCNFG_CCIE_MASK (0x80U) +#define FTFE_FCNFG_CCIE_SHIFT (7U) +#define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK) + +/*! @name FSEC - Flash Security Register */ +#define FTFE_FSEC_SEC_MASK (0x3U) +#define FTFE_FSEC_SEC_SHIFT (0U) +#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK) +#define FTFE_FSEC_FSLACC_MASK (0xCU) +#define FTFE_FSEC_FSLACC_SHIFT (2U) +#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK) +#define FTFE_FSEC_MEEN_MASK (0x30U) +#define FTFE_FSEC_MEEN_SHIFT (4U) +#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK) +#define FTFE_FSEC_KEYEN_MASK (0xC0U) +#define FTFE_FSEC_KEYEN_SHIFT (6U) +#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK) + +/*! @name FOPT - Flash Option Register */ +#define FTFE_FOPT_OPT_MASK (0xFFU) +#define FTFE_FOPT_OPT_SHIFT (0U) +#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK) + +/*! @name FCCOB3 - Flash Common Command Object Registers */ +#define FTFE_FCCOB3_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB3_CCOBn_SHIFT (0U) +#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK) + +/*! @name FCCOB2 - Flash Common Command Object Registers */ +#define FTFE_FCCOB2_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB2_CCOBn_SHIFT (0U) +#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK) + +/*! @name FCCOB1 - Flash Common Command Object Registers */ +#define FTFE_FCCOB1_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB1_CCOBn_SHIFT (0U) +#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK) + +/*! @name FCCOB0 - Flash Common Command Object Registers */ +#define FTFE_FCCOB0_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB0_CCOBn_SHIFT (0U) +#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK) + +/*! @name FCCOB7 - Flash Common Command Object Registers */ +#define FTFE_FCCOB7_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB7_CCOBn_SHIFT (0U) +#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK) + +/*! @name FCCOB6 - Flash Common Command Object Registers */ +#define FTFE_FCCOB6_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB6_CCOBn_SHIFT (0U) +#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK) + +/*! @name FCCOB5 - Flash Common Command Object Registers */ +#define FTFE_FCCOB5_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB5_CCOBn_SHIFT (0U) +#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK) + +/*! @name FCCOB4 - Flash Common Command Object Registers */ +#define FTFE_FCCOB4_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB4_CCOBn_SHIFT (0U) +#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK) + +/*! @name FCCOBB - Flash Common Command Object Registers */ +#define FTFE_FCCOBB_CCOBn_MASK (0xFFU) +#define FTFE_FCCOBB_CCOBn_SHIFT (0U) +#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK) + +/*! @name FCCOBA - Flash Common Command Object Registers */ +#define FTFE_FCCOBA_CCOBn_MASK (0xFFU) +#define FTFE_FCCOBA_CCOBn_SHIFT (0U) +#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK) + +/*! @name FCCOB9 - Flash Common Command Object Registers */ +#define FTFE_FCCOB9_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB9_CCOBn_SHIFT (0U) +#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK) + +/*! @name FCCOB8 - Flash Common Command Object Registers */ +#define FTFE_FCCOB8_CCOBn_MASK (0xFFU) +#define FTFE_FCCOB8_CCOBn_SHIFT (0U) +#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK) + +/*! @name FPROT3 - Program Flash Protection Registers */ +#define FTFE_FPROT3_PROT_MASK (0xFFU) +#define FTFE_FPROT3_PROT_SHIFT (0U) +#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK) + +/*! @name FPROT2 - Program Flash Protection Registers */ +#define FTFE_FPROT2_PROT_MASK (0xFFU) +#define FTFE_FPROT2_PROT_SHIFT (0U) +#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK) + +/*! @name FPROT1 - Program Flash Protection Registers */ +#define FTFE_FPROT1_PROT_MASK (0xFFU) +#define FTFE_FPROT1_PROT_SHIFT (0U) +#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK) + +/*! @name FPROT0 - Program Flash Protection Registers */ +#define FTFE_FPROT0_PROT_MASK (0xFFU) +#define FTFE_FPROT0_PROT_SHIFT (0U) +#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK) + + +/*! + * @} + */ /* end of group FTFE_Register_Masks */ + + +/* FTFE - Peripheral instance base addresses */ +/** Peripheral FTFE base address */ +#define FTFE_BASE (0x40020000u) +/** Peripheral FTFE base pointer */ +#define FTFE ((FTFE_Type *)FTFE_BASE) +/** Array initializer of FTFE peripheral base addresses */ +#define FTFE_BASE_ADDRS { FTFE_BASE } +/** Array initializer of FTFE peripheral base pointers */ +#define FTFE_BASE_PTRS { FTFE } +/** Interrupt vectors for the FTFE peripheral type */ +#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn } +#define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn } + +/*! + * @} + */ /* end of group FTFE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FTM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer + * @{ + */ + +/** FTM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ + __IO uint32_t CNT; /**< Counter, offset: 0x4 */ + __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ + struct { /* offset: 0xC, array step: 0x8 */ + __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ + __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ + } CONTROLS[8]; + __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ + __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ + __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ + __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ + __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ + __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ + __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ + __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ + __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ + __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ + __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ + __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ + __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ + __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */ + __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ + __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ + __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ + __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ + __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ + __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ +} FTM_Type; + +/* ---------------------------------------------------------------------------- + -- FTM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Register_Masks FTM Register Masks + * @{ + */ + +/*! @name SC - Status And Control */ +#define FTM_SC_PS_MASK (0x7U) +#define FTM_SC_PS_SHIFT (0U) +#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) +#define FTM_SC_CLKS_MASK (0x18U) +#define FTM_SC_CLKS_SHIFT (3U) +#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) +#define FTM_SC_CPWMS_MASK (0x20U) +#define FTM_SC_CPWMS_SHIFT (5U) +#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) +#define FTM_SC_TOIE_MASK (0x40U) +#define FTM_SC_TOIE_SHIFT (6U) +#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) +#define FTM_SC_TOF_MASK (0x80U) +#define FTM_SC_TOF_SHIFT (7U) +#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) + +/*! @name CNT - Counter */ +#define FTM_CNT_COUNT_MASK (0xFFFFU) +#define FTM_CNT_COUNT_SHIFT (0U) +#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) + +/*! @name MOD - Modulo */ +#define FTM_MOD_MOD_MASK (0xFFFFU) +#define FTM_MOD_MOD_SHIFT (0U) +#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) + +/*! @name CnSC - Channel (n) Status And Control */ +#define FTM_CnSC_DMA_MASK (0x1U) +#define FTM_CnSC_DMA_SHIFT (0U) +#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK) +#define FTM_CnSC_ELSA_MASK (0x4U) +#define FTM_CnSC_ELSA_SHIFT (2U) +#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) +#define FTM_CnSC_ELSB_MASK (0x8U) +#define FTM_CnSC_ELSB_SHIFT (3U) +#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) +#define FTM_CnSC_MSA_MASK (0x10U) +#define FTM_CnSC_MSA_SHIFT (4U) +#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) +#define FTM_CnSC_MSB_MASK (0x20U) +#define FTM_CnSC_MSB_SHIFT (5U) +#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) +#define FTM_CnSC_CHIE_MASK (0x40U) +#define FTM_CnSC_CHIE_SHIFT (6U) +#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) +#define FTM_CnSC_CHF_MASK (0x80U) +#define FTM_CnSC_CHF_SHIFT (7U) +#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) + +/* The count of FTM_CnSC */ +#define FTM_CnSC_COUNT (8U) + +/*! @name CnV - Channel (n) Value */ +#define FTM_CnV_VAL_MASK (0xFFFFU) +#define FTM_CnV_VAL_SHIFT (0U) +#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) + +/* The count of FTM_CnV */ +#define FTM_CnV_COUNT (8U) + +/*! @name CNTIN - Counter Initial Value */ +#define FTM_CNTIN_INIT_MASK (0xFFFFU) +#define FTM_CNTIN_INIT_SHIFT (0U) +#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) + +/*! @name STATUS - Capture And Compare Status */ +#define FTM_STATUS_CH0F_MASK (0x1U) +#define FTM_STATUS_CH0F_SHIFT (0U) +#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) +#define FTM_STATUS_CH1F_MASK (0x2U) +#define FTM_STATUS_CH1F_SHIFT (1U) +#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) +#define FTM_STATUS_CH2F_MASK (0x4U) +#define FTM_STATUS_CH2F_SHIFT (2U) +#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) +#define FTM_STATUS_CH3F_MASK (0x8U) +#define FTM_STATUS_CH3F_SHIFT (3U) +#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) +#define FTM_STATUS_CH4F_MASK (0x10U) +#define FTM_STATUS_CH4F_SHIFT (4U) +#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) +#define FTM_STATUS_CH5F_MASK (0x20U) +#define FTM_STATUS_CH5F_SHIFT (5U) +#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) +#define FTM_STATUS_CH6F_MASK (0x40U) +#define FTM_STATUS_CH6F_SHIFT (6U) +#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) +#define FTM_STATUS_CH7F_MASK (0x80U) +#define FTM_STATUS_CH7F_SHIFT (7U) +#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) + +/*! @name MODE - Features Mode Selection */ +#define FTM_MODE_FTMEN_MASK (0x1U) +#define FTM_MODE_FTMEN_SHIFT (0U) +#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) +#define FTM_MODE_INIT_MASK (0x2U) +#define FTM_MODE_INIT_SHIFT (1U) +#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) +#define FTM_MODE_WPDIS_MASK (0x4U) +#define FTM_MODE_WPDIS_SHIFT (2U) +#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) +#define FTM_MODE_PWMSYNC_MASK (0x8U) +#define FTM_MODE_PWMSYNC_SHIFT (3U) +#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) +#define FTM_MODE_CAPTEST_MASK (0x10U) +#define FTM_MODE_CAPTEST_SHIFT (4U) +#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) +#define FTM_MODE_FAULTM_MASK (0x60U) +#define FTM_MODE_FAULTM_SHIFT (5U) +#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) +#define FTM_MODE_FAULTIE_MASK (0x80U) +#define FTM_MODE_FAULTIE_SHIFT (7U) +#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) + +/*! @name SYNC - Synchronization */ +#define FTM_SYNC_CNTMIN_MASK (0x1U) +#define FTM_SYNC_CNTMIN_SHIFT (0U) +#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) +#define FTM_SYNC_CNTMAX_MASK (0x2U) +#define FTM_SYNC_CNTMAX_SHIFT (1U) +#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) +#define FTM_SYNC_REINIT_MASK (0x4U) +#define FTM_SYNC_REINIT_SHIFT (2U) +#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) +#define FTM_SYNC_SYNCHOM_MASK (0x8U) +#define FTM_SYNC_SYNCHOM_SHIFT (3U) +#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) +#define FTM_SYNC_TRIG0_MASK (0x10U) +#define FTM_SYNC_TRIG0_SHIFT (4U) +#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) +#define FTM_SYNC_TRIG1_MASK (0x20U) +#define FTM_SYNC_TRIG1_SHIFT (5U) +#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) +#define FTM_SYNC_TRIG2_MASK (0x40U) +#define FTM_SYNC_TRIG2_SHIFT (6U) +#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) +#define FTM_SYNC_SWSYNC_MASK (0x80U) +#define FTM_SYNC_SWSYNC_SHIFT (7U) +#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) + +/*! @name OUTINIT - Initial State For Channels Output */ +#define FTM_OUTINIT_CH0OI_MASK (0x1U) +#define FTM_OUTINIT_CH0OI_SHIFT (0U) +#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) +#define FTM_OUTINIT_CH1OI_MASK (0x2U) +#define FTM_OUTINIT_CH1OI_SHIFT (1U) +#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) +#define FTM_OUTINIT_CH2OI_MASK (0x4U) +#define FTM_OUTINIT_CH2OI_SHIFT (2U) +#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) +#define FTM_OUTINIT_CH3OI_MASK (0x8U) +#define FTM_OUTINIT_CH3OI_SHIFT (3U) +#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) +#define FTM_OUTINIT_CH4OI_MASK (0x10U) +#define FTM_OUTINIT_CH4OI_SHIFT (4U) +#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) +#define FTM_OUTINIT_CH5OI_MASK (0x20U) +#define FTM_OUTINIT_CH5OI_SHIFT (5U) +#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) +#define FTM_OUTINIT_CH6OI_MASK (0x40U) +#define FTM_OUTINIT_CH6OI_SHIFT (6U) +#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) +#define FTM_OUTINIT_CH7OI_MASK (0x80U) +#define FTM_OUTINIT_CH7OI_SHIFT (7U) +#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) + +/*! @name OUTMASK - Output Mask */ +#define FTM_OUTMASK_CH0OM_MASK (0x1U) +#define FTM_OUTMASK_CH0OM_SHIFT (0U) +#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) +#define FTM_OUTMASK_CH1OM_MASK (0x2U) +#define FTM_OUTMASK_CH1OM_SHIFT (1U) +#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) +#define FTM_OUTMASK_CH2OM_MASK (0x4U) +#define FTM_OUTMASK_CH2OM_SHIFT (2U) +#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) +#define FTM_OUTMASK_CH3OM_MASK (0x8U) +#define FTM_OUTMASK_CH3OM_SHIFT (3U) +#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) +#define FTM_OUTMASK_CH4OM_MASK (0x10U) +#define FTM_OUTMASK_CH4OM_SHIFT (4U) +#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) +#define FTM_OUTMASK_CH5OM_MASK (0x20U) +#define FTM_OUTMASK_CH5OM_SHIFT (5U) +#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) +#define FTM_OUTMASK_CH6OM_MASK (0x40U) +#define FTM_OUTMASK_CH6OM_SHIFT (6U) +#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) +#define FTM_OUTMASK_CH7OM_MASK (0x80U) +#define FTM_OUTMASK_CH7OM_SHIFT (7U) +#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) + +/*! @name COMBINE - Function For Linked Channels */ +#define FTM_COMBINE_COMBINE0_MASK (0x1U) +#define FTM_COMBINE_COMBINE0_SHIFT (0U) +#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) +#define FTM_COMBINE_COMP0_MASK (0x2U) +#define FTM_COMBINE_COMP0_SHIFT (1U) +#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) +#define FTM_COMBINE_DECAPEN0_MASK (0x4U) +#define FTM_COMBINE_DECAPEN0_SHIFT (2U) +#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) +#define FTM_COMBINE_DECAP0_MASK (0x8U) +#define FTM_COMBINE_DECAP0_SHIFT (3U) +#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) +#define FTM_COMBINE_DTEN0_MASK (0x10U) +#define FTM_COMBINE_DTEN0_SHIFT (4U) +#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) +#define FTM_COMBINE_SYNCEN0_MASK (0x20U) +#define FTM_COMBINE_SYNCEN0_SHIFT (5U) +#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) +#define FTM_COMBINE_FAULTEN0_MASK (0x40U) +#define FTM_COMBINE_FAULTEN0_SHIFT (6U) +#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) +#define FTM_COMBINE_COMBINE1_MASK (0x100U) +#define FTM_COMBINE_COMBINE1_SHIFT (8U) +#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) +#define FTM_COMBINE_COMP1_MASK (0x200U) +#define FTM_COMBINE_COMP1_SHIFT (9U) +#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) +#define FTM_COMBINE_DECAPEN1_MASK (0x400U) +#define FTM_COMBINE_DECAPEN1_SHIFT (10U) +#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) +#define FTM_COMBINE_DECAP1_MASK (0x800U) +#define FTM_COMBINE_DECAP1_SHIFT (11U) +#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) +#define FTM_COMBINE_DTEN1_MASK (0x1000U) +#define FTM_COMBINE_DTEN1_SHIFT (12U) +#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) +#define FTM_COMBINE_SYNCEN1_MASK (0x2000U) +#define FTM_COMBINE_SYNCEN1_SHIFT (13U) +#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) +#define FTM_COMBINE_FAULTEN1_MASK (0x4000U) +#define FTM_COMBINE_FAULTEN1_SHIFT (14U) +#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) +#define FTM_COMBINE_COMBINE2_MASK (0x10000U) +#define FTM_COMBINE_COMBINE2_SHIFT (16U) +#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) +#define FTM_COMBINE_COMP2_MASK (0x20000U) +#define FTM_COMBINE_COMP2_SHIFT (17U) +#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) +#define FTM_COMBINE_DECAPEN2_MASK (0x40000U) +#define FTM_COMBINE_DECAPEN2_SHIFT (18U) +#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) +#define FTM_COMBINE_DECAP2_MASK (0x80000U) +#define FTM_COMBINE_DECAP2_SHIFT (19U) +#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) +#define FTM_COMBINE_DTEN2_MASK (0x100000U) +#define FTM_COMBINE_DTEN2_SHIFT (20U) +#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) +#define FTM_COMBINE_SYNCEN2_MASK (0x200000U) +#define FTM_COMBINE_SYNCEN2_SHIFT (21U) +#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) +#define FTM_COMBINE_FAULTEN2_MASK (0x400000U) +#define FTM_COMBINE_FAULTEN2_SHIFT (22U) +#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) +#define FTM_COMBINE_COMBINE3_MASK (0x1000000U) +#define FTM_COMBINE_COMBINE3_SHIFT (24U) +#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) +#define FTM_COMBINE_COMP3_MASK (0x2000000U) +#define FTM_COMBINE_COMP3_SHIFT (25U) +#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) +#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) +#define FTM_COMBINE_DECAPEN3_SHIFT (26U) +#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) +#define FTM_COMBINE_DECAP3_MASK (0x8000000U) +#define FTM_COMBINE_DECAP3_SHIFT (27U) +#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) +#define FTM_COMBINE_DTEN3_MASK (0x10000000U) +#define FTM_COMBINE_DTEN3_SHIFT (28U) +#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) +#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) +#define FTM_COMBINE_SYNCEN3_SHIFT (29U) +#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) +#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) +#define FTM_COMBINE_FAULTEN3_SHIFT (30U) +#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) + +/*! @name DEADTIME - Deadtime Insertion Control */ +#define FTM_DEADTIME_DTVAL_MASK (0x3FU) +#define FTM_DEADTIME_DTVAL_SHIFT (0U) +#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) +#define FTM_DEADTIME_DTPS_MASK (0xC0U) +#define FTM_DEADTIME_DTPS_SHIFT (6U) +#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) + +/*! @name EXTTRIG - FTM External Trigger */ +#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) +#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) +#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) +#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) +#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) +#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) +#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) +#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) +#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) +#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) +#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) +#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) +#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) +#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) +#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) +#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) +#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) +#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) +#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) +#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) +#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) +#define FTM_EXTTRIG_TRIGF_MASK (0x80U) +#define FTM_EXTTRIG_TRIGF_SHIFT (7U) +#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) + +/*! @name POL - Channels Polarity */ +#define FTM_POL_POL0_MASK (0x1U) +#define FTM_POL_POL0_SHIFT (0U) +#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) +#define FTM_POL_POL1_MASK (0x2U) +#define FTM_POL_POL1_SHIFT (1U) +#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) +#define FTM_POL_POL2_MASK (0x4U) +#define FTM_POL_POL2_SHIFT (2U) +#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) +#define FTM_POL_POL3_MASK (0x8U) +#define FTM_POL_POL3_SHIFT (3U) +#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) +#define FTM_POL_POL4_MASK (0x10U) +#define FTM_POL_POL4_SHIFT (4U) +#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) +#define FTM_POL_POL5_MASK (0x20U) +#define FTM_POL_POL5_SHIFT (5U) +#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) +#define FTM_POL_POL6_MASK (0x40U) +#define FTM_POL_POL6_SHIFT (6U) +#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) +#define FTM_POL_POL7_MASK (0x80U) +#define FTM_POL_POL7_SHIFT (7U) +#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) + +/*! @name FMS - Fault Mode Status */ +#define FTM_FMS_FAULTF0_MASK (0x1U) +#define FTM_FMS_FAULTF0_SHIFT (0U) +#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) +#define FTM_FMS_FAULTF1_MASK (0x2U) +#define FTM_FMS_FAULTF1_SHIFT (1U) +#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) +#define FTM_FMS_FAULTF2_MASK (0x4U) +#define FTM_FMS_FAULTF2_SHIFT (2U) +#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) +#define FTM_FMS_FAULTF3_MASK (0x8U) +#define FTM_FMS_FAULTF3_SHIFT (3U) +#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) +#define FTM_FMS_FAULTIN_MASK (0x20U) +#define FTM_FMS_FAULTIN_SHIFT (5U) +#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) +#define FTM_FMS_WPEN_MASK (0x40U) +#define FTM_FMS_WPEN_SHIFT (6U) +#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) +#define FTM_FMS_FAULTF_MASK (0x80U) +#define FTM_FMS_FAULTF_SHIFT (7U) +#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) + +/*! @name FILTER - Input Capture Filter Control */ +#define FTM_FILTER_CH0FVAL_MASK (0xFU) +#define FTM_FILTER_CH0FVAL_SHIFT (0U) +#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) +#define FTM_FILTER_CH1FVAL_MASK (0xF0U) +#define FTM_FILTER_CH1FVAL_SHIFT (4U) +#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) +#define FTM_FILTER_CH2FVAL_MASK (0xF00U) +#define FTM_FILTER_CH2FVAL_SHIFT (8U) +#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) +#define FTM_FILTER_CH3FVAL_MASK (0xF000U) +#define FTM_FILTER_CH3FVAL_SHIFT (12U) +#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) + +/*! @name FLTCTRL - Fault Control */ +#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) +#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) +#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) +#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) +#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) +#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) +#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) +#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) +#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) +#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) +#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) +#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) +#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) +#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) +#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) +#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) +#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) +#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) +#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) +#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) +#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) +#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) +#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) +#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) +#define FTM_FLTCTRL_FFVAL_MASK (0xF00U) +#define FTM_FLTCTRL_FFVAL_SHIFT (8U) +#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) + +/*! @name QDCTRL - Quadrature Decoder Control And Status */ +#define FTM_QDCTRL_QUADEN_MASK (0x1U) +#define FTM_QDCTRL_QUADEN_SHIFT (0U) +#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK) +#define FTM_QDCTRL_TOFDIR_MASK (0x2U) +#define FTM_QDCTRL_TOFDIR_SHIFT (1U) +#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK) +#define FTM_QDCTRL_QUADIR_MASK (0x4U) +#define FTM_QDCTRL_QUADIR_SHIFT (2U) +#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK) +#define FTM_QDCTRL_QUADMODE_MASK (0x8U) +#define FTM_QDCTRL_QUADMODE_SHIFT (3U) +#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK) +#define FTM_QDCTRL_PHBPOL_MASK (0x10U) +#define FTM_QDCTRL_PHBPOL_SHIFT (4U) +#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK) +#define FTM_QDCTRL_PHAPOL_MASK (0x20U) +#define FTM_QDCTRL_PHAPOL_SHIFT (5U) +#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK) +#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U) +#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U) +#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK) +#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U) +#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U) +#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK) + +/*! @name CONF - Configuration */ +#define FTM_CONF_NUMTOF_MASK (0x1FU) +#define FTM_CONF_NUMTOF_SHIFT (0U) +#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK) +#define FTM_CONF_BDMMODE_MASK (0xC0U) +#define FTM_CONF_BDMMODE_SHIFT (6U) +#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) +#define FTM_CONF_GTBEEN_MASK (0x200U) +#define FTM_CONF_GTBEEN_SHIFT (9U) +#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) +#define FTM_CONF_GTBEOUT_MASK (0x400U) +#define FTM_CONF_GTBEOUT_SHIFT (10U) +#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) + +/*! @name FLTPOL - FTM Fault Input Polarity */ +#define FTM_FLTPOL_FLT0POL_MASK (0x1U) +#define FTM_FLTPOL_FLT0POL_SHIFT (0U) +#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) +#define FTM_FLTPOL_FLT1POL_MASK (0x2U) +#define FTM_FLTPOL_FLT1POL_SHIFT (1U) +#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) +#define FTM_FLTPOL_FLT2POL_MASK (0x4U) +#define FTM_FLTPOL_FLT2POL_SHIFT (2U) +#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) +#define FTM_FLTPOL_FLT3POL_MASK (0x8U) +#define FTM_FLTPOL_FLT3POL_SHIFT (3U) +#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) + +/*! @name SYNCONF - Synchronization Configuration */ +#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) +#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) +#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) +#define FTM_SYNCONF_CNTINC_MASK (0x4U) +#define FTM_SYNCONF_CNTINC_SHIFT (2U) +#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) +#define FTM_SYNCONF_INVC_MASK (0x10U) +#define FTM_SYNCONF_INVC_SHIFT (4U) +#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) +#define FTM_SYNCONF_SWOC_MASK (0x20U) +#define FTM_SYNCONF_SWOC_SHIFT (5U) +#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) +#define FTM_SYNCONF_SYNCMODE_MASK (0x80U) +#define FTM_SYNCONF_SYNCMODE_SHIFT (7U) +#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) +#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) +#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) +#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) +#define FTM_SYNCONF_SWWRBUF_MASK (0x200U) +#define FTM_SYNCONF_SWWRBUF_SHIFT (9U) +#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) +#define FTM_SYNCONF_SWOM_MASK (0x400U) +#define FTM_SYNCONF_SWOM_SHIFT (10U) +#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) +#define FTM_SYNCONF_SWINVC_MASK (0x800U) +#define FTM_SYNCONF_SWINVC_SHIFT (11U) +#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) +#define FTM_SYNCONF_SWSOC_MASK (0x1000U) +#define FTM_SYNCONF_SWSOC_SHIFT (12U) +#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) +#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) +#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) +#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) +#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) +#define FTM_SYNCONF_HWWRBUF_SHIFT (17U) +#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) +#define FTM_SYNCONF_HWOM_MASK (0x40000U) +#define FTM_SYNCONF_HWOM_SHIFT (18U) +#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) +#define FTM_SYNCONF_HWINVC_MASK (0x80000U) +#define FTM_SYNCONF_HWINVC_SHIFT (19U) +#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) +#define FTM_SYNCONF_HWSOC_MASK (0x100000U) +#define FTM_SYNCONF_HWSOC_SHIFT (20U) +#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) + +/*! @name INVCTRL - FTM Inverting Control */ +#define FTM_INVCTRL_INV0EN_MASK (0x1U) +#define FTM_INVCTRL_INV0EN_SHIFT (0U) +#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) +#define FTM_INVCTRL_INV1EN_MASK (0x2U) +#define FTM_INVCTRL_INV1EN_SHIFT (1U) +#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) +#define FTM_INVCTRL_INV2EN_MASK (0x4U) +#define FTM_INVCTRL_INV2EN_SHIFT (2U) +#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) +#define FTM_INVCTRL_INV3EN_MASK (0x8U) +#define FTM_INVCTRL_INV3EN_SHIFT (3U) +#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) + +/*! @name SWOCTRL - FTM Software Output Control */ +#define FTM_SWOCTRL_CH0OC_MASK (0x1U) +#define FTM_SWOCTRL_CH0OC_SHIFT (0U) +#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) +#define FTM_SWOCTRL_CH1OC_MASK (0x2U) +#define FTM_SWOCTRL_CH1OC_SHIFT (1U) +#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) +#define FTM_SWOCTRL_CH2OC_MASK (0x4U) +#define FTM_SWOCTRL_CH2OC_SHIFT (2U) +#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) +#define FTM_SWOCTRL_CH3OC_MASK (0x8U) +#define FTM_SWOCTRL_CH3OC_SHIFT (3U) +#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) +#define FTM_SWOCTRL_CH4OC_MASK (0x10U) +#define FTM_SWOCTRL_CH4OC_SHIFT (4U) +#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) +#define FTM_SWOCTRL_CH5OC_MASK (0x20U) +#define FTM_SWOCTRL_CH5OC_SHIFT (5U) +#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) +#define FTM_SWOCTRL_CH6OC_MASK (0x40U) +#define FTM_SWOCTRL_CH6OC_SHIFT (6U) +#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) +#define FTM_SWOCTRL_CH7OC_MASK (0x80U) +#define FTM_SWOCTRL_CH7OC_SHIFT (7U) +#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) +#define FTM_SWOCTRL_CH0OCV_MASK (0x100U) +#define FTM_SWOCTRL_CH0OCV_SHIFT (8U) +#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) +#define FTM_SWOCTRL_CH1OCV_MASK (0x200U) +#define FTM_SWOCTRL_CH1OCV_SHIFT (9U) +#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) +#define FTM_SWOCTRL_CH2OCV_MASK (0x400U) +#define FTM_SWOCTRL_CH2OCV_SHIFT (10U) +#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) +#define FTM_SWOCTRL_CH3OCV_MASK (0x800U) +#define FTM_SWOCTRL_CH3OCV_SHIFT (11U) +#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) +#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) +#define FTM_SWOCTRL_CH4OCV_SHIFT (12U) +#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) +#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) +#define FTM_SWOCTRL_CH5OCV_SHIFT (13U) +#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) +#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) +#define FTM_SWOCTRL_CH6OCV_SHIFT (14U) +#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) +#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) +#define FTM_SWOCTRL_CH7OCV_SHIFT (15U) +#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) + +/*! @name PWMLOAD - FTM PWM Load */ +#define FTM_PWMLOAD_CH0SEL_MASK (0x1U) +#define FTM_PWMLOAD_CH0SEL_SHIFT (0U) +#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) +#define FTM_PWMLOAD_CH1SEL_MASK (0x2U) +#define FTM_PWMLOAD_CH1SEL_SHIFT (1U) +#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) +#define FTM_PWMLOAD_CH2SEL_MASK (0x4U) +#define FTM_PWMLOAD_CH2SEL_SHIFT (2U) +#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) +#define FTM_PWMLOAD_CH3SEL_MASK (0x8U) +#define FTM_PWMLOAD_CH3SEL_SHIFT (3U) +#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) +#define FTM_PWMLOAD_CH4SEL_MASK (0x10U) +#define FTM_PWMLOAD_CH4SEL_SHIFT (4U) +#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) +#define FTM_PWMLOAD_CH5SEL_MASK (0x20U) +#define FTM_PWMLOAD_CH5SEL_SHIFT (5U) +#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) +#define FTM_PWMLOAD_CH6SEL_MASK (0x40U) +#define FTM_PWMLOAD_CH6SEL_SHIFT (6U) +#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) +#define FTM_PWMLOAD_CH7SEL_MASK (0x80U) +#define FTM_PWMLOAD_CH7SEL_SHIFT (7U) +#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) +#define FTM_PWMLOAD_LDOK_MASK (0x200U) +#define FTM_PWMLOAD_LDOK_SHIFT (9U) +#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) + + +/*! + * @} + */ /* end of group FTM_Register_Masks */ + + +/* FTM - Peripheral instance base addresses */ +/** Peripheral FTM0 base address */ +#define FTM0_BASE (0x40038000u) +/** Peripheral FTM0 base pointer */ +#define FTM0 ((FTM_Type *)FTM0_BASE) +/** Peripheral FTM1 base address */ +#define FTM1_BASE (0x40039000u) +/** Peripheral FTM1 base pointer */ +#define FTM1 ((FTM_Type *)FTM1_BASE) +/** Peripheral FTM2 base address */ +#define FTM2_BASE (0x4003A000u) +/** Peripheral FTM2 base pointer */ +#define FTM2 ((FTM_Type *)FTM2_BASE) +/** Peripheral FTM3 base address */ +#define FTM3_BASE (0x400B9000u) +/** Peripheral FTM3 base pointer */ +#define FTM3 ((FTM_Type *)FTM3_BASE) +/** Array initializer of FTM peripheral base addresses */ +#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE } +/** Array initializer of FTM peripheral base pointers */ +#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 } +/** Interrupt vectors for the FTM peripheral type */ +#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn } + +/*! + * @} + */ /* end of group FTM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ + __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ + __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ + __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ + __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ + __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name PDOR - Port Data Output Register */ +#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) +#define GPIO_PDOR_PDO_SHIFT (0U) +#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) + +/*! @name PSOR - Port Set Output Register */ +#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) +#define GPIO_PSOR_PTSO_SHIFT (0U) +#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) + +/*! @name PCOR - Port Clear Output Register */ +#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) +#define GPIO_PCOR_PTCO_SHIFT (0U) +#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) + +/*! @name PTOR - Port Toggle Output Register */ +#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) +#define GPIO_PTOR_PTTO_SHIFT (0U) +#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) + +/*! @name PDIR - Port Data Input Register */ +#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) +#define GPIO_PDIR_PDI_SHIFT (0U) +#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) + +/*! @name PDDR - Port Data Direction Register */ +#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) +#define GPIO_PDDR_PDD_SHIFT (0U) +#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIOA base address */ +#define GPIOA_BASE (0x400FF000u) +/** Peripheral GPIOA base pointer */ +#define GPIOA ((GPIO_Type *)GPIOA_BASE) +/** Peripheral GPIOB base address */ +#define GPIOB_BASE (0x400FF040u) +/** Peripheral GPIOB base pointer */ +#define GPIOB ((GPIO_Type *)GPIOB_BASE) +/** Peripheral GPIOC base address */ +#define GPIOC_BASE (0x400FF080u) +/** Peripheral GPIOC base pointer */ +#define GPIOC ((GPIO_Type *)GPIOC_BASE) +/** Peripheral GPIOD base address */ +#define GPIOD_BASE (0x400FF0C0u) +/** Peripheral GPIOD base pointer */ +#define GPIOD ((GPIO_Type *)GPIOD_BASE) +/** Peripheral GPIOE base address */ +#define GPIOE_BASE (0x400FF100u) +/** Peripheral GPIOE base pointer */ +#define GPIOE ((GPIO_Type *)GPIOE_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ + __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ + __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ + __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ + __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ + __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ + __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ + __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ + __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ + __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ + __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ + __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name A1 - I2C Address Register 1 */ +#define I2C_A1_AD_MASK (0xFEU) +#define I2C_A1_AD_SHIFT (1U) +#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) + +/*! @name F - I2C Frequency Divider register */ +#define I2C_F_ICR_MASK (0x3FU) +#define I2C_F_ICR_SHIFT (0U) +#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) +#define I2C_F_MULT_MASK (0xC0U) +#define I2C_F_MULT_SHIFT (6U) +#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) + +/*! @name C1 - I2C Control Register 1 */ +#define I2C_C1_DMAEN_MASK (0x1U) +#define I2C_C1_DMAEN_SHIFT (0U) +#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) +#define I2C_C1_WUEN_MASK (0x2U) +#define I2C_C1_WUEN_SHIFT (1U) +#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) +#define I2C_C1_RSTA_MASK (0x4U) +#define I2C_C1_RSTA_SHIFT (2U) +#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) +#define I2C_C1_TXAK_MASK (0x8U) +#define I2C_C1_TXAK_SHIFT (3U) +#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) +#define I2C_C1_TX_MASK (0x10U) +#define I2C_C1_TX_SHIFT (4U) +#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) +#define I2C_C1_MST_MASK (0x20U) +#define I2C_C1_MST_SHIFT (5U) +#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) +#define I2C_C1_IICIE_MASK (0x40U) +#define I2C_C1_IICIE_SHIFT (6U) +#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) +#define I2C_C1_IICEN_MASK (0x80U) +#define I2C_C1_IICEN_SHIFT (7U) +#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) + +/*! @name S - I2C Status register */ +#define I2C_S_RXAK_MASK (0x1U) +#define I2C_S_RXAK_SHIFT (0U) +#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) +#define I2C_S_IICIF_MASK (0x2U) +#define I2C_S_IICIF_SHIFT (1U) +#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) +#define I2C_S_SRW_MASK (0x4U) +#define I2C_S_SRW_SHIFT (2U) +#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) +#define I2C_S_RAM_MASK (0x8U) +#define I2C_S_RAM_SHIFT (3U) +#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) +#define I2C_S_ARBL_MASK (0x10U) +#define I2C_S_ARBL_SHIFT (4U) +#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) +#define I2C_S_BUSY_MASK (0x20U) +#define I2C_S_BUSY_SHIFT (5U) +#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) +#define I2C_S_IAAS_MASK (0x40U) +#define I2C_S_IAAS_SHIFT (6U) +#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) +#define I2C_S_TCF_MASK (0x80U) +#define I2C_S_TCF_SHIFT (7U) +#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) + +/*! @name D - I2C Data I/O register */ +#define I2C_D_DATA_MASK (0xFFU) +#define I2C_D_DATA_SHIFT (0U) +#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) + +/*! @name C2 - I2C Control Register 2 */ +#define I2C_C2_AD_MASK (0x7U) +#define I2C_C2_AD_SHIFT (0U) +#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) +#define I2C_C2_RMEN_MASK (0x8U) +#define I2C_C2_RMEN_SHIFT (3U) +#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) +#define I2C_C2_SBRC_MASK (0x10U) +#define I2C_C2_SBRC_SHIFT (4U) +#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) +#define I2C_C2_HDRS_MASK (0x20U) +#define I2C_C2_HDRS_SHIFT (5U) +#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) +#define I2C_C2_ADEXT_MASK (0x40U) +#define I2C_C2_ADEXT_SHIFT (6U) +#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) +#define I2C_C2_GCAEN_MASK (0x80U) +#define I2C_C2_GCAEN_SHIFT (7U) +#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) + +/*! @name FLT - I2C Programmable Input Glitch Filter register */ +#define I2C_FLT_FLT_MASK (0xFU) +#define I2C_FLT_FLT_SHIFT (0U) +#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) +#define I2C_FLT_STARTF_MASK (0x10U) +#define I2C_FLT_STARTF_SHIFT (4U) +#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) +#define I2C_FLT_SSIE_MASK (0x20U) +#define I2C_FLT_SSIE_SHIFT (5U) +#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) +#define I2C_FLT_STOPF_MASK (0x40U) +#define I2C_FLT_STOPF_SHIFT (6U) +#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) +#define I2C_FLT_SHEN_MASK (0x80U) +#define I2C_FLT_SHEN_SHIFT (7U) +#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) + +/*! @name RA - I2C Range Address register */ +#define I2C_RA_RAD_MASK (0xFEU) +#define I2C_RA_RAD_SHIFT (1U) +#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) + +/*! @name SMB - I2C SMBus Control and Status register */ +#define I2C_SMB_SHTF2IE_MASK (0x1U) +#define I2C_SMB_SHTF2IE_SHIFT (0U) +#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) +#define I2C_SMB_SHTF2_MASK (0x2U) +#define I2C_SMB_SHTF2_SHIFT (1U) +#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) +#define I2C_SMB_SHTF1_MASK (0x4U) +#define I2C_SMB_SHTF1_SHIFT (2U) +#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) +#define I2C_SMB_SLTF_MASK (0x8U) +#define I2C_SMB_SLTF_SHIFT (3U) +#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) +#define I2C_SMB_TCKSEL_MASK (0x10U) +#define I2C_SMB_TCKSEL_SHIFT (4U) +#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) +#define I2C_SMB_SIICAEN_MASK (0x20U) +#define I2C_SMB_SIICAEN_SHIFT (5U) +#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) +#define I2C_SMB_ALERTEN_MASK (0x40U) +#define I2C_SMB_ALERTEN_SHIFT (6U) +#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) +#define I2C_SMB_FACK_MASK (0x80U) +#define I2C_SMB_FACK_SHIFT (7U) +#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) + +/*! @name A2 - I2C Address Register 2 */ +#define I2C_A2_SAD_MASK (0xFEU) +#define I2C_A2_SAD_SHIFT (1U) +#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) + +/*! @name SLTH - I2C SCL Low Timeout Register High */ +#define I2C_SLTH_SSLT_MASK (0xFFU) +#define I2C_SLTH_SSLT_SHIFT (0U) +#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) + +/*! @name SLTL - I2C SCL Low Timeout Register Low */ +#define I2C_SLTL_SSLT_MASK (0xFFU) +#define I2C_SLTL_SSLT_SHIFT (0U) +#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C0 base address */ +#define I2C0_BASE (0x40066000u) +/** Peripheral I2C0 base pointer */ +#define I2C0 ((I2C_Type *)I2C0_BASE) +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x40067000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Peripheral I2C2 base address */ +#define I2C2_BASE (0x400E6000u) +/** Peripheral I2C2 base pointer */ +#define I2C2 ((I2C_Type *)I2C2_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { I2C0, I2C1, I2C2 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[24]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_3[28]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ + uint8_t RESERVED_4[8]; + __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[24]; + __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_6[24]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ + uint8_t RESERVED_7[28]; + __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ + __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name TCSR - SAI Transmit Control Register */ +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +#define I2S_TCR1_TFW_MASK (0x7U) +#define I2S_TCR1_TFW_SHIFT (0U) +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK (0x30000U) +#define I2S_TCR3_TCE_SHIFT (16U) +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) + +/*! @name TDR - SAI Transmit Data Register */ +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (2U) + +/*! @name TFR - SAI Transmit FIFO Register */ +#define I2S_TFR_RFP_MASK (0xFU) +#define I2S_TFR_RFP_SHIFT (0U) +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK (0xF0000U) +#define I2S_TFR_WFP_SHIFT (16U) +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (2U) + +/*! @name TMR - SAI Transmit Mask Register */ +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) + +/*! @name RCSR - SAI Receive Control Register */ +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +#define I2S_RCR1_RFW_MASK (0x7U) +#define I2S_RCR1_RFW_SHIFT (0U) +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK (0x30000U) +#define I2S_RCR3_RCE_SHIFT (16U) +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) + +/*! @name RDR - SAI Receive Data Register */ +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (2U) + +/*! @name RFR - SAI Receive FIFO Register */ +#define I2S_RFR_RFP_MASK (0xFU) +#define I2S_RFR_RFP_SHIFT (0U) +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) +#define I2S_RFR_WFP_MASK (0xF0000U) +#define I2S_RFR_WFP_SHIFT (16U) +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (2U) + +/*! @name RMR - SAI Receive Mask Register */ +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) + +/*! @name MCR - SAI MCLK Control Register */ +#define I2S_MCR_MICS_MASK (0x3000000U) +#define I2S_MCR_MICS_SHIFT (24U) +#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK) +#define I2S_MCR_MOE_MASK (0x40000000U) +#define I2S_MCR_MOE_SHIFT (30U) +#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) +#define I2S_MCR_DUF_MASK (0x80000000U) +#define I2S_MCR_DUF_SHIFT (31U) +#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK) + +/*! @name MDR - SAI MCLK Divide Register */ +#define I2S_MDR_DIVIDE_MASK (0xFFFU) +#define I2S_MDR_DIVIDE_SHIFT (0U) +#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK) +#define I2S_MDR_FRACT_MASK (0xFF000U) +#define I2S_MDR_FRACT_SHIFT (12U) +#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK) + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S0 base address */ +#define I2S0_BASE (0x4002F000u) +/** Peripheral I2S0 base pointer */ +#define I2S0 ((I2S_Type *)I2S0_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { I2S0_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { I2S0 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { I2S0_Rx_IRQn } +#define I2S_TX_IRQS { I2S0_Tx_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LLWU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer + * @{ + */ + +/** LLWU - Register Layout Typedef */ +typedef struct { + __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ + __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ + __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ + __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ + __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ + __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ + __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ + __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ + __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ + __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ + __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */ +} LLWU_Type; + +/* ---------------------------------------------------------------------------- + -- LLWU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LLWU_Register_Masks LLWU Register Masks + * @{ + */ + +/*! @name PE1 - LLWU Pin Enable 1 register */ +#define LLWU_PE1_WUPE0_MASK (0x3U) +#define LLWU_PE1_WUPE0_SHIFT (0U) +#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) +#define LLWU_PE1_WUPE1_MASK (0xCU) +#define LLWU_PE1_WUPE1_SHIFT (2U) +#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) +#define LLWU_PE1_WUPE2_MASK (0x30U) +#define LLWU_PE1_WUPE2_SHIFT (4U) +#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) +#define LLWU_PE1_WUPE3_MASK (0xC0U) +#define LLWU_PE1_WUPE3_SHIFT (6U) +#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) + +/*! @name PE2 - LLWU Pin Enable 2 register */ +#define LLWU_PE2_WUPE4_MASK (0x3U) +#define LLWU_PE2_WUPE4_SHIFT (0U) +#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) +#define LLWU_PE2_WUPE5_MASK (0xCU) +#define LLWU_PE2_WUPE5_SHIFT (2U) +#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) +#define LLWU_PE2_WUPE6_MASK (0x30U) +#define LLWU_PE2_WUPE6_SHIFT (4U) +#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) +#define LLWU_PE2_WUPE7_MASK (0xC0U) +#define LLWU_PE2_WUPE7_SHIFT (6U) +#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) + +/*! @name PE3 - LLWU Pin Enable 3 register */ +#define LLWU_PE3_WUPE8_MASK (0x3U) +#define LLWU_PE3_WUPE8_SHIFT (0U) +#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) +#define LLWU_PE3_WUPE9_MASK (0xCU) +#define LLWU_PE3_WUPE9_SHIFT (2U) +#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) +#define LLWU_PE3_WUPE10_MASK (0x30U) +#define LLWU_PE3_WUPE10_SHIFT (4U) +#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) +#define LLWU_PE3_WUPE11_MASK (0xC0U) +#define LLWU_PE3_WUPE11_SHIFT (6U) +#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) + +/*! @name PE4 - LLWU Pin Enable 4 register */ +#define LLWU_PE4_WUPE12_MASK (0x3U) +#define LLWU_PE4_WUPE12_SHIFT (0U) +#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) +#define LLWU_PE4_WUPE13_MASK (0xCU) +#define LLWU_PE4_WUPE13_SHIFT (2U) +#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) +#define LLWU_PE4_WUPE14_MASK (0x30U) +#define LLWU_PE4_WUPE14_SHIFT (4U) +#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) +#define LLWU_PE4_WUPE15_MASK (0xC0U) +#define LLWU_PE4_WUPE15_SHIFT (6U) +#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) + +/*! @name ME - LLWU Module Enable register */ +#define LLWU_ME_WUME0_MASK (0x1U) +#define LLWU_ME_WUME0_SHIFT (0U) +#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) +#define LLWU_ME_WUME1_MASK (0x2U) +#define LLWU_ME_WUME1_SHIFT (1U) +#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) +#define LLWU_ME_WUME2_MASK (0x4U) +#define LLWU_ME_WUME2_SHIFT (2U) +#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) +#define LLWU_ME_WUME3_MASK (0x8U) +#define LLWU_ME_WUME3_SHIFT (3U) +#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) +#define LLWU_ME_WUME4_MASK (0x10U) +#define LLWU_ME_WUME4_SHIFT (4U) +#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) +#define LLWU_ME_WUME5_MASK (0x20U) +#define LLWU_ME_WUME5_SHIFT (5U) +#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) +#define LLWU_ME_WUME6_MASK (0x40U) +#define LLWU_ME_WUME6_SHIFT (6U) +#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) +#define LLWU_ME_WUME7_MASK (0x80U) +#define LLWU_ME_WUME7_SHIFT (7U) +#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) + +/*! @name F1 - LLWU Flag 1 register */ +#define LLWU_F1_WUF0_MASK (0x1U) +#define LLWU_F1_WUF0_SHIFT (0U) +#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) +#define LLWU_F1_WUF1_MASK (0x2U) +#define LLWU_F1_WUF1_SHIFT (1U) +#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) +#define LLWU_F1_WUF2_MASK (0x4U) +#define LLWU_F1_WUF2_SHIFT (2U) +#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) +#define LLWU_F1_WUF3_MASK (0x8U) +#define LLWU_F1_WUF3_SHIFT (3U) +#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) +#define LLWU_F1_WUF4_MASK (0x10U) +#define LLWU_F1_WUF4_SHIFT (4U) +#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) +#define LLWU_F1_WUF5_MASK (0x20U) +#define LLWU_F1_WUF5_SHIFT (5U) +#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) +#define LLWU_F1_WUF6_MASK (0x40U) +#define LLWU_F1_WUF6_SHIFT (6U) +#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) +#define LLWU_F1_WUF7_MASK (0x80U) +#define LLWU_F1_WUF7_SHIFT (7U) +#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) + +/*! @name F2 - LLWU Flag 2 register */ +#define LLWU_F2_WUF8_MASK (0x1U) +#define LLWU_F2_WUF8_SHIFT (0U) +#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) +#define LLWU_F2_WUF9_MASK (0x2U) +#define LLWU_F2_WUF9_SHIFT (1U) +#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) +#define LLWU_F2_WUF10_MASK (0x4U) +#define LLWU_F2_WUF10_SHIFT (2U) +#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) +#define LLWU_F2_WUF11_MASK (0x8U) +#define LLWU_F2_WUF11_SHIFT (3U) +#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) +#define LLWU_F2_WUF12_MASK (0x10U) +#define LLWU_F2_WUF12_SHIFT (4U) +#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) +#define LLWU_F2_WUF13_MASK (0x20U) +#define LLWU_F2_WUF13_SHIFT (5U) +#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) +#define LLWU_F2_WUF14_MASK (0x40U) +#define LLWU_F2_WUF14_SHIFT (6U) +#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) +#define LLWU_F2_WUF15_MASK (0x80U) +#define LLWU_F2_WUF15_SHIFT (7U) +#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) + +/*! @name F3 - LLWU Flag 3 register */ +#define LLWU_F3_MWUF0_MASK (0x1U) +#define LLWU_F3_MWUF0_SHIFT (0U) +#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) +#define LLWU_F3_MWUF1_MASK (0x2U) +#define LLWU_F3_MWUF1_SHIFT (1U) +#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) +#define LLWU_F3_MWUF2_MASK (0x4U) +#define LLWU_F3_MWUF2_SHIFT (2U) +#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) +#define LLWU_F3_MWUF3_MASK (0x8U) +#define LLWU_F3_MWUF3_SHIFT (3U) +#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) +#define LLWU_F3_MWUF4_MASK (0x10U) +#define LLWU_F3_MWUF4_SHIFT (4U) +#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) +#define LLWU_F3_MWUF5_MASK (0x20U) +#define LLWU_F3_MWUF5_SHIFT (5U) +#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) +#define LLWU_F3_MWUF6_MASK (0x40U) +#define LLWU_F3_MWUF6_SHIFT (6U) +#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) +#define LLWU_F3_MWUF7_MASK (0x80U) +#define LLWU_F3_MWUF7_SHIFT (7U) +#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) + +/*! @name FILT1 - LLWU Pin Filter 1 register */ +#define LLWU_FILT1_FILTSEL_MASK (0xFU) +#define LLWU_FILT1_FILTSEL_SHIFT (0U) +#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) +#define LLWU_FILT1_FILTE_MASK (0x60U) +#define LLWU_FILT1_FILTE_SHIFT (5U) +#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) +#define LLWU_FILT1_FILTF_MASK (0x80U) +#define LLWU_FILT1_FILTF_SHIFT (7U) +#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) + +/*! @name FILT2 - LLWU Pin Filter 2 register */ +#define LLWU_FILT2_FILTSEL_MASK (0xFU) +#define LLWU_FILT2_FILTSEL_SHIFT (0U) +#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) +#define LLWU_FILT2_FILTE_MASK (0x60U) +#define LLWU_FILT2_FILTE_SHIFT (5U) +#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) +#define LLWU_FILT2_FILTF_MASK (0x80U) +#define LLWU_FILT2_FILTF_SHIFT (7U) +#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) + +/*! @name RST - LLWU Reset Enable register */ +#define LLWU_RST_RSTFILT_MASK (0x1U) +#define LLWU_RST_RSTFILT_SHIFT (0U) +#define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK) +#define LLWU_RST_LLRSTE_MASK (0x2U) +#define LLWU_RST_LLRSTE_SHIFT (1U) +#define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK) + + +/*! + * @} + */ /* end of group LLWU_Register_Masks */ + + +/* LLWU - Peripheral instance base addresses */ +/** Peripheral LLWU base address */ +#define LLWU_BASE (0x4007C000u) +/** Peripheral LLWU base pointer */ +#define LLWU ((LLWU_Type *)LLWU_BASE) +/** Array initializer of LLWU peripheral base addresses */ +#define LLWU_BASE_ADDRS { LLWU_BASE } +/** Array initializer of LLWU peripheral base pointers */ +#define LLWU_BASE_PTRS { LLWU } +/** Interrupt vectors for the LLWU peripheral type */ +#define LLWU_IRQS { LLWU_IRQn } + +/*! + * @} + */ /* end of group LLWU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ + __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ + __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ + __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/*! @name CSR - Low Power Timer Control Status Register */ +#define LPTMR_CSR_TEN_MASK (0x1U) +#define LPTMR_CSR_TEN_SHIFT (0U) +#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) +#define LPTMR_CSR_TMS_MASK (0x2U) +#define LPTMR_CSR_TMS_SHIFT (1U) +#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) +#define LPTMR_CSR_TFC_MASK (0x4U) +#define LPTMR_CSR_TFC_SHIFT (2U) +#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) +#define LPTMR_CSR_TPP_MASK (0x8U) +#define LPTMR_CSR_TPP_SHIFT (3U) +#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) +#define LPTMR_CSR_TPS_MASK (0x30U) +#define LPTMR_CSR_TPS_SHIFT (4U) +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) +#define LPTMR_CSR_TIE_MASK (0x40U) +#define LPTMR_CSR_TIE_SHIFT (6U) +#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) +#define LPTMR_CSR_TCF_MASK (0x80U) +#define LPTMR_CSR_TCF_SHIFT (7U) +#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) + +/*! @name PSR - Low Power Timer Prescale Register */ +#define LPTMR_PSR_PCS_MASK (0x3U) +#define LPTMR_PSR_PCS_SHIFT (0U) +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) +#define LPTMR_PSR_PBYP_MASK (0x4U) +#define LPTMR_PSR_PBYP_SHIFT (2U) +#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) +#define LPTMR_PSR_PRESCALE_MASK (0x78U) +#define LPTMR_PSR_PRESCALE_SHIFT (3U) +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) + +/*! @name CMR - Low Power Timer Compare Register */ +#define LPTMR_CMR_COMPARE_MASK (0xFFFFU) +#define LPTMR_CMR_COMPARE_SHIFT (0U) +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) + +/*! @name CNR - Low Power Timer Counter Register */ +#define LPTMR_CNR_COUNTER_MASK (0xFFFFU) +#define LPTMR_CNR_COUNTER_SHIFT (0U) +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) + + +/*! + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x40040000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/*! + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MCG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer + * @{ + */ + +/** MCG - Register Layout Typedef */ +typedef struct { + __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ + __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ + __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ + __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ + __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ + __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ + __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */ + uint8_t RESERVED_0[1]; + __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ + uint8_t RESERVED_1[1]; + __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ + __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ + __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ + __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ +} MCG_Type; + +/* ---------------------------------------------------------------------------- + -- MCG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCG_Register_Masks MCG Register Masks + * @{ + */ + +/*! @name C1 - MCG Control 1 Register */ +#define MCG_C1_IREFSTEN_MASK (0x1U) +#define MCG_C1_IREFSTEN_SHIFT (0U) +#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) +#define MCG_C1_IRCLKEN_MASK (0x2U) +#define MCG_C1_IRCLKEN_SHIFT (1U) +#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) +#define MCG_C1_IREFS_MASK (0x4U) +#define MCG_C1_IREFS_SHIFT (2U) +#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) +#define MCG_C1_FRDIV_MASK (0x38U) +#define MCG_C1_FRDIV_SHIFT (3U) +#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) +#define MCG_C1_CLKS_MASK (0xC0U) +#define MCG_C1_CLKS_SHIFT (6U) +#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) + +/*! @name C2 - MCG Control 2 Register */ +#define MCG_C2_IRCS_MASK (0x1U) +#define MCG_C2_IRCS_SHIFT (0U) +#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) +#define MCG_C2_LP_MASK (0x2U) +#define MCG_C2_LP_SHIFT (1U) +#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) +#define MCG_C2_EREFS_MASK (0x4U) +#define MCG_C2_EREFS_SHIFT (2U) +#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK) +#define MCG_C2_HGO_MASK (0x8U) +#define MCG_C2_HGO_SHIFT (3U) +#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK) +#define MCG_C2_RANGE_MASK (0x30U) +#define MCG_C2_RANGE_SHIFT (4U) +#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK) +#define MCG_C2_FCFTRIM_MASK (0x40U) +#define MCG_C2_FCFTRIM_SHIFT (6U) +#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK) +#define MCG_C2_LOCRE0_MASK (0x80U) +#define MCG_C2_LOCRE0_SHIFT (7U) +#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) + +/*! @name C3 - MCG Control 3 Register */ +#define MCG_C3_SCTRIM_MASK (0xFFU) +#define MCG_C3_SCTRIM_SHIFT (0U) +#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) + +/*! @name C4 - MCG Control 4 Register */ +#define MCG_C4_SCFTRIM_MASK (0x1U) +#define MCG_C4_SCFTRIM_SHIFT (0U) +#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) +#define MCG_C4_FCTRIM_MASK (0x1EU) +#define MCG_C4_FCTRIM_SHIFT (1U) +#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) +#define MCG_C4_DRST_DRS_MASK (0x60U) +#define MCG_C4_DRST_DRS_SHIFT (5U) +#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) +#define MCG_C4_DMX32_MASK (0x80U) +#define MCG_C4_DMX32_SHIFT (7U) +#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) + +/*! @name C5 - MCG Control 5 Register */ +#define MCG_C5_PRDIV0_MASK (0x1FU) +#define MCG_C5_PRDIV0_SHIFT (0U) +#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK) +#define MCG_C5_PLLSTEN0_MASK (0x20U) +#define MCG_C5_PLLSTEN0_SHIFT (5U) +#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK) +#define MCG_C5_PLLCLKEN0_MASK (0x40U) +#define MCG_C5_PLLCLKEN0_SHIFT (6U) +#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK) + +/*! @name C6 - MCG Control 6 Register */ +#define MCG_C6_VDIV0_MASK (0x1FU) +#define MCG_C6_VDIV0_SHIFT (0U) +#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK) +#define MCG_C6_CME0_MASK (0x20U) +#define MCG_C6_CME0_SHIFT (5U) +#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) +#define MCG_C6_PLLS_MASK (0x40U) +#define MCG_C6_PLLS_SHIFT (6U) +#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK) +#define MCG_C6_LOLIE0_MASK (0x80U) +#define MCG_C6_LOLIE0_SHIFT (7U) +#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK) + +/*! @name S - MCG Status Register */ +#define MCG_S_IRCST_MASK (0x1U) +#define MCG_S_IRCST_SHIFT (0U) +#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) +#define MCG_S_OSCINIT0_MASK (0x2U) +#define MCG_S_OSCINIT0_SHIFT (1U) +#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) +#define MCG_S_CLKST_MASK (0xCU) +#define MCG_S_CLKST_SHIFT (2U) +#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) +#define MCG_S_IREFST_MASK (0x10U) +#define MCG_S_IREFST_SHIFT (4U) +#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) +#define MCG_S_PLLST_MASK (0x20U) +#define MCG_S_PLLST_SHIFT (5U) +#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK) +#define MCG_S_LOCK0_MASK (0x40U) +#define MCG_S_LOCK0_SHIFT (6U) +#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK) +#define MCG_S_LOLS0_MASK (0x80U) +#define MCG_S_LOLS0_SHIFT (7U) +#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK) + +/*! @name SC - MCG Status and Control Register */ +#define MCG_SC_LOCS0_MASK (0x1U) +#define MCG_SC_LOCS0_SHIFT (0U) +#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) +#define MCG_SC_FCRDIV_MASK (0xEU) +#define MCG_SC_FCRDIV_SHIFT (1U) +#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) +#define MCG_SC_FLTPRSRV_MASK (0x10U) +#define MCG_SC_FLTPRSRV_SHIFT (4U) +#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) +#define MCG_SC_ATMF_MASK (0x20U) +#define MCG_SC_ATMF_SHIFT (5U) +#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) +#define MCG_SC_ATMS_MASK (0x40U) +#define MCG_SC_ATMS_SHIFT (6U) +#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) +#define MCG_SC_ATME_MASK (0x80U) +#define MCG_SC_ATME_SHIFT (7U) +#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) + +/*! @name ATCVH - MCG Auto Trim Compare Value High Register */ +#define MCG_ATCVH_ATCVH_MASK (0xFFU) +#define MCG_ATCVH_ATCVH_SHIFT (0U) +#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) + +/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ +#define MCG_ATCVL_ATCVL_MASK (0xFFU) +#define MCG_ATCVL_ATCVL_SHIFT (0U) +#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) + +/*! @name C7 - MCG Control 7 Register */ +#define MCG_C7_OSCSEL_MASK (0x3U) +#define MCG_C7_OSCSEL_SHIFT (0U) +#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK) + +/*! @name C8 - MCG Control 8 Register */ +#define MCG_C8_LOCS1_MASK (0x1U) +#define MCG_C8_LOCS1_SHIFT (0U) +#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK) +#define MCG_C8_CME1_MASK (0x20U) +#define MCG_C8_CME1_SHIFT (5U) +#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK) +#define MCG_C8_LOLRE_MASK (0x40U) +#define MCG_C8_LOLRE_SHIFT (6U) +#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK) +#define MCG_C8_LOCRE1_MASK (0x80U) +#define MCG_C8_LOCRE1_SHIFT (7U) +#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK) + + +/*! + * @} + */ /* end of group MCG_Register_Masks */ + + +/* MCG - Peripheral instance base addresses */ +/** Peripheral MCG base address */ +#define MCG_BASE (0x40064000u) +/** Peripheral MCG base pointer */ +#define MCG ((MCG_Type *)MCG_BASE) +/** Array initializer of MCG peripheral base addresses */ +#define MCG_BASE_ADDRS { MCG_BASE } +/** Array initializer of MCG peripheral base pointers */ +#define MCG_BASE_PTRS { MCG } + +/*! + * @} + */ /* end of group MCG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer + * @{ + */ + +/** MCM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[8]; + __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ + __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ + __IO uint32_t CR; /**< Control Register, offset: 0xC */ + __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */ + __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */ + __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */ + __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */ + uint8_t RESERVED_1[16]; + __IO uint32_t PID; /**< Process ID register, offset: 0x30 */ +} MCM_Type; + +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ +#define MCM_PLASC_ASC_MASK (0xFFU) +#define MCM_PLASC_ASC_SHIFT (0U) +#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) + +/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ +#define MCM_PLAMC_AMC_MASK (0xFFU) +#define MCM_PLAMC_AMC_SHIFT (0U) +#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) + +/*! @name CR - Control Register */ +#define MCM_CR_SRAMUAP_MASK (0x3000000U) +#define MCM_CR_SRAMUAP_SHIFT (24U) +#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK) +#define MCM_CR_SRAMUWP_MASK (0x4000000U) +#define MCM_CR_SRAMUWP_SHIFT (26U) +#define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK) +#define MCM_CR_SRAMLAP_MASK (0x30000000U) +#define MCM_CR_SRAMLAP_SHIFT (28U) +#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK) +#define MCM_CR_SRAMLWP_MASK (0x40000000U) +#define MCM_CR_SRAMLWP_SHIFT (30U) +#define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK) + +/*! @name ISCR - Interrupt Status Register */ +#define MCM_ISCR_IRQ_MASK (0x2U) +#define MCM_ISCR_IRQ_SHIFT (1U) +#define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK) +#define MCM_ISCR_NMI_MASK (0x4U) +#define MCM_ISCR_NMI_SHIFT (2U) +#define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK) +#define MCM_ISCR_DHREQ_MASK (0x8U) +#define MCM_ISCR_DHREQ_SHIFT (3U) +#define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK) +#define MCM_ISCR_FIOC_MASK (0x100U) +#define MCM_ISCR_FIOC_SHIFT (8U) +#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK) +#define MCM_ISCR_FDZC_MASK (0x200U) +#define MCM_ISCR_FDZC_SHIFT (9U) +#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK) +#define MCM_ISCR_FOFC_MASK (0x400U) +#define MCM_ISCR_FOFC_SHIFT (10U) +#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK) +#define MCM_ISCR_FUFC_MASK (0x800U) +#define MCM_ISCR_FUFC_SHIFT (11U) +#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK) +#define MCM_ISCR_FIXC_MASK (0x1000U) +#define MCM_ISCR_FIXC_SHIFT (12U) +#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK) +#define MCM_ISCR_FIDC_MASK (0x8000U) +#define MCM_ISCR_FIDC_SHIFT (15U) +#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK) +#define MCM_ISCR_FIOCE_MASK (0x1000000U) +#define MCM_ISCR_FIOCE_SHIFT (24U) +#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK) +#define MCM_ISCR_FDZCE_MASK (0x2000000U) +#define MCM_ISCR_FDZCE_SHIFT (25U) +#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK) +#define MCM_ISCR_FOFCE_MASK (0x4000000U) +#define MCM_ISCR_FOFCE_SHIFT (26U) +#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK) +#define MCM_ISCR_FUFCE_MASK (0x8000000U) +#define MCM_ISCR_FUFCE_SHIFT (27U) +#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK) +#define MCM_ISCR_FIXCE_MASK (0x10000000U) +#define MCM_ISCR_FIXCE_SHIFT (28U) +#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK) +#define MCM_ISCR_FIDCE_MASK (0x80000000U) +#define MCM_ISCR_FIDCE_SHIFT (31U) +#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) + +/*! @name ETBCC - ETB Counter Control register */ +#define MCM_ETBCC_CNTEN_MASK (0x1U) +#define MCM_ETBCC_CNTEN_SHIFT (0U) +#define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK) +#define MCM_ETBCC_RSPT_MASK (0x6U) +#define MCM_ETBCC_RSPT_SHIFT (1U) +#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK) +#define MCM_ETBCC_RLRQ_MASK (0x8U) +#define MCM_ETBCC_RLRQ_SHIFT (3U) +#define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK) +#define MCM_ETBCC_ETDIS_MASK (0x10U) +#define MCM_ETBCC_ETDIS_SHIFT (4U) +#define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK) +#define MCM_ETBCC_ITDIS_MASK (0x20U) +#define MCM_ETBCC_ITDIS_SHIFT (5U) +#define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK) + +/*! @name ETBRL - ETB Reload register */ +#define MCM_ETBRL_RELOAD_MASK (0x7FFU) +#define MCM_ETBRL_RELOAD_SHIFT (0U) +#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK) + +/*! @name ETBCNT - ETB Counter Value register */ +#define MCM_ETBCNT_COUNTER_MASK (0x7FFU) +#define MCM_ETBCNT_COUNTER_SHIFT (0U) +#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK) + +/*! @name PID - Process ID register */ +#define MCM_PID_PID_MASK (0xFFU) +#define MCM_PID_PID_SHIFT (0U) +#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK) + + +/*! + * @} + */ /* end of group MCM_Register_Masks */ + + +/* MCM - Peripheral instance base addresses */ +/** Peripheral MCM base address */ +#define MCM_BASE (0xE0080000u) +/** Peripheral MCM base pointer */ +#define MCM ((MCM_Type *)MCM_BASE) +/** Array initializer of MCM peripheral base addresses */ +#define MCM_BASE_ADDRS { MCM_BASE } +/** Array initializer of MCM peripheral base pointers */ +#define MCM_BASE_PTRS { MCM } +/** Interrupt vectors for the MCM peripheral type */ +#define MCM_IRQS { MCM_IRQn } + +/*! + * @} + */ /* end of group MCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- NV Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer + * @{ + */ + +/** NV - Register Layout Typedef */ +typedef struct { + __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ + __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ + __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ + __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ + __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ + __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ + __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ + __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ + __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ + __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ + __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ + __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ + __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ + __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ + __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */ + __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */ +} NV_Type; + +/* ---------------------------------------------------------------------------- + -- NV Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NV_Register_Masks NV Register Masks + * @{ + */ + +/*! @name BACKKEY3 - Backdoor Comparison Key 3. */ +#define NV_BACKKEY3_KEY_MASK (0xFFU) +#define NV_BACKKEY3_KEY_SHIFT (0U) +#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) + +/*! @name BACKKEY2 - Backdoor Comparison Key 2. */ +#define NV_BACKKEY2_KEY_MASK (0xFFU) +#define NV_BACKKEY2_KEY_SHIFT (0U) +#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) + +/*! @name BACKKEY1 - Backdoor Comparison Key 1. */ +#define NV_BACKKEY1_KEY_MASK (0xFFU) +#define NV_BACKKEY1_KEY_SHIFT (0U) +#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) + +/*! @name BACKKEY0 - Backdoor Comparison Key 0. */ +#define NV_BACKKEY0_KEY_MASK (0xFFU) +#define NV_BACKKEY0_KEY_SHIFT (0U) +#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) + +/*! @name BACKKEY7 - Backdoor Comparison Key 7. */ +#define NV_BACKKEY7_KEY_MASK (0xFFU) +#define NV_BACKKEY7_KEY_SHIFT (0U) +#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) + +/*! @name BACKKEY6 - Backdoor Comparison Key 6. */ +#define NV_BACKKEY6_KEY_MASK (0xFFU) +#define NV_BACKKEY6_KEY_SHIFT (0U) +#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) + +/*! @name BACKKEY5 - Backdoor Comparison Key 5. */ +#define NV_BACKKEY5_KEY_MASK (0xFFU) +#define NV_BACKKEY5_KEY_SHIFT (0U) +#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) + +/*! @name BACKKEY4 - Backdoor Comparison Key 4. */ +#define NV_BACKKEY4_KEY_MASK (0xFFU) +#define NV_BACKKEY4_KEY_SHIFT (0U) +#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) + +/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ +#define NV_FPROT3_PROT_MASK (0xFFU) +#define NV_FPROT3_PROT_SHIFT (0U) +#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) + +/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ +#define NV_FPROT2_PROT_MASK (0xFFU) +#define NV_FPROT2_PROT_SHIFT (0U) +#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) + +/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ +#define NV_FPROT1_PROT_MASK (0xFFU) +#define NV_FPROT1_PROT_SHIFT (0U) +#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) + +/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ +#define NV_FPROT0_PROT_MASK (0xFFU) +#define NV_FPROT0_PROT_SHIFT (0U) +#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) + +/*! @name FSEC - Non-volatile Flash Security Register */ +#define NV_FSEC_SEC_MASK (0x3U) +#define NV_FSEC_SEC_SHIFT (0U) +#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) +#define NV_FSEC_FSLACC_MASK (0xCU) +#define NV_FSEC_FSLACC_SHIFT (2U) +#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) +#define NV_FSEC_MEEN_MASK (0x30U) +#define NV_FSEC_MEEN_SHIFT (4U) +#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) +#define NV_FSEC_KEYEN_MASK (0xC0U) +#define NV_FSEC_KEYEN_SHIFT (6U) +#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) + +/*! @name FOPT - Non-volatile Flash Option Register */ +#define NV_FOPT_LPBOOT_MASK (0x1U) +#define NV_FOPT_LPBOOT_SHIFT (0U) +#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK) +#define NV_FOPT_EZPORT_DIS_MASK (0x2U) +#define NV_FOPT_EZPORT_DIS_SHIFT (1U) +#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK) + +/*! @name FEPROT - Non-volatile EERAM Protection Register */ +#define NV_FEPROT_EPROT_MASK (0xFFU) +#define NV_FEPROT_EPROT_SHIFT (0U) +#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK) + +/*! @name FDPROT - Non-volatile D-Flash Protection Register */ +#define NV_FDPROT_DPROT_MASK (0xFFU) +#define NV_FDPROT_DPROT_SHIFT (0U) +#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK) + + +/*! + * @} + */ /* end of group NV_Register_Masks */ + + +/* NV - Peripheral instance base addresses */ +/** Peripheral FTFE_FlashConfig base address */ +#define FTFE_FlashConfig_BASE (0x400u) +/** Peripheral FTFE_FlashConfig base pointer */ +#define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE) +/** Array initializer of NV peripheral base addresses */ +#define NV_BASE_ADDRS { FTFE_FlashConfig_BASE } +/** Array initializer of NV peripheral base pointers */ +#define NV_BASE_PTRS { FTFE_FlashConfig } + +/*! + * @} + */ /* end of group NV_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer + * @{ + */ + +/** OSC - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ +} OSC_Type; + +/* ---------------------------------------------------------------------------- + -- OSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSC_Register_Masks OSC Register Masks + * @{ + */ + +/*! @name CR - OSC Control Register */ +#define OSC_CR_SC16P_MASK (0x1U) +#define OSC_CR_SC16P_SHIFT (0U) +#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) +#define OSC_CR_SC8P_MASK (0x2U) +#define OSC_CR_SC8P_SHIFT (1U) +#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) +#define OSC_CR_SC4P_MASK (0x4U) +#define OSC_CR_SC4P_SHIFT (2U) +#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) +#define OSC_CR_SC2P_MASK (0x8U) +#define OSC_CR_SC2P_SHIFT (3U) +#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) +#define OSC_CR_EREFSTEN_MASK (0x20U) +#define OSC_CR_EREFSTEN_SHIFT (5U) +#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) +#define OSC_CR_ERCLKEN_MASK (0x80U) +#define OSC_CR_ERCLKEN_SHIFT (7U) +#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) + + +/*! + * @} + */ /* end of group OSC_Register_Masks */ + + +/* OSC - Peripheral instance base addresses */ +/** Peripheral OSC base address */ +#define OSC_BASE (0x40065000u) +/** Peripheral OSC base pointer */ +#define OSC ((OSC_Type *)OSC_BASE) +/** Array initializer of OSC peripheral base addresses */ +#define OSC_BASE_ADDRS { OSC_BASE } +/** Array initializer of OSC peripheral base pointers */ +#define OSC_BASE_PTRS { OSC } + +/*! + * @} + */ /* end of group OSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PDB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer + * @{ + */ + +/** PDB - Register Layout Typedef */ +typedef struct { + __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ + __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ + __I uint32_t CNT; /**< Counter register, offset: 0x8 */ + __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x28 */ + __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */ + __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */ + __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */ + uint8_t RESERVED_0[24]; + } CH[2]; + uint8_t RESERVED_0[240]; + struct { /* offset: 0x150, array step: 0x8 */ + __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */ + __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */ + } DAC[2]; + uint8_t RESERVED_1[48]; + __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ + __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */ +} PDB_Type; + +/* ---------------------------------------------------------------------------- + -- PDB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDB_Register_Masks PDB Register Masks + * @{ + */ + +/*! @name SC - Status and Control register */ +#define PDB_SC_LDOK_MASK (0x1U) +#define PDB_SC_LDOK_SHIFT (0U) +#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK) +#define PDB_SC_CONT_MASK (0x2U) +#define PDB_SC_CONT_SHIFT (1U) +#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK) +#define PDB_SC_MULT_MASK (0xCU) +#define PDB_SC_MULT_SHIFT (2U) +#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK) +#define PDB_SC_PDBIE_MASK (0x20U) +#define PDB_SC_PDBIE_SHIFT (5U) +#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK) +#define PDB_SC_PDBIF_MASK (0x40U) +#define PDB_SC_PDBIF_SHIFT (6U) +#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK) +#define PDB_SC_PDBEN_MASK (0x80U) +#define PDB_SC_PDBEN_SHIFT (7U) +#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK) +#define PDB_SC_TRGSEL_MASK (0xF00U) +#define PDB_SC_TRGSEL_SHIFT (8U) +#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK) +#define PDB_SC_PRESCALER_MASK (0x7000U) +#define PDB_SC_PRESCALER_SHIFT (12U) +#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK) +#define PDB_SC_DMAEN_MASK (0x8000U) +#define PDB_SC_DMAEN_SHIFT (15U) +#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK) +#define PDB_SC_SWTRIG_MASK (0x10000U) +#define PDB_SC_SWTRIG_SHIFT (16U) +#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK) +#define PDB_SC_PDBEIE_MASK (0x20000U) +#define PDB_SC_PDBEIE_SHIFT (17U) +#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK) +#define PDB_SC_LDMOD_MASK (0xC0000U) +#define PDB_SC_LDMOD_SHIFT (18U) +#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK) + +/*! @name MOD - Modulus register */ +#define PDB_MOD_MOD_MASK (0xFFFFU) +#define PDB_MOD_MOD_SHIFT (0U) +#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK) + +/*! @name CNT - Counter register */ +#define PDB_CNT_CNT_MASK (0xFFFFU) +#define PDB_CNT_CNT_SHIFT (0U) +#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK) + +/*! @name IDLY - Interrupt Delay register */ +#define PDB_IDLY_IDLY_MASK (0xFFFFU) +#define PDB_IDLY_IDLY_SHIFT (0U) +#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK) + +/*! @name C1 - Channel n Control register 1 */ +#define PDB_C1_EN_MASK (0xFFU) +#define PDB_C1_EN_SHIFT (0U) +#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK) +#define PDB_C1_TOS_MASK (0xFF00U) +#define PDB_C1_TOS_SHIFT (8U) +#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK) +#define PDB_C1_BB_MASK (0xFF0000U) +#define PDB_C1_BB_SHIFT (16U) +#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK) + +/* The count of PDB_C1 */ +#define PDB_C1_COUNT (2U) + +/*! @name S - Channel n Status register */ +#define PDB_S_ERR_MASK (0xFFU) +#define PDB_S_ERR_SHIFT (0U) +#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK) +#define PDB_S_CF_MASK (0xFF0000U) +#define PDB_S_CF_SHIFT (16U) +#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK) + +/* The count of PDB_S */ +#define PDB_S_COUNT (2U) + +/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */ +#define PDB_DLY_DLY_MASK (0xFFFFU) +#define PDB_DLY_DLY_SHIFT (0U) +#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK) + +/* The count of PDB_DLY */ +#define PDB_DLY_COUNT (2U) + +/* The count of PDB_DLY */ +#define PDB_DLY_COUNT2 (2U) + +/*! @name INTC - DAC Interval Trigger n Control register */ +#define PDB_INTC_TOE_MASK (0x1U) +#define PDB_INTC_TOE_SHIFT (0U) +#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK) +#define PDB_INTC_EXT_MASK (0x2U) +#define PDB_INTC_EXT_SHIFT (1U) +#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK) + +/* The count of PDB_INTC */ +#define PDB_INTC_COUNT (2U) + +/*! @name INT - DAC Interval n register */ +#define PDB_INT_INT_MASK (0xFFFFU) +#define PDB_INT_INT_SHIFT (0U) +#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK) + +/* The count of PDB_INT */ +#define PDB_INT_COUNT (2U) + +/*! @name POEN - Pulse-Out n Enable register */ +#define PDB_POEN_POEN_MASK (0xFFU) +#define PDB_POEN_POEN_SHIFT (0U) +#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK) + +/*! @name PODLY - Pulse-Out n Delay register */ +#define PDB_PODLY_DLY2_MASK (0xFFFFU) +#define PDB_PODLY_DLY2_SHIFT (0U) +#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK) +#define PDB_PODLY_DLY1_MASK (0xFFFF0000U) +#define PDB_PODLY_DLY1_SHIFT (16U) +#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK) + +/* The count of PDB_PODLY */ +#define PDB_PODLY_COUNT (3U) + + +/*! + * @} + */ /* end of group PDB_Register_Masks */ + + +/* PDB - Peripheral instance base addresses */ +/** Peripheral PDB0 base address */ +#define PDB0_BASE (0x40036000u) +/** Peripheral PDB0 base pointer */ +#define PDB0 ((PDB_Type *)PDB0_BASE) +/** Array initializer of PDB peripheral base addresses */ +#define PDB_BASE_ADDRS { PDB0_BASE } +/** Array initializer of PDB peripheral base pointers */ +#define PDB_BASE_PTRS { PDB0 } +/** Interrupt vectors for the PDB peripheral type */ +#define PDB_IRQS { PDB0_IRQn } + +/*! + * @} + */ /* end of group PDB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer + * @{ + */ + +/** PIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ + uint8_t RESERVED_0[252]; + struct { /* offset: 0x100, array step: 0x10 */ + __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ + __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ + } CHANNEL[4]; +} PIT_Type; + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/*! @name MCR - PIT Module Control Register */ +#define PIT_MCR_FRZ_MASK (0x1U) +#define PIT_MCR_FRZ_SHIFT (0U) +#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) +#define PIT_MCR_MDIS_MASK (0x2U) +#define PIT_MCR_MDIS_SHIFT (1U) +#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) + +/*! @name LDVAL - Timer Load Value Register */ +#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) +#define PIT_LDVAL_TSV_SHIFT (0U) +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) + +/* The count of PIT_LDVAL */ +#define PIT_LDVAL_COUNT (4U) + +/*! @name CVAL - Current Timer Value Register */ +#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) +#define PIT_CVAL_TVL_SHIFT (0U) +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) + +/* The count of PIT_CVAL */ +#define PIT_CVAL_COUNT (4U) + +/*! @name TCTRL - Timer Control Register */ +#define PIT_TCTRL_TEN_MASK (0x1U) +#define PIT_TCTRL_TEN_SHIFT (0U) +#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) +#define PIT_TCTRL_TIE_MASK (0x2U) +#define PIT_TCTRL_TIE_SHIFT (1U) +#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) +#define PIT_TCTRL_CHN_MASK (0x4U) +#define PIT_TCTRL_CHN_SHIFT (2U) +#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) + +/* The count of PIT_TCTRL */ +#define PIT_TCTRL_COUNT (4U) + +/*! @name TFLG - Timer Flag Register */ +#define PIT_TFLG_TIF_MASK (0x1U) +#define PIT_TFLG_TIF_SHIFT (0U) +#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) + +/* The count of PIT_TFLG */ +#define PIT_TFLG_COUNT (4U) + + +/*! + * @} + */ /* end of group PIT_Register_Masks */ + + +/* PIT - Peripheral instance base addresses */ +/** Peripheral PIT base address */ +#define PIT_BASE (0x40037000u) +/** Peripheral PIT base pointer */ +#define PIT ((PIT_Type *)PIT_BASE) +/** Array initializer of PIT peripheral base addresses */ +#define PIT_BASE_ADDRS { PIT_BASE } +/** Array initializer of PIT peripheral base pointers */ +#define PIT_BASE_PTRS { PIT } +/** Interrupt vectors for the PIT peripheral type */ +#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } } + +/*! + * @} + */ /* end of group PIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer + * @{ + */ + +/** PMC - Register Layout Typedef */ +typedef struct { + __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ + __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ + __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ +} PMC_Type; + +/* ---------------------------------------------------------------------------- + -- PMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMC_Register_Masks PMC Register Masks + * @{ + */ + +/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ +#define PMC_LVDSC1_LVDV_MASK (0x3U) +#define PMC_LVDSC1_LVDV_SHIFT (0U) +#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) +#define PMC_LVDSC1_LVDRE_MASK (0x10U) +#define PMC_LVDSC1_LVDRE_SHIFT (4U) +#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) +#define PMC_LVDSC1_LVDIE_MASK (0x20U) +#define PMC_LVDSC1_LVDIE_SHIFT (5U) +#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) +#define PMC_LVDSC1_LVDACK_MASK (0x40U) +#define PMC_LVDSC1_LVDACK_SHIFT (6U) +#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) +#define PMC_LVDSC1_LVDF_MASK (0x80U) +#define PMC_LVDSC1_LVDF_SHIFT (7U) +#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) + +/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ +#define PMC_LVDSC2_LVWV_MASK (0x3U) +#define PMC_LVDSC2_LVWV_SHIFT (0U) +#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) +#define PMC_LVDSC2_LVWIE_MASK (0x20U) +#define PMC_LVDSC2_LVWIE_SHIFT (5U) +#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) +#define PMC_LVDSC2_LVWACK_MASK (0x40U) +#define PMC_LVDSC2_LVWACK_SHIFT (6U) +#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) +#define PMC_LVDSC2_LVWF_MASK (0x80U) +#define PMC_LVDSC2_LVWF_SHIFT (7U) +#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) + +/*! @name REGSC - Regulator Status And Control register */ +#define PMC_REGSC_BGBE_MASK (0x1U) +#define PMC_REGSC_BGBE_SHIFT (0U) +#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) +#define PMC_REGSC_REGONS_MASK (0x4U) +#define PMC_REGSC_REGONS_SHIFT (2U) +#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) +#define PMC_REGSC_ACKISO_MASK (0x8U) +#define PMC_REGSC_ACKISO_SHIFT (3U) +#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) +#define PMC_REGSC_BGEN_MASK (0x10U) +#define PMC_REGSC_BGEN_SHIFT (4U) +#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) + + +/*! + * @} + */ /* end of group PMC_Register_Masks */ + + +/* PMC - Peripheral instance base addresses */ +/** Peripheral PMC base address */ +#define PMC_BASE (0x4007D000u) +/** Peripheral PMC base pointer */ +#define PMC ((PMC_Type *)PMC_BASE) +/** Array initializer of PMC peripheral base addresses */ +#define PMC_BASE_ADDRS { PMC_BASE } +/** Array initializer of PMC peripheral base pointers */ +#define PMC_BASE_PTRS { PMC } +/** Interrupt vectors for the PMC peripheral type */ +#define PMC_IRQS { LVD_LVW_IRQn } + +/*! + * @} + */ /* end of group PMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PORT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer + * @{ + */ + +/** PORT - Register Layout Typedef */ +typedef struct { + __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ + __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ + __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ + uint8_t RESERVED_0[24]; + __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ + uint8_t RESERVED_1[28]; + __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ + __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ + __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ +} PORT_Type; + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/*! @name PCR - Pin Control Register n */ +#define PORT_PCR_PS_MASK (0x1U) +#define PORT_PCR_PS_SHIFT (0U) +#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) +#define PORT_PCR_PE_MASK (0x2U) +#define PORT_PCR_PE_SHIFT (1U) +#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) +#define PORT_PCR_SRE_MASK (0x4U) +#define PORT_PCR_SRE_SHIFT (2U) +#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) +#define PORT_PCR_PFE_MASK (0x10U) +#define PORT_PCR_PFE_SHIFT (4U) +#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) +#define PORT_PCR_ODE_MASK (0x20U) +#define PORT_PCR_ODE_SHIFT (5U) +#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) +#define PORT_PCR_DSE_MASK (0x40U) +#define PORT_PCR_DSE_SHIFT (6U) +#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) +#define PORT_PCR_MUX_MASK (0x700U) +#define PORT_PCR_MUX_SHIFT (8U) +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) +#define PORT_PCR_LK_MASK (0x8000U) +#define PORT_PCR_LK_SHIFT (15U) +#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) +#define PORT_PCR_IRQC_MASK (0xF0000U) +#define PORT_PCR_IRQC_SHIFT (16U) +#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) +#define PORT_PCR_ISF_MASK (0x1000000U) +#define PORT_PCR_ISF_SHIFT (24U) +#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) + +/* The count of PORT_PCR */ +#define PORT_PCR_COUNT (32U) + +/*! @name GPCLR - Global Pin Control Low Register */ +#define PORT_GPCLR_GPWD_MASK (0xFFFFU) +#define PORT_GPCLR_GPWD_SHIFT (0U) +#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) +#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) +#define PORT_GPCLR_GPWE_SHIFT (16U) +#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) + +/*! @name GPCHR - Global Pin Control High Register */ +#define PORT_GPCHR_GPWD_MASK (0xFFFFU) +#define PORT_GPCHR_GPWD_SHIFT (0U) +#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) +#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) +#define PORT_GPCHR_GPWE_SHIFT (16U) +#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) + +/*! @name ISFR - Interrupt Status Flag Register */ +#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) +#define PORT_ISFR_ISF_SHIFT (0U) +#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) + +/*! @name DFER - Digital Filter Enable Register */ +#define PORT_DFER_DFE_MASK (0xFFFFFFFFU) +#define PORT_DFER_DFE_SHIFT (0U) +#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) + +/*! @name DFCR - Digital Filter Clock Register */ +#define PORT_DFCR_CS_MASK (0x1U) +#define PORT_DFCR_CS_SHIFT (0U) +#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) + +/*! @name DFWR - Digital Filter Width Register */ +#define PORT_DFWR_FILT_MASK (0x1FU) +#define PORT_DFWR_FILT_SHIFT (0U) +#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) + + +/*! + * @} + */ /* end of group PORT_Register_Masks */ + + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORTA base address */ +#define PORTA_BASE (0x40049000u) +/** Peripheral PORTA base pointer */ +#define PORTA ((PORT_Type *)PORTA_BASE) +/** Peripheral PORTB base address */ +#define PORTB_BASE (0x4004A000u) +/** Peripheral PORTB base pointer */ +#define PORTB ((PORT_Type *)PORTB_BASE) +/** Peripheral PORTC base address */ +#define PORTC_BASE (0x4004B000u) +/** Peripheral PORTC base pointer */ +#define PORTC ((PORT_Type *)PORTC_BASE) +/** Peripheral PORTD base address */ +#define PORTD_BASE (0x4004C000u) +/** Peripheral PORTD base pointer */ +#define PORTD ((PORT_Type *)PORTD_BASE) +/** Peripheral PORTE base address */ +#define PORTE_BASE (0x4004D000u) +/** Peripheral PORTE base pointer */ +#define PORTE ((PORT_Type *)PORTE_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } +/** Interrupt vectors for the PORT peripheral type */ +#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn } + +/*! + * @} + */ /* end of group PORT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer + * @{ + */ + +/** RCM - Register Layout Typedef */ +typedef struct { + __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ + __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ + uint8_t RESERVED_0[2]; + __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ + __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ + uint8_t RESERVED_1[1]; + __I uint8_t MR; /**< Mode Register, offset: 0x7 */ +} RCM_Type; + +/* ---------------------------------------------------------------------------- + -- RCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RCM_Register_Masks RCM Register Masks + * @{ + */ + +/*! @name SRS0 - System Reset Status Register 0 */ +#define RCM_SRS0_WAKEUP_MASK (0x1U) +#define RCM_SRS0_WAKEUP_SHIFT (0U) +#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) +#define RCM_SRS0_LVD_MASK (0x2U) +#define RCM_SRS0_LVD_SHIFT (1U) +#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) +#define RCM_SRS0_LOC_MASK (0x4U) +#define RCM_SRS0_LOC_SHIFT (2U) +#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) +#define RCM_SRS0_LOL_MASK (0x8U) +#define RCM_SRS0_LOL_SHIFT (3U) +#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK) +#define RCM_SRS0_WDOG_MASK (0x20U) +#define RCM_SRS0_WDOG_SHIFT (5U) +#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) +#define RCM_SRS0_PIN_MASK (0x40U) +#define RCM_SRS0_PIN_SHIFT (6U) +#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) +#define RCM_SRS0_POR_MASK (0x80U) +#define RCM_SRS0_POR_SHIFT (7U) +#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) + +/*! @name SRS1 - System Reset Status Register 1 */ +#define RCM_SRS1_JTAG_MASK (0x1U) +#define RCM_SRS1_JTAG_SHIFT (0U) +#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK) +#define RCM_SRS1_LOCKUP_MASK (0x2U) +#define RCM_SRS1_LOCKUP_SHIFT (1U) +#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) +#define RCM_SRS1_SW_MASK (0x4U) +#define RCM_SRS1_SW_SHIFT (2U) +#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) +#define RCM_SRS1_MDM_AP_MASK (0x8U) +#define RCM_SRS1_MDM_AP_SHIFT (3U) +#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) +#define RCM_SRS1_EZPT_MASK (0x10U) +#define RCM_SRS1_EZPT_SHIFT (4U) +#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK) +#define RCM_SRS1_SACKERR_MASK (0x20U) +#define RCM_SRS1_SACKERR_SHIFT (5U) +#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) + +/*! @name RPFC - Reset Pin Filter Control register */ +#define RCM_RPFC_RSTFLTSRW_MASK (0x3U) +#define RCM_RPFC_RSTFLTSRW_SHIFT (0U) +#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) +#define RCM_RPFC_RSTFLTSS_MASK (0x4U) +#define RCM_RPFC_RSTFLTSS_SHIFT (2U) +#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) + +/*! @name RPFW - Reset Pin Filter Width register */ +#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) +#define RCM_RPFW_RSTFLTSEL_SHIFT (0U) +#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) + +/*! @name MR - Mode Register */ +#define RCM_MR_EZP_MS_MASK (0x2U) +#define RCM_MR_EZP_MS_SHIFT (1U) +#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK) + + +/*! + * @} + */ /* end of group RCM_Register_Masks */ + + +/* RCM - Peripheral instance base addresses */ +/** Peripheral RCM base address */ +#define RCM_BASE (0x4007F000u) +/** Peripheral RCM base pointer */ +#define RCM ((RCM_Type *)RCM_BASE) +/** Array initializer of RCM peripheral base addresses */ +#define RCM_BASE_ADDRS { RCM_BASE } +/** Array initializer of RCM peripheral base pointers */ +#define RCM_BASE_PTRS { RCM } + +/*! + * @} + */ /* end of group RCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RFSYS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer + * @{ + */ + +/** RFSYS - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ +} RFSYS_Type; + +/* ---------------------------------------------------------------------------- + -- RFSYS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFSYS_Register_Masks RFSYS Register Masks + * @{ + */ + +/*! @name REG - Register file register */ +#define RFSYS_REG_LL_MASK (0xFFU) +#define RFSYS_REG_LL_SHIFT (0U) +#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) +#define RFSYS_REG_LH_MASK (0xFF00U) +#define RFSYS_REG_LH_SHIFT (8U) +#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK) +#define RFSYS_REG_HL_MASK (0xFF0000U) +#define RFSYS_REG_HL_SHIFT (16U) +#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK) +#define RFSYS_REG_HH_MASK (0xFF000000U) +#define RFSYS_REG_HH_SHIFT (24U) +#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) + +/* The count of RFSYS_REG */ +#define RFSYS_REG_COUNT (8U) + + +/*! + * @} + */ /* end of group RFSYS_Register_Masks */ + + +/* RFSYS - Peripheral instance base addresses */ +/** Peripheral RFSYS base address */ +#define RFSYS_BASE (0x40041000u) +/** Peripheral RFSYS base pointer */ +#define RFSYS ((RFSYS_Type *)RFSYS_BASE) +/** Array initializer of RFSYS peripheral base addresses */ +#define RFSYS_BASE_ADDRS { RFSYS_BASE } +/** Array initializer of RFSYS peripheral base pointers */ +#define RFSYS_BASE_PTRS { RFSYS } + +/*! + * @} + */ /* end of group RFSYS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RFVBAT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer + * @{ + */ + +/** RFVBAT - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */ +} RFVBAT_Type; + +/* ---------------------------------------------------------------------------- + -- RFVBAT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks + * @{ + */ + +/*! @name REG - VBAT register file register */ +#define RFVBAT_REG_LL_MASK (0xFFU) +#define RFVBAT_REG_LL_SHIFT (0U) +#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK) +#define RFVBAT_REG_LH_MASK (0xFF00U) +#define RFVBAT_REG_LH_SHIFT (8U) +#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK) +#define RFVBAT_REG_HL_MASK (0xFF0000U) +#define RFVBAT_REG_HL_SHIFT (16U) +#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK) +#define RFVBAT_REG_HH_MASK (0xFF000000U) +#define RFVBAT_REG_HH_SHIFT (24U) +#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK) + +/* The count of RFVBAT_REG */ +#define RFVBAT_REG_COUNT (8U) + + +/*! + * @} + */ /* end of group RFVBAT_Register_Masks */ + + +/* RFVBAT - Peripheral instance base addresses */ +/** Peripheral RFVBAT base address */ +#define RFVBAT_BASE (0x4003E000u) +/** Peripheral RFVBAT base pointer */ +#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE) +/** Array initializer of RFVBAT peripheral base addresses */ +#define RFVBAT_BASE_ADDRS { RFVBAT_BASE } +/** Array initializer of RFVBAT peripheral base pointers */ +#define RFVBAT_BASE_PTRS { RFVBAT } + +/*! + * @} + */ /* end of group RFVBAT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */ + __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */ + __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */ + __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name CR - RNGA Control Register */ +#define RNG_CR_GO_MASK (0x1U) +#define RNG_CR_GO_SHIFT (0U) +#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK) +#define RNG_CR_HA_MASK (0x2U) +#define RNG_CR_HA_SHIFT (1U) +#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK) +#define RNG_CR_INTM_MASK (0x4U) +#define RNG_CR_INTM_SHIFT (2U) +#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK) +#define RNG_CR_CLRI_MASK (0x8U) +#define RNG_CR_CLRI_SHIFT (3U) +#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK) +#define RNG_CR_SLP_MASK (0x10U) +#define RNG_CR_SLP_SHIFT (4U) +#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK) + +/*! @name SR - RNGA Status Register */ +#define RNG_SR_SECV_MASK (0x1U) +#define RNG_SR_SECV_SHIFT (0U) +#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK) +#define RNG_SR_LRS_MASK (0x2U) +#define RNG_SR_LRS_SHIFT (1U) +#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK) +#define RNG_SR_ORU_MASK (0x4U) +#define RNG_SR_ORU_SHIFT (2U) +#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK) +#define RNG_SR_ERRI_MASK (0x8U) +#define RNG_SR_ERRI_SHIFT (3U) +#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK) +#define RNG_SR_SLP_MASK (0x10U) +#define RNG_SR_SLP_SHIFT (4U) +#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK) +#define RNG_SR_OREG_LVL_MASK (0xFF00U) +#define RNG_SR_OREG_LVL_SHIFT (8U) +#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK) +#define RNG_SR_OREG_SIZE_MASK (0xFF0000U) +#define RNG_SR_OREG_SIZE_SHIFT (16U) +#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK) + +/*! @name ER - RNGA Entropy Register */ +#define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU) +#define RNG_ER_EXT_ENT_SHIFT (0U) +#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK) + +/*! @name OR - RNGA Output Register */ +#define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU) +#define RNG_OR_RANDOUT_SHIFT (0U) +#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK) + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +/** Peripheral RNG base address */ +#define RNG_BASE (0x40029000u) +/** Peripheral RNG base pointer */ +#define RNG ((RNG_Type *)RNG_BASE) +/** Array initializer of RNG peripheral base addresses */ +#define RNG_BASE_ADDRS { RNG_BASE } +/** Array initializer of RNG peripheral base pointers */ +#define RNG_BASE_PTRS { RNG } +/** Interrupt vectors for the RNG peripheral type */ +#define RNG_IRQS { RNG_IRQn } + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ + __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ + __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ + __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ + __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ + __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ + __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ + __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ + uint8_t RESERVED_0[2016]; + __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ + __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name TSR - RTC Time Seconds Register */ +#define RTC_TSR_TSR_MASK (0xFFFFFFFFU) +#define RTC_TSR_TSR_SHIFT (0U) +#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) + +/*! @name TPR - RTC Time Prescaler Register */ +#define RTC_TPR_TPR_MASK (0xFFFFU) +#define RTC_TPR_TPR_SHIFT (0U) +#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) + +/*! @name TAR - RTC Time Alarm Register */ +#define RTC_TAR_TAR_MASK (0xFFFFFFFFU) +#define RTC_TAR_TAR_SHIFT (0U) +#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) + +/*! @name TCR - RTC Time Compensation Register */ +#define RTC_TCR_TCR_MASK (0xFFU) +#define RTC_TCR_TCR_SHIFT (0U) +#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) +#define RTC_TCR_CIR_MASK (0xFF00U) +#define RTC_TCR_CIR_SHIFT (8U) +#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) +#define RTC_TCR_TCV_MASK (0xFF0000U) +#define RTC_TCR_TCV_SHIFT (16U) +#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) +#define RTC_TCR_CIC_MASK (0xFF000000U) +#define RTC_TCR_CIC_SHIFT (24U) +#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) + +/*! @name CR - RTC Control Register */ +#define RTC_CR_SWR_MASK (0x1U) +#define RTC_CR_SWR_SHIFT (0U) +#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) +#define RTC_CR_WPE_MASK (0x2U) +#define RTC_CR_WPE_SHIFT (1U) +#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) +#define RTC_CR_SUP_MASK (0x4U) +#define RTC_CR_SUP_SHIFT (2U) +#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) +#define RTC_CR_UM_MASK (0x8U) +#define RTC_CR_UM_SHIFT (3U) +#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) +#define RTC_CR_WPS_MASK (0x10U) +#define RTC_CR_WPS_SHIFT (4U) +#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) +#define RTC_CR_OSCE_MASK (0x100U) +#define RTC_CR_OSCE_SHIFT (8U) +#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) +#define RTC_CR_CLKO_MASK (0x200U) +#define RTC_CR_CLKO_SHIFT (9U) +#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) +#define RTC_CR_SC16P_MASK (0x400U) +#define RTC_CR_SC16P_SHIFT (10U) +#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) +#define RTC_CR_SC8P_MASK (0x800U) +#define RTC_CR_SC8P_SHIFT (11U) +#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) +#define RTC_CR_SC4P_MASK (0x1000U) +#define RTC_CR_SC4P_SHIFT (12U) +#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) +#define RTC_CR_SC2P_MASK (0x2000U) +#define RTC_CR_SC2P_SHIFT (13U) +#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) + +/*! @name SR - RTC Status Register */ +#define RTC_SR_TIF_MASK (0x1U) +#define RTC_SR_TIF_SHIFT (0U) +#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) +#define RTC_SR_TOF_MASK (0x2U) +#define RTC_SR_TOF_SHIFT (1U) +#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) +#define RTC_SR_TAF_MASK (0x4U) +#define RTC_SR_TAF_SHIFT (2U) +#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) +#define RTC_SR_TCE_MASK (0x10U) +#define RTC_SR_TCE_SHIFT (4U) +#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) + +/*! @name LR - RTC Lock Register */ +#define RTC_LR_TCL_MASK (0x8U) +#define RTC_LR_TCL_SHIFT (3U) +#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) +#define RTC_LR_CRL_MASK (0x10U) +#define RTC_LR_CRL_SHIFT (4U) +#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) +#define RTC_LR_SRL_MASK (0x20U) +#define RTC_LR_SRL_SHIFT (5U) +#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) +#define RTC_LR_LRL_MASK (0x40U) +#define RTC_LR_LRL_SHIFT (6U) +#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) + +/*! @name IER - RTC Interrupt Enable Register */ +#define RTC_IER_TIIE_MASK (0x1U) +#define RTC_IER_TIIE_SHIFT (0U) +#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) +#define RTC_IER_TOIE_MASK (0x2U) +#define RTC_IER_TOIE_SHIFT (1U) +#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) +#define RTC_IER_TAIE_MASK (0x4U) +#define RTC_IER_TAIE_SHIFT (2U) +#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) +#define RTC_IER_TSIE_MASK (0x10U) +#define RTC_IER_TSIE_SHIFT (4U) +#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) +#define RTC_IER_WPON_MASK (0x80U) +#define RTC_IER_WPON_SHIFT (7U) +#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) + +/*! @name WAR - RTC Write Access Register */ +#define RTC_WAR_TSRW_MASK (0x1U) +#define RTC_WAR_TSRW_SHIFT (0U) +#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) +#define RTC_WAR_TPRW_MASK (0x2U) +#define RTC_WAR_TPRW_SHIFT (1U) +#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) +#define RTC_WAR_TARW_MASK (0x4U) +#define RTC_WAR_TARW_SHIFT (2U) +#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) +#define RTC_WAR_TCRW_MASK (0x8U) +#define RTC_WAR_TCRW_SHIFT (3U) +#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) +#define RTC_WAR_CRW_MASK (0x10U) +#define RTC_WAR_CRW_SHIFT (4U) +#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) +#define RTC_WAR_SRW_MASK (0x20U) +#define RTC_WAR_SRW_SHIFT (5U) +#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) +#define RTC_WAR_LRW_MASK (0x40U) +#define RTC_WAR_LRW_SHIFT (6U) +#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) +#define RTC_WAR_IERW_MASK (0x80U) +#define RTC_WAR_IERW_SHIFT (7U) +#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) + +/*! @name RAR - RTC Read Access Register */ +#define RTC_RAR_TSRR_MASK (0x1U) +#define RTC_RAR_TSRR_SHIFT (0U) +#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) +#define RTC_RAR_TPRR_MASK (0x2U) +#define RTC_RAR_TPRR_SHIFT (1U) +#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) +#define RTC_RAR_TARR_MASK (0x4U) +#define RTC_RAR_TARR_SHIFT (2U) +#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) +#define RTC_RAR_TCRR_MASK (0x8U) +#define RTC_RAR_TCRR_SHIFT (3U) +#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) +#define RTC_RAR_CRR_MASK (0x10U) +#define RTC_RAR_CRR_SHIFT (4U) +#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) +#define RTC_RAR_SRR_MASK (0x20U) +#define RTC_RAR_SRR_SHIFT (5U) +#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) +#define RTC_RAR_LRR_MASK (0x40U) +#define RTC_RAR_LRR_SHIFT (6U) +#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) +#define RTC_RAR_IERR_MASK (0x80U) +#define RTC_RAR_IERR_SHIFT (7U) +#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC base address */ +#define RTC_BASE (0x4003D000u) +/** Peripheral RTC base pointer */ +#define RTC ((RTC_Type *)RTC_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } +#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer + * @{ + */ + +/** SDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */ + __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */ + __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */ + __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */ + __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */ + __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */ + __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */ + __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */ + __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */ + __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */ + __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */ + __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */ + __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */ + __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */ + uint8_t RESERVED_0[8]; + __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */ + __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */ + __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */ + uint8_t RESERVED_1[100]; + __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */ + __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */ + uint8_t RESERVED_2[52]; + __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */ +} SDHC_Type; + +/* ---------------------------------------------------------------------------- + -- SDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDHC_Register_Masks SDHC Register Masks + * @{ + */ + +/*! @name DSADDR - DMA System Address register */ +#define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU) +#define SDHC_DSADDR_DSADDR_SHIFT (2U) +#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK) + +/*! @name BLKATTR - Block Attributes register */ +#define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU) +#define SDHC_BLKATTR_BLKSIZE_SHIFT (0U) +#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK) +#define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U) +#define SDHC_BLKATTR_BLKCNT_SHIFT (16U) +#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK) + +/*! @name CMDARG - Command Argument register */ +#define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU) +#define SDHC_CMDARG_CMDARG_SHIFT (0U) +#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK) + +/*! @name XFERTYP - Transfer Type register */ +#define SDHC_XFERTYP_DMAEN_MASK (0x1U) +#define SDHC_XFERTYP_DMAEN_SHIFT (0U) +#define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK) +#define SDHC_XFERTYP_BCEN_MASK (0x2U) +#define SDHC_XFERTYP_BCEN_SHIFT (1U) +#define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK) +#define SDHC_XFERTYP_AC12EN_MASK (0x4U) +#define SDHC_XFERTYP_AC12EN_SHIFT (2U) +#define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK) +#define SDHC_XFERTYP_DTDSEL_MASK (0x10U) +#define SDHC_XFERTYP_DTDSEL_SHIFT (4U) +#define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK) +#define SDHC_XFERTYP_MSBSEL_MASK (0x20U) +#define SDHC_XFERTYP_MSBSEL_SHIFT (5U) +#define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK) +#define SDHC_XFERTYP_RSPTYP_MASK (0x30000U) +#define SDHC_XFERTYP_RSPTYP_SHIFT (16U) +#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK) +#define SDHC_XFERTYP_CCCEN_MASK (0x80000U) +#define SDHC_XFERTYP_CCCEN_SHIFT (19U) +#define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK) +#define SDHC_XFERTYP_CICEN_MASK (0x100000U) +#define SDHC_XFERTYP_CICEN_SHIFT (20U) +#define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK) +#define SDHC_XFERTYP_DPSEL_MASK (0x200000U) +#define SDHC_XFERTYP_DPSEL_SHIFT (21U) +#define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK) +#define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U) +#define SDHC_XFERTYP_CMDTYP_SHIFT (22U) +#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK) +#define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U) +#define SDHC_XFERTYP_CMDINX_SHIFT (24U) +#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK) + +/*! @name CMDRSP - Command Response 0..Command Response 3 */ +#define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU) +#define SDHC_CMDRSP_CMDRSP0_SHIFT (0U) +#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK) +#define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU) +#define SDHC_CMDRSP_CMDRSP1_SHIFT (0U) +#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK) +#define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU) +#define SDHC_CMDRSP_CMDRSP2_SHIFT (0U) +#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK) +#define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU) +#define SDHC_CMDRSP_CMDRSP3_SHIFT (0U) +#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK) + +/* The count of SDHC_CMDRSP */ +#define SDHC_CMDRSP_COUNT (4U) + +/*! @name DATPORT - Buffer Data Port register */ +#define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU) +#define SDHC_DATPORT_DATCONT_SHIFT (0U) +#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK) + +/*! @name PRSSTAT - Present State register */ +#define SDHC_PRSSTAT_CIHB_MASK (0x1U) +#define SDHC_PRSSTAT_CIHB_SHIFT (0U) +#define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK) +#define SDHC_PRSSTAT_CDIHB_MASK (0x2U) +#define SDHC_PRSSTAT_CDIHB_SHIFT (1U) +#define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK) +#define SDHC_PRSSTAT_DLA_MASK (0x4U) +#define SDHC_PRSSTAT_DLA_SHIFT (2U) +#define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK) +#define SDHC_PRSSTAT_SDSTB_MASK (0x8U) +#define SDHC_PRSSTAT_SDSTB_SHIFT (3U) +#define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK) +#define SDHC_PRSSTAT_IPGOFF_MASK (0x10U) +#define SDHC_PRSSTAT_IPGOFF_SHIFT (4U) +#define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK) +#define SDHC_PRSSTAT_HCKOFF_MASK (0x20U) +#define SDHC_PRSSTAT_HCKOFF_SHIFT (5U) +#define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK) +#define SDHC_PRSSTAT_PEROFF_MASK (0x40U) +#define SDHC_PRSSTAT_PEROFF_SHIFT (6U) +#define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK) +#define SDHC_PRSSTAT_SDOFF_MASK (0x80U) +#define SDHC_PRSSTAT_SDOFF_SHIFT (7U) +#define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK) +#define SDHC_PRSSTAT_WTA_MASK (0x100U) +#define SDHC_PRSSTAT_WTA_SHIFT (8U) +#define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK) +#define SDHC_PRSSTAT_RTA_MASK (0x200U) +#define SDHC_PRSSTAT_RTA_SHIFT (9U) +#define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK) +#define SDHC_PRSSTAT_BWEN_MASK (0x400U) +#define SDHC_PRSSTAT_BWEN_SHIFT (10U) +#define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK) +#define SDHC_PRSSTAT_BREN_MASK (0x800U) +#define SDHC_PRSSTAT_BREN_SHIFT (11U) +#define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK) +#define SDHC_PRSSTAT_CINS_MASK (0x10000U) +#define SDHC_PRSSTAT_CINS_SHIFT (16U) +#define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK) +#define SDHC_PRSSTAT_CLSL_MASK (0x800000U) +#define SDHC_PRSSTAT_CLSL_SHIFT (23U) +#define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK) +#define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U) +#define SDHC_PRSSTAT_DLSL_SHIFT (24U) +#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK) + +/*! @name PROCTL - Protocol Control register */ +#define SDHC_PROCTL_LCTL_MASK (0x1U) +#define SDHC_PROCTL_LCTL_SHIFT (0U) +#define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK) +#define SDHC_PROCTL_DTW_MASK (0x6U) +#define SDHC_PROCTL_DTW_SHIFT (1U) +#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK) +#define SDHC_PROCTL_D3CD_MASK (0x8U) +#define SDHC_PROCTL_D3CD_SHIFT (3U) +#define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK) +#define SDHC_PROCTL_EMODE_MASK (0x30U) +#define SDHC_PROCTL_EMODE_SHIFT (4U) +#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK) +#define SDHC_PROCTL_CDTL_MASK (0x40U) +#define SDHC_PROCTL_CDTL_SHIFT (6U) +#define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK) +#define SDHC_PROCTL_CDSS_MASK (0x80U) +#define SDHC_PROCTL_CDSS_SHIFT (7U) +#define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK) +#define SDHC_PROCTL_DMAS_MASK (0x300U) +#define SDHC_PROCTL_DMAS_SHIFT (8U) +#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK) +#define SDHC_PROCTL_SABGREQ_MASK (0x10000U) +#define SDHC_PROCTL_SABGREQ_SHIFT (16U) +#define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK) +#define SDHC_PROCTL_CREQ_MASK (0x20000U) +#define SDHC_PROCTL_CREQ_SHIFT (17U) +#define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK) +#define SDHC_PROCTL_RWCTL_MASK (0x40000U) +#define SDHC_PROCTL_RWCTL_SHIFT (18U) +#define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK) +#define SDHC_PROCTL_IABG_MASK (0x80000U) +#define SDHC_PROCTL_IABG_SHIFT (19U) +#define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK) +#define SDHC_PROCTL_WECINT_MASK (0x1000000U) +#define SDHC_PROCTL_WECINT_SHIFT (24U) +#define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK) +#define SDHC_PROCTL_WECINS_MASK (0x2000000U) +#define SDHC_PROCTL_WECINS_SHIFT (25U) +#define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK) +#define SDHC_PROCTL_WECRM_MASK (0x4000000U) +#define SDHC_PROCTL_WECRM_SHIFT (26U) +#define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK) + +/*! @name SYSCTL - System Control register */ +#define SDHC_SYSCTL_IPGEN_MASK (0x1U) +#define SDHC_SYSCTL_IPGEN_SHIFT (0U) +#define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK) +#define SDHC_SYSCTL_HCKEN_MASK (0x2U) +#define SDHC_SYSCTL_HCKEN_SHIFT (1U) +#define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK) +#define SDHC_SYSCTL_PEREN_MASK (0x4U) +#define SDHC_SYSCTL_PEREN_SHIFT (2U) +#define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK) +#define SDHC_SYSCTL_SDCLKEN_MASK (0x8U) +#define SDHC_SYSCTL_SDCLKEN_SHIFT (3U) +#define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK) +#define SDHC_SYSCTL_DVS_MASK (0xF0U) +#define SDHC_SYSCTL_DVS_SHIFT (4U) +#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK) +#define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U) +#define SDHC_SYSCTL_SDCLKFS_SHIFT (8U) +#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK) +#define SDHC_SYSCTL_DTOCV_MASK (0xF0000U) +#define SDHC_SYSCTL_DTOCV_SHIFT (16U) +#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK) +#define SDHC_SYSCTL_RSTA_MASK (0x1000000U) +#define SDHC_SYSCTL_RSTA_SHIFT (24U) +#define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK) +#define SDHC_SYSCTL_RSTC_MASK (0x2000000U) +#define SDHC_SYSCTL_RSTC_SHIFT (25U) +#define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK) +#define SDHC_SYSCTL_RSTD_MASK (0x4000000U) +#define SDHC_SYSCTL_RSTD_SHIFT (26U) +#define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK) +#define SDHC_SYSCTL_INITA_MASK (0x8000000U) +#define SDHC_SYSCTL_INITA_SHIFT (27U) +#define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK) + +/*! @name IRQSTAT - Interrupt Status register */ +#define SDHC_IRQSTAT_CC_MASK (0x1U) +#define SDHC_IRQSTAT_CC_SHIFT (0U) +#define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK) +#define SDHC_IRQSTAT_TC_MASK (0x2U) +#define SDHC_IRQSTAT_TC_SHIFT (1U) +#define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK) +#define SDHC_IRQSTAT_BGE_MASK (0x4U) +#define SDHC_IRQSTAT_BGE_SHIFT (2U) +#define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK) +#define SDHC_IRQSTAT_DINT_MASK (0x8U) +#define SDHC_IRQSTAT_DINT_SHIFT (3U) +#define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK) +#define SDHC_IRQSTAT_BWR_MASK (0x10U) +#define SDHC_IRQSTAT_BWR_SHIFT (4U) +#define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK) +#define SDHC_IRQSTAT_BRR_MASK (0x20U) +#define SDHC_IRQSTAT_BRR_SHIFT (5U) +#define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK) +#define SDHC_IRQSTAT_CINS_MASK (0x40U) +#define SDHC_IRQSTAT_CINS_SHIFT (6U) +#define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK) +#define SDHC_IRQSTAT_CRM_MASK (0x80U) +#define SDHC_IRQSTAT_CRM_SHIFT (7U) +#define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK) +#define SDHC_IRQSTAT_CINT_MASK (0x100U) +#define SDHC_IRQSTAT_CINT_SHIFT (8U) +#define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK) +#define SDHC_IRQSTAT_CTOE_MASK (0x10000U) +#define SDHC_IRQSTAT_CTOE_SHIFT (16U) +#define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK) +#define SDHC_IRQSTAT_CCE_MASK (0x20000U) +#define SDHC_IRQSTAT_CCE_SHIFT (17U) +#define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK) +#define SDHC_IRQSTAT_CEBE_MASK (0x40000U) +#define SDHC_IRQSTAT_CEBE_SHIFT (18U) +#define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK) +#define SDHC_IRQSTAT_CIE_MASK (0x80000U) +#define SDHC_IRQSTAT_CIE_SHIFT (19U) +#define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK) +#define SDHC_IRQSTAT_DTOE_MASK (0x100000U) +#define SDHC_IRQSTAT_DTOE_SHIFT (20U) +#define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK) +#define SDHC_IRQSTAT_DCE_MASK (0x200000U) +#define SDHC_IRQSTAT_DCE_SHIFT (21U) +#define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK) +#define SDHC_IRQSTAT_DEBE_MASK (0x400000U) +#define SDHC_IRQSTAT_DEBE_SHIFT (22U) +#define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK) +#define SDHC_IRQSTAT_AC12E_MASK (0x1000000U) +#define SDHC_IRQSTAT_AC12E_SHIFT (24U) +#define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK) +#define SDHC_IRQSTAT_DMAE_MASK (0x10000000U) +#define SDHC_IRQSTAT_DMAE_SHIFT (28U) +#define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK) + +/*! @name IRQSTATEN - Interrupt Status Enable register */ +#define SDHC_IRQSTATEN_CCSEN_MASK (0x1U) +#define SDHC_IRQSTATEN_CCSEN_SHIFT (0U) +#define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK) +#define SDHC_IRQSTATEN_TCSEN_MASK (0x2U) +#define SDHC_IRQSTATEN_TCSEN_SHIFT (1U) +#define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK) +#define SDHC_IRQSTATEN_BGESEN_MASK (0x4U) +#define SDHC_IRQSTATEN_BGESEN_SHIFT (2U) +#define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK) +#define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U) +#define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U) +#define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK) +#define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U) +#define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U) +#define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK) +#define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U) +#define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U) +#define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK) +#define SDHC_IRQSTATEN_CINSEN_MASK (0x40U) +#define SDHC_IRQSTATEN_CINSEN_SHIFT (6U) +#define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK) +#define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U) +#define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U) +#define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK) +#define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U) +#define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U) +#define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK) +#define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U) +#define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U) +#define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK) +#define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U) +#define SDHC_IRQSTATEN_CCESEN_SHIFT (17U) +#define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK) +#define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U) +#define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U) +#define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK) +#define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U) +#define SDHC_IRQSTATEN_CIESEN_SHIFT (19U) +#define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK) +#define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U) +#define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U) +#define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK) +#define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U) +#define SDHC_IRQSTATEN_DCESEN_SHIFT (21U) +#define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK) +#define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U) +#define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U) +#define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK) +#define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U) +#define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U) +#define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK) +#define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U) +#define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U) +#define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK) + +/*! @name IRQSIGEN - Interrupt Signal Enable register */ +#define SDHC_IRQSIGEN_CCIEN_MASK (0x1U) +#define SDHC_IRQSIGEN_CCIEN_SHIFT (0U) +#define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK) +#define SDHC_IRQSIGEN_TCIEN_MASK (0x2U) +#define SDHC_IRQSIGEN_TCIEN_SHIFT (1U) +#define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK) +#define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U) +#define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U) +#define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK) +#define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U) +#define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U) +#define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK) +#define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U) +#define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U) +#define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK) +#define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U) +#define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U) +#define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK) +#define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U) +#define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U) +#define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK) +#define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U) +#define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U) +#define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK) +#define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U) +#define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U) +#define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK) +#define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U) +#define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U) +#define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK) +#define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U) +#define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U) +#define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK) +#define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U) +#define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U) +#define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK) +#define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U) +#define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U) +#define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK) +#define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U) +#define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U) +#define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK) +#define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U) +#define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U) +#define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK) +#define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U) +#define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U) +#define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK) +#define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U) +#define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U) +#define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK) +#define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U) +#define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U) +#define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK) + +/*! @name AC12ERR - Auto CMD12 Error Status Register */ +#define SDHC_AC12ERR_AC12NE_MASK (0x1U) +#define SDHC_AC12ERR_AC12NE_SHIFT (0U) +#define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK) +#define SDHC_AC12ERR_AC12TOE_MASK (0x2U) +#define SDHC_AC12ERR_AC12TOE_SHIFT (1U) +#define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK) +#define SDHC_AC12ERR_AC12EBE_MASK (0x4U) +#define SDHC_AC12ERR_AC12EBE_SHIFT (2U) +#define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK) +#define SDHC_AC12ERR_AC12CE_MASK (0x8U) +#define SDHC_AC12ERR_AC12CE_SHIFT (3U) +#define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK) +#define SDHC_AC12ERR_AC12IE_MASK (0x10U) +#define SDHC_AC12ERR_AC12IE_SHIFT (4U) +#define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK) +#define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U) +#define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U) +#define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK) + +/*! @name HTCAPBLT - Host Controller Capabilities */ +#define SDHC_HTCAPBLT_MBL_MASK (0x70000U) +#define SDHC_HTCAPBLT_MBL_SHIFT (16U) +#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK) +#define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U) +#define SDHC_HTCAPBLT_ADMAS_SHIFT (20U) +#define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK) +#define SDHC_HTCAPBLT_HSS_MASK (0x200000U) +#define SDHC_HTCAPBLT_HSS_SHIFT (21U) +#define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK) +#define SDHC_HTCAPBLT_DMAS_MASK (0x400000U) +#define SDHC_HTCAPBLT_DMAS_SHIFT (22U) +#define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK) +#define SDHC_HTCAPBLT_SRS_MASK (0x800000U) +#define SDHC_HTCAPBLT_SRS_SHIFT (23U) +#define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK) +#define SDHC_HTCAPBLT_VS33_MASK (0x1000000U) +#define SDHC_HTCAPBLT_VS33_SHIFT (24U) +#define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK) + +/*! @name WML - Watermark Level Register */ +#define SDHC_WML_RDWML_MASK (0xFFU) +#define SDHC_WML_RDWML_SHIFT (0U) +#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK) +#define SDHC_WML_WRWML_MASK (0xFF0000U) +#define SDHC_WML_WRWML_SHIFT (16U) +#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK) + +/*! @name FEVT - Force Event register */ +#define SDHC_FEVT_AC12NE_MASK (0x1U) +#define SDHC_FEVT_AC12NE_SHIFT (0U) +#define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK) +#define SDHC_FEVT_AC12TOE_MASK (0x2U) +#define SDHC_FEVT_AC12TOE_SHIFT (1U) +#define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK) +#define SDHC_FEVT_AC12CE_MASK (0x4U) +#define SDHC_FEVT_AC12CE_SHIFT (2U) +#define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK) +#define SDHC_FEVT_AC12EBE_MASK (0x8U) +#define SDHC_FEVT_AC12EBE_SHIFT (3U) +#define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK) +#define SDHC_FEVT_AC12IE_MASK (0x10U) +#define SDHC_FEVT_AC12IE_SHIFT (4U) +#define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK) +#define SDHC_FEVT_CNIBAC12E_MASK (0x80U) +#define SDHC_FEVT_CNIBAC12E_SHIFT (7U) +#define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK) +#define SDHC_FEVT_CTOE_MASK (0x10000U) +#define SDHC_FEVT_CTOE_SHIFT (16U) +#define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK) +#define SDHC_FEVT_CCE_MASK (0x20000U) +#define SDHC_FEVT_CCE_SHIFT (17U) +#define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK) +#define SDHC_FEVT_CEBE_MASK (0x40000U) +#define SDHC_FEVT_CEBE_SHIFT (18U) +#define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK) +#define SDHC_FEVT_CIE_MASK (0x80000U) +#define SDHC_FEVT_CIE_SHIFT (19U) +#define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK) +#define SDHC_FEVT_DTOE_MASK (0x100000U) +#define SDHC_FEVT_DTOE_SHIFT (20U) +#define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK) +#define SDHC_FEVT_DCE_MASK (0x200000U) +#define SDHC_FEVT_DCE_SHIFT (21U) +#define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK) +#define SDHC_FEVT_DEBE_MASK (0x400000U) +#define SDHC_FEVT_DEBE_SHIFT (22U) +#define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK) +#define SDHC_FEVT_AC12E_MASK (0x1000000U) +#define SDHC_FEVT_AC12E_SHIFT (24U) +#define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK) +#define SDHC_FEVT_DMAE_MASK (0x10000000U) +#define SDHC_FEVT_DMAE_SHIFT (28U) +#define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK) +#define SDHC_FEVT_CINT_MASK (0x80000000U) +#define SDHC_FEVT_CINT_SHIFT (31U) +#define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK) + +/*! @name ADMAES - ADMA Error Status register */ +#define SDHC_ADMAES_ADMAES_MASK (0x3U) +#define SDHC_ADMAES_ADMAES_SHIFT (0U) +#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK) +#define SDHC_ADMAES_ADMALME_MASK (0x4U) +#define SDHC_ADMAES_ADMALME_SHIFT (2U) +#define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK) +#define SDHC_ADMAES_ADMADCE_MASK (0x8U) +#define SDHC_ADMAES_ADMADCE_SHIFT (3U) +#define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK) + +/*! @name ADSADDR - ADMA System Addressregister */ +#define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU) +#define SDHC_ADSADDR_ADSADDR_SHIFT (2U) +#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK) + +/*! @name VENDOR - Vendor Specific register */ +#define SDHC_VENDOR_EXTDMAEN_MASK (0x1U) +#define SDHC_VENDOR_EXTDMAEN_SHIFT (0U) +#define SDHC_VENDOR_EXTDMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK) +#define SDHC_VENDOR_EXBLKNU_MASK (0x2U) +#define SDHC_VENDOR_EXBLKNU_SHIFT (1U) +#define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK) +#define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U) +#define SDHC_VENDOR_INTSTVAL_SHIFT (16U) +#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK) + +/*! @name MMCBOOT - MMC Boot register */ +#define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU) +#define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U) +#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK) +#define SDHC_MMCBOOT_BOOTACK_MASK (0x10U) +#define SDHC_MMCBOOT_BOOTACK_SHIFT (4U) +#define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK) +#define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U) +#define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U) +#define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK) +#define SDHC_MMCBOOT_BOOTEN_MASK (0x40U) +#define SDHC_MMCBOOT_BOOTEN_SHIFT (6U) +#define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK) +#define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U) +#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U) +#define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK) +#define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U) +#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U) +#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK) + +/*! @name HOSTVER - Host Controller Version */ +#define SDHC_HOSTVER_SVN_MASK (0xFFU) +#define SDHC_HOSTVER_SVN_SHIFT (0U) +#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK) +#define SDHC_HOSTVER_VVN_MASK (0xFF00U) +#define SDHC_HOSTVER_VVN_SHIFT (8U) +#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK) + + +/*! + * @} + */ /* end of group SDHC_Register_Masks */ + + +/* SDHC - Peripheral instance base addresses */ +/** Peripheral SDHC base address */ +#define SDHC_BASE (0x400B1000u) +/** Peripheral SDHC base pointer */ +#define SDHC ((SDHC_Type *)SDHC_BASE) +/** Array initializer of SDHC peripheral base addresses */ +#define SDHC_BASE_ADDRS { SDHC_BASE } +/** Array initializer of SDHC peripheral base pointers */ +#define SDHC_BASE_PTRS { SDHC } +/** Interrupt vectors for the SDHC peripheral type */ +#define SDHC_IRQS { SDHC_IRQn } + +/*! + * @} + */ /* end of group SDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer + * @{ + */ + +/** SIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ + __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ + uint8_t RESERVED_0[4092]; + __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ + __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ + uint8_t RESERVED_3[8]; + __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ + __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */ + __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */ + __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */ + __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ + __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ + __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ + __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ + __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ + __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */ + __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ + __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ + __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ + __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ + __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ + __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ +} SIM_Type; + +/* ---------------------------------------------------------------------------- + -- SIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Register_Masks SIM Register Masks + * @{ + */ + +/*! @name SOPT1 - System Options Register 1 */ +#define SIM_SOPT1_RAMSIZE_MASK (0xF000U) +#define SIM_SOPT1_RAMSIZE_SHIFT (12U) +#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK) +#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) +#define SIM_SOPT1_OSC32KSEL_SHIFT (18U) +#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) +#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U) +#define SIM_SOPT1_USBVSTBY_SHIFT (29U) +#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK) +#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U) +#define SIM_SOPT1_USBSSTBY_SHIFT (30U) +#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK) +#define SIM_SOPT1_USBREGEN_MASK (0x80000000U) +#define SIM_SOPT1_USBREGEN_SHIFT (31U) +#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK) + +/*! @name SOPT1CFG - SOPT1 Configuration Register */ +#define SIM_SOPT1CFG_URWE_MASK (0x1000000U) +#define SIM_SOPT1CFG_URWE_SHIFT (24U) +#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK) +#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U) +#define SIM_SOPT1CFG_UVSWE_SHIFT (25U) +#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK) +#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U) +#define SIM_SOPT1CFG_USSWE_SHIFT (26U) +#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK) + +/*! @name SOPT2 - System Options Register 2 */ +#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U) +#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U) +#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK) +#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U) +#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U) +#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK) +#define SIM_SOPT2_FBSL_MASK (0x300U) +#define SIM_SOPT2_FBSL_SHIFT (8U) +#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK) +#define SIM_SOPT2_PTD7PAD_MASK (0x800U) +#define SIM_SOPT2_PTD7PAD_SHIFT (11U) +#define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK) +#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U) +#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U) +#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK) +#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U) +#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U) +#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK) +#define SIM_SOPT2_USBSRC_MASK (0x40000U) +#define SIM_SOPT2_USBSRC_SHIFT (18U) +#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) +#define SIM_SOPT2_SDHCSRC_MASK (0x30000000U) +#define SIM_SOPT2_SDHCSRC_SHIFT (28U) +#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK) + +/*! @name SOPT4 - System Options Register 4 */ +#define SIM_SOPT4_FTM0FLT0_MASK (0x1U) +#define SIM_SOPT4_FTM0FLT0_SHIFT (0U) +#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK) +#define SIM_SOPT4_FTM0FLT1_MASK (0x2U) +#define SIM_SOPT4_FTM0FLT1_SHIFT (1U) +#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK) +#define SIM_SOPT4_FTM0FLT2_MASK (0x4U) +#define SIM_SOPT4_FTM0FLT2_SHIFT (2U) +#define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK) +#define SIM_SOPT4_FTM1FLT0_MASK (0x10U) +#define SIM_SOPT4_FTM1FLT0_SHIFT (4U) +#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK) +#define SIM_SOPT4_FTM2FLT0_MASK (0x100U) +#define SIM_SOPT4_FTM2FLT0_SHIFT (8U) +#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK) +#define SIM_SOPT4_FTM3FLT0_MASK (0x1000U) +#define SIM_SOPT4_FTM3FLT0_SHIFT (12U) +#define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK) +#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U) +#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U) +#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK) +#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U) +#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U) +#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK) +#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U) +#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U) +#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK) +#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U) +#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U) +#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK) +#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U) +#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U) +#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK) +#define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U) +#define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U) +#define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK) +#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U) +#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U) +#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK) +#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U) +#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U) +#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK) +#define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U) +#define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U) +#define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK) +#define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U) +#define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U) +#define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK) + +/*! @name SOPT5 - System Options Register 5 */ +#define SIM_SOPT5_UART0TXSRC_MASK (0x3U) +#define SIM_SOPT5_UART0TXSRC_SHIFT (0U) +#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK) +#define SIM_SOPT5_UART0RXSRC_MASK (0xCU) +#define SIM_SOPT5_UART0RXSRC_SHIFT (2U) +#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK) +#define SIM_SOPT5_UART1TXSRC_MASK (0x30U) +#define SIM_SOPT5_UART1TXSRC_SHIFT (4U) +#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK) +#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U) +#define SIM_SOPT5_UART1RXSRC_SHIFT (6U) +#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK) + +/*! @name SOPT7 - System Options Register 7 */ +#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) +#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) +#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) +#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) +#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) +#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) +#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U) +#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U) +#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK) +#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U) +#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U) +#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK) +#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U) +#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U) +#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK) +#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U) +#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U) +#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK) + +/*! @name SDID - System Device Identification Register */ +#define SIM_SDID_PINID_MASK (0xFU) +#define SIM_SDID_PINID_SHIFT (0U) +#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) +#define SIM_SDID_FAMID_MASK (0x70U) +#define SIM_SDID_FAMID_SHIFT (4U) +#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) +#define SIM_SDID_DIEID_MASK (0xF80U) +#define SIM_SDID_DIEID_SHIFT (7U) +#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) +#define SIM_SDID_REVID_MASK (0xF000U) +#define SIM_SDID_REVID_SHIFT (12U) +#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) +#define SIM_SDID_SERIESID_MASK (0xF00000U) +#define SIM_SDID_SERIESID_SHIFT (20U) +#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) +#define SIM_SDID_SUBFAMID_MASK (0xF000000U) +#define SIM_SDID_SUBFAMID_SHIFT (24U) +#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) +#define SIM_SDID_FAMILYID_MASK (0xF0000000U) +#define SIM_SDID_FAMILYID_SHIFT (28U) +#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK) + +/*! @name SCGC1 - System Clock Gating Control Register 1 */ +#define SIM_SCGC1_I2C2_MASK (0x40U) +#define SIM_SCGC1_I2C2_SHIFT (6U) +#define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK) +#define SIM_SCGC1_UART4_MASK (0x400U) +#define SIM_SCGC1_UART4_SHIFT (10U) +#define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK) +#define SIM_SCGC1_UART5_MASK (0x800U) +#define SIM_SCGC1_UART5_SHIFT (11U) +#define SIM_SCGC1_UART5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK) + +/*! @name SCGC2 - System Clock Gating Control Register 2 */ +#define SIM_SCGC2_DAC0_MASK (0x1000U) +#define SIM_SCGC2_DAC0_SHIFT (12U) +#define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK) +#define SIM_SCGC2_DAC1_MASK (0x2000U) +#define SIM_SCGC2_DAC1_SHIFT (13U) +#define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK) + +/*! @name SCGC3 - System Clock Gating Control Register 3 */ +#define SIM_SCGC3_RNGA_MASK (0x1U) +#define SIM_SCGC3_RNGA_SHIFT (0U) +#define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK) +#define SIM_SCGC3_SPI2_MASK (0x1000U) +#define SIM_SCGC3_SPI2_SHIFT (12U) +#define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK) +#define SIM_SCGC3_SDHC_MASK (0x20000U) +#define SIM_SCGC3_SDHC_SHIFT (17U) +#define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK) +#define SIM_SCGC3_FTM2_MASK (0x1000000U) +#define SIM_SCGC3_FTM2_SHIFT (24U) +#define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK) +#define SIM_SCGC3_FTM3_MASK (0x2000000U) +#define SIM_SCGC3_FTM3_SHIFT (25U) +#define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK) +#define SIM_SCGC3_ADC1_MASK (0x8000000U) +#define SIM_SCGC3_ADC1_SHIFT (27U) +#define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK) + +/*! @name SCGC4 - System Clock Gating Control Register 4 */ +#define SIM_SCGC4_EWM_MASK (0x2U) +#define SIM_SCGC4_EWM_SHIFT (1U) +#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK) +#define SIM_SCGC4_CMT_MASK (0x4U) +#define SIM_SCGC4_CMT_SHIFT (2U) +#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK) +#define SIM_SCGC4_I2C0_MASK (0x40U) +#define SIM_SCGC4_I2C0_SHIFT (6U) +#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) +#define SIM_SCGC4_I2C1_MASK (0x80U) +#define SIM_SCGC4_I2C1_SHIFT (7U) +#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) +#define SIM_SCGC4_UART0_MASK (0x400U) +#define SIM_SCGC4_UART0_SHIFT (10U) +#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK) +#define SIM_SCGC4_UART1_MASK (0x800U) +#define SIM_SCGC4_UART1_SHIFT (11U) +#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK) +#define SIM_SCGC4_UART2_MASK (0x1000U) +#define SIM_SCGC4_UART2_SHIFT (12U) +#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) +#define SIM_SCGC4_UART3_MASK (0x2000U) +#define SIM_SCGC4_UART3_SHIFT (13U) +#define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK) +#define SIM_SCGC4_USBOTG_MASK (0x40000U) +#define SIM_SCGC4_USBOTG_SHIFT (18U) +#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK) +#define SIM_SCGC4_CMP_MASK (0x80000U) +#define SIM_SCGC4_CMP_SHIFT (19U) +#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) +#define SIM_SCGC4_VREF_MASK (0x100000U) +#define SIM_SCGC4_VREF_SHIFT (20U) +#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) + +/*! @name SCGC5 - System Clock Gating Control Register 5 */ +#define SIM_SCGC5_LPTMR_MASK (0x1U) +#define SIM_SCGC5_LPTMR_SHIFT (0U) +#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK) +#define SIM_SCGC5_PORTA_MASK (0x200U) +#define SIM_SCGC5_PORTA_SHIFT (9U) +#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) +#define SIM_SCGC5_PORTB_MASK (0x400U) +#define SIM_SCGC5_PORTB_SHIFT (10U) +#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) +#define SIM_SCGC5_PORTC_MASK (0x800U) +#define SIM_SCGC5_PORTC_SHIFT (11U) +#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) +#define SIM_SCGC5_PORTD_MASK (0x1000U) +#define SIM_SCGC5_PORTD_SHIFT (12U) +#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) +#define SIM_SCGC5_PORTE_MASK (0x2000U) +#define SIM_SCGC5_PORTE_SHIFT (13U) +#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) + +/*! @name SCGC6 - System Clock Gating Control Register 6 */ +#define SIM_SCGC6_FTF_MASK (0x1U) +#define SIM_SCGC6_FTF_SHIFT (0U) +#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK) +#define SIM_SCGC6_DMAMUX_MASK (0x2U) +#define SIM_SCGC6_DMAMUX_SHIFT (1U) +#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK) +#define SIM_SCGC6_FLEXCAN0_MASK (0x10U) +#define SIM_SCGC6_FLEXCAN0_SHIFT (4U) +#define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK) +#define SIM_SCGC6_RNGA_MASK (0x200U) +#define SIM_SCGC6_RNGA_SHIFT (9U) +#define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK) +#define SIM_SCGC6_SPI0_MASK (0x1000U) +#define SIM_SCGC6_SPI0_SHIFT (12U) +#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK) +#define SIM_SCGC6_SPI1_MASK (0x2000U) +#define SIM_SCGC6_SPI1_SHIFT (13U) +#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK) +#define SIM_SCGC6_I2S_MASK (0x8000U) +#define SIM_SCGC6_I2S_SHIFT (15U) +#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK) +#define SIM_SCGC6_CRC_MASK (0x40000U) +#define SIM_SCGC6_CRC_SHIFT (18U) +#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) +#define SIM_SCGC6_USBDCD_MASK (0x200000U) +#define SIM_SCGC6_USBDCD_SHIFT (21U) +#define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK) +#define SIM_SCGC6_PDB_MASK (0x400000U) +#define SIM_SCGC6_PDB_SHIFT (22U) +#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK) +#define SIM_SCGC6_PIT_MASK (0x800000U) +#define SIM_SCGC6_PIT_SHIFT (23U) +#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK) +#define SIM_SCGC6_FTM0_MASK (0x1000000U) +#define SIM_SCGC6_FTM0_SHIFT (24U) +#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK) +#define SIM_SCGC6_FTM1_MASK (0x2000000U) +#define SIM_SCGC6_FTM1_SHIFT (25U) +#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK) +#define SIM_SCGC6_FTM2_MASK (0x4000000U) +#define SIM_SCGC6_FTM2_SHIFT (26U) +#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK) +#define SIM_SCGC6_ADC0_MASK (0x8000000U) +#define SIM_SCGC6_ADC0_SHIFT (27U) +#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) +#define SIM_SCGC6_RTC_MASK (0x20000000U) +#define SIM_SCGC6_RTC_SHIFT (29U) +#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) +#define SIM_SCGC6_DAC0_MASK (0x80000000U) +#define SIM_SCGC6_DAC0_SHIFT (31U) +#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK) + +/*! @name SCGC7 - System Clock Gating Control Register 7 */ +#define SIM_SCGC7_FLEXBUS_MASK (0x1U) +#define SIM_SCGC7_FLEXBUS_SHIFT (0U) +#define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK) +#define SIM_SCGC7_DMA_MASK (0x2U) +#define SIM_SCGC7_DMA_SHIFT (1U) +#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) +#define SIM_SCGC7_MPU_MASK (0x4U) +#define SIM_SCGC7_MPU_SHIFT (2U) +#define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK) + +/*! @name CLKDIV1 - System Clock Divider Register 1 */ +#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U) +#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) +#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) +#define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U) +#define SIM_CLKDIV1_OUTDIV3_SHIFT (20U) +#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK) +#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U) +#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U) +#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK) +#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) +#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) +#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) + +/*! @name CLKDIV2 - System Clock Divider Register 2 */ +#define SIM_CLKDIV2_USBFRAC_MASK (0x1U) +#define SIM_CLKDIV2_USBFRAC_SHIFT (0U) +#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK) +#define SIM_CLKDIV2_USBDIV_MASK (0xEU) +#define SIM_CLKDIV2_USBDIV_SHIFT (1U) +#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK) + +/*! @name FCFG1 - Flash Configuration Register 1 */ +#define SIM_FCFG1_FLASHDIS_MASK (0x1U) +#define SIM_FCFG1_FLASHDIS_SHIFT (0U) +#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) +#define SIM_FCFG1_FLASHDOZE_MASK (0x2U) +#define SIM_FCFG1_FLASHDOZE_SHIFT (1U) +#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) +#define SIM_FCFG1_DEPART_MASK (0xF00U) +#define SIM_FCFG1_DEPART_SHIFT (8U) +#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK) +#define SIM_FCFG1_EESIZE_MASK (0xF0000U) +#define SIM_FCFG1_EESIZE_SHIFT (16U) +#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK) +#define SIM_FCFG1_PFSIZE_MASK (0xF000000U) +#define SIM_FCFG1_PFSIZE_SHIFT (24U) +#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) +#define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U) +#define SIM_FCFG1_NVMSIZE_SHIFT (28U) +#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK) + +/*! @name FCFG2 - Flash Configuration Register 2 */ +#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U) +#define SIM_FCFG2_MAXADDR1_SHIFT (16U) +#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK) +#define SIM_FCFG2_PFLSH_MASK (0x800000U) +#define SIM_FCFG2_PFLSH_SHIFT (23U) +#define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK) +#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) +#define SIM_FCFG2_MAXADDR0_SHIFT (24U) +#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) + +/*! @name UIDH - Unique Identification Register High */ +#define SIM_UIDH_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDH_UID_SHIFT (0U) +#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK) + +/*! @name UIDMH - Unique Identification Register Mid-High */ +#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDMH_UID_SHIFT (0U) +#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) + +/*! @name UIDML - Unique Identification Register Mid Low */ +#define SIM_UIDML_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDML_UID_SHIFT (0U) +#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) + +/*! @name UIDL - Unique Identification Register Low */ +#define SIM_UIDL_UID_MASK (0xFFFFFFFFU) +#define SIM_UIDL_UID_SHIFT (0U) +#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) + + +/*! + * @} + */ /* end of group SIM_Register_Masks */ + + +/* SIM - Peripheral instance base addresses */ +/** Peripheral SIM base address */ +#define SIM_BASE (0x40047000u) +/** Peripheral SIM base pointer */ +#define SIM ((SIM_Type *)SIM_BASE) +/** Array initializer of SIM peripheral base addresses */ +#define SIM_BASE_ADDRS { SIM_BASE } +/** Array initializer of SIM peripheral base pointers */ +#define SIM_BASE_PTRS { SIM } + +/*! + * @} + */ /* end of group SIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer + * @{ + */ + +/** SMC - Register Layout Typedef */ +typedef struct { + __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ + __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ + __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */ + __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ +} SMC_Type; + +/* ---------------------------------------------------------------------------- + -- SMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMC_Register_Masks SMC Register Masks + * @{ + */ + +/*! @name PMPROT - Power Mode Protection register */ +#define SMC_PMPROT_AVLLS_MASK (0x2U) +#define SMC_PMPROT_AVLLS_SHIFT (1U) +#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) +#define SMC_PMPROT_ALLS_MASK (0x8U) +#define SMC_PMPROT_ALLS_SHIFT (3U) +#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) +#define SMC_PMPROT_AVLP_MASK (0x20U) +#define SMC_PMPROT_AVLP_SHIFT (5U) +#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) + +/*! @name PMCTRL - Power Mode Control register */ +#define SMC_PMCTRL_STOPM_MASK (0x7U) +#define SMC_PMCTRL_STOPM_SHIFT (0U) +#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) +#define SMC_PMCTRL_STOPA_MASK (0x8U) +#define SMC_PMCTRL_STOPA_SHIFT (3U) +#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) +#define SMC_PMCTRL_RUNM_MASK (0x60U) +#define SMC_PMCTRL_RUNM_SHIFT (5U) +#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) +#define SMC_PMCTRL_LPWUI_MASK (0x80U) +#define SMC_PMCTRL_LPWUI_SHIFT (7U) +#define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK) + +/*! @name VLLSCTRL - VLLS Control register */ +#define SMC_VLLSCTRL_VLLSM_MASK (0x7U) +#define SMC_VLLSCTRL_VLLSM_SHIFT (0U) +#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK) +#define SMC_VLLSCTRL_PORPO_MASK (0x20U) +#define SMC_VLLSCTRL_PORPO_SHIFT (5U) +#define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK) + +/*! @name PMSTAT - Power Mode Status register */ +#define SMC_PMSTAT_PMSTAT_MASK (0x7FU) +#define SMC_PMSTAT_PMSTAT_SHIFT (0U) +#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) + + +/*! + * @} + */ /* end of group SMC_Register_Masks */ + + +/* SMC - Peripheral instance base addresses */ +/** Peripheral SMC base address */ +#define SMC_BASE (0x4007E000u) +/** Peripheral SMC base pointer */ +#define SMC ((SMC_Type *)SMC_BASE) +/** Array initializer of SMC peripheral base addresses */ +#define SMC_BASE_ADDRS { SMC_BASE } +/** Array initializer of SMC peripheral base pointers */ +#define SMC_BASE_PTRS { SMC } + +/*! + * @} + */ /* end of group SMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ + __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ + }; + uint8_t RESERVED_1[24]; + __IO uint32_t SR; /**< Status Register, offset: 0x2C */ + __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ + union { /* offset: 0x34 */ + __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ + __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ + }; + __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ + __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */ + __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */ + __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */ + __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */ + uint8_t RESERVED_2[48]; + __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */ + __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */ + __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */ + __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define SPI_MCR_HALT_MASK (0x1U) +#define SPI_MCR_HALT_SHIFT (0U) +#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK) +#define SPI_MCR_SMPL_PT_MASK (0x300U) +#define SPI_MCR_SMPL_PT_SHIFT (8U) +#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK) +#define SPI_MCR_CLR_RXF_MASK (0x400U) +#define SPI_MCR_CLR_RXF_SHIFT (10U) +#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK) +#define SPI_MCR_CLR_TXF_MASK (0x800U) +#define SPI_MCR_CLR_TXF_SHIFT (11U) +#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK) +#define SPI_MCR_DIS_RXF_MASK (0x1000U) +#define SPI_MCR_DIS_RXF_SHIFT (12U) +#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK) +#define SPI_MCR_DIS_TXF_MASK (0x2000U) +#define SPI_MCR_DIS_TXF_SHIFT (13U) +#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK) +#define SPI_MCR_MDIS_MASK (0x4000U) +#define SPI_MCR_MDIS_SHIFT (14U) +#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK) +#define SPI_MCR_DOZE_MASK (0x8000U) +#define SPI_MCR_DOZE_SHIFT (15U) +#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK) +#define SPI_MCR_PCSIS_MASK (0x3F0000U) +#define SPI_MCR_PCSIS_SHIFT (16U) +#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK) +#define SPI_MCR_ROOE_MASK (0x1000000U) +#define SPI_MCR_ROOE_SHIFT (24U) +#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK) +#define SPI_MCR_PCSSE_MASK (0x2000000U) +#define SPI_MCR_PCSSE_SHIFT (25U) +#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK) +#define SPI_MCR_MTFE_MASK (0x4000000U) +#define SPI_MCR_MTFE_SHIFT (26U) +#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK) +#define SPI_MCR_FRZ_MASK (0x8000000U) +#define SPI_MCR_FRZ_SHIFT (27U) +#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK) +#define SPI_MCR_DCONF_MASK (0x30000000U) +#define SPI_MCR_DCONF_SHIFT (28U) +#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK) +#define SPI_MCR_CONT_SCKE_MASK (0x40000000U) +#define SPI_MCR_CONT_SCKE_SHIFT (30U) +#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK) +#define SPI_MCR_MSTR_MASK (0x80000000U) +#define SPI_MCR_MSTR_SHIFT (31U) +#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK) + +/*! @name TCR - Transfer Count Register */ +#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) +#define SPI_TCR_SPI_TCNT_SHIFT (16U) +#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK) + +/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ +#define SPI_CTAR_BR_MASK (0xFU) +#define SPI_CTAR_BR_SHIFT (0U) +#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK) +#define SPI_CTAR_DT_MASK (0xF0U) +#define SPI_CTAR_DT_SHIFT (4U) +#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK) +#define SPI_CTAR_ASC_MASK (0xF00U) +#define SPI_CTAR_ASC_SHIFT (8U) +#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK) +#define SPI_CTAR_CSSCK_MASK (0xF000U) +#define SPI_CTAR_CSSCK_SHIFT (12U) +#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK) +#define SPI_CTAR_PBR_MASK (0x30000U) +#define SPI_CTAR_PBR_SHIFT (16U) +#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK) +#define SPI_CTAR_PDT_MASK (0xC0000U) +#define SPI_CTAR_PDT_SHIFT (18U) +#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK) +#define SPI_CTAR_PASC_MASK (0x300000U) +#define SPI_CTAR_PASC_SHIFT (20U) +#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK) +#define SPI_CTAR_PCSSCK_MASK (0xC00000U) +#define SPI_CTAR_PCSSCK_SHIFT (22U) +#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK) +#define SPI_CTAR_LSBFE_MASK (0x1000000U) +#define SPI_CTAR_LSBFE_SHIFT (24U) +#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK) +#define SPI_CTAR_CPHA_MASK (0x2000000U) +#define SPI_CTAR_CPHA_SHIFT (25U) +#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK) +#define SPI_CTAR_CPOL_MASK (0x4000000U) +#define SPI_CTAR_CPOL_SHIFT (26U) +#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK) +#define SPI_CTAR_FMSZ_MASK (0x78000000U) +#define SPI_CTAR_FMSZ_SHIFT (27U) +#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK) +#define SPI_CTAR_DBR_MASK (0x80000000U) +#define SPI_CTAR_DBR_SHIFT (31U) +#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK) + +/* The count of SPI_CTAR */ +#define SPI_CTAR_COUNT (2U) + +/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */ +#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U) +#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U) +#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK) +#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U) +#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U) +#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK) +#define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U) +#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U) +#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK) + +/* The count of SPI_CTAR_SLAVE */ +#define SPI_CTAR_SLAVE_COUNT (1U) + +/*! @name SR - Status Register */ +#define SPI_SR_POPNXTPTR_MASK (0xFU) +#define SPI_SR_POPNXTPTR_SHIFT (0U) +#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK) +#define SPI_SR_RXCTR_MASK (0xF0U) +#define SPI_SR_RXCTR_SHIFT (4U) +#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK) +#define SPI_SR_TXNXTPTR_MASK (0xF00U) +#define SPI_SR_TXNXTPTR_SHIFT (8U) +#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK) +#define SPI_SR_TXCTR_MASK (0xF000U) +#define SPI_SR_TXCTR_SHIFT (12U) +#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK) +#define SPI_SR_RFDF_MASK (0x20000U) +#define SPI_SR_RFDF_SHIFT (17U) +#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK) +#define SPI_SR_RFOF_MASK (0x80000U) +#define SPI_SR_RFOF_SHIFT (19U) +#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK) +#define SPI_SR_TFFF_MASK (0x2000000U) +#define SPI_SR_TFFF_SHIFT (25U) +#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK) +#define SPI_SR_TFUF_MASK (0x8000000U) +#define SPI_SR_TFUF_SHIFT (27U) +#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK) +#define SPI_SR_EOQF_MASK (0x10000000U) +#define SPI_SR_EOQF_SHIFT (28U) +#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK) +#define SPI_SR_TXRXS_MASK (0x40000000U) +#define SPI_SR_TXRXS_SHIFT (30U) +#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK) +#define SPI_SR_TCF_MASK (0x80000000U) +#define SPI_SR_TCF_SHIFT (31U) +#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK) + +/*! @name RSER - DMA/Interrupt Request Select and Enable Register */ +#define SPI_RSER_RFDF_DIRS_MASK (0x10000U) +#define SPI_RSER_RFDF_DIRS_SHIFT (16U) +#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK) +#define SPI_RSER_RFDF_RE_MASK (0x20000U) +#define SPI_RSER_RFDF_RE_SHIFT (17U) +#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK) +#define SPI_RSER_RFOF_RE_MASK (0x80000U) +#define SPI_RSER_RFOF_RE_SHIFT (19U) +#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK) +#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U) +#define SPI_RSER_TFFF_DIRS_SHIFT (24U) +#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK) +#define SPI_RSER_TFFF_RE_MASK (0x2000000U) +#define SPI_RSER_TFFF_RE_SHIFT (25U) +#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK) +#define SPI_RSER_TFUF_RE_MASK (0x8000000U) +#define SPI_RSER_TFUF_RE_SHIFT (27U) +#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK) +#define SPI_RSER_EOQF_RE_MASK (0x10000000U) +#define SPI_RSER_EOQF_RE_SHIFT (28U) +#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK) +#define SPI_RSER_TCF_RE_MASK (0x80000000U) +#define SPI_RSER_TCF_RE_SHIFT (31U) +#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK) + +/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ +#define SPI_PUSHR_TXDATA_MASK (0xFFFFU) +#define SPI_PUSHR_TXDATA_SHIFT (0U) +#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK) +#define SPI_PUSHR_PCS_MASK (0x3F0000U) +#define SPI_PUSHR_PCS_SHIFT (16U) +#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK) +#define SPI_PUSHR_CTCNT_MASK (0x4000000U) +#define SPI_PUSHR_CTCNT_SHIFT (26U) +#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK) +#define SPI_PUSHR_EOQ_MASK (0x8000000U) +#define SPI_PUSHR_EOQ_SHIFT (27U) +#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK) +#define SPI_PUSHR_CTAS_MASK (0x70000000U) +#define SPI_PUSHR_CTAS_SHIFT (28U) +#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK) +#define SPI_PUSHR_CONT_MASK (0x80000000U) +#define SPI_PUSHR_CONT_SHIFT (31U) +#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK) + +/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */ +#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU) +#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U) +#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK) + +/*! @name POPR - POP RX FIFO Register */ +#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_POPR_RXDATA_SHIFT (0U) +#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK) + +/*! @name TXFR0 - Transmit FIFO Registers */ +#define SPI_TXFR0_TXDATA_MASK (0xFFFFU) +#define SPI_TXFR0_TXDATA_SHIFT (0U) +#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK) +#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U) +#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U) +#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK) + +/*! @name TXFR1 - Transmit FIFO Registers */ +#define SPI_TXFR1_TXDATA_MASK (0xFFFFU) +#define SPI_TXFR1_TXDATA_SHIFT (0U) +#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK) +#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U) +#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U) +#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK) + +/*! @name TXFR2 - Transmit FIFO Registers */ +#define SPI_TXFR2_TXDATA_MASK (0xFFFFU) +#define SPI_TXFR2_TXDATA_SHIFT (0U) +#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK) +#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U) +#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U) +#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK) + +/*! @name TXFR3 - Transmit FIFO Registers */ +#define SPI_TXFR3_TXDATA_MASK (0xFFFFU) +#define SPI_TXFR3_TXDATA_SHIFT (0U) +#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK) +#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U) +#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U) +#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK) + +/*! @name RXFR0 - Receive FIFO Registers */ +#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_RXFR0_RXDATA_SHIFT (0U) +#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK) + +/*! @name RXFR1 - Receive FIFO Registers */ +#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_RXFR1_RXDATA_SHIFT (0U) +#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK) + +/*! @name RXFR2 - Receive FIFO Registers */ +#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_RXFR2_RXDATA_SHIFT (0U) +#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK) + +/*! @name RXFR3 - Receive FIFO Registers */ +#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU) +#define SPI_RXFR3_RXDATA_SHIFT (0U) +#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK) + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +/** Peripheral SPI0 base address */ +#define SPI0_BASE (0x4002C000u) +/** Peripheral SPI0 base pointer */ +#define SPI0 ((SPI_Type *)SPI0_BASE) +/** Peripheral SPI1 base address */ +#define SPI1_BASE (0x4002D000u) +/** Peripheral SPI1 base pointer */ +#define SPI1 ((SPI_Type *)SPI1_BASE) +/** Peripheral SPI2 base address */ +#define SPI2_BASE (0x400AC000u) +/** Peripheral SPI2 base pointer */ +#define SPI2 ((SPI_Type *)SPI2_BASE) +/** Array initializer of SPI peripheral base addresses */ +#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE } +/** Array initializer of SPI peripheral base pointers */ +#define SPI_BASE_PTRS { SPI0, SPI1, SPI2 } +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSMPU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer + * @{ + */ + +/** SYSMPU - Register Layout Typedef */ +typedef struct { + __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + struct { /* offset: 0x10, array step: 0x8 */ + __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */ + __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */ + } SP[5]; + uint8_t RESERVED_1[968]; + __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */ + uint8_t RESERVED_2[832]; + __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */ +} SYSMPU_Type; + +/* ---------------------------------------------------------------------------- + -- SYSMPU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks + * @{ + */ + +/*! @name CESR - Control/Error Status Register */ +#define SYSMPU_CESR_VLD_MASK (0x1U) +#define SYSMPU_CESR_VLD_SHIFT (0U) +#define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK) +#define SYSMPU_CESR_NRGD_MASK (0xF00U) +#define SYSMPU_CESR_NRGD_SHIFT (8U) +#define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK) +#define SYSMPU_CESR_NSP_MASK (0xF000U) +#define SYSMPU_CESR_NSP_SHIFT (12U) +#define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK) +#define SYSMPU_CESR_HRL_MASK (0xF0000U) +#define SYSMPU_CESR_HRL_SHIFT (16U) +#define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK) +#define SYSMPU_CESR_SPERR_MASK (0xF8000000U) +#define SYSMPU_CESR_SPERR_SHIFT (27U) +#define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK) + +/*! @name EAR - Error Address Register, slave port n */ +#define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU) +#define SYSMPU_EAR_EADDR_SHIFT (0U) +#define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK) + +/* The count of SYSMPU_EAR */ +#define SYSMPU_EAR_COUNT (5U) + +/*! @name EDR - Error Detail Register, slave port n */ +#define SYSMPU_EDR_ERW_MASK (0x1U) +#define SYSMPU_EDR_ERW_SHIFT (0U) +#define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK) +#define SYSMPU_EDR_EATTR_MASK (0xEU) +#define SYSMPU_EDR_EATTR_SHIFT (1U) +#define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK) +#define SYSMPU_EDR_EMN_MASK (0xF0U) +#define SYSMPU_EDR_EMN_SHIFT (4U) +#define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK) +#define SYSMPU_EDR_EPID_MASK (0xFF00U) +#define SYSMPU_EDR_EPID_SHIFT (8U) +#define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK) +#define SYSMPU_EDR_EACD_MASK (0xFFFF0000U) +#define SYSMPU_EDR_EACD_SHIFT (16U) +#define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK) + +/* The count of SYSMPU_EDR */ +#define SYSMPU_EDR_COUNT (5U) + +/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */ +#define SYSMPU_WORD_VLD_MASK (0x1U) +#define SYSMPU_WORD_VLD_SHIFT (0U) +#define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK) +#define SYSMPU_WORD_M0UM_MASK (0x7U) +#define SYSMPU_WORD_M0UM_SHIFT (0U) +#define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK) +#define SYSMPU_WORD_M0SM_MASK (0x18U) +#define SYSMPU_WORD_M0SM_SHIFT (3U) +#define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK) +#define SYSMPU_WORD_M0PE_MASK (0x20U) +#define SYSMPU_WORD_M0PE_SHIFT (5U) +#define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK) +#define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U) +#define SYSMPU_WORD_ENDADDR_SHIFT (5U) +#define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK) +#define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U) +#define SYSMPU_WORD_SRTADDR_SHIFT (5U) +#define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK) +#define SYSMPU_WORD_M1UM_MASK (0x1C0U) +#define SYSMPU_WORD_M1UM_SHIFT (6U) +#define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK) +#define SYSMPU_WORD_M1SM_MASK (0x600U) +#define SYSMPU_WORD_M1SM_SHIFT (9U) +#define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK) +#define SYSMPU_WORD_M1PE_MASK (0x800U) +#define SYSMPU_WORD_M1PE_SHIFT (11U) +#define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK) +#define SYSMPU_WORD_M2UM_MASK (0x7000U) +#define SYSMPU_WORD_M2UM_SHIFT (12U) +#define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK) +#define SYSMPU_WORD_M2SM_MASK (0x18000U) +#define SYSMPU_WORD_M2SM_SHIFT (15U) +#define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK) +#define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U) +#define SYSMPU_WORD_PIDMASK_SHIFT (16U) +#define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK) +#define SYSMPU_WORD_M2PE_MASK (0x20000U) +#define SYSMPU_WORD_M2PE_SHIFT (17U) +#define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK) +#define SYSMPU_WORD_M3UM_MASK (0x1C0000U) +#define SYSMPU_WORD_M3UM_SHIFT (18U) +#define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK) +#define SYSMPU_WORD_M3SM_MASK (0x600000U) +#define SYSMPU_WORD_M3SM_SHIFT (21U) +#define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK) +#define SYSMPU_WORD_M3PE_MASK (0x800000U) +#define SYSMPU_WORD_M3PE_SHIFT (23U) +#define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK) +#define SYSMPU_WORD_PID_MASK (0xFF000000U) +#define SYSMPU_WORD_PID_SHIFT (24U) +#define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK) +#define SYSMPU_WORD_M4WE_MASK (0x1000000U) +#define SYSMPU_WORD_M4WE_SHIFT (24U) +#define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK) +#define SYSMPU_WORD_M4RE_MASK (0x2000000U) +#define SYSMPU_WORD_M4RE_SHIFT (25U) +#define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK) +#define SYSMPU_WORD_M5WE_MASK (0x4000000U) +#define SYSMPU_WORD_M5WE_SHIFT (26U) +#define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK) +#define SYSMPU_WORD_M5RE_MASK (0x8000000U) +#define SYSMPU_WORD_M5RE_SHIFT (27U) +#define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK) +#define SYSMPU_WORD_M6WE_MASK (0x10000000U) +#define SYSMPU_WORD_M6WE_SHIFT (28U) +#define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK) +#define SYSMPU_WORD_M6RE_MASK (0x20000000U) +#define SYSMPU_WORD_M6RE_SHIFT (29U) +#define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK) +#define SYSMPU_WORD_M7WE_MASK (0x40000000U) +#define SYSMPU_WORD_M7WE_SHIFT (30U) +#define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK) +#define SYSMPU_WORD_M7RE_MASK (0x80000000U) +#define SYSMPU_WORD_M7RE_SHIFT (31U) +#define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK) + +/* The count of SYSMPU_WORD */ +#define SYSMPU_WORD_COUNT (12U) + +/* The count of SYSMPU_WORD */ +#define SYSMPU_WORD_COUNT2 (4U) + +/*! @name RGDAAC - Region Descriptor Alternate Access Control n */ +#define SYSMPU_RGDAAC_M0UM_MASK (0x7U) +#define SYSMPU_RGDAAC_M0UM_SHIFT (0U) +#define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK) +#define SYSMPU_RGDAAC_M0SM_MASK (0x18U) +#define SYSMPU_RGDAAC_M0SM_SHIFT (3U) +#define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK) +#define SYSMPU_RGDAAC_M0PE_MASK (0x20U) +#define SYSMPU_RGDAAC_M0PE_SHIFT (5U) +#define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK) +#define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U) +#define SYSMPU_RGDAAC_M1UM_SHIFT (6U) +#define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK) +#define SYSMPU_RGDAAC_M1SM_MASK (0x600U) +#define SYSMPU_RGDAAC_M1SM_SHIFT (9U) +#define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK) +#define SYSMPU_RGDAAC_M1PE_MASK (0x800U) +#define SYSMPU_RGDAAC_M1PE_SHIFT (11U) +#define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK) +#define SYSMPU_RGDAAC_M2UM_MASK (0x7000U) +#define SYSMPU_RGDAAC_M2UM_SHIFT (12U) +#define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK) +#define SYSMPU_RGDAAC_M2SM_MASK (0x18000U) +#define SYSMPU_RGDAAC_M2SM_SHIFT (15U) +#define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK) +#define SYSMPU_RGDAAC_M2PE_MASK (0x20000U) +#define SYSMPU_RGDAAC_M2PE_SHIFT (17U) +#define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK) +#define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U) +#define SYSMPU_RGDAAC_M3UM_SHIFT (18U) +#define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK) +#define SYSMPU_RGDAAC_M3SM_MASK (0x600000U) +#define SYSMPU_RGDAAC_M3SM_SHIFT (21U) +#define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK) +#define SYSMPU_RGDAAC_M3PE_MASK (0x800000U) +#define SYSMPU_RGDAAC_M3PE_SHIFT (23U) +#define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK) +#define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U) +#define SYSMPU_RGDAAC_M4WE_SHIFT (24U) +#define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK) +#define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U) +#define SYSMPU_RGDAAC_M4RE_SHIFT (25U) +#define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK) +#define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U) +#define SYSMPU_RGDAAC_M5WE_SHIFT (26U) +#define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK) +#define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U) +#define SYSMPU_RGDAAC_M5RE_SHIFT (27U) +#define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK) +#define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U) +#define SYSMPU_RGDAAC_M6WE_SHIFT (28U) +#define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK) +#define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U) +#define SYSMPU_RGDAAC_M6RE_SHIFT (29U) +#define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK) +#define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U) +#define SYSMPU_RGDAAC_M7WE_SHIFT (30U) +#define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK) +#define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U) +#define SYSMPU_RGDAAC_M7RE_SHIFT (31U) +#define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK) + +/* The count of SYSMPU_RGDAAC */ +#define SYSMPU_RGDAAC_COUNT (12U) + + +/*! + * @} + */ /* end of group SYSMPU_Register_Masks */ + + +/* SYSMPU - Peripheral instance base addresses */ +/** Peripheral SYSMPU base address */ +#define SYSMPU_BASE (0x4000D000u) +/** Peripheral SYSMPU base pointer */ +#define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE) +/** Array initializer of SYSMPU peripheral base addresses */ +#define SYSMPU_BASE_ADDRS { SYSMPU_BASE } +/** Array initializer of SYSMPU peripheral base pointers */ +#define SYSMPU_BASE_PTRS { SYSMPU } + +/*! + * @} + */ /* end of group SYSMPU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/** UART - Register Layout Typedef */ +typedef struct { + __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ + __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ + __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ + __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ + __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ + __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ + __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ + __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ + __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ + __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ + __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ + __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ + __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ + __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ + __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */ + uint8_t RESERVED_0[1]; + __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ + __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ + __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ + __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ + __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ + __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ + __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ + uint8_t RESERVED_1[1]; + __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ + __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ + __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ + union { /* offset: 0x1B */ + __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ + __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ + }; + __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ + __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ + __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ + __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ +} UART_Type; + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/*! @name BDH - UART Baud Rate Registers: High */ +#define UART_BDH_SBR_MASK (0x1FU) +#define UART_BDH_SBR_SHIFT (0U) +#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) +#define UART_BDH_SBNS_MASK (0x20U) +#define UART_BDH_SBNS_SHIFT (5U) +#define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK) +#define UART_BDH_RXEDGIE_MASK (0x40U) +#define UART_BDH_RXEDGIE_SHIFT (6U) +#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) +#define UART_BDH_LBKDIE_MASK (0x80U) +#define UART_BDH_LBKDIE_SHIFT (7U) +#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) + +/*! @name BDL - UART Baud Rate Registers: Low */ +#define UART_BDL_SBR_MASK (0xFFU) +#define UART_BDL_SBR_SHIFT (0U) +#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) + +/*! @name C1 - UART Control Register 1 */ +#define UART_C1_PT_MASK (0x1U) +#define UART_C1_PT_SHIFT (0U) +#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) +#define UART_C1_PE_MASK (0x2U) +#define UART_C1_PE_SHIFT (1U) +#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) +#define UART_C1_ILT_MASK (0x4U) +#define UART_C1_ILT_SHIFT (2U) +#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) +#define UART_C1_WAKE_MASK (0x8U) +#define UART_C1_WAKE_SHIFT (3U) +#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) +#define UART_C1_M_MASK (0x10U) +#define UART_C1_M_SHIFT (4U) +#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) +#define UART_C1_RSRC_MASK (0x20U) +#define UART_C1_RSRC_SHIFT (5U) +#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) +#define UART_C1_UARTSWAI_MASK (0x40U) +#define UART_C1_UARTSWAI_SHIFT (6U) +#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) +#define UART_C1_LOOPS_MASK (0x80U) +#define UART_C1_LOOPS_SHIFT (7U) +#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) + +/*! @name C2 - UART Control Register 2 */ +#define UART_C2_SBK_MASK (0x1U) +#define UART_C2_SBK_SHIFT (0U) +#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) +#define UART_C2_RWU_MASK (0x2U) +#define UART_C2_RWU_SHIFT (1U) +#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) +#define UART_C2_RE_MASK (0x4U) +#define UART_C2_RE_SHIFT (2U) +#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) +#define UART_C2_TE_MASK (0x8U) +#define UART_C2_TE_SHIFT (3U) +#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) +#define UART_C2_ILIE_MASK (0x10U) +#define UART_C2_ILIE_SHIFT (4U) +#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) +#define UART_C2_RIE_MASK (0x20U) +#define UART_C2_RIE_SHIFT (5U) +#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) +#define UART_C2_TCIE_MASK (0x40U) +#define UART_C2_TCIE_SHIFT (6U) +#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) +#define UART_C2_TIE_MASK (0x80U) +#define UART_C2_TIE_SHIFT (7U) +#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) + +/*! @name S1 - UART Status Register 1 */ +#define UART_S1_PF_MASK (0x1U) +#define UART_S1_PF_SHIFT (0U) +#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) +#define UART_S1_FE_MASK (0x2U) +#define UART_S1_FE_SHIFT (1U) +#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) +#define UART_S1_NF_MASK (0x4U) +#define UART_S1_NF_SHIFT (2U) +#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) +#define UART_S1_OR_MASK (0x8U) +#define UART_S1_OR_SHIFT (3U) +#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) +#define UART_S1_IDLE_MASK (0x10U) +#define UART_S1_IDLE_SHIFT (4U) +#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) +#define UART_S1_RDRF_MASK (0x20U) +#define UART_S1_RDRF_SHIFT (5U) +#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) +#define UART_S1_TC_MASK (0x40U) +#define UART_S1_TC_SHIFT (6U) +#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) +#define UART_S1_TDRE_MASK (0x80U) +#define UART_S1_TDRE_SHIFT (7U) +#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) + +/*! @name S2 - UART Status Register 2 */ +#define UART_S2_RAF_MASK (0x1U) +#define UART_S2_RAF_SHIFT (0U) +#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) +#define UART_S2_LBKDE_MASK (0x2U) +#define UART_S2_LBKDE_SHIFT (1U) +#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) +#define UART_S2_BRK13_MASK (0x4U) +#define UART_S2_BRK13_SHIFT (2U) +#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) +#define UART_S2_RWUID_MASK (0x8U) +#define UART_S2_RWUID_SHIFT (3U) +#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) +#define UART_S2_RXINV_MASK (0x10U) +#define UART_S2_RXINV_SHIFT (4U) +#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) +#define UART_S2_MSBF_MASK (0x20U) +#define UART_S2_MSBF_SHIFT (5U) +#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK) +#define UART_S2_RXEDGIF_MASK (0x40U) +#define UART_S2_RXEDGIF_SHIFT (6U) +#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) +#define UART_S2_LBKDIF_MASK (0x80U) +#define UART_S2_LBKDIF_SHIFT (7U) +#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) + +/*! @name C3 - UART Control Register 3 */ +#define UART_C3_PEIE_MASK (0x1U) +#define UART_C3_PEIE_SHIFT (0U) +#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) +#define UART_C3_FEIE_MASK (0x2U) +#define UART_C3_FEIE_SHIFT (1U) +#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) +#define UART_C3_NEIE_MASK (0x4U) +#define UART_C3_NEIE_SHIFT (2U) +#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) +#define UART_C3_ORIE_MASK (0x8U) +#define UART_C3_ORIE_SHIFT (3U) +#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) +#define UART_C3_TXINV_MASK (0x10U) +#define UART_C3_TXINV_SHIFT (4U) +#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) +#define UART_C3_TXDIR_MASK (0x20U) +#define UART_C3_TXDIR_SHIFT (5U) +#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) +#define UART_C3_T8_MASK (0x40U) +#define UART_C3_T8_SHIFT (6U) +#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) +#define UART_C3_R8_MASK (0x80U) +#define UART_C3_R8_SHIFT (7U) +#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) + +/*! @name D - UART Data Register */ +#define UART_D_RT_MASK (0xFFU) +#define UART_D_RT_SHIFT (0U) +#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK) + +/*! @name MA1 - UART Match Address Registers 1 */ +#define UART_MA1_MA_MASK (0xFFU) +#define UART_MA1_MA_SHIFT (0U) +#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK) + +/*! @name MA2 - UART Match Address Registers 2 */ +#define UART_MA2_MA_MASK (0xFFU) +#define UART_MA2_MA_SHIFT (0U) +#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK) + +/*! @name C4 - UART Control Register 4 */ +#define UART_C4_BRFA_MASK (0x1FU) +#define UART_C4_BRFA_SHIFT (0U) +#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK) +#define UART_C4_M10_MASK (0x20U) +#define UART_C4_M10_SHIFT (5U) +#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK) +#define UART_C4_MAEN2_MASK (0x40U) +#define UART_C4_MAEN2_SHIFT (6U) +#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK) +#define UART_C4_MAEN1_MASK (0x80U) +#define UART_C4_MAEN1_SHIFT (7U) +#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK) + +/*! @name C5 - UART Control Register 5 */ +#define UART_C5_LBKDDMAS_MASK (0x8U) +#define UART_C5_LBKDDMAS_SHIFT (3U) +#define UART_C5_LBKDDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_LBKDDMAS_SHIFT)) & UART_C5_LBKDDMAS_MASK) +#define UART_C5_ILDMAS_MASK (0x10U) +#define UART_C5_ILDMAS_SHIFT (4U) +#define UART_C5_ILDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_ILDMAS_SHIFT)) & UART_C5_ILDMAS_MASK) +#define UART_C5_RDMAS_MASK (0x20U) +#define UART_C5_RDMAS_SHIFT (5U) +#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK) +#define UART_C5_TCDMAS_MASK (0x40U) +#define UART_C5_TCDMAS_SHIFT (6U) +#define UART_C5_TCDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TCDMAS_SHIFT)) & UART_C5_TCDMAS_MASK) +#define UART_C5_TDMAS_MASK (0x80U) +#define UART_C5_TDMAS_SHIFT (7U) +#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK) + +/*! @name ED - UART Extended Data Register */ +#define UART_ED_PARITYE_MASK (0x40U) +#define UART_ED_PARITYE_SHIFT (6U) +#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK) +#define UART_ED_NOISY_MASK (0x80U) +#define UART_ED_NOISY_SHIFT (7U) +#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK) + +/*! @name MODEM - UART Modem Register */ +#define UART_MODEM_TXCTSE_MASK (0x1U) +#define UART_MODEM_TXCTSE_SHIFT (0U) +#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK) +#define UART_MODEM_TXRTSE_MASK (0x2U) +#define UART_MODEM_TXRTSE_SHIFT (1U) +#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK) +#define UART_MODEM_TXRTSPOL_MASK (0x4U) +#define UART_MODEM_TXRTSPOL_SHIFT (2U) +#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK) +#define UART_MODEM_RXRTSE_MASK (0x8U) +#define UART_MODEM_RXRTSE_SHIFT (3U) +#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK) + +/*! @name IR - UART Infrared Register */ +#define UART_IR_TNP_MASK (0x3U) +#define UART_IR_TNP_SHIFT (0U) +#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK) +#define UART_IR_IREN_MASK (0x4U) +#define UART_IR_IREN_SHIFT (2U) +#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK) + +/*! @name PFIFO - UART FIFO Parameters */ +#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U) +#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U) +#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK) +#define UART_PFIFO_RXFE_MASK (0x8U) +#define UART_PFIFO_RXFE_SHIFT (3U) +#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK) +#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U) +#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U) +#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK) +#define UART_PFIFO_TXFE_MASK (0x80U) +#define UART_PFIFO_TXFE_SHIFT (7U) +#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK) + +/*! @name CFIFO - UART FIFO Control Register */ +#define UART_CFIFO_RXUFE_MASK (0x1U) +#define UART_CFIFO_RXUFE_SHIFT (0U) +#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK) +#define UART_CFIFO_TXOFE_MASK (0x2U) +#define UART_CFIFO_TXOFE_SHIFT (1U) +#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK) +#define UART_CFIFO_RXOFE_MASK (0x4U) +#define UART_CFIFO_RXOFE_SHIFT (2U) +#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK) +#define UART_CFIFO_RXFLUSH_MASK (0x40U) +#define UART_CFIFO_RXFLUSH_SHIFT (6U) +#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK) +#define UART_CFIFO_TXFLUSH_MASK (0x80U) +#define UART_CFIFO_TXFLUSH_SHIFT (7U) +#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK) + +/*! @name SFIFO - UART FIFO Status Register */ +#define UART_SFIFO_RXUF_MASK (0x1U) +#define UART_SFIFO_RXUF_SHIFT (0U) +#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK) +#define UART_SFIFO_TXOF_MASK (0x2U) +#define UART_SFIFO_TXOF_SHIFT (1U) +#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK) +#define UART_SFIFO_RXOF_MASK (0x4U) +#define UART_SFIFO_RXOF_SHIFT (2U) +#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK) +#define UART_SFIFO_RXEMPT_MASK (0x40U) +#define UART_SFIFO_RXEMPT_SHIFT (6U) +#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK) +#define UART_SFIFO_TXEMPT_MASK (0x80U) +#define UART_SFIFO_TXEMPT_SHIFT (7U) +#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK) + +/*! @name TWFIFO - UART FIFO Transmit Watermark */ +#define UART_TWFIFO_TXWATER_MASK (0xFFU) +#define UART_TWFIFO_TXWATER_SHIFT (0U) +#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK) + +/*! @name TCFIFO - UART FIFO Transmit Count */ +#define UART_TCFIFO_TXCOUNT_MASK (0xFFU) +#define UART_TCFIFO_TXCOUNT_SHIFT (0U) +#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK) + +/*! @name RWFIFO - UART FIFO Receive Watermark */ +#define UART_RWFIFO_RXWATER_MASK (0xFFU) +#define UART_RWFIFO_RXWATER_SHIFT (0U) +#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK) + +/*! @name RCFIFO - UART FIFO Receive Count */ +#define UART_RCFIFO_RXCOUNT_MASK (0xFFU) +#define UART_RCFIFO_RXCOUNT_SHIFT (0U) +#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK) + +/*! @name C7816 - UART 7816 Control Register */ +#define UART_C7816_ISO_7816E_MASK (0x1U) +#define UART_C7816_ISO_7816E_SHIFT (0U) +#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK) +#define UART_C7816_TTYPE_MASK (0x2U) +#define UART_C7816_TTYPE_SHIFT (1U) +#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK) +#define UART_C7816_INIT_MASK (0x4U) +#define UART_C7816_INIT_SHIFT (2U) +#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK) +#define UART_C7816_ANACK_MASK (0x8U) +#define UART_C7816_ANACK_SHIFT (3U) +#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK) +#define UART_C7816_ONACK_MASK (0x10U) +#define UART_C7816_ONACK_SHIFT (4U) +#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK) + +/*! @name IE7816 - UART 7816 Interrupt Enable Register */ +#define UART_IE7816_RXTE_MASK (0x1U) +#define UART_IE7816_RXTE_SHIFT (0U) +#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK) +#define UART_IE7816_TXTE_MASK (0x2U) +#define UART_IE7816_TXTE_SHIFT (1U) +#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK) +#define UART_IE7816_GTVE_MASK (0x4U) +#define UART_IE7816_GTVE_SHIFT (2U) +#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK) +#define UART_IE7816_INITDE_MASK (0x10U) +#define UART_IE7816_INITDE_SHIFT (4U) +#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK) +#define UART_IE7816_BWTE_MASK (0x20U) +#define UART_IE7816_BWTE_SHIFT (5U) +#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK) +#define UART_IE7816_CWTE_MASK (0x40U) +#define UART_IE7816_CWTE_SHIFT (6U) +#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK) +#define UART_IE7816_WTE_MASK (0x80U) +#define UART_IE7816_WTE_SHIFT (7U) +#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK) + +/*! @name IS7816 - UART 7816 Interrupt Status Register */ +#define UART_IS7816_RXT_MASK (0x1U) +#define UART_IS7816_RXT_SHIFT (0U) +#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK) +#define UART_IS7816_TXT_MASK (0x2U) +#define UART_IS7816_TXT_SHIFT (1U) +#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK) +#define UART_IS7816_GTV_MASK (0x4U) +#define UART_IS7816_GTV_SHIFT (2U) +#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK) +#define UART_IS7816_INITD_MASK (0x10U) +#define UART_IS7816_INITD_SHIFT (4U) +#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK) +#define UART_IS7816_BWT_MASK (0x20U) +#define UART_IS7816_BWT_SHIFT (5U) +#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK) +#define UART_IS7816_CWT_MASK (0x40U) +#define UART_IS7816_CWT_SHIFT (6U) +#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK) +#define UART_IS7816_WT_MASK (0x80U) +#define UART_IS7816_WT_SHIFT (7U) +#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK) + +/*! @name WP7816T0 - UART 7816 Wait Parameter Register */ +#define UART_WP7816T0_WI_MASK (0xFFU) +#define UART_WP7816T0_WI_SHIFT (0U) +#define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK) + +/*! @name WP7816T1 - UART 7816 Wait Parameter Register */ +#define UART_WP7816T1_BWI_MASK (0xFU) +#define UART_WP7816T1_BWI_SHIFT (0U) +#define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK) +#define UART_WP7816T1_CWI_MASK (0xF0U) +#define UART_WP7816T1_CWI_SHIFT (4U) +#define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK) + +/*! @name WN7816 - UART 7816 Wait N Register */ +#define UART_WN7816_GTN_MASK (0xFFU) +#define UART_WN7816_GTN_SHIFT (0U) +#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK) + +/*! @name WF7816 - UART 7816 Wait FD Register */ +#define UART_WF7816_GTFD_MASK (0xFFU) +#define UART_WF7816_GTFD_SHIFT (0U) +#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK) + +/*! @name ET7816 - UART 7816 Error Threshold Register */ +#define UART_ET7816_RXTHRESHOLD_MASK (0xFU) +#define UART_ET7816_RXTHRESHOLD_SHIFT (0U) +#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK) +#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U) +#define UART_ET7816_TXTHRESHOLD_SHIFT (4U) +#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK) + +/*! @name TL7816 - UART 7816 Transmit Length Register */ +#define UART_TL7816_TLEN_MASK (0xFFU) +#define UART_TL7816_TLEN_SHIFT (0U) +#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK) + + +/*! + * @} + */ /* end of group UART_Register_Masks */ + + +/* UART - Peripheral instance base addresses */ +/** Peripheral UART0 base address */ +#define UART0_BASE (0x4006A000u) +/** Peripheral UART0 base pointer */ +#define UART0 ((UART_Type *)UART0_BASE) +/** Peripheral UART1 base address */ +#define UART1_BASE (0x4006B000u) +/** Peripheral UART1 base pointer */ +#define UART1 ((UART_Type *)UART1_BASE) +/** Peripheral UART2 base address */ +#define UART2_BASE (0x4006C000u) +/** Peripheral UART2 base pointer */ +#define UART2 ((UART_Type *)UART2_BASE) +/** Peripheral UART3 base address */ +#define UART3_BASE (0x4006D000u) +/** Peripheral UART3 base pointer */ +#define UART3 ((UART_Type *)UART3_BASE) +/** Peripheral UART4 base address */ +#define UART4_BASE (0x400EA000u) +/** Peripheral UART4 base pointer */ +#define UART4 ((UART_Type *)UART4_BASE) +/** Peripheral UART5 base address */ +#define UART5_BASE (0x400EB000u) +/** Peripheral UART5 base pointer */ +#define UART5 ((UART_Type *)UART5_BASE) +/** Array initializer of UART peripheral base addresses */ +#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE } +/** Array initializer of UART peripheral base pointers */ +#define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 } +/** Interrupt vectors for the UART peripheral type */ +#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn } +#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn } +#define UART_LON_IRQS { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } + +/*! + * @} + */ /* end of group UART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ + uint8_t RESERVED_0[3]; + __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ + uint8_t RESERVED_1[3]; + __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ + uint8_t RESERVED_2[3]; + __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ + uint8_t RESERVED_3[3]; + __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ + uint8_t RESERVED_4[3]; + __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */ + uint8_t RESERVED_5[3]; + __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ + uint8_t RESERVED_6[3]; + __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ + uint8_t RESERVED_7[99]; + __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ + uint8_t RESERVED_8[3]; + __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ + uint8_t RESERVED_9[3]; + __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ + uint8_t RESERVED_10[3]; + __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ + uint8_t RESERVED_11[3]; + __I uint8_t STAT; /**< Status register, offset: 0x90 */ + uint8_t RESERVED_12[3]; + __IO uint8_t CTL; /**< Control register, offset: 0x94 */ + uint8_t RESERVED_13[3]; + __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ + uint8_t RESERVED_14[3]; + __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ + uint8_t RESERVED_15[3]; + __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ + uint8_t RESERVED_16[3]; + __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ + uint8_t RESERVED_17[3]; + __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */ + uint8_t RESERVED_18[3]; + __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */ + uint8_t RESERVED_19[3]; + __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ + uint8_t RESERVED_20[3]; + __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ + uint8_t RESERVED_21[11]; + struct { /* offset: 0xC0, array step: 0x4 */ + __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_0[3]; + } ENDPOINT[16]; + __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ + uint8_t RESERVED_22[3]; + __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ + uint8_t RESERVED_23[3]; + __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ + uint8_t RESERVED_24[3]; + __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ + uint8_t RESERVED_25[7]; + __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ + uint8_t RESERVED_26[43]; + __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ + uint8_t RESERVED_27[3]; + __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */ + uint8_t RESERVED_28[23]; + __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name PERID - Peripheral ID register */ +#define USB_PERID_ID_MASK (0x3FU) +#define USB_PERID_ID_SHIFT (0U) +#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) + +/*! @name IDCOMP - Peripheral ID Complement register */ +#define USB_IDCOMP_NID_MASK (0x3FU) +#define USB_IDCOMP_NID_SHIFT (0U) +#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) + +/*! @name REV - Peripheral Revision register */ +#define USB_REV_REV_MASK (0xFFU) +#define USB_REV_REV_SHIFT (0U) +#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) + +/*! @name ADDINFO - Peripheral Additional Info register */ +#define USB_ADDINFO_IEHOST_MASK (0x1U) +#define USB_ADDINFO_IEHOST_SHIFT (0U) +#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) +#define USB_ADDINFO_IRQNUM_MASK (0xF8U) +#define USB_ADDINFO_IRQNUM_SHIFT (3U) +#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK) + +/*! @name OTGISTAT - OTG Interrupt Status register */ +#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U) +#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U) +#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK) +#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U) +#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U) +#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK) +#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U) +#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U) +#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK) +#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) +#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) +#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) +#define USB_OTGISTAT_ONEMSEC_MASK (0x40U) +#define USB_OTGISTAT_ONEMSEC_SHIFT (6U) +#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) +#define USB_OTGISTAT_IDCHG_MASK (0x80U) +#define USB_OTGISTAT_IDCHG_SHIFT (7U) +#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK) + +/*! @name OTGICR - OTG Interrupt Control register */ +#define USB_OTGICR_AVBUSEN_MASK (0x1U) +#define USB_OTGICR_AVBUSEN_SHIFT (0U) +#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK) +#define USB_OTGICR_BSESSEN_MASK (0x4U) +#define USB_OTGICR_BSESSEN_SHIFT (2U) +#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK) +#define USB_OTGICR_SESSVLDEN_MASK (0x8U) +#define USB_OTGICR_SESSVLDEN_SHIFT (3U) +#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK) +#define USB_OTGICR_LINESTATEEN_MASK (0x20U) +#define USB_OTGICR_LINESTATEEN_SHIFT (5U) +#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) +#define USB_OTGICR_ONEMSECEN_MASK (0x40U) +#define USB_OTGICR_ONEMSECEN_SHIFT (6U) +#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) +#define USB_OTGICR_IDEN_MASK (0x80U) +#define USB_OTGICR_IDEN_SHIFT (7U) +#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK) + +/*! @name OTGSTAT - OTG Status register */ +#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U) +#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U) +#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK) +#define USB_OTGSTAT_BSESSEND_MASK (0x4U) +#define USB_OTGSTAT_BSESSEND_SHIFT (2U) +#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK) +#define USB_OTGSTAT_SESS_VLD_MASK (0x8U) +#define USB_OTGSTAT_SESS_VLD_SHIFT (3U) +#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK) +#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) +#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) +#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) +#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) +#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) +#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) +#define USB_OTGSTAT_ID_MASK (0x80U) +#define USB_OTGSTAT_ID_SHIFT (7U) +#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK) + +/*! @name OTGCTL - OTG Control register */ +#define USB_OTGCTL_OTGEN_MASK (0x4U) +#define USB_OTGCTL_OTGEN_SHIFT (2U) +#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) +#define USB_OTGCTL_DMLOW_MASK (0x10U) +#define USB_OTGCTL_DMLOW_SHIFT (4U) +#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) +#define USB_OTGCTL_DPLOW_MASK (0x20U) +#define USB_OTGCTL_DPLOW_SHIFT (5U) +#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) +#define USB_OTGCTL_DPHIGH_MASK (0x80U) +#define USB_OTGCTL_DPHIGH_SHIFT (7U) +#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) + +/*! @name ISTAT - Interrupt Status register */ +#define USB_ISTAT_USBRST_MASK (0x1U) +#define USB_ISTAT_USBRST_SHIFT (0U) +#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) +#define USB_ISTAT_ERROR_MASK (0x2U) +#define USB_ISTAT_ERROR_SHIFT (1U) +#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) +#define USB_ISTAT_SOFTOK_MASK (0x4U) +#define USB_ISTAT_SOFTOK_SHIFT (2U) +#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) +#define USB_ISTAT_TOKDNE_MASK (0x8U) +#define USB_ISTAT_TOKDNE_SHIFT (3U) +#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) +#define USB_ISTAT_SLEEP_MASK (0x10U) +#define USB_ISTAT_SLEEP_SHIFT (4U) +#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) +#define USB_ISTAT_RESUME_MASK (0x20U) +#define USB_ISTAT_RESUME_SHIFT (5U) +#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) +#define USB_ISTAT_ATTACH_MASK (0x40U) +#define USB_ISTAT_ATTACH_SHIFT (6U) +#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) +#define USB_ISTAT_STALL_MASK (0x80U) +#define USB_ISTAT_STALL_SHIFT (7U) +#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) + +/*! @name INTEN - Interrupt Enable register */ +#define USB_INTEN_USBRSTEN_MASK (0x1U) +#define USB_INTEN_USBRSTEN_SHIFT (0U) +#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) +#define USB_INTEN_ERROREN_MASK (0x2U) +#define USB_INTEN_ERROREN_SHIFT (1U) +#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) +#define USB_INTEN_SOFTOKEN_MASK (0x4U) +#define USB_INTEN_SOFTOKEN_SHIFT (2U) +#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) +#define USB_INTEN_TOKDNEEN_MASK (0x8U) +#define USB_INTEN_TOKDNEEN_SHIFT (3U) +#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) +#define USB_INTEN_SLEEPEN_MASK (0x10U) +#define USB_INTEN_SLEEPEN_SHIFT (4U) +#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) +#define USB_INTEN_RESUMEEN_MASK (0x20U) +#define USB_INTEN_RESUMEEN_SHIFT (5U) +#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) +#define USB_INTEN_ATTACHEN_MASK (0x40U) +#define USB_INTEN_ATTACHEN_SHIFT (6U) +#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) +#define USB_INTEN_STALLEN_MASK (0x80U) +#define USB_INTEN_STALLEN_SHIFT (7U) +#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) + +/*! @name ERRSTAT - Error Interrupt Status register */ +#define USB_ERRSTAT_PIDERR_MASK (0x1U) +#define USB_ERRSTAT_PIDERR_SHIFT (0U) +#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) +#define USB_ERRSTAT_CRC5EOF_MASK (0x2U) +#define USB_ERRSTAT_CRC5EOF_SHIFT (1U) +#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) +#define USB_ERRSTAT_CRC16_MASK (0x4U) +#define USB_ERRSTAT_CRC16_SHIFT (2U) +#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) +#define USB_ERRSTAT_DFN8_MASK (0x8U) +#define USB_ERRSTAT_DFN8_SHIFT (3U) +#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) +#define USB_ERRSTAT_BTOERR_MASK (0x10U) +#define USB_ERRSTAT_BTOERR_SHIFT (4U) +#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) +#define USB_ERRSTAT_DMAERR_MASK (0x20U) +#define USB_ERRSTAT_DMAERR_SHIFT (5U) +#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) +#define USB_ERRSTAT_BTSERR_MASK (0x80U) +#define USB_ERRSTAT_BTSERR_SHIFT (7U) +#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) + +/*! @name ERREN - Error Interrupt Enable register */ +#define USB_ERREN_PIDERREN_MASK (0x1U) +#define USB_ERREN_PIDERREN_SHIFT (0U) +#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) +#define USB_ERREN_CRC5EOFEN_MASK (0x2U) +#define USB_ERREN_CRC5EOFEN_SHIFT (1U) +#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) +#define USB_ERREN_CRC16EN_MASK (0x4U) +#define USB_ERREN_CRC16EN_SHIFT (2U) +#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) +#define USB_ERREN_DFN8EN_MASK (0x8U) +#define USB_ERREN_DFN8EN_SHIFT (3U) +#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) +#define USB_ERREN_BTOERREN_MASK (0x10U) +#define USB_ERREN_BTOERREN_SHIFT (4U) +#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) +#define USB_ERREN_DMAERREN_MASK (0x20U) +#define USB_ERREN_DMAERREN_SHIFT (5U) +#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) +#define USB_ERREN_BTSERREN_MASK (0x80U) +#define USB_ERREN_BTSERREN_SHIFT (7U) +#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) + +/*! @name STAT - Status register */ +#define USB_STAT_ODD_MASK (0x4U) +#define USB_STAT_ODD_SHIFT (2U) +#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) +#define USB_STAT_TX_MASK (0x8U) +#define USB_STAT_TX_SHIFT (3U) +#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) +#define USB_STAT_ENDP_MASK (0xF0U) +#define USB_STAT_ENDP_SHIFT (4U) +#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) + +/*! @name CTL - Control register */ +#define USB_CTL_USBENSOFEN_MASK (0x1U) +#define USB_CTL_USBENSOFEN_SHIFT (0U) +#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) +#define USB_CTL_ODDRST_MASK (0x2U) +#define USB_CTL_ODDRST_SHIFT (1U) +#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) +#define USB_CTL_RESUME_MASK (0x4U) +#define USB_CTL_RESUME_SHIFT (2U) +#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) +#define USB_CTL_HOSTMODEEN_MASK (0x8U) +#define USB_CTL_HOSTMODEEN_SHIFT (3U) +#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) +#define USB_CTL_RESET_MASK (0x10U) +#define USB_CTL_RESET_SHIFT (4U) +#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) +#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) +#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) +#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) +#define USB_CTL_SE0_MASK (0x40U) +#define USB_CTL_SE0_SHIFT (6U) +#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) +#define USB_CTL_JSTATE_MASK (0x80U) +#define USB_CTL_JSTATE_SHIFT (7U) +#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) + +/*! @name ADDR - Address register */ +#define USB_ADDR_ADDR_MASK (0x7FU) +#define USB_ADDR_ADDR_SHIFT (0U) +#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) +#define USB_ADDR_LSEN_MASK (0x80U) +#define USB_ADDR_LSEN_SHIFT (7U) +#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) + +/*! @name BDTPAGE1 - BDT Page register 1 */ +#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) +#define USB_BDTPAGE1_BDTBA_SHIFT (1U) +#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) + +/*! @name FRMNUML - Frame Number register Low */ +#define USB_FRMNUML_FRM_MASK (0xFFU) +#define USB_FRMNUML_FRM_SHIFT (0U) +#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) + +/*! @name FRMNUMH - Frame Number register High */ +#define USB_FRMNUMH_FRM_MASK (0x7U) +#define USB_FRMNUMH_FRM_SHIFT (0U) +#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) + +/*! @name TOKEN - Token register */ +#define USB_TOKEN_TOKENENDPT_MASK (0xFU) +#define USB_TOKEN_TOKENENDPT_SHIFT (0U) +#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) +#define USB_TOKEN_TOKENPID_MASK (0xF0U) +#define USB_TOKEN_TOKENPID_SHIFT (4U) +#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) + +/*! @name SOFTHLD - SOF Threshold register */ +#define USB_SOFTHLD_CNT_MASK (0xFFU) +#define USB_SOFTHLD_CNT_SHIFT (0U) +#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) + +/*! @name BDTPAGE2 - BDT Page Register 2 */ +#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE2_BDTBA_SHIFT (0U) +#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) + +/*! @name BDTPAGE3 - BDT Page Register 3 */ +#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE3_BDTBA_SHIFT (0U) +#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) + +/*! @name ENDPT - Endpoint Control register */ +#define USB_ENDPT_EPHSHK_MASK (0x1U) +#define USB_ENDPT_EPHSHK_SHIFT (0U) +#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) +#define USB_ENDPT_EPSTALL_MASK (0x2U) +#define USB_ENDPT_EPSTALL_SHIFT (1U) +#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) +#define USB_ENDPT_EPTXEN_MASK (0x4U) +#define USB_ENDPT_EPTXEN_SHIFT (2U) +#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) +#define USB_ENDPT_EPRXEN_MASK (0x8U) +#define USB_ENDPT_EPRXEN_SHIFT (3U) +#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) +#define USB_ENDPT_EPCTLDIS_MASK (0x10U) +#define USB_ENDPT_EPCTLDIS_SHIFT (4U) +#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) +#define USB_ENDPT_RETRYDIS_MASK (0x40U) +#define USB_ENDPT_RETRYDIS_SHIFT (6U) +#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) +#define USB_ENDPT_HOSTWOHUB_MASK (0x80U) +#define USB_ENDPT_HOSTWOHUB_SHIFT (7U) +#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) + +/* The count of USB_ENDPT */ +#define USB_ENDPT_COUNT (16U) + +/*! @name USBCTRL - USB Control register */ +#define USB_USBCTRL_PDE_MASK (0x40U) +#define USB_USBCTRL_PDE_SHIFT (6U) +#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) +#define USB_USBCTRL_SUSP_MASK (0x80U) +#define USB_USBCTRL_SUSP_SHIFT (7U) +#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) + +/*! @name OBSERVE - USB OTG Observe register */ +#define USB_OBSERVE_DMPD_MASK (0x10U) +#define USB_OBSERVE_DMPD_SHIFT (4U) +#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) +#define USB_OBSERVE_DPPD_MASK (0x40U) +#define USB_OBSERVE_DPPD_SHIFT (6U) +#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) +#define USB_OBSERVE_DPPU_MASK (0x80U) +#define USB_OBSERVE_DPPU_SHIFT (7U) +#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) + +/*! @name CONTROL - USB OTG Control register */ +#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) +#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) +#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) + +/*! @name USBTRC0 - USB Transceiver Control register 0 */ +#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) +#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) +#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) +#define USB_USBTRC0_SYNC_DET_MASK (0x2U) +#define USB_USBTRC0_SYNC_DET_SHIFT (1U) +#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) +#define USB_USBTRC0_USBRESMEN_MASK (0x20U) +#define USB_USBTRC0_USBRESMEN_SHIFT (5U) +#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) +#define USB_USBTRC0_USBRESET_MASK (0x80U) +#define USB_USBTRC0_USBRESET_SHIFT (7U) +#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) + +/*! @name USBFRMADJUST - Frame Adjust Register */ +#define USB_USBFRMADJUST_ADJ_MASK (0xFFU) +#define USB_USBFRMADJUST_ADJ_SHIFT (0U) +#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) + +/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) + +/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */ +#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U) +#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U) +#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) + +/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x40072000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBDCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer + * @{ + */ + +/** USBDCD - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */ + __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */ + __I uint32_t STATUS; /**< Status register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */ + __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */ + union { /* offset: 0x18 */ + __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */ + __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */ + }; +} USBDCD_Type; + +/* ---------------------------------------------------------------------------- + -- USBDCD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBDCD_Register_Masks USBDCD Register Masks + * @{ + */ + +/*! @name CONTROL - Control register */ +#define USBDCD_CONTROL_IACK_MASK (0x1U) +#define USBDCD_CONTROL_IACK_SHIFT (0U) +#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK) +#define USBDCD_CONTROL_IF_MASK (0x100U) +#define USBDCD_CONTROL_IF_SHIFT (8U) +#define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK) +#define USBDCD_CONTROL_IE_MASK (0x10000U) +#define USBDCD_CONTROL_IE_SHIFT (16U) +#define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK) +#define USBDCD_CONTROL_BC12_MASK (0x20000U) +#define USBDCD_CONTROL_BC12_SHIFT (17U) +#define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK) +#define USBDCD_CONTROL_START_MASK (0x1000000U) +#define USBDCD_CONTROL_START_SHIFT (24U) +#define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK) +#define USBDCD_CONTROL_SR_MASK (0x2000000U) +#define USBDCD_CONTROL_SR_SHIFT (25U) +#define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK) + +/*! @name CLOCK - Clock register */ +#define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) +#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) +#define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK) +#define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) +#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) +#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK) + +/*! @name STATUS - Status register */ +#define USBDCD_STATUS_SEQ_RES_MASK (0x30000U) +#define USBDCD_STATUS_SEQ_RES_SHIFT (16U) +#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK) +#define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U) +#define USBDCD_STATUS_SEQ_STAT_SHIFT (18U) +#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK) +#define USBDCD_STATUS_ERR_MASK (0x100000U) +#define USBDCD_STATUS_ERR_SHIFT (20U) +#define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK) +#define USBDCD_STATUS_TO_MASK (0x200000U) +#define USBDCD_STATUS_TO_SHIFT (21U) +#define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK) +#define USBDCD_STATUS_ACTIVE_MASK (0x400000U) +#define USBDCD_STATUS_ACTIVE_SHIFT (22U) +#define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK) + +/*! @name TIMER0 - TIMER0 register */ +#define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU) +#define USBDCD_TIMER0_TUNITCON_SHIFT (0U) +#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK) +#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) +#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U) +#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK) + +/*! @name TIMER1 - TIMER1 register */ +#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) +#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) +#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK) +#define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) +#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U) +#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK) + +/*! @name TIMER2_BC11 - TIMER2_BC11 register */ +#define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) +#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) +#define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK) +#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) +#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) +#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK) + +/*! @name TIMER2_BC12 - TIMER2_BC12 register */ +#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) +#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) +#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK) +#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) +#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) +#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) + + +/*! + * @} + */ /* end of group USBDCD_Register_Masks */ + + +/* USBDCD - Peripheral instance base addresses */ +/** Peripheral USBDCD base address */ +#define USBDCD_BASE (0x40035000u) +/** Peripheral USBDCD base pointer */ +#define USBDCD ((USBDCD_Type *)USBDCD_BASE) +/** Array initializer of USBDCD peripheral base addresses */ +#define USBDCD_BASE_ADDRS { USBDCD_BASE } +/** Array initializer of USBDCD peripheral base pointers */ +#define USBDCD_BASE_PTRS { USBDCD } +/** Interrupt vectors for the USBDCD peripheral type */ +#define USBDCD_IRQS { USBDCD_IRQn } + +/*! + * @} + */ /* end of group USBDCD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VREF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer + * @{ + */ + +/** VREF - Register Layout Typedef */ +typedef struct { + __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ + __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ +} VREF_Type; + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/*! @name TRM - VREF Trim Register */ +#define VREF_TRM_TRIM_MASK (0x3FU) +#define VREF_TRM_TRIM_SHIFT (0U) +#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) +#define VREF_TRM_CHOPEN_MASK (0x40U) +#define VREF_TRM_CHOPEN_SHIFT (6U) +#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) + +/*! @name SC - VREF Status and Control Register */ +#define VREF_SC_MODE_LV_MASK (0x3U) +#define VREF_SC_MODE_LV_SHIFT (0U) +#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) +#define VREF_SC_VREFST_MASK (0x4U) +#define VREF_SC_VREFST_SHIFT (2U) +#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) +#define VREF_SC_ICOMPEN_MASK (0x20U) +#define VREF_SC_ICOMPEN_SHIFT (5U) +#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) +#define VREF_SC_REGEN_MASK (0x40U) +#define VREF_SC_REGEN_SHIFT (6U) +#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) +#define VREF_SC_VREFEN_MASK (0x80U) +#define VREF_SC_VREFEN_SHIFT (7U) +#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) + + +/*! + * @} + */ /* end of group VREF_Register_Masks */ + + +/* VREF - Peripheral instance base addresses */ +/** Peripheral VREF base address */ +#define VREF_BASE (0x40074000u) +/** Peripheral VREF base pointer */ +#define VREF ((VREF_Type *)VREF_BASE) +/** Array initializer of VREF peripheral base addresses */ +#define VREF_BASE_ADDRS { VREF_BASE } +/** Array initializer of VREF peripheral base pointers */ +#define VREF_BASE_PTRS { VREF } + +/*! + * @} + */ /* end of group VREF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ + __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ + __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ + __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ + __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ + __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ + __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */ + __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */ + __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ + __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ + __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */ + __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name STCTRLH - Watchdog Status and Control Register High */ +#define WDOG_STCTRLH_WDOGEN_MASK (0x1U) +#define WDOG_STCTRLH_WDOGEN_SHIFT (0U) +#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK) +#define WDOG_STCTRLH_CLKSRC_MASK (0x2U) +#define WDOG_STCTRLH_CLKSRC_SHIFT (1U) +#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK) +#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U) +#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U) +#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK) +#define WDOG_STCTRLH_WINEN_MASK (0x8U) +#define WDOG_STCTRLH_WINEN_SHIFT (3U) +#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK) +#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U) +#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U) +#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK) +#define WDOG_STCTRLH_DBGEN_MASK (0x20U) +#define WDOG_STCTRLH_DBGEN_SHIFT (5U) +#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK) +#define WDOG_STCTRLH_STOPEN_MASK (0x40U) +#define WDOG_STCTRLH_STOPEN_SHIFT (6U) +#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK) +#define WDOG_STCTRLH_WAITEN_MASK (0x80U) +#define WDOG_STCTRLH_WAITEN_SHIFT (7U) +#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK) +#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U) +#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U) +#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK) +#define WDOG_STCTRLH_TESTSEL_MASK (0x800U) +#define WDOG_STCTRLH_TESTSEL_SHIFT (11U) +#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK) +#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U) +#define WDOG_STCTRLH_BYTESEL_SHIFT (12U) +#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK) +#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U) +#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U) +#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK) + +/*! @name STCTRLL - Watchdog Status and Control Register Low */ +#define WDOG_STCTRLL_INTFLG_MASK (0x8000U) +#define WDOG_STCTRLL_INTFLG_SHIFT (15U) +#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK) + +/*! @name TOVALH - Watchdog Time-out Value Register High */ +#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU) +#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) +#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) + +/*! @name TOVALL - Watchdog Time-out Value Register Low */ +#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU) +#define WDOG_TOVALL_TOVALLOW_SHIFT (0U) +#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) + +/*! @name WINH - Watchdog Window Register High */ +#define WDOG_WINH_WINHIGH_MASK (0xFFFFU) +#define WDOG_WINH_WINHIGH_SHIFT (0U) +#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) + +/*! @name WINL - Watchdog Window Register Low */ +#define WDOG_WINL_WINLOW_MASK (0xFFFFU) +#define WDOG_WINL_WINLOW_SHIFT (0U) +#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) + +/*! @name REFRESH - Watchdog Refresh register */ +#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU) +#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U) +#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK) + +/*! @name UNLOCK - Watchdog Unlock register */ +#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU) +#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U) +#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK) + +/*! @name TMROUTH - Watchdog Timer Output Register High */ +#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU) +#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U) +#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK) + +/*! @name TMROUTL - Watchdog Timer Output Register Low */ +#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU) +#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U) +#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK) + +/*! @name RSTCNT - Watchdog Reset Count register */ +#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU) +#define WDOG_RSTCNT_RSTCNT_SHIFT (0U) +#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK) + +/*! @name PRESC - Watchdog Prescaler register */ +#define WDOG_PRESC_PRESCVAL_MASK (0x700U) +#define WDOG_PRESC_PRESCVAL_SHIFT (8U) +#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK) + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG base address */ +#define WDOG_BASE (0x40052000u) +/** Peripheral WDOG base pointer */ +#define WDOG ((WDOG_Type *)WDOG_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { WDOG_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { WDOG } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { WDOG_EWM_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__CWCC__) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK +#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT +#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK +#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT +#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK +#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT +#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x) +#define MCM_ISR_REG(base) MCM_ISCR_REG(base) +#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK +#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT +#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK +#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT +#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK +#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT +#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK +#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT +#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK +#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT +#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK +#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT +#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK +#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT +#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK +#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT +#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK +#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT +#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK +#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT +#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK +#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT +#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK +#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT +#define DSPI0 SPI0 +#define DSPI1 SPI1 +#define DSPI2 SPI2 +#define FLEXCAN0 CAN0 +#define PTA_BASE GPIOA_BASE +#define PTA GPIOA +#define PTB_BASE GPIOB_BASE +#define PTB GPIOB +#define PTC_BASE GPIOC_BASE +#define PTC GPIOC +#define PTD_BASE GPIOD_BASE +#define PTD GPIOD +#define PTE_BASE GPIOE_BASE +#define PTE GPIOE +#define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base) +#define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base) +#define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK +#define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT +#define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x) +#define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK +#define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT +#define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x) +#define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK +#define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT +#define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x) +#define Watchdog_IRQn WDOG_EWM_IRQn +#define Watchdog_IRQHandler WDOG_EWM_IRQHandler +#define LPTimer_IRQn LPTMR0_IRQn +#define LPTimer_IRQHandler LPTMR0_IRQHandler +#define LLW_IRQn LLWU_IRQn +#define LLW_IRQHandler LLWU_IRQHandler +#define DMAMUX0 DMAMUX +#define WDOG0 WDOG +#define MCM0 MCM +#define RTC0 RTC + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MK24F12_H_ */ + diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/MK24F12_features.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/MK24F12_features.h new file mode 100644 index 00000000000..723d7e27a05 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/MK24F12_features.h @@ -0,0 +1,1981 @@ +/* +** ################################################################### +** Version: rev. 2.14, 2016-03-21 +** Build: b170228 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2013-08-12) +** Initial version. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** MCG - registers updated. +** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-09) +** DMA - EARS register removed. +** AIPS0, AIPS1 - MPRA register updated. +** - rev. 2.3 (2014-01-24) +** Update according to reference manual rev. 2 +** ENET, MCG, MCM, SIM, USB - registers updated +** - rev. 2.4 (2014-01-30) +** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. +** - rev. 2.5 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK24F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** - rev. 2.6 (2014-08-28) +** Update of system files - default clock configuration changed. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 2.7 (2014-10-14) +** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. +** - rev. 2.8 (2015-01-21) +** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances +** - rev. 2.9 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** - rev. 2.10 (2015-05-19) +** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. +** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. +** Added features for PDB and PORT. +** - rev. 2.11 (2015-05-25) +** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS +** - rev. 2.12 (2015-05-27) +** Several USB features added. +** - rev. 2.13 (2015-06-08) +** FTM features BUS_CLOCK and FAST_CLOCK removed. +** - rev. 2.14 (2016-03-21) +** Added MK24FN1M0CAJ12 part. +** +** ################################################################### +*/ + +#ifndef _MK24F12_FEATURES_H_ +#define _MK24F12_FEATURES_H_ + +/* SOC module features */ + +#if defined(CPU_MK24FN1M0CAJ12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) + /* @brief ACMP availability on the SoC. */ + #define FSL_FEATURE_SOC_ACMP_COUNT (0) + /* @brief ADC16 availability on the SoC. */ + #define FSL_FEATURE_SOC_ADC16_COUNT (2) + /* @brief ADC12 availability on the SoC. */ + #define FSL_FEATURE_SOC_ADC12_COUNT (0) + /* @brief AFE availability on the SoC. */ + #define FSL_FEATURE_SOC_AFE_COUNT (0) + /* @brief AIPS availability on the SoC. */ + #define FSL_FEATURE_SOC_AIPS_COUNT (2) + /* @brief AOI availability on the SoC. */ + #define FSL_FEATURE_SOC_AOI_COUNT (0) + /* @brief AXBS availability on the SoC. */ + #define FSL_FEATURE_SOC_AXBS_COUNT (1) + /* @brief ASMC availability on the SoC. */ + #define FSL_FEATURE_SOC_ASMC_COUNT (0) + /* @brief CADC availability on the SoC. */ + #define FSL_FEATURE_SOC_CADC_COUNT (0) + /* @brief FLEXCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) + /* @brief MMCAU availability on the SoC. */ + #define FSL_FEATURE_SOC_MMCAU_COUNT (1) + /* @brief CMP availability on the SoC. */ + #define FSL_FEATURE_SOC_CMP_COUNT (3) + /* @brief CMT availability on the SoC. */ + #define FSL_FEATURE_SOC_CMT_COUNT (1) + /* @brief CNC availability on the SoC. */ + #define FSL_FEATURE_SOC_CNC_COUNT (0) + /* @brief CRC availability on the SoC. */ + #define FSL_FEATURE_SOC_CRC_COUNT (1) + /* @brief DAC availability on the SoC. */ + #define FSL_FEATURE_SOC_DAC_COUNT (2) + /* @brief DAC32 availability on the SoC. */ + #define FSL_FEATURE_SOC_DAC32_COUNT (0) + /* @brief DCDC availability on the SoC. */ + #define FSL_FEATURE_SOC_DCDC_COUNT (0) + /* @brief DDR availability on the SoC. */ + #define FSL_FEATURE_SOC_DDR_COUNT (0) + /* @brief DMA availability on the SoC. */ + #define FSL_FEATURE_SOC_DMA_COUNT (0) + /* @brief EDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_EDMA_COUNT (1) + /* @brief DMAMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) + /* @brief DRY availability on the SoC. */ + #define FSL_FEATURE_SOC_DRY_COUNT (0) + /* @brief DSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_DSPI_COUNT (3) + /* @brief EMVSIM availability on the SoC. */ + #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) + /* @brief ENC availability on the SoC. */ + #define FSL_FEATURE_SOC_ENC_COUNT (0) + /* @brief ENET availability on the SoC. */ + #define FSL_FEATURE_SOC_ENET_COUNT (0) + /* @brief EWM availability on the SoC. */ + #define FSL_FEATURE_SOC_EWM_COUNT (1) + /* @brief FB availability on the SoC. */ + #define FSL_FEATURE_SOC_FB_COUNT (1) + /* @brief FGPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_FGPIO_COUNT (0) + /* @brief FLEXIO availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) + /* @brief FMC availability on the SoC. */ + #define FSL_FEATURE_SOC_FMC_COUNT (1) + /* @brief FSKDT availability on the SoC. */ + #define FSL_FEATURE_SOC_FSKDT_COUNT (0) + /* @brief FTFA availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFA_COUNT (0) + /* @brief FTFE availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFE_COUNT (1) + /* @brief FTFL availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFL_COUNT (0) + /* @brief FTM availability on the SoC. */ + #define FSL_FEATURE_SOC_FTM_COUNT (4) + /* @brief FTMRA availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRA_COUNT (0) + /* @brief FTMRE availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRE_COUNT (0) + /* @brief FTMRH availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRH_COUNT (0) + /* @brief GPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_GPIO_COUNT (5) + /* @brief HSADC availability on the SoC. */ + #define FSL_FEATURE_SOC_HSADC_COUNT (0) + /* @brief I2C availability on the SoC. */ + #define FSL_FEATURE_SOC_I2C_COUNT (3) + /* @brief I2S availability on the SoC. */ + #define FSL_FEATURE_SOC_I2S_COUNT (1) + /* @brief ICS availability on the SoC. */ + #define FSL_FEATURE_SOC_ICS_COUNT (0) + /* @brief INTMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_INTMUX_COUNT (0) + /* @brief IRQ availability on the SoC. */ + #define FSL_FEATURE_SOC_IRQ_COUNT (0) + /* @brief KBI availability on the SoC. */ + #define FSL_FEATURE_SOC_KBI_COUNT (0) + /* @brief SLCD availability on the SoC. */ + #define FSL_FEATURE_SOC_SLCD_COUNT (0) + /* @brief LCDC availability on the SoC. */ + #define FSL_FEATURE_SOC_LCDC_COUNT (0) + /* @brief LDO availability on the SoC. */ + #define FSL_FEATURE_SOC_LDO_COUNT (0) + /* @brief LLWU availability on the SoC. */ + #define FSL_FEATURE_SOC_LLWU_COUNT (1) + /* @brief LMEM availability on the SoC. */ + #define FSL_FEATURE_SOC_LMEM_COUNT (0) + /* @brief LPI2C availability on the SoC. */ + #define FSL_FEATURE_SOC_LPI2C_COUNT (0) + /* @brief LPIT availability on the SoC. */ + #define FSL_FEATURE_SOC_LPIT_COUNT (0) + /* @brief LPSCI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSCI_COUNT (0) + /* @brief LPSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSPI_COUNT (0) + /* @brief LPTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTMR_COUNT (1) + /* @brief LPTPM availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTPM_COUNT (0) + /* @brief LPUART availability on the SoC. */ + #define FSL_FEATURE_SOC_LPUART_COUNT (0) + /* @brief LTC availability on the SoC. */ + #define FSL_FEATURE_SOC_LTC_COUNT (0) + /* @brief MC availability on the SoC. */ + #define FSL_FEATURE_SOC_MC_COUNT (0) + /* @brief MCG availability on the SoC. */ + #define FSL_FEATURE_SOC_MCG_COUNT (1) + /* @brief MCGLITE availability on the SoC. */ + #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) + /* @brief MCM availability on the SoC. */ + #define FSL_FEATURE_SOC_MCM_COUNT (1) + /* @brief MMAU availability on the SoC. */ + #define FSL_FEATURE_SOC_MMAU_COUNT (0) + /* @brief MMDVSQ availability on the SoC. */ + #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) + /* @brief SYSMPU availability on the SoC. */ + #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) + /* @brief MSCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_MSCAN_COUNT (0) + /* @brief MSCM availability on the SoC. */ + #define FSL_FEATURE_SOC_MSCM_COUNT (0) + /* @brief MTB availability on the SoC. */ + #define FSL_FEATURE_SOC_MTB_COUNT (0) + /* @brief MTBDWT availability on the SoC. */ + #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) + /* @brief MU availability on the SoC. */ + #define FSL_FEATURE_SOC_MU_COUNT (0) + /* @brief NFC availability on the SoC. */ + #define FSL_FEATURE_SOC_NFC_COUNT (0) + /* @brief OPAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_OPAMP_COUNT (0) + /* @brief OSC availability on the SoC. */ + #define FSL_FEATURE_SOC_OSC_COUNT (1) + /* @brief OSC32 availability on the SoC. */ + #define FSL_FEATURE_SOC_OSC32_COUNT (0) + /* @brief OTFAD availability on the SoC. */ + #define FSL_FEATURE_SOC_OTFAD_COUNT (0) + /* @brief PDB availability on the SoC. */ + #define FSL_FEATURE_SOC_PDB_COUNT (1) + /* @brief PCC availability on the SoC. */ + #define FSL_FEATURE_SOC_PCC_COUNT (0) + /* @brief PGA availability on the SoC. */ + #define FSL_FEATURE_SOC_PGA_COUNT (0) + /* @brief PIT availability on the SoC. */ + #define FSL_FEATURE_SOC_PIT_COUNT (1) + /* @brief PMC availability on the SoC. */ + #define FSL_FEATURE_SOC_PMC_COUNT (1) + /* @brief PORT availability on the SoC. */ + #define FSL_FEATURE_SOC_PORT_COUNT (5) + /* @brief PWM availability on the SoC. */ + #define FSL_FEATURE_SOC_PWM_COUNT (0) + /* @brief PWT availability on the SoC. */ + #define FSL_FEATURE_SOC_PWT_COUNT (0) + /* @brief QuadSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) + /* @brief RCM availability on the SoC. */ + #define FSL_FEATURE_SOC_RCM_COUNT (1) + /* @brief RFSYS availability on the SoC. */ + #define FSL_FEATURE_SOC_RFSYS_COUNT (1) + /* @brief RFVBAT availability on the SoC. */ + #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) + /* @brief RNG availability on the SoC. */ + #define FSL_FEATURE_SOC_RNG_COUNT (1) + /* @brief RNGB availability on the SoC. */ + #define FSL_FEATURE_SOC_RNGB_COUNT (0) + /* @brief ROM availability on the SoC. */ + #define FSL_FEATURE_SOC_ROM_COUNT (0) + /* @brief RSIM availability on the SoC. */ + #define FSL_FEATURE_SOC_RSIM_COUNT (0) + /* @brief RTC availability on the SoC. */ + #define FSL_FEATURE_SOC_RTC_COUNT (1) + /* @brief SCG availability on the SoC. */ + #define FSL_FEATURE_SOC_SCG_COUNT (0) + /* @brief SCI availability on the SoC. */ + #define FSL_FEATURE_SOC_SCI_COUNT (0) + /* @brief SDHC availability on the SoC. */ + #define FSL_FEATURE_SOC_SDHC_COUNT (1) + /* @brief SDRAM availability on the SoC. */ + #define FSL_FEATURE_SOC_SDRAM_COUNT (0) + /* @brief SEMA42 availability on the SoC. */ + #define FSL_FEATURE_SOC_SEMA42_COUNT (0) + /* @brief SIM availability on the SoC. */ + #define FSL_FEATURE_SOC_SIM_COUNT (1) + /* @brief SMC availability on the SoC. */ + #define FSL_FEATURE_SOC_SMC_COUNT (1) + /* @brief SPI availability on the SoC. */ + #define FSL_FEATURE_SOC_SPI_COUNT (0) + /* @brief TMR availability on the SoC. */ + #define FSL_FEATURE_SOC_TMR_COUNT (0) + /* @brief TPM availability on the SoC. */ + #define FSL_FEATURE_SOC_TPM_COUNT (0) + /* @brief TRGMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) + /* @brief TRIAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) + /* @brief TRNG availability on the SoC. */ + #define FSL_FEATURE_SOC_TRNG_COUNT (0) + /* @brief TSI availability on the SoC. */ + #define FSL_FEATURE_SOC_TSI_COUNT (0) + /* @brief TSTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_TSTMR_COUNT (0) + /* @brief UART availability on the SoC. */ + #define FSL_FEATURE_SOC_UART_COUNT (6) + /* @brief USB availability on the SoC. */ + #define FSL_FEATURE_SOC_USB_COUNT (1) + /* @brief USBDCD availability on the SoC. */ + #define FSL_FEATURE_SOC_USBDCD_COUNT (1) + /* @brief USBHS availability on the SoC. */ + #define FSL_FEATURE_SOC_USBHS_COUNT (0) + /* @brief USBHSDCD availability on the SoC. */ + #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) + /* @brief USBPHY availability on the SoC. */ + #define FSL_FEATURE_SOC_USBPHY_COUNT (0) + /* @brief VREF availability on the SoC. */ + #define FSL_FEATURE_SOC_VREF_COUNT (1) + /* @brief WDOG availability on the SoC. */ + #define FSL_FEATURE_SOC_WDOG_COUNT (1) + /* @brief XBAR availability on the SoC. */ + #define FSL_FEATURE_SOC_XBAR_COUNT (0) + /* @brief XBARA availability on the SoC. */ + #define FSL_FEATURE_SOC_XBARA_COUNT (0) + /* @brief XBARB availability on the SoC. */ + #define FSL_FEATURE_SOC_XBARB_COUNT (0) + /* @brief XCVR availability on the SoC. */ + #define FSL_FEATURE_SOC_XCVR_COUNT (0) + /* @brief XRDC availability on the SoC. */ + #define FSL_FEATURE_SOC_XRDC_COUNT (0) + /* @brief ZLL availability on the SoC. */ + #define FSL_FEATURE_SOC_ZLL_COUNT (0) +#elif defined(CPU_MK24FN1M0VLL12) + /* @brief ACMP availability on the SoC. */ + #define FSL_FEATURE_SOC_ACMP_COUNT (0) + /* @brief ADC16 availability on the SoC. */ + #define FSL_FEATURE_SOC_ADC16_COUNT (2) + /* @brief ADC12 availability on the SoC. */ + #define FSL_FEATURE_SOC_ADC12_COUNT (0) + /* @brief AFE availability on the SoC. */ + #define FSL_FEATURE_SOC_AFE_COUNT (0) + /* @brief AIPS availability on the SoC. */ + #define FSL_FEATURE_SOC_AIPS_COUNT (2) + /* @brief AOI availability on the SoC. */ + #define FSL_FEATURE_SOC_AOI_COUNT (0) + /* @brief AXBS availability on the SoC. */ + #define FSL_FEATURE_SOC_AXBS_COUNT (1) + /* @brief ASMC availability on the SoC. */ + #define FSL_FEATURE_SOC_ASMC_COUNT (0) + /* @brief CADC availability on the SoC. */ + #define FSL_FEATURE_SOC_CADC_COUNT (0) + /* @brief FLEXCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) + /* @brief MMCAU availability on the SoC. */ + #define FSL_FEATURE_SOC_MMCAU_COUNT (1) + /* @brief CMP availability on the SoC. */ + #define FSL_FEATURE_SOC_CMP_COUNT (3) + /* @brief CMT availability on the SoC. */ + #define FSL_FEATURE_SOC_CMT_COUNT (1) + /* @brief CNC availability on the SoC. */ + #define FSL_FEATURE_SOC_CNC_COUNT (0) + /* @brief CRC availability on the SoC. */ + #define FSL_FEATURE_SOC_CRC_COUNT (1) + /* @brief DAC availability on the SoC. */ + #define FSL_FEATURE_SOC_DAC_COUNT (1) + /* @brief DAC32 availability on the SoC. */ + #define FSL_FEATURE_SOC_DAC32_COUNT (0) + /* @brief DCDC availability on the SoC. */ + #define FSL_FEATURE_SOC_DCDC_COUNT (0) + /* @brief DDR availability on the SoC. */ + #define FSL_FEATURE_SOC_DDR_COUNT (0) + /* @brief DMA availability on the SoC. */ + #define FSL_FEATURE_SOC_DMA_COUNT (0) + /* @brief EDMA availability on the SoC. */ + #define FSL_FEATURE_SOC_EDMA_COUNT (1) + /* @brief DMAMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) + /* @brief DRY availability on the SoC. */ + #define FSL_FEATURE_SOC_DRY_COUNT (0) + /* @brief DSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_DSPI_COUNT (3) + /* @brief EMVSIM availability on the SoC. */ + #define FSL_FEATURE_SOC_EMVSIM_COUNT (0) + /* @brief ENC availability on the SoC. */ + #define FSL_FEATURE_SOC_ENC_COUNT (0) + /* @brief ENET availability on the SoC. */ + #define FSL_FEATURE_SOC_ENET_COUNT (0) + /* @brief EWM availability on the SoC. */ + #define FSL_FEATURE_SOC_EWM_COUNT (1) + /* @brief FB availability on the SoC. */ + #define FSL_FEATURE_SOC_FB_COUNT (1) + /* @brief FGPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_FGPIO_COUNT (0) + /* @brief FLEXIO availability on the SoC. */ + #define FSL_FEATURE_SOC_FLEXIO_COUNT (0) + /* @brief FMC availability on the SoC. */ + #define FSL_FEATURE_SOC_FMC_COUNT (1) + /* @brief FSKDT availability on the SoC. */ + #define FSL_FEATURE_SOC_FSKDT_COUNT (0) + /* @brief FTFA availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFA_COUNT (0) + /* @brief FTFE availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFE_COUNT (1) + /* @brief FTFL availability on the SoC. */ + #define FSL_FEATURE_SOC_FTFL_COUNT (0) + /* @brief FTM availability on the SoC. */ + #define FSL_FEATURE_SOC_FTM_COUNT (4) + /* @brief FTMRA availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRA_COUNT (0) + /* @brief FTMRE availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRE_COUNT (0) + /* @brief FTMRH availability on the SoC. */ + #define FSL_FEATURE_SOC_FTMRH_COUNT (0) + /* @brief GPIO availability on the SoC. */ + #define FSL_FEATURE_SOC_GPIO_COUNT (5) + /* @brief HSADC availability on the SoC. */ + #define FSL_FEATURE_SOC_HSADC_COUNT (0) + /* @brief I2C availability on the SoC. */ + #define FSL_FEATURE_SOC_I2C_COUNT (3) + /* @brief I2S availability on the SoC. */ + #define FSL_FEATURE_SOC_I2S_COUNT (1) + /* @brief ICS availability on the SoC. */ + #define FSL_FEATURE_SOC_ICS_COUNT (0) + /* @brief INTMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_INTMUX_COUNT (0) + /* @brief IRQ availability on the SoC. */ + #define FSL_FEATURE_SOC_IRQ_COUNT (0) + /* @brief KBI availability on the SoC. */ + #define FSL_FEATURE_SOC_KBI_COUNT (0) + /* @brief SLCD availability on the SoC. */ + #define FSL_FEATURE_SOC_SLCD_COUNT (0) + /* @brief LCDC availability on the SoC. */ + #define FSL_FEATURE_SOC_LCDC_COUNT (0) + /* @brief LDO availability on the SoC. */ + #define FSL_FEATURE_SOC_LDO_COUNT (0) + /* @brief LLWU availability on the SoC. */ + #define FSL_FEATURE_SOC_LLWU_COUNT (1) + /* @brief LMEM availability on the SoC. */ + #define FSL_FEATURE_SOC_LMEM_COUNT (0) + /* @brief LPI2C availability on the SoC. */ + #define FSL_FEATURE_SOC_LPI2C_COUNT (0) + /* @brief LPIT availability on the SoC. */ + #define FSL_FEATURE_SOC_LPIT_COUNT (0) + /* @brief LPSCI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSCI_COUNT (0) + /* @brief LPSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_LPSPI_COUNT (0) + /* @brief LPTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTMR_COUNT (1) + /* @brief LPTPM availability on the SoC. */ + #define FSL_FEATURE_SOC_LPTPM_COUNT (0) + /* @brief LPUART availability on the SoC. */ + #define FSL_FEATURE_SOC_LPUART_COUNT (0) + /* @brief LTC availability on the SoC. */ + #define FSL_FEATURE_SOC_LTC_COUNT (0) + /* @brief MC availability on the SoC. */ + #define FSL_FEATURE_SOC_MC_COUNT (0) + /* @brief MCG availability on the SoC. */ + #define FSL_FEATURE_SOC_MCG_COUNT (1) + /* @brief MCGLITE availability on the SoC. */ + #define FSL_FEATURE_SOC_MCGLITE_COUNT (0) + /* @brief MCM availability on the SoC. */ + #define FSL_FEATURE_SOC_MCM_COUNT (1) + /* @brief MMAU availability on the SoC. */ + #define FSL_FEATURE_SOC_MMAU_COUNT (0) + /* @brief MMDVSQ availability on the SoC. */ + #define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) + /* @brief SYSMPU availability on the SoC. */ + #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) + /* @brief MSCAN availability on the SoC. */ + #define FSL_FEATURE_SOC_MSCAN_COUNT (0) + /* @brief MSCM availability on the SoC. */ + #define FSL_FEATURE_SOC_MSCM_COUNT (0) + /* @brief MTB availability on the SoC. */ + #define FSL_FEATURE_SOC_MTB_COUNT (0) + /* @brief MTBDWT availability on the SoC. */ + #define FSL_FEATURE_SOC_MTBDWT_COUNT (0) + /* @brief MU availability on the SoC. */ + #define FSL_FEATURE_SOC_MU_COUNT (0) + /* @brief NFC availability on the SoC. */ + #define FSL_FEATURE_SOC_NFC_COUNT (0) + /* @brief OPAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_OPAMP_COUNT (0) + /* @brief OSC availability on the SoC. */ + #define FSL_FEATURE_SOC_OSC_COUNT (1) + /* @brief OSC32 availability on the SoC. */ + #define FSL_FEATURE_SOC_OSC32_COUNT (0) + /* @brief OTFAD availability on the SoC. */ + #define FSL_FEATURE_SOC_OTFAD_COUNT (0) + /* @brief PDB availability on the SoC. */ + #define FSL_FEATURE_SOC_PDB_COUNT (1) + /* @brief PCC availability on the SoC. */ + #define FSL_FEATURE_SOC_PCC_COUNT (0) + /* @brief PGA availability on the SoC. */ + #define FSL_FEATURE_SOC_PGA_COUNT (0) + /* @brief PIT availability on the SoC. */ + #define FSL_FEATURE_SOC_PIT_COUNT (1) + /* @brief PMC availability on the SoC. */ + #define FSL_FEATURE_SOC_PMC_COUNT (1) + /* @brief PORT availability on the SoC. */ + #define FSL_FEATURE_SOC_PORT_COUNT (5) + /* @brief PWM availability on the SoC. */ + #define FSL_FEATURE_SOC_PWM_COUNT (0) + /* @brief PWT availability on the SoC. */ + #define FSL_FEATURE_SOC_PWT_COUNT (0) + /* @brief QuadSPI availability on the SoC. */ + #define FSL_FEATURE_SOC_QuadSPI_COUNT (0) + /* @brief RCM availability on the SoC. */ + #define FSL_FEATURE_SOC_RCM_COUNT (1) + /* @brief RFSYS availability on the SoC. */ + #define FSL_FEATURE_SOC_RFSYS_COUNT (1) + /* @brief RFVBAT availability on the SoC. */ + #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) + /* @brief RNG availability on the SoC. */ + #define FSL_FEATURE_SOC_RNG_COUNT (1) + /* @brief RNGB availability on the SoC. */ + #define FSL_FEATURE_SOC_RNGB_COUNT (0) + /* @brief ROM availability on the SoC. */ + #define FSL_FEATURE_SOC_ROM_COUNT (0) + /* @brief RSIM availability on the SoC. */ + #define FSL_FEATURE_SOC_RSIM_COUNT (0) + /* @brief RTC availability on the SoC. */ + #define FSL_FEATURE_SOC_RTC_COUNT (1) + /* @brief SCG availability on the SoC. */ + #define FSL_FEATURE_SOC_SCG_COUNT (0) + /* @brief SCI availability on the SoC. */ + #define FSL_FEATURE_SOC_SCI_COUNT (0) + /* @brief SDHC availability on the SoC. */ + #define FSL_FEATURE_SOC_SDHC_COUNT (1) + /* @brief SDRAM availability on the SoC. */ + #define FSL_FEATURE_SOC_SDRAM_COUNT (0) + /* @brief SEMA42 availability on the SoC. */ + #define FSL_FEATURE_SOC_SEMA42_COUNT (0) + /* @brief SIM availability on the SoC. */ + #define FSL_FEATURE_SOC_SIM_COUNT (1) + /* @brief SMC availability on the SoC. */ + #define FSL_FEATURE_SOC_SMC_COUNT (1) + /* @brief SPI availability on the SoC. */ + #define FSL_FEATURE_SOC_SPI_COUNT (0) + /* @brief TMR availability on the SoC. */ + #define FSL_FEATURE_SOC_TMR_COUNT (0) + /* @brief TPM availability on the SoC. */ + #define FSL_FEATURE_SOC_TPM_COUNT (0) + /* @brief TRGMUX availability on the SoC. */ + #define FSL_FEATURE_SOC_TRGMUX_COUNT (0) + /* @brief TRIAMP availability on the SoC. */ + #define FSL_FEATURE_SOC_TRIAMP_COUNT (0) + /* @brief TRNG availability on the SoC. */ + #define FSL_FEATURE_SOC_TRNG_COUNT (0) + /* @brief TSI availability on the SoC. */ + #define FSL_FEATURE_SOC_TSI_COUNT (0) + /* @brief TSTMR availability on the SoC. */ + #define FSL_FEATURE_SOC_TSTMR_COUNT (0) + /* @brief UART availability on the SoC. */ + #define FSL_FEATURE_SOC_UART_COUNT (5) + /* @brief USB availability on the SoC. */ + #define FSL_FEATURE_SOC_USB_COUNT (1) + /* @brief USBDCD availability on the SoC. */ + #define FSL_FEATURE_SOC_USBDCD_COUNT (1) + /* @brief USBHS availability on the SoC. */ + #define FSL_FEATURE_SOC_USBHS_COUNT (0) + /* @brief USBHSDCD availability on the SoC. */ + #define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) + /* @brief USBPHY availability on the SoC. */ + #define FSL_FEATURE_SOC_USBPHY_COUNT (0) + /* @brief VREF availability on the SoC. */ + #define FSL_FEATURE_SOC_VREF_COUNT (1) + /* @brief WDOG availability on the SoC. */ + #define FSL_FEATURE_SOC_WDOG_COUNT (1) + /* @brief XBAR availability on the SoC. */ + #define FSL_FEATURE_SOC_XBAR_COUNT (0) + /* @brief XBARA availability on the SoC. */ + #define FSL_FEATURE_SOC_XBARA_COUNT (0) + /* @brief XBARB availability on the SoC. */ + #define FSL_FEATURE_SOC_XBARB_COUNT (0) + /* @brief XCVR availability on the SoC. */ + #define FSL_FEATURE_SOC_XCVR_COUNT (0) + /* @brief XRDC availability on the SoC. */ + #define FSL_FEATURE_SOC_XRDC_COUNT (0) + /* @brief ZLL availability on the SoC. */ + #define FSL_FEATURE_SOC_ZLL_COUNT (0) +#endif + +/* ADC16 module features */ + +/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ +#define FSL_FEATURE_ADC16_HAS_PGA (0) +/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) +/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ +#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) +/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ +#define FSL_FEATURE_ADC16_HAS_DMA (1) +/* @brief Has differential mode (bitfield SC1x[DIFF]). */ +#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) +/* @brief Has FIFO (bit SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_HAS_FIFO (0) +/* @brief FIFO size if available (bitfield SC4[AFDEP]). */ +#define FSL_FEATURE_ADC16_FIFO_SIZE (0) +/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ +#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) +/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ +#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) +/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ +#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) +/* @brief Has HW averaging (bit SC3[AVGE]). */ +#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) +/* @brief Has offset correction (register OFS). */ +#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) +/* @brief Maximum ADC resolution. */ +#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) +/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ +#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_TIMING_REGISTER (0) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) +/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ +#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) +/* @brief Has bitfield name BUF31TO0M. */ +#define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0) +/* @brief Number of interrupt vectors. */ +#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* CRC module features */ + +/* @brief Has data register with name CRC */ +#define FSL_FEATURE_CRC_HAS_CRC_REG (0) + +/* DAC module features */ + +/* @brief Define the size of hardware buffer */ +#define FSL_FEATURE_DAC_BUFFER_SIZE (16) +/* @brief Define whether the buffer supports watermark event detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) +/* @brief Define whether the buffer supports watermark selection detection or not. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) +/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) +/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) +/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) +/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ +#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) +/* @brief Define whether FIFO buffer mode is available or not. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) +/* @brief Define whether swing buffer mode is available or not.. */ +#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_EDMA_COUNT * 16) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 16) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (0) + +/* FLEXBUS module features */ + +/* No feature definitions */ + +/* FLASH module features */ + +/* @brief Is of type FTFA. */ +#define FSL_FEATURE_FLASH_IS_FTFA (0) +/* @brief Is of type FTFE. */ +#define FSL_FEATURE_FLASH_IS_FTFE (1) +/* @brief Is of type FTFL. */ +#define FSL_FEATURE_FLASH_IS_FTFL (0) +/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ +#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) +/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ +#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) +/* @brief Has EEPROM region protection (register FEPROT). */ +#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) +/* @brief Has data flash region protection (register FDPROT). */ +#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) +/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ +#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) +/* @brief Has flash cache control in FMC module. */ +#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) +/* @brief Has flash cache control in MCM module. */ +#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) +/* @brief Has flash cache control in MSCM module. */ +#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) +/* @brief Has prefetch speculation control in flash, such as kv5x. */ +#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) +/* @brief P-Flash start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) +/* @brief P-Flash block size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) +/* @brief P-Flash write unit size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) +/* @brief P-Flash data path width. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) +/* @brief P-Flash block swap feature. */ +#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1) +/* @brief P-Flash protection region count. */ +#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) +/* @brief Has FlexNVM memory. */ +#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) +/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ +#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) +/* @brief FlexNVM block count. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) +/* @brief FlexNVM block size. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) +/* @brief FlexNVM sector size. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) +/* @brief FlexNVM write unit size. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) +/* @brief FlexNVM data path width. */ +#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) +/* @brief Has FlexRAM memory. */ +#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) +/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ +#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) +/* @brief FlexRAM size. */ +#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) +/* @brief Has 0x00 Read 1s Block command. */ +#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) +/* @brief Has 0x01 Read 1s Section command. */ +#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) +/* @brief Has 0x02 Program Check command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) +/* @brief Has 0x03 Read Resource command. */ +#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) +/* @brief Has 0x06 Program Longword command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) +/* @brief Has 0x07 Program Phrase command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) +/* @brief Has 0x08 Erase Flash Block command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) +/* @brief Has 0x09 Erase Flash Sector command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) +/* @brief Has 0x0B Program Section command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) +/* @brief Has 0x40 Read 1s All Blocks command. */ +#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) +/* @brief Has 0x41 Read Once command. */ +#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) +/* @brief Has 0x43 Program Once command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) +/* @brief Has 0x44 Erase All Blocks command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) +/* @brief Has 0x45 Verify Backdoor Access Key command. */ +#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) +/* @brief Has 0x46 Swap Control command. */ +#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1) +/* @brief Has 0x49 Erase All Blocks Unsecure command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) +/* @brief Has 0x4A Read 1s All Execute-only Segments command. */ +#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) +/* @brief Has 0x4B Erase All Execute-only Segments command. */ +#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) +/* @brief Has 0x80 Program Partition command. */ +#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) +/* @brief Has 0x81 Set FlexRAM Function command. */ +#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) +/* @brief P-Flash Erase/Read 1st all block command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) +/* @brief P-Flash Erase sector command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) +/* @brief P-Flash Rrogram/Verify section command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) +/* @brief P-Flash Read resource command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) +/* @brief P-Flash Program check command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) +/* @brief P-Flash Program check command address alignment. */ +#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16) +/* @brief FlexNVM Erase/Read 1st all block command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Erase sector command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Rrogram/Verify section command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Read resource command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM Program check command address alignment. */ +#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) +/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF) +/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF) +/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF) +/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) +/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) +/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) +/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) +/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) +/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) +/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) +/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) +/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) +/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) +/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) +/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) +/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) +/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) +/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) +/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ +#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) + +/* FTM module features */ + +/* @brief Number of channels. */ +#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ + ((x) == FTM0 ? (8) : \ + ((x) == FTM1 ? (2) : \ + ((x) == FTM2 ? (2) : \ + ((x) == FTM3 ? (8) : (-1))))) +/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ +#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) +/* @brief Has extended deadtime value. */ +#define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) +/* @brief Enable pwm output for the module. */ +#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) +/* @brief Has half-cycle reload for the module. */ +#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) +/* @brief Has reload interrupt. */ +#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) +/* @brief Has reload initialization trigger. */ +#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) + +/* GPIO module features */ + +/* @brief Has fast (single cycle) access capability via a dedicated memory region. */ +#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0) +/* @brief Has port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1) + +/* I2C module features */ + +/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ +#define FSL_FEATURE_I2C_HAS_SMBUS (1) +/* @brief Maximum supported baud rate in kilobit per second. */ +#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) +/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ +#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) +/* @brief Has DMA support (register bit C1[DMAEN]). */ +#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) +/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) +/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ +#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) +/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ +#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) +/* @brief Maximum width of the glitch filter in number of bus clocks. */ +#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) +/* @brief Has control of the drive capability of the I2C pins. */ +#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) +/* @brief Has double buffering support (register S2). */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) +/* @brief Has double buffer enable. */ +#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNT (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) +/* @brief Ihe interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (1) + +/* LLWU module features */ + +/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) +/* @brief Has pins 8-15 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) +/* @brief Maximum number of internal modules connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) +/* @brief Number of digital filters. */ +#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) +/* @brief Has MF register. */ +#define FSL_FEATURE_LLWU_HAS_MF (0) +/* @brief Has PF register. */ +#define FSL_FEATURE_LLWU_HAS_PF (0) +/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ +#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) +/* @brief Has no internal module wakeup flag register. */ +#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) +/* @brief Has external pin 0 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) +/* @brief Has external pin 1 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) +/* @brief Has external pin 2 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) +/* @brief Has external pin 3 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) +/* @brief Has external pin 4 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) +/* @brief Has external pin 5 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) +/* @brief Has external pin 6 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) +/* @brief Has external pin 7 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) +/* @brief Has external pin 8 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) +/* @brief Has external pin 9 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) +/* @brief Has external pin 10 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) +/* @brief Has external pin 11 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) +/* @brief Has external pin 12 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) +/* @brief Has external pin 13 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) +/* @brief Has external pin 14 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) +/* @brief Has external pin 15 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) +/* @brief Has external pin 16 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) +/* @brief Has external pin 17 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) +/* @brief Has external pin 18 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) +/* @brief Has external pin 19 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) +/* @brief Has external pin 20 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) +/* @brief Has external pin 21 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) +/* @brief Has external pin 22 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) +/* @brief Has external pin 23 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) +/* @brief Has external pin 24 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) +/* @brief Has external pin 25 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) +/* @brief Has external pin 26 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) +/* @brief Has external pin 27 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) +/* @brief Has external pin 28 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) +/* @brief Has external pin 29 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) +/* @brief Has external pin 30 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) +/* @brief Has external pin 31 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) +/* @brief Index of port of external pin. */ +#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) +/* @brief Number of external pin port on specified port. */ +#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) +/* @brief Has internal module 0 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) +/* @brief Has internal module 1 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) +/* @brief Has internal module 2 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) +/* @brief Has internal module 3 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) +/* @brief Has internal module 4 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) +/* @brief Has internal module 5 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) +/* @brief Has internal module 6 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) +/* @brief Has internal module 7 connected to LLWU device. */ +#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) +/* @brief Has Version ID Register (LLWU_VERID). */ +#define FSL_FEATURE_LLWU_HAS_VERID (0) +/* @brief Has Parameter Register (LLWU_PARAM). */ +#define FSL_FEATURE_LLWU_HAS_PARAM (0) +/* @brief Width of registers of the LLWU. */ +#define FSL_FEATURE_LLWU_REG_BITWIDTH (8) +/* @brief Has DMA Enable register (LLWU_DE). */ +#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) + +/* MCG module features */ + +/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) +/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ +#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) +/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ +#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) +/* @brief PLL reference clock low range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) +/* @brief PLL reference clock high range. OSCCLK/PLL_R. */ +#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) +/* @brief The PLL clock is divided by 2 before VCO divider. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) +/* @brief FRDIV supports 1280. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) +/* @brief FRDIV supports 1536. */ +#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) +/* @brief MCGFFCLK divider. */ +#define FSL_FEATURE_MCG_FFCLK_DIV (1) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ +#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) +/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ +#define FSL_FEATURE_MCG_HAS_RTC_32K (1) +/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_PLL1 (0) +/* @brief Has 48MHz internal oscillator. */ +#define FSL_FEATURE_MCG_HAS_IRC_48M (1) +/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ +#define FSL_FEATURE_MCG_HAS_OSC1 (0) +/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ +#define FSL_FEATURE_MCG_HAS_FCFTRIM (1) +/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ +#define FSL_FEATURE_MCG_HAS_LOLRE (1) +/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ +#define FSL_FEATURE_MCG_USE_OSCSEL (1) +/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ +#define FSL_FEATURE_MCG_USE_PLLREFSEL (0) +/* @brief TBD */ +#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) +/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ +#define FSL_FEATURE_MCG_HAS_PLL (1) +/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) +/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ +#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) +/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ +#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) +/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ +#define FSL_FEATURE_MCG_HAS_FLL (1) +/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) +/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ +#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) +/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) +/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ +#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) +/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ +#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) +/* @brief Has external clock monitor (register bit C6[CME]). */ +#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) +/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ +#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) +/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ +#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) +/* @brief Has PEI mode or PBI mode. */ +#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) +/* @brief Reset clock mode is BLPI. */ +#define FSL_FEATURE_MCG_RESET_IS_BLPI (0) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85) + +/* OSC module features */ + +/* @brief Has OSC1 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC1 (0) +/* @brief Has OSC0 external oscillator. */ +#define FSL_FEATURE_OSC_HAS_OSC0 (0) +/* @brief Has OSC external oscillator (without index). */ +#define FSL_FEATURE_OSC_HAS_OSC (1) +/* @brief Number of OSC external oscillators. */ +#define FSL_FEATURE_OSC_OSC_COUNT (1) +/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ +#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) + +/* PDB module features */ + +/* @brief Define the count of supporting ADC pre-trigger for each channel. */ +#define FSL_FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (2) +/* @brief Has DAC support. */ +#define FSL_FEATURE_PDB_HAS_DAC (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (4) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) + +/* PMC module features */ + +/* @brief Has Bandgap Enable In VLPx Operation support. */ +#define FSL_FEATURE_PMC_HAS_BGEN (1) +/* @brief Has Bandgap Buffer Enable. */ +#define FSL_FEATURE_PMC_HAS_BGBE (1) +/* @brief Has Bandgap Buffer Drive Select. */ +#define FSL_FEATURE_PMC_HAS_BGBDS (0) +/* @brief Has Low-Voltage Detect Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVDV (1) +/* @brief Has Low-Voltage Warning Voltage Select support. */ +#define FSL_FEATURE_PMC_HAS_LVWV (1) +/* @brief Has LPO. */ +#define FSL_FEATURE_PMC_HAS_LPO (0) +/* @brief Has VLPx option PMC_REGSC[VLPO]. */ +#define FSL_FEATURE_PMC_HAS_VLPO (0) +/* @brief Has acknowledge isolation support. */ +#define FSL_FEATURE_PMC_HAS_ACKISO (1) +/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ +#define FSL_FEATURE_PMC_HAS_REGFPM (0) +/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ +#define FSL_FEATURE_PMC_HAS_REGONS (1) +/* @brief Has PMC_HVDSC1. */ +#define FSL_FEATURE_PMC_HAS_HVDSC1 (0) +/* @brief Has PMC_PARAM. */ +#define FSL_FEATURE_PMC_HAS_PARAM (0) +/* @brief Has PMC_VERID. */ +#define FSL_FEATURE_PMC_HAS_VERID (0) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) +/* @brief Has DMA request (register bit field PCR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Has separate drive strength register (HDRVE). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) +/* @brief Has glitch filter (register IOFLT). */ +#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* RCM module features */ + +/* @brief Has Loss-of-Lock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOL (1) +/* @brief Has Loss-of-Clock Reset support. */ +#define FSL_FEATURE_RCM_HAS_LOC (1) +/* @brief Has JTAG generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_JTAG (1) +/* @brief Has EzPort generated Reset support. */ +#define FSL_FEATURE_RCM_HAS_EZPORT (1) +/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ +#define FSL_FEATURE_RCM_HAS_EZPMS (1) +/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ +#define FSL_FEATURE_RCM_HAS_BOOTROM (0) +/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ +#define FSL_FEATURE_RCM_HAS_SSRS (0) +/* @brief Has Version ID Register (RCM_VERID). */ +#define FSL_FEATURE_RCM_HAS_VERID (0) +/* @brief Has Parameter Register (RCM_PARAM). */ +#define FSL_FEATURE_RCM_HAS_PARAM (0) +/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ +#define FSL_FEATURE_RCM_HAS_SRIE (0) +/* @brief Width of registers of the RCM. */ +#define FSL_FEATURE_RCM_REG_WIDTH (8) +/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ +#define FSL_FEATURE_RCM_HAS_CORE1 (0) +/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ +#define FSL_FEATURE_RCM_HAS_MDM_AP (1) +/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ +#define FSL_FEATURE_RCM_HAS_WAKEUP (1) + +/* RTC module features */ + +/* @brief Has wakeup pin. */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) +/* @brief Has wakeup pin selection (bit field CR[WPS]). */ +#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) +/* @brief Has low power features (registers MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_MONOTONIC (0) +/* @brief Has read/write access control (registers WAR and RAR). */ +#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) +/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ +#define FSL_FEATURE_RTC_HAS_SECURITY (0) +/* @brief Has RTC_CLKIN available. */ +#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) +/* @brief Has prescaler adjust for LPO. */ +#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) +/* @brief Has Clock Pin Enable field. */ +#define FSL_FEATURE_RTC_HAS_CPE (0) +/* @brief Has Timer Seconds Interrupt Configuration field. */ +#define FSL_FEATURE_RTC_HAS_TSIC (0) +/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ +#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) + +/* SDHC module features */ + +/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ +#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1) +/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ +#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) +/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ +#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) + +/* SIM module features */ + +/* @brief Has USB FS divider. */ +#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) +/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ +#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) +/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) +/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) +/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) +/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ +#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) +/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) +/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) +/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) +/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) +/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) +/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PCR (0) +/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_MCC (0) +/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ +#define FSL_FEATURE_SIM_OPT_HAS_ODE (0) +/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ +#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) +/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ +#define FSL_FEATURE_SIM_OPT_UART_COUNT (4) +/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) +/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) +/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) +/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) +/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) +/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ +#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) +/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) +/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) +/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) +/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) +/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) +/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) +/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) +/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) +/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) +/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) +/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ +#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) +/* @brief Has FTM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM (1) +/* @brief Number of FTM modules. */ +#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) +/* @brief Number of FTM triggers with selectable source. */ +#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) +/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) +/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) +/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) +/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) +/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) +/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) +/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3) +/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) +/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) +/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ +#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) +/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) +/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ +#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) +/* @brief Has TPM module(s) configuration. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM (0) +/* @brief The highest TPM module index. */ +#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) +/* @brief Has TPM module with index 0. */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) +/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) +/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) +/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) +/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) +/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) +/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) +/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) +/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) +/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ +#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) +/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) +/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) +/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) +/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) +/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) +/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) +/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) +/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) +/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) +/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) +/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) +/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) +/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) +/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) +/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) +/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ +#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) +/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ +#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) +/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) +/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1) +/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) +/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) +/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) +/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) +/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) +/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ +#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) +/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) +/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) +/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) +/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ +#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) +/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) +/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) +/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) +/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) +/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) +/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) +/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) +/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ +#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) +/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) +/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) +/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) +/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) +/* @brief Has device die ID (register bit field SDID[DIEID]). */ +#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) +/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ +#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) +/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) +/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) +/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) +/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) +/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) +/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) +/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) +/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) +/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) +/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) +/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) +/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ +#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) +/* @brief Has miscellanious control register (register MCR). */ +#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) +/* @brief Has COP watchdog (registers COPC and SRVCOP). */ +#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) +/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ +#define FSL_FEATURE_SIM_HAS_COP_STOP (0) +/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ +#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) + +/* SMC module features */ + +/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ +#define FSL_FEATURE_SMC_HAS_PSTOPO (0) +/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ +#define FSL_FEATURE_SMC_HAS_LPOPO (0) +/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ +#define FSL_FEATURE_SMC_HAS_PORPO (1) +/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ +#define FSL_FEATURE_SMC_HAS_LPWUI (1) +/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ +#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) +/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) +/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ +#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) +/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ +#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) +/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ +#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) +/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ +#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ +#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) +/* @brief Has stop submode. */ +#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) +/* @brief Has stop submode 0(VLLS0). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) +/* @brief Has stop submode 2(VLLS2). */ +#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) +/* @brief Has SMC_PARAM. */ +#define FSL_FEATURE_SMC_HAS_PARAM (0) +/* @brief Has SMC_VERID. */ +#define FSL_FEATURE_SMC_HAS_VERID (0) +/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ +#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) +/* @brief Has tamper reset (register bit SRS[TAMPER]). */ +#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) +/* @brief Has security violation reset (register bit SRS[SECVIO]). */ +#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) + +/* DSPI module features */ + +/* @brief Receive/transmit FIFO size in number of items. */ +#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ + ((x) == DSPI0 ? (4) : \ + ((x) == DSPI1 ? (1) : \ + ((x) == DSPI2 ? (1) : (-1)))) +/* @brief Maximum transfer data width in bits. */ +#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) +/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ +#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) +/* @brief Number of chip select pins. */ +#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) +/* @brief Has chip select strobe capability on the PCS5 pin. */ +#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) +/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) +/* @brief Has 16-bit data transfer support. */ +#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ + ((x) == DSPI0 ? (1) : \ + ((x) == DSPI1 ? (0) : \ + ((x) == DSPI2 ? (0) : (-1)))) + +/* SYSMPU module features */ + +/* @brief Specifies number of descriptors available. */ +#define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12) +/* @brief Has process identifier support. */ +#define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) +/* @brief Total number of MPU slave. */ +#define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5) +/* @brief Total number of MPU master. */ +#define FSL_FEATURE_SYSMPU_MASTER_COUNT (6) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* UART module features */ + +#if defined(CPU_MK24FN1M0CAJ12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) + /* @brief If 10-bit mode is supported. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == UART0 ? (8) : \ + ((x) == UART1 ? (8) : \ + ((x) == UART2 ? (1) : \ + ((x) == UART3 ? (1) : \ + ((x) == UART4 ? (1) : \ + ((x) == UART5 ? (1) : (-1))))))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) + /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ + #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) + /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ + #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) + /* @brief Has separate DMA RX and TX requests. */ + #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ + ((x) == UART0 ? (1) : \ + ((x) == UART1 ? (1) : \ + ((x) == UART2 ? (1) : \ + ((x) == UART3 ? (1) : \ + ((x) == UART4 ? (0) : \ + ((x) == UART5 ? (0) : (-1))))))) +#elif defined(CPU_MK24FN1M0VLL12) + /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ + #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) + /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) + /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_HAS_FIFO (1) + /* @brief Hardware flow control (RTS, CTS) is supported. */ + #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) + /* @brief Infrared (modulation) is supported. */ + #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) + /* @brief 2 bits long stop bit is available. */ + #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) + /* @brief If 10-bit mode is supported. */ + #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) + /* @brief Baud rate fine adjustment is available. */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) + /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) + /* @brief Baud rate oversampling is available. */ + #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) + /* @brief Peripheral type. */ + #define FSL_FEATURE_UART_IS_SCI (0) + /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ + #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ + ((x) == UART0 ? (8) : \ + ((x) == UART1 ? (8) : \ + ((x) == UART2 ? (1) : \ + ((x) == UART3 ? (1) : \ + ((x) == UART4 ? (1) : (-1)))))) + /* @brief Maximal data width without parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9) + /* @brief Maximal data width with parity bit. */ + #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10) + /* @brief Supports two match addresses to filter incoming frames. */ + #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) + /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) + /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ + #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) + /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ + #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) + /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ + #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) + /* @brief Has improved smart card (ISO7816 protocol) support. */ + #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) + /* @brief Has local operation network (CEA709.1-B protocol) support. */ + #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) + /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ + #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) + /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ + #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) + /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ + #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) + /* @brief Has separate DMA RX and TX requests. */ + #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ + ((x) == UART0 ? (1) : \ + ((x) == UART1 ? (1) : \ + ((x) == UART2 ? (1) : \ + ((x) == UART3 ? (1) : \ + ((x) == UART4 ? (0) : (-1)))))) +#endif /* defined(CPU_MK24FN1M0CAJ12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) */ + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) + +/* VREF module features */ + +/* @brief Has chop oscillator (bit TRM[CHOPEN]) */ +#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) +/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ +#define FSL_FEATURE_VREF_HAS_COMPENSATION (1) +/* @brief If high/low buffer mode supported */ +#define FSL_FEATURE_VREF_MODE_LV_TYPE (1) +/* @brief Module has also low reference (registers VREFL/VREFH) */ +#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) +/* @brief Has VREF_TRM4. */ +#define FSL_FEATURE_VREF_HAS_TRM4 (0) + +/* WDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) +/* @brief Has Wait mode support. */ +#define FSL_FEATURE_WDOG_HAS_WAITEN (1) + +#endif /* _MK24F12_FEATURES_H_ */ + diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/RTE_Device.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/RTE_Device.h new file mode 100644 index 00000000000..5905d52a7aa --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/RTE_Device.h @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +/* UART select, UART0-UART5 */ +#define RTE_USART0 0 +#define RTE_USART0_DMA_EN 0 +#define RTE_USART1 0 +#define RTE_USART1_DMA_EN 0 +#define RTE_USART2 0 +#define RTE_USART2_DMA_EN 0 +#define RTE_USART3 0 +#define RTE_USART3_DMA_EN 0 +#define RTE_USART4 0 +#define RTE_USART4_DMA_EN 0 +#define RTE_USART5 0 +#define RTE_USART5_DMA_EN 0 + +/* UART RX Buffer configuration. */ +#define USART_RX_BUFFER_LEN 64 +#define USART0_RX_BUFFER_ENABLE 0 +#define USART1_RX_BUFFER_ENABLE 0 +#define USART2_RX_BUFFER_ENABLE 0 +#define USART3_RX_BUFFER_ENABLE 0 +#define USART4_RX_BUFFER_ENABLE 0 +#define USART5_RX_BUFFER_ENABLE 0 + +#define RTE_USART0_DMA_TX_CH 0 +#define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Tx +#define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 +#define RTE_USART0_DMA_TX_DMA_BASE DMA0 +#define RTE_USART0_DMA_RX_CH 1 +#define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Rx +#define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0 +#define RTE_USART0_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART1_DMA_TX_CH 0 +#define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx +#define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0 +#define RTE_USART1_DMA_TX_DMA_BASE DMA0 +#define RTE_USART1_DMA_RX_CH 1 +#define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx +#define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0 +#define RTE_USART1_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART2_DMA_TX_CH 0 +#define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx +#define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0 +#define RTE_USART2_DMA_TX_DMA_BASE DMA0 +#define RTE_USART2_DMA_RX_CH 1 +#define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx +#define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0 +#define RTE_USART2_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART3_DMA_TX_CH 0 +#define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Tx +#define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX0 +#define RTE_USART3_DMA_TX_DMA_BASE DMA0 +#define RTE_USART3_DMA_RX_CH 1 +#define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Rx +#define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX0 +#define RTE_USART3_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART4_DMA_TX_CH 0 +#define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART4 +#define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX0 +#define RTE_USART4_DMA_TX_DMA_BASE DMA0 +#define RTE_USART4_DMA_RX_CH 1 +#define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART4 +#define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX0 +#define RTE_USART4_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART5_DMA_TX_CH 0 +#define RTE_USART5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART5 +#define RTE_USART5_DMA_TX_DMAMUX_BASE DMAMUX0 +#define RTE_USART5_DMA_TX_DMA_BASE DMA0 +#define RTE_USART5_DMA_RX_CH 1 +#define RTE_USART5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART5 +#define RTE_USART5_DMA_RX_DMAMUX_BASE DMAMUX0 +#define RTE_USART5_DMA_RX_DMA_BASE DMA0 + + +/* I2C select, I2C0 - I2C2. */ +#define RTE_I2C0 0 +#define RTE_I2C0_DMA_EN 0 +#define RTE_I2C1 0 +#define RTE_I2C1_DMA_EN 0 +#define RTE_I2C2 0 +#define RTE_I2C2_DMA_EN 0 + +/*I2C configuration*/ +#define RTE_I2C0_Master_DMA_BASE DMA0 +#define RTE_I2C0_Master_DMA_CH 0 +#define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0 +#define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 + +#define RTE_I2C1_Master_DMA_BASE DMA0 +#define RTE_I2C1_Master_DMA_CH 1 +#define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0 +#define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1 + +#define RTE_I2C2_Master_DMA_BASE DMA0 +#define RTE_I2C2_Master_DMA_CH 2 +#define RTE_I2C2_Master_DMAMUX_BASE DMAMUX0 +#define RTE_I2C2_Master_PERI_SEL kDmaRequestMux0I2C2 + +/* SPI select, DSPI0 - DSPI2. */ +#define RTE_SPI0 0 +#define RTE_SPI0_DMA_EN 0 +#define RTE_SPI1 0 +#define RTE_SPI1_DMA_EN 0 +#define RTE_SPI2 0 +#define RTE_SPI2_DMA_EN 0 + +/* DSPI configuration. */ +#define RTE_SPI0_PCS_TO_SCK_DELAY 1000 +#define RTE_SPI0_SCK_TO_PSC_DELAY 1000 +#define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 +#define RTE_SPI0_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 +#define RTE_SPI0_DMA_TX_CH 0 +#define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx +#define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0 +#define RTE_SPI0_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI0_DMA_RX_CH 1 +#define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx +#define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0 +#define RTE_SPI0_DMA_RX_DMA_BASE DMA0 +#define RTE_SPI0_DMA_LINK_DMA_BASE DMA0 +#define RTE_SPI0_DMA_LINK_CH 2 + +#define RTE_SPI1_PCS_TO_SCK_DELAY 1000 +#define RTE_SPI1_SCK_TO_PSC_DELAY 1000 +#define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 +#define RTE_SPI1_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 +#define RTE_SPI1_DMA_TX_CH 4 +#define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1 +#define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0 +#define RTE_SPI1_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI1_DMA_RX_CH 3 +#define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1 +#define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0 +#define RTE_SPI1_DMA_RX_DMA_BASE DMA0 +#define RTE_SPI1_DMA_LINK_DMA_BASE DMA0 +#define RTE_SPI1_DMA_LINK_CH 2 + +#define RTE_SPI2_PCS_TO_SCK_DELAY 1000 +#define RTE_SPI2_SCK_TO_PSC_DELAY 1000 +#define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000 +#define RTE_SPI2_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 +#define RTE_SPI2_DMA_TX_CH 6 +#define RTE_SPI2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2 +#define RTE_SPI2_DMA_TX_DMAMUX_BASE DMAMUX0 +#define RTE_SPI2_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI2_DMA_RX_CH 7 +#define RTE_SPI2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2 +#define RTE_SPI2_DMA_RX_DMAMUX_BASE DMAMUX0 +#define RTE_SPI2_DMA_RX_DMA_BASE DMA0 +#define RTE_SPI2_DMA_LINK_DMA_BASE DMA0 +#define RTE_SPI2_DMA_LINK_CH 8 + +#endif /* __RTE_DEVICE_H */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/MK24FN1M0xxx12.sct b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/MK24FN1M0xxx12.sct new file mode 100644 index 00000000000..7cee92692d5 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/MK24FN1M0xxx12.sct @@ -0,0 +1,96 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MK24FN1M0CAJ12 +** MK24FN1M0VDC12 +** MK24FN1M0VLL12 +** MK24FN1M0VLQ12 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: K24P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.8, 2016-03-21 +** Build: b160321 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ +#define __ram_vector_table__ 1 + +#if (defined(__ram_vector_table__)) + #define __ram_vector_table_size__ 0x00000400 +#else + #define __ram_vector_table_size__ 0x00000000 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_flash_config_start 0x00000400 +#define m_flash_config_size 0x00000010 + +#define m_text_start 0x00000410 +#define m_text_size 0x000FFBF0 + +#define m_interrupts_ram_start 0x1FFF0000 +#define m_interrupts_ram_size __ram_vector_table_size__ + +#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) +#define m_data_size (0x00010000 - m_interrupts_ram_size) + +#define m_data_2_start 0x20000000 +#define m_data_2_size 0x00030000 + + +LR_m_text m_interrupts_start m_text_size+m_interrupts_size+m_flash_config_size { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_flash_config m_flash_config_start m_flash_config_size { ; load address = execution address + * (FlashConfig) + } + ER_m_text m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM1 m_data_2_start m_data_2_size { ; RW data + .ANY (+RW +ZI) + } + VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { + } +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/startup_MK24F12.s b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/startup_MK24F12.s new file mode 100644 index 00000000000..ddfb954790a --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/startup_MK24F12.s @@ -0,0 +1,1023 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MK24F12.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File +; * MK24F12 +; * @version: 2.8 +; * @date: 2016-3-21 +; * @build: b160321 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + +__initial_sp EQU 0x20030000 ; Top of RAM + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete + DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete + DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete + DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete + DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete + DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete + DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete + DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete + DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete + DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete + DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete + DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete + DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete + DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete + DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete + DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete + DCD DMA_Error_IRQHandler ;DMA Error Interrupt + DCD MCM_IRQHandler ;Normal Interrupt + DCD FTFE_IRQHandler ;FTFE Command complete interrupt + DCD Read_Collision_IRQHandler ;Read Collision Interrupt + DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit + DCD WDOG_EWM_IRQHandler ;WDOG Interrupt + DCD RNG_IRQHandler ;RNG Interrupt + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 Interrupt + DCD SPI1_IRQHandler ;SPI1 Interrupt + DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt + DCD UART0_LON_IRQHandler ;UART0 LON interrupt + DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt + DCD UART0_ERR_IRQHandler ;UART0 Error interrupt + DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt + DCD UART1_ERR_IRQHandler ;UART1 Error interrupt + DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt + DCD UART2_ERR_IRQHandler ;UART2 Error interrupt + DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt + DCD UART3_ERR_IRQHandler ;UART3 Error interrupt + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD CMP1_IRQHandler ;CMP1 interrupt + DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt + DCD CMT_IRQHandler ;CMT interrupt + DCD RTC_IRQHandler ;RTC interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ;PDB0 Interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD USBDCD_IRQHandler ;USBDCD Interrupt + DCD Reserved71_IRQHandler ;Reserved interrupt 71 + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD MCG_IRQHandler ;MCG Interrupt + DCD LPTMR0_IRQHandler ;LPTimer interrupt + DCD PORTA_IRQHandler ;Port A interrupt + DCD PORTB_IRQHandler ;Port B interrupt + DCD PORTC_IRQHandler ;Port C interrupt + DCD PORTD_IRQHandler ;Port D interrupt + DCD PORTE_IRQHandler ;Port E interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD SPI2_IRQHandler ;SPI2 Interrupt + DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt + DCD UART4_ERR_IRQHandler ;UART4 Error interrupt + DCD UART5_RX_TX_IRQHandler ;UART5 Receive/Transmit interrupt + DCD UART5_ERR_IRQHandler ;UART5 Error interrupt + DCD CMP2_IRQHandler ;CMP2 interrupt + DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt + DCD DAC1_IRQHandler ;DAC1 interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD I2C2_IRQHandler ;I2C2 interrupt + DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt + DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt + DCD CAN0_Error_IRQHandler ;CAN0 error interrupt + DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt + DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt + DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt + DCD SDHC_IRQHandler ;SDHC interrupt + DCD Reserved98_IRQHandler ;Reserved interrupt 98 + DCD Reserved99_IRQHandler ;Reserved interrupt 99 + DCD Reserved100_IRQHandler ;Reserved interrupt 100 + DCD Reserved101_IRQHandler ;Reserved interrupt 101 + DCD DefaultISR ;102 + DCD DefaultISR ;103 + DCD DefaultISR ;104 + DCD DefaultISR ;105 + DCD DefaultISR ;106 + DCD DefaultISR ;107 + DCD DefaultISR ;108 + DCD DefaultISR ;109 + DCD DefaultISR ;110 + DCD DefaultISR ;111 + DCD DefaultISR ;112 + DCD DefaultISR ;113 + DCD DefaultISR ;114 + DCD DefaultISR ;115 + DCD DefaultISR ;116 + DCD DefaultISR ;117 + DCD DefaultISR ;118 + DCD DefaultISR ;119 + DCD DefaultISR ;120 + DCD DefaultISR ;121 + DCD DefaultISR ;122 + DCD DefaultISR ;123 + DCD DefaultISR ;124 + DCD DefaultISR ;125 + DCD DefaultISR ;126 + DCD DefaultISR ;127 + DCD DefaultISR ;128 + DCD DefaultISR ;129 + DCD DefaultISR ;130 + DCD DefaultISR ;131 + DCD DefaultISR ;132 + DCD DefaultISR ;133 + DCD DefaultISR ;134 + DCD DefaultISR ;135 + DCD DefaultISR ;136 + DCD DefaultISR ;137 + DCD DefaultISR ;138 + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; Flash Configuration +; 16-byte flash configuration field that stores default protection settings (loaded on reset) +; and security information that allows the MCU to restrict access to the FTFL module. +; Backdoor Comparison Key +; Backdoor Comparison Key 0. <0x0-0xFF:2> +; Backdoor Comparison Key 1. <0x0-0xFF:2> +; Backdoor Comparison Key 2. <0x0-0xFF:2> +; Backdoor Comparison Key 3. <0x0-0xFF:2> +; Backdoor Comparison Key 4. <0x0-0xFF:2> +; Backdoor Comparison Key 5. <0x0-0xFF:2> +; Backdoor Comparison Key 6. <0x0-0xFF:2> +; Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; +; Program flash protection bytes (FPROT) +; Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; Each bit protects a 1/32 region of the program flash memory. +; FPROT0 +; Program Flash Region Protect Register 0 +; 1/32 - 8/32 region +; FPROT0.0 +; FPROT0.1 +; FPROT0.2 +; FPROT0.3 +; FPROT0.4 +; FPROT0.5 +; FPROT0.6 +; FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; +; FPROT1 +; Program Flash Region Protect Register 1 +; 9/32 - 16/32 region +; FPROT1.0 +; FPROT1.1 +; FPROT1.2 +; FPROT1.3 +; FPROT1.4 +; FPROT1.5 +; FPROT1.6 +; FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; +; FPROT2 +; Program Flash Region Protect Register 2 +; 17/32 - 24/32 region +; FPROT2.0 +; FPROT2.1 +; FPROT2.2 +; FPROT2.3 +; FPROT2.4 +; FPROT2.5 +; FPROT2.6 +; FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; +; FPROT3 +; Program Flash Region Protect Register 3 +; 25/32 - 32/32 region +; FPROT3.0 +; FPROT3.1 +; FPROT3.2 +; FPROT3.3 +; FPROT3.4 +; FPROT3.5 +; FPROT3.6 +; FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; +; +; Data flash protection byte (FDPROT) +; Each bit protects a 1/8 region of the data flash memory. +; (Program flash only devices: Reserved) +; FDPROT.0 +; FDPROT.1 +; FDPROT.2 +; FDPROT.3 +; FDPROT.4 +; FDPROT.5 +; FDPROT.6 +; FDPROT.7 +nFDPROT EQU 0x00 +FDPROT EQU nFDPROT:EOR:0xFF +; +; EEPROM protection byte (FEPROT) +; FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. +; (Program flash only devices: Reserved) +; FEPROT.0 +; FEPROT.1 +; FEPROT.2 +; FEPROT.3 +; FEPROT.4 +; FEPROT.5 +; FEPROT.6 +; FEPROT.7 +nFEPROT EQU 0x00 +FEPROT EQU nFEPROT:EOR:0xFF +; +; Flash nonvolatile option byte (FOPT) +; Allows the user to customize the operation of the MCU at boot time. +; LPBOOT +; <0=> Low-power boot +; <1=> Normal boot +; EZPORT_DIS +; <0=> EzPort operation is disabled +; <1=> EzPort operation is enabled +FOPT EQU 0xFF +; +; Flash security byte (FSEC) +; WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; Flash Security +; FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; Freescale Failure Analysis Access Code +; MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; Backdoor Key Security Enable +FSEC EQU 0xFE +; +; + IF :LNOT::DEF:RAM_TARGET + AREA FlashConfig, DATA, READONLY +__FlashConfig + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , FEPROT , FDPROT + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + IF :LNOT::DEF:RAM_TARGET + REQUIRE FlashConfig + ENDIF + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +DMA1_IRQHandler\ + PROC + EXPORT DMA1_IRQHandler [WEAK] + LDR R0, =DMA1_DriverIRQHandler + BX R0 + ENDP + +DMA2_IRQHandler\ + PROC + EXPORT DMA2_IRQHandler [WEAK] + LDR R0, =DMA2_DriverIRQHandler + BX R0 + ENDP + +DMA3_IRQHandler\ + PROC + EXPORT DMA3_IRQHandler [WEAK] + LDR R0, =DMA3_DriverIRQHandler + BX R0 + ENDP + +DMA4_IRQHandler\ + PROC + EXPORT DMA4_IRQHandler [WEAK] + LDR R0, =DMA4_DriverIRQHandler + BX R0 + ENDP + +DMA5_IRQHandler\ + PROC + EXPORT DMA5_IRQHandler [WEAK] + LDR R0, =DMA5_DriverIRQHandler + BX R0 + ENDP + +DMA6_IRQHandler\ + PROC + EXPORT DMA6_IRQHandler [WEAK] + LDR R0, =DMA6_DriverIRQHandler + BX R0 + ENDP + +DMA7_IRQHandler\ + PROC + EXPORT DMA7_IRQHandler [WEAK] + LDR R0, =DMA7_DriverIRQHandler + BX R0 + ENDP + +DMA8_IRQHandler\ + PROC + EXPORT DMA8_IRQHandler [WEAK] + LDR R0, =DMA8_DriverIRQHandler + BX R0 + ENDP + +DMA9_IRQHandler\ + PROC + EXPORT DMA9_IRQHandler [WEAK] + LDR R0, =DMA9_DriverIRQHandler + BX R0 + ENDP + +DMA10_IRQHandler\ + PROC + EXPORT DMA10_IRQHandler [WEAK] + LDR R0, =DMA10_DriverIRQHandler + BX R0 + ENDP + +DMA11_IRQHandler\ + PROC + EXPORT DMA11_IRQHandler [WEAK] + LDR R0, =DMA11_DriverIRQHandler + BX R0 + ENDP + +DMA12_IRQHandler\ + PROC + EXPORT DMA12_IRQHandler [WEAK] + LDR R0, =DMA12_DriverIRQHandler + BX R0 + ENDP + +DMA13_IRQHandler\ + PROC + EXPORT DMA13_IRQHandler [WEAK] + LDR R0, =DMA13_DriverIRQHandler + BX R0 + ENDP + +DMA14_IRQHandler\ + PROC + EXPORT DMA14_IRQHandler [WEAK] + LDR R0, =DMA14_DriverIRQHandler + BX R0 + ENDP + +DMA15_IRQHandler\ + PROC + EXPORT DMA15_IRQHandler [WEAK] + LDR R0, =DMA15_DriverIRQHandler + BX R0 + ENDP + +DMA_Error_IRQHandler\ + PROC + EXPORT DMA_Error_IRQHandler [WEAK] + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + ENDP + +I2C0_IRQHandler\ + PROC + EXPORT I2C0_IRQHandler [WEAK] + LDR R0, =I2C0_DriverIRQHandler + BX R0 + ENDP + +I2C1_IRQHandler\ + PROC + EXPORT I2C1_IRQHandler [WEAK] + LDR R0, =I2C1_DriverIRQHandler + BX R0 + ENDP + +SPI0_IRQHandler\ + PROC + EXPORT SPI0_IRQHandler [WEAK] + LDR R0, =SPI0_DriverIRQHandler + BX R0 + ENDP + +SPI1_IRQHandler\ + PROC + EXPORT SPI1_IRQHandler [WEAK] + LDR R0, =SPI1_DriverIRQHandler + BX R0 + ENDP + +I2S0_Tx_IRQHandler\ + PROC + EXPORT I2S0_Tx_IRQHandler [WEAK] + LDR R0, =I2S0_Tx_DriverIRQHandler + BX R0 + ENDP + +I2S0_Rx_IRQHandler\ + PROC + EXPORT I2S0_Rx_IRQHandler [WEAK] + LDR R0, =I2S0_Rx_DriverIRQHandler + BX R0 + ENDP + +UART0_LON_IRQHandler\ + PROC + EXPORT UART0_LON_IRQHandler [WEAK] + LDR R0, =UART0_LON_DriverIRQHandler + BX R0 + ENDP + +UART0_RX_TX_IRQHandler\ + PROC + EXPORT UART0_RX_TX_IRQHandler [WEAK] + LDR R0, =UART0_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART0_ERR_IRQHandler\ + PROC + EXPORT UART0_ERR_IRQHandler [WEAK] + LDR R0, =UART0_ERR_DriverIRQHandler + BX R0 + ENDP + +UART1_RX_TX_IRQHandler\ + PROC + EXPORT UART1_RX_TX_IRQHandler [WEAK] + LDR R0, =UART1_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART1_ERR_IRQHandler\ + PROC + EXPORT UART1_ERR_IRQHandler [WEAK] + LDR R0, =UART1_ERR_DriverIRQHandler + BX R0 + ENDP + +UART2_RX_TX_IRQHandler\ + PROC + EXPORT UART2_RX_TX_IRQHandler [WEAK] + LDR R0, =UART2_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART2_ERR_IRQHandler\ + PROC + EXPORT UART2_ERR_IRQHandler [WEAK] + LDR R0, =UART2_ERR_DriverIRQHandler + BX R0 + ENDP + +UART3_RX_TX_IRQHandler\ + PROC + EXPORT UART3_RX_TX_IRQHandler [WEAK] + LDR R0, =UART3_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART3_ERR_IRQHandler\ + PROC + EXPORT UART3_ERR_IRQHandler [WEAK] + LDR R0, =UART3_ERR_DriverIRQHandler + BX R0 + ENDP + +SPI2_IRQHandler\ + PROC + EXPORT SPI2_IRQHandler [WEAK] + LDR R0, =SPI2_DriverIRQHandler + BX R0 + ENDP + +UART4_RX_TX_IRQHandler\ + PROC + EXPORT UART4_RX_TX_IRQHandler [WEAK] + LDR R0, =UART4_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART4_ERR_IRQHandler\ + PROC + EXPORT UART4_ERR_IRQHandler [WEAK] + LDR R0, =UART4_ERR_DriverIRQHandler + BX R0 + ENDP + +UART5_RX_TX_IRQHandler\ + PROC + EXPORT UART5_RX_TX_IRQHandler [WEAK] + LDR R0, =UART5_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART5_ERR_IRQHandler\ + PROC + EXPORT UART5_ERR_IRQHandler [WEAK] + LDR R0, =UART5_ERR_DriverIRQHandler + BX R0 + ENDP + +I2C2_IRQHandler\ + PROC + EXPORT I2C2_IRQHandler [WEAK] + LDR R0, =I2C2_DriverIRQHandler + BX R0 + ENDP + +CAN0_ORed_Message_buffer_IRQHandler\ + PROC + EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Bus_Off_IRQHandler\ + PROC + EXPORT CAN0_Bus_Off_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Error_IRQHandler\ + PROC + EXPORT CAN0_Error_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Tx_Warning_IRQHandler\ + PROC + EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Rx_Warning_IRQHandler\ + PROC + EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Wake_Up_IRQHandler\ + PROC + EXPORT CAN0_Wake_Up_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +SDHC_IRQHandler\ + PROC + EXPORT SDHC_IRQHandler [WEAK] + LDR R0, =SDHC_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT DMA1_DriverIRQHandler [WEAK] + EXPORT DMA2_DriverIRQHandler [WEAK] + EXPORT DMA3_DriverIRQHandler [WEAK] + EXPORT DMA4_DriverIRQHandler [WEAK] + EXPORT DMA5_DriverIRQHandler [WEAK] + EXPORT DMA6_DriverIRQHandler [WEAK] + EXPORT DMA7_DriverIRQHandler [WEAK] + EXPORT DMA8_DriverIRQHandler [WEAK] + EXPORT DMA9_DriverIRQHandler [WEAK] + EXPORT DMA10_DriverIRQHandler [WEAK] + EXPORT DMA11_DriverIRQHandler [WEAK] + EXPORT DMA12_DriverIRQHandler [WEAK] + EXPORT DMA13_DriverIRQHandler [WEAK] + EXPORT DMA14_DriverIRQHandler [WEAK] + EXPORT DMA15_DriverIRQHandler [WEAK] + EXPORT DMA_Error_DriverIRQHandler [WEAK] + EXPORT MCM_IRQHandler [WEAK] + EXPORT FTFE_IRQHandler [WEAK] + EXPORT Read_Collision_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT WDOG_EWM_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT I2C0_DriverIRQHandler [WEAK] + EXPORT I2C1_DriverIRQHandler [WEAK] + EXPORT SPI0_DriverIRQHandler [WEAK] + EXPORT SPI1_DriverIRQHandler [WEAK] + EXPORT I2S0_Tx_DriverIRQHandler [WEAK] + EXPORT I2S0_Rx_DriverIRQHandler [WEAK] + EXPORT UART0_LON_DriverIRQHandler [WEAK] + EXPORT UART0_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART0_ERR_DriverIRQHandler [WEAK] + EXPORT UART1_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART1_ERR_DriverIRQHandler [WEAK] + EXPORT UART2_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART2_ERR_DriverIRQHandler [WEAK] + EXPORT UART3_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART3_ERR_DriverIRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT FTM0_IRQHandler [WEAK] + EXPORT FTM1_IRQHandler [WEAK] + EXPORT FTM2_IRQHandler [WEAK] + EXPORT CMT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT PIT1_IRQHandler [WEAK] + EXPORT PIT2_IRQHandler [WEAK] + EXPORT PIT3_IRQHandler [WEAK] + EXPORT PDB0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USBDCD_IRQHandler [WEAK] + EXPORT Reserved71_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT SWI_IRQHandler [WEAK] + EXPORT SPI2_DriverIRQHandler [WEAK] + EXPORT UART4_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART4_ERR_DriverIRQHandler [WEAK] + EXPORT UART5_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART5_ERR_DriverIRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT FTM3_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT I2C2_DriverIRQHandler [WEAK] + EXPORT CAN0_DriverIRQHandler [WEAK] + EXPORT SDHC_DriverIRQHandler [WEAK] + EXPORT Reserved98_IRQHandler [WEAK] + EXPORT Reserved99_IRQHandler [WEAK] + EXPORT Reserved100_IRQHandler [WEAK] + EXPORT Reserved101_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +DMA8_DriverIRQHandler +DMA9_DriverIRQHandler +DMA10_DriverIRQHandler +DMA11_DriverIRQHandler +DMA12_DriverIRQHandler +DMA13_DriverIRQHandler +DMA14_DriverIRQHandler +DMA15_DriverIRQHandler +DMA_Error_DriverIRQHandler +MCM_IRQHandler +FTFE_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +WDOG_EWM_IRQHandler +RNG_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +I2S0_Tx_DriverIRQHandler +I2S0_Rx_DriverIRQHandler +UART0_LON_DriverIRQHandler +UART0_RX_TX_DriverIRQHandler +UART0_ERR_DriverIRQHandler +UART1_RX_TX_DriverIRQHandler +UART1_ERR_DriverIRQHandler +UART2_RX_TX_DriverIRQHandler +UART2_ERR_DriverIRQHandler +UART3_RX_TX_DriverIRQHandler +UART3_ERR_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +Reserved71_IRQHandler +DAC0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +SPI2_DriverIRQHandler +UART4_RX_TX_DriverIRQHandler +UART4_ERR_DriverIRQHandler +UART5_RX_TX_DriverIRQHandler +UART5_ERR_DriverIRQHandler +CMP2_IRQHandler +FTM3_IRQHandler +DAC1_IRQHandler +ADC1_IRQHandler +I2C2_DriverIRQHandler +CAN0_DriverIRQHandler +SDHC_DriverIRQHandler +Reserved98_IRQHandler +Reserved99_IRQHandler +Reserved100_IRQHandler +Reserved101_IRQHandler +DefaultISR + B DefaultISR + ENDP + ALIGN + + + END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 00000000000..2438e9db8cb --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2017 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/MK24FN1M0xxx12.ld b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/MK24FN1M0xxx12.ld new file mode 100644 index 00000000000..4847b765165 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/MK24FN1M0xxx12.ld @@ -0,0 +1,363 @@ +/* +** ################################################################### +** Processors: MK64FN1M0VDC12 +** MK64FN1M0VLL12 +** MK64FN1M0VLQ12 +** MK64FN1M0VMD12 +** +** Compiler: GNU C Compiler +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151217 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +__ram_vector_table__ = 1; + +/* Heap 1/4 of ram and stack 1/8 */ +__stack_size__ = 0x8000; +__heap_size__ = 0x10000; + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 + m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x000FFBF0 + m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 + m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .flash_config : + { + . = ALIGN(4); + KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */ + . = ALIGN(4); + } > m_flash_config + + /* The program code and other data goes into internal flash */ + /* Note: The uVisor expects this section at a fixed location, as specified by + * the porting process configuration parameter: FLASH_OFFSET. */ + __UVISOR_TEXT_OFFSET = 0x410; + __UVISOR_TEXT_START = ORIGIN(m_interrupts) + __UVISOR_TEXT_OFFSET; + .text __UVISOR_TEXT_START : + { + /* uVisor code and data */ + . = ALIGN(4); + __uvisor_main_start = .; + *(.uvisor.main) + __uvisor_main_end = .; + + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + .interrupts_ram : + { + . = ALIGN(4); + __VECTOR_RAM__ = .; + __interrupts_ram_start__ = .; /* Create a global symbol at data start */ + *(.m_interrupts_ram) /* This is a user defined section */ + . += M_VECTOR_RAM_SIZE; + . = ALIGN(4); + __interrupts_ram_end__ = .; /* Define a global symbol at data end */ + } > m_data + + /* Ensure that the uVisor BSS section is put first after the relocated + * interrupt table in SRAM. */ + /* Note: The uVisor expects this section at a fixed location, as specified by + * the porting process configuration parameter: SRAM_OFFSET. */ + __UVISOR_SRAM_OFFSET = 0x400; + __UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET; + ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START, + "The ISR relocation region overlaps with the uVisor BSS section.") + .uvisor.bss __UVISOR_BSS_START (NOLOAD): + { + . = ALIGN(32); + __uvisor_bss_start = .; + + /* protected uvisor main bss */ + . = ALIGN(32); + __uvisor_bss_main_start = .; + KEEP(*(.keep.uvisor.bss.main)) + . = ALIGN(32); + __uvisor_bss_main_end = .; + + /* protected uvisor secure boxes bss */ + . = ALIGN(32); + __uvisor_bss_boxes_start = .; + KEEP(*(.keep.uvisor.bss.boxes)) + . = ALIGN(32); + __uvisor_bss_boxes_end = .; + + . = ALIGN(32); + __uvisor_bss_end = .; + } > m_data + + /* Heap space for the page allocator */ + .page_heap (NOLOAD) : + { + . = ALIGN(32); + __uvisor_page_start = .; + KEEP(*(.keep.uvisor.page_heap)) + . = ALIGN(32); + __uvisor_page_end = .; + } > m_data_2 + + __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts); + __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0; + + .data : + { + PROVIDE(__etext = LOADADDR(.data)); /* Define a global symbol at end of code, */ + PROVIDE(__DATA_ROM = LOADADDR(.data)); /* Symbol is used by startup for data initialization. */ + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data_2 AT > m_text + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* uVisor configuration section + * This section must be located after all other flash regions. */ + .uvisor.secure : + { + . = ALIGN(32); + __uvisor_secure_start = .; + + /* uVisor secure boxes configuration tables */ + . = ALIGN(32); + __uvisor_cfgtbl_start = .; + KEEP(*(.keep.uvisor.cfgtbl)) + . = ALIGN(32); + __uvisor_cfgtbl_end = .; + + /* Pointers to the uVisor secure boxes configuration tables */ + /* Note: Do not add any further alignment here, as uVisor will need to have + * access to the exact list of pointers. */ + __uvisor_cfgtbl_ptr_start = .; + KEEP(*(.keep.uvisor.cfgtbl_ptr_first)) + KEEP(*(.keep.uvisor.cfgtbl_ptr)) + __uvisor_cfgtbl_ptr_end = .; + + /* Pointers to all boxes register gateways. These are grouped here to allow + * discoverability and firmware verification. */ + __uvisor_register_gateway_ptr_start = .; + KEEP(*(.keep.uvisor.register_gateway_ptr)) + __uvisor_register_gateway_ptr_end = .; + + . = ALIGN(32); + __uvisor_secure_end = .; + } > m_text + + /* Uninitialized data section + * This region is not initialized by the C/C++ library and can be used to + * store state across soft reboots. */ + .uninitialized (NOLOAD): + { + . = ALIGN(32); + __uninitialized_start = .; + *(.uninitialized) + KEEP(*(.keep.uninitialized)) + . = ALIGN(32); + __uninitialized_end = .; + } > m_data_2 + + USB_RAM_GAP = DEFINED(__usb_ram_size__) ? __usb_ram_size__ : 0x800; + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + . = ALIGN(512); + USB_RAM_START = .; + . += USB_RAM_GAP; + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data_2 + + .heap : + { + . = ALIGN(8); + __uvisor_heap_start = .; + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + __uvisor_heap_end = .; + } > m_data_2 + + m_usb_bdt USB_RAM_START (NOLOAD) : + { + *(m_usb_bdt) + USB_RAM_BDT_END = .; + } + + m_usb_global USB_RAM_BDT_END (NOLOAD) : + { + *(m_usb_global) + } + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap") + + /* Provide the physical memory boundaries for uVisor. */ + __uvisor_flash_start = ORIGIN(m_interrupts); + __uvisor_flash_end = ORIGIN(m_text) + LENGTH(m_text); + __uvisor_sram_start = ORIGIN(m_data); + __uvisor_sram_end = ORIGIN(m_data_2) + LENGTH(m_data_2); +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/startup_MK24F12.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/startup_MK24F12.S new file mode 100644 index 00000000000..d9e1c5b92ba --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_GCC_ARM/startup_MK24F12.S @@ -0,0 +1,958 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: startup_MK24F12.s */ +/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ +/* MK24F12 */ +/* @version: 2.8 */ +/* @date: 2016-3-21 */ +/* @build: b170112 */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. */ +/* Copyright 2016 - 2017 NXP */ +/* Redistribution and use in source and binary forms, with or without modification, */ +/* are permitted provided that the following conditions are met: */ +/* */ +/* o Redistributions of source code must retain the above copyright notice, this list */ +/* of conditions and the following disclaimer. */ +/* */ +/* o Redistributions in binary form must reproduce the above copyright notice, this */ +/* list of conditions and the following disclaimer in the documentation and/or */ +/* other materials provided with the distribution. */ +/* */ +/* o Neither the name of the copyright holder nor the names of its */ +/* contributors may be used to endorse or promote products derived from this */ +/* software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ +/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ +/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ +/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ +/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ +/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ +/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/ + .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/ + .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/ + .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/ + .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/ + .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/ + .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/ + .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/ + .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/ + .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/ + .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/ + .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/ + .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/ + .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/ + .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/ + .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/ + .long DMA_Error_IRQHandler /* DMA Error Interrupt*/ + .long MCM_IRQHandler /* Normal Interrupt*/ + .long FTFE_IRQHandler /* FTFE Command complete interrupt*/ + .long Read_Collision_IRQHandler /* Read Collision Interrupt*/ + .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/ + .long LLWU_IRQHandler /* Low Leakage Wakeup Unit*/ + .long WDOG_EWM_IRQHandler /* WDOG Interrupt*/ + .long RNG_IRQHandler /* RNG Interrupt*/ + .long I2C0_IRQHandler /* I2C0 interrupt*/ + .long I2C1_IRQHandler /* I2C1 interrupt*/ + .long SPI0_IRQHandler /* SPI0 Interrupt*/ + .long SPI1_IRQHandler /* SPI1 Interrupt*/ + .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/ + .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/ + .long UART0_LON_IRQHandler /* UART0 LON interrupt*/ + .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/ + .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/ + .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/ + .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/ + .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/ + .long UART2_ERR_IRQHandler /* UART2 Error interrupt*/ + .long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt*/ + .long UART3_ERR_IRQHandler /* UART3 Error interrupt*/ + .long ADC0_IRQHandler /* ADC0 interrupt*/ + .long CMP0_IRQHandler /* CMP0 interrupt*/ + .long CMP1_IRQHandler /* CMP1 interrupt*/ + .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/ + .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/ + .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/ + .long CMT_IRQHandler /* CMT interrupt*/ + .long RTC_IRQHandler /* RTC interrupt*/ + .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/ + .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/ + .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/ + .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/ + .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/ + .long PDB0_IRQHandler /* PDB0 Interrupt*/ + .long USB0_IRQHandler /* USB0 interrupt*/ + .long USBDCD_IRQHandler /* USBDCD Interrupt*/ + .long Reserved71_IRQHandler /* Reserved interrupt 71*/ + .long DAC0_IRQHandler /* DAC0 interrupt*/ + .long MCG_IRQHandler /* MCG Interrupt*/ + .long LPTMR0_IRQHandler /* LPTimer interrupt*/ + .long PORTA_IRQHandler /* Port A interrupt*/ + .long PORTB_IRQHandler /* Port B interrupt*/ + .long PORTC_IRQHandler /* Port C interrupt*/ + .long PORTD_IRQHandler /* Port D interrupt*/ + .long PORTE_IRQHandler /* Port E interrupt*/ + .long SWI_IRQHandler /* Software interrupt*/ + .long SPI2_IRQHandler /* SPI2 Interrupt*/ + .long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt*/ + .long UART4_ERR_IRQHandler /* UART4 Error interrupt*/ + .long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt*/ + .long UART5_ERR_IRQHandler /* UART5 Error interrupt*/ + .long CMP2_IRQHandler /* CMP2 interrupt*/ + .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/ + .long DAC1_IRQHandler /* DAC1 interrupt*/ + .long ADC1_IRQHandler /* ADC1 interrupt*/ + .long I2C2_IRQHandler /* I2C2 interrupt*/ + .long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/ + .long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/ + .long CAN0_Error_IRQHandler /* CAN0 error interrupt*/ + .long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/ + .long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/ + .long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/ + .long SDHC_IRQHandler /* SDHC interrupt*/ + .long Reserved98_IRQHandler /* Reserved interrupt 98*/ + .long Reserved99_IRQHandler /* Reserved interrupt 99*/ + .long Reserved100_IRQHandler /* Reserved interrupt 100*/ + .long Reserved101_IRQHandler /* Reserved interrupt 101*/ + .long DefaultISR /* 102*/ + .long DefaultISR /* 103*/ + .long DefaultISR /* 104*/ + .long DefaultISR /* 105*/ + .long DefaultISR /* 106*/ + .long DefaultISR /* 107*/ + .long DefaultISR /* 108*/ + .long DefaultISR /* 109*/ + .long DefaultISR /* 110*/ + .long DefaultISR /* 111*/ + .long DefaultISR /* 112*/ + .long DefaultISR /* 113*/ + .long DefaultISR /* 114*/ + .long DefaultISR /* 115*/ + .long DefaultISR /* 116*/ + .long DefaultISR /* 117*/ + .long DefaultISR /* 118*/ + .long DefaultISR /* 119*/ + .long DefaultISR /* 120*/ + .long DefaultISR /* 121*/ + .long DefaultISR /* 122*/ + .long DefaultISR /* 123*/ + .long DefaultISR /* 124*/ + .long DefaultISR /* 125*/ + .long DefaultISR /* 126*/ + .long DefaultISR /* 127*/ + .long DefaultISR /* 128*/ + .long DefaultISR /* 129*/ + .long DefaultISR /* 130*/ + .long DefaultISR /* 131*/ + .long DefaultISR /* 132*/ + .long DefaultISR /* 133*/ + .long DefaultISR /* 134*/ + .long DefaultISR /* 135*/ + .long DefaultISR /* 136*/ + .long DefaultISR /* 137*/ + .long DefaultISR /* 138*/ + .long DefaultISR /* 139*/ + .long DefaultISR /* 140*/ + .long DefaultISR /* 141*/ + .long DefaultISR /* 142*/ + .long DefaultISR /* 143*/ + .long DefaultISR /* 144*/ + .long DefaultISR /* 145*/ + .long DefaultISR /* 146*/ + .long DefaultISR /* 147*/ + .long DefaultISR /* 148*/ + .long DefaultISR /* 149*/ + .long DefaultISR /* 150*/ + .long DefaultISR /* 151*/ + .long DefaultISR /* 152*/ + .long DefaultISR /* 153*/ + .long DefaultISR /* 154*/ + .long DefaultISR /* 155*/ + .long DefaultISR /* 156*/ + .long DefaultISR /* 157*/ + .long DefaultISR /* 158*/ + .long DefaultISR /* 159*/ + .long DefaultISR /* 160*/ + .long DefaultISR /* 161*/ + .long DefaultISR /* 162*/ + .long DefaultISR /* 163*/ + .long DefaultISR /* 164*/ + .long DefaultISR /* 165*/ + .long DefaultISR /* 166*/ + .long DefaultISR /* 167*/ + .long DefaultISR /* 168*/ + .long DefaultISR /* 169*/ + .long DefaultISR /* 170*/ + .long DefaultISR /* 171*/ + .long DefaultISR /* 172*/ + .long DefaultISR /* 173*/ + .long DefaultISR /* 174*/ + .long DefaultISR /* 175*/ + .long DefaultISR /* 176*/ + .long DefaultISR /* 177*/ + .long DefaultISR /* 178*/ + .long DefaultISR /* 179*/ + .long DefaultISR /* 180*/ + .long DefaultISR /* 181*/ + .long DefaultISR /* 182*/ + .long DefaultISR /* 183*/ + .long DefaultISR /* 184*/ + .long DefaultISR /* 185*/ + .long DefaultISR /* 186*/ + .long DefaultISR /* 187*/ + .long DefaultISR /* 188*/ + .long DefaultISR /* 189*/ + .long DefaultISR /* 190*/ + .long DefaultISR /* 191*/ + .long DefaultISR /* 192*/ + .long DefaultISR /* 193*/ + .long DefaultISR /* 194*/ + .long DefaultISR /* 195*/ + .long DefaultISR /* 196*/ + .long DefaultISR /* 197*/ + .long DefaultISR /* 198*/ + .long DefaultISR /* 199*/ + .long DefaultISR /* 200*/ + .long DefaultISR /* 201*/ + .long DefaultISR /* 202*/ + .long DefaultISR /* 203*/ + .long DefaultISR /* 204*/ + .long DefaultISR /* 205*/ + .long DefaultISR /* 206*/ + .long DefaultISR /* 207*/ + .long DefaultISR /* 208*/ + .long DefaultISR /* 209*/ + .long DefaultISR /* 210*/ + .long DefaultISR /* 211*/ + .long DefaultISR /* 212*/ + .long DefaultISR /* 213*/ + .long DefaultISR /* 214*/ + .long DefaultISR /* 215*/ + .long DefaultISR /* 216*/ + .long DefaultISR /* 217*/ + .long DefaultISR /* 218*/ + .long DefaultISR /* 219*/ + .long DefaultISR /* 220*/ + .long DefaultISR /* 221*/ + .long DefaultISR /* 222*/ + .long DefaultISR /* 223*/ + .long DefaultISR /* 224*/ + .long DefaultISR /* 225*/ + .long DefaultISR /* 226*/ + .long DefaultISR /* 227*/ + .long DefaultISR /* 228*/ + .long DefaultISR /* 229*/ + .long DefaultISR /* 230*/ + .long DefaultISR /* 231*/ + .long DefaultISR /* 232*/ + .long DefaultISR /* 233*/ + .long DefaultISR /* 234*/ + .long DefaultISR /* 235*/ + .long DefaultISR /* 236*/ + .long DefaultISR /* 237*/ + .long DefaultISR /* 238*/ + .long DefaultISR /* 239*/ + .long DefaultISR /* 240*/ + .long DefaultISR /* 241*/ + .long DefaultISR /* 242*/ + .long DefaultISR /* 243*/ + .long DefaultISR /* 244*/ + .long DefaultISR /* 245*/ + .long DefaultISR /* 246*/ + .long DefaultISR /* 247*/ + .long DefaultISR /* 248*/ + .long DefaultISR /* 249*/ + .long DefaultISR /* 250*/ + .long DefaultISR /* 251*/ + .long DefaultISR /* 252*/ + .long DefaultISR /* 253*/ + .long DefaultISR /* 254*/ + .long 0xFFFFFFFF /* Reserved for user TRIM value*/ + + .size __isr_vector, . - __isr_vector + +/* Flash Configuration */ + .section .FlashConfig, "a" + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFF + .long 0xFFFFFFFE + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak DMA2_IRQHandler + .type DMA2_IRQHandler, %function +DMA2_IRQHandler: + ldr r0,=DMA2_DriverIRQHandler + bx r0 + .size DMA2_IRQHandler, . - DMA2_IRQHandler + + .align 1 + .thumb_func + .weak DMA3_IRQHandler + .type DMA3_IRQHandler, %function +DMA3_IRQHandler: + ldr r0,=DMA3_DriverIRQHandler + bx r0 + .size DMA3_IRQHandler, . - DMA3_IRQHandler + + .align 1 + .thumb_func + .weak DMA4_IRQHandler + .type DMA4_IRQHandler, %function +DMA4_IRQHandler: + ldr r0,=DMA4_DriverIRQHandler + bx r0 + .size DMA4_IRQHandler, . - DMA4_IRQHandler + + .align 1 + .thumb_func + .weak DMA5_IRQHandler + .type DMA5_IRQHandler, %function +DMA5_IRQHandler: + ldr r0,=DMA5_DriverIRQHandler + bx r0 + .size DMA5_IRQHandler, . - DMA5_IRQHandler + + .align 1 + .thumb_func + .weak DMA6_IRQHandler + .type DMA6_IRQHandler, %function +DMA6_IRQHandler: + ldr r0,=DMA6_DriverIRQHandler + bx r0 + .size DMA6_IRQHandler, . - DMA6_IRQHandler + + .align 1 + .thumb_func + .weak DMA7_IRQHandler + .type DMA7_IRQHandler, %function +DMA7_IRQHandler: + ldr r0,=DMA7_DriverIRQHandler + bx r0 + .size DMA7_IRQHandler, . - DMA7_IRQHandler + + .align 1 + .thumb_func + .weak DMA8_IRQHandler + .type DMA8_IRQHandler, %function +DMA8_IRQHandler: + ldr r0,=DMA8_DriverIRQHandler + bx r0 + .size DMA8_IRQHandler, . - DMA8_IRQHandler + + .align 1 + .thumb_func + .weak DMA9_IRQHandler + .type DMA9_IRQHandler, %function +DMA9_IRQHandler: + ldr r0,=DMA9_DriverIRQHandler + bx r0 + .size DMA9_IRQHandler, . - DMA9_IRQHandler + + .align 1 + .thumb_func + .weak DMA10_IRQHandler + .type DMA10_IRQHandler, %function +DMA10_IRQHandler: + ldr r0,=DMA10_DriverIRQHandler + bx r0 + .size DMA10_IRQHandler, . - DMA10_IRQHandler + + .align 1 + .thumb_func + .weak DMA11_IRQHandler + .type DMA11_IRQHandler, %function +DMA11_IRQHandler: + ldr r0,=DMA11_DriverIRQHandler + bx r0 + .size DMA11_IRQHandler, . - DMA11_IRQHandler + + .align 1 + .thumb_func + .weak DMA12_IRQHandler + .type DMA12_IRQHandler, %function +DMA12_IRQHandler: + ldr r0,=DMA12_DriverIRQHandler + bx r0 + .size DMA12_IRQHandler, . - DMA12_IRQHandler + + .align 1 + .thumb_func + .weak DMA13_IRQHandler + .type DMA13_IRQHandler, %function +DMA13_IRQHandler: + ldr r0,=DMA13_DriverIRQHandler + bx r0 + .size DMA13_IRQHandler, . - DMA13_IRQHandler + + .align 1 + .thumb_func + .weak DMA14_IRQHandler + .type DMA14_IRQHandler, %function +DMA14_IRQHandler: + ldr r0,=DMA14_DriverIRQHandler + bx r0 + .size DMA14_IRQHandler, . - DMA14_IRQHandler + + .align 1 + .thumb_func + .weak DMA15_IRQHandler + .type DMA15_IRQHandler, %function +DMA15_IRQHandler: + ldr r0,=DMA15_DriverIRQHandler + bx r0 + .size DMA15_IRQHandler, . - DMA15_IRQHandler + + .align 1 + .thumb_func + .weak DMA_Error_IRQHandler + .type DMA_Error_IRQHandler, %function +DMA_Error_IRQHandler: + ldr r0,=DMA_Error_DriverIRQHandler + bx r0 + .size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler + + .align 1 + .thumb_func + .weak I2C0_IRQHandler + .type I2C0_IRQHandler, %function +I2C0_IRQHandler: + ldr r0,=I2C0_DriverIRQHandler + bx r0 + .size I2C0_IRQHandler, . - I2C0_IRQHandler + + .align 1 + .thumb_func + .weak I2C1_IRQHandler + .type I2C1_IRQHandler, %function +I2C1_IRQHandler: + ldr r0,=I2C1_DriverIRQHandler + bx r0 + .size I2C1_IRQHandler, . - I2C1_IRQHandler + + .align 1 + .thumb_func + .weak SPI0_IRQHandler + .type SPI0_IRQHandler, %function +SPI0_IRQHandler: + ldr r0,=SPI0_DriverIRQHandler + bx r0 + .size SPI0_IRQHandler, . - SPI0_IRQHandler + + .align 1 + .thumb_func + .weak SPI1_IRQHandler + .type SPI1_IRQHandler, %function +SPI1_IRQHandler: + ldr r0,=SPI1_DriverIRQHandler + bx r0 + .size SPI1_IRQHandler, . - SPI1_IRQHandler + + .align 1 + .thumb_func + .weak I2S0_Tx_IRQHandler + .type I2S0_Tx_IRQHandler, %function +I2S0_Tx_IRQHandler: + ldr r0,=I2S0_Tx_DriverIRQHandler + bx r0 + .size I2S0_Tx_IRQHandler, . - I2S0_Tx_IRQHandler + + .align 1 + .thumb_func + .weak I2S0_Rx_IRQHandler + .type I2S0_Rx_IRQHandler, %function +I2S0_Rx_IRQHandler: + ldr r0,=I2S0_Rx_DriverIRQHandler + bx r0 + .size I2S0_Rx_IRQHandler, . - I2S0_Rx_IRQHandler + + .align 1 + .thumb_func + .weak UART0_LON_IRQHandler + .type UART0_LON_IRQHandler, %function +UART0_LON_IRQHandler: + ldr r0,=UART0_LON_DriverIRQHandler + bx r0 + .size UART0_LON_IRQHandler, . - UART0_LON_IRQHandler + + .align 1 + .thumb_func + .weak UART0_RX_TX_IRQHandler + .type UART0_RX_TX_IRQHandler, %function +UART0_RX_TX_IRQHandler: + ldr r0,=UART0_RX_TX_DriverIRQHandler + bx r0 + .size UART0_RX_TX_IRQHandler, . - UART0_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART0_ERR_IRQHandler + .type UART0_ERR_IRQHandler, %function +UART0_ERR_IRQHandler: + ldr r0,=UART0_ERR_DriverIRQHandler + bx r0 + .size UART0_ERR_IRQHandler, . - UART0_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART1_RX_TX_IRQHandler + .type UART1_RX_TX_IRQHandler, %function +UART1_RX_TX_IRQHandler: + ldr r0,=UART1_RX_TX_DriverIRQHandler + bx r0 + .size UART1_RX_TX_IRQHandler, . - UART1_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART1_ERR_IRQHandler + .type UART1_ERR_IRQHandler, %function +UART1_ERR_IRQHandler: + ldr r0,=UART1_ERR_DriverIRQHandler + bx r0 + .size UART1_ERR_IRQHandler, . - UART1_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART2_RX_TX_IRQHandler + .type UART2_RX_TX_IRQHandler, %function +UART2_RX_TX_IRQHandler: + ldr r0,=UART2_RX_TX_DriverIRQHandler + bx r0 + .size UART2_RX_TX_IRQHandler, . - UART2_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART2_ERR_IRQHandler + .type UART2_ERR_IRQHandler, %function +UART2_ERR_IRQHandler: + ldr r0,=UART2_ERR_DriverIRQHandler + bx r0 + .size UART2_ERR_IRQHandler, . - UART2_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART3_RX_TX_IRQHandler + .type UART3_RX_TX_IRQHandler, %function +UART3_RX_TX_IRQHandler: + ldr r0,=UART3_RX_TX_DriverIRQHandler + bx r0 + .size UART3_RX_TX_IRQHandler, . - UART3_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART3_ERR_IRQHandler + .type UART3_ERR_IRQHandler, %function +UART3_ERR_IRQHandler: + ldr r0,=UART3_ERR_DriverIRQHandler + bx r0 + .size UART3_ERR_IRQHandler, . - UART3_ERR_IRQHandler + + .align 1 + .thumb_func + .weak SPI2_IRQHandler + .type SPI2_IRQHandler, %function +SPI2_IRQHandler: + ldr r0,=SPI2_DriverIRQHandler + bx r0 + .size SPI2_IRQHandler, . - SPI2_IRQHandler + + .align 1 + .thumb_func + .weak UART4_RX_TX_IRQHandler + .type UART4_RX_TX_IRQHandler, %function +UART4_RX_TX_IRQHandler: + ldr r0,=UART4_RX_TX_DriverIRQHandler + bx r0 + .size UART4_RX_TX_IRQHandler, . - UART4_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART4_ERR_IRQHandler + .type UART4_ERR_IRQHandler, %function +UART4_ERR_IRQHandler: + ldr r0,=UART4_ERR_DriverIRQHandler + bx r0 + .size UART4_ERR_IRQHandler, . - UART4_ERR_IRQHandler + + .align 1 + .thumb_func + .weak UART5_RX_TX_IRQHandler + .type UART5_RX_TX_IRQHandler, %function +UART5_RX_TX_IRQHandler: + ldr r0,=UART5_RX_TX_DriverIRQHandler + bx r0 + .size UART5_RX_TX_IRQHandler, . - UART5_RX_TX_IRQHandler + + .align 1 + .thumb_func + .weak UART5_ERR_IRQHandler + .type UART5_ERR_IRQHandler, %function +UART5_ERR_IRQHandler: + ldr r0,=UART5_ERR_DriverIRQHandler + bx r0 + .size UART5_ERR_IRQHandler, . - UART5_ERR_IRQHandler + + .align 1 + .thumb_func + .weak I2C2_IRQHandler + .type I2C2_IRQHandler, %function +I2C2_IRQHandler: + ldr r0,=I2C2_DriverIRQHandler + bx r0 + .size I2C2_IRQHandler, . - I2C2_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_ORed_Message_buffer_IRQHandler + .type CAN0_ORed_Message_buffer_IRQHandler, %function +CAN0_ORed_Message_buffer_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_ORed_Message_buffer_IRQHandler, . - CAN0_ORed_Message_buffer_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Bus_Off_IRQHandler + .type CAN0_Bus_Off_IRQHandler, %function +CAN0_Bus_Off_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Bus_Off_IRQHandler, . - CAN0_Bus_Off_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Error_IRQHandler + .type CAN0_Error_IRQHandler, %function +CAN0_Error_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Error_IRQHandler, . - CAN0_Error_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Tx_Warning_IRQHandler + .type CAN0_Tx_Warning_IRQHandler, %function +CAN0_Tx_Warning_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Tx_Warning_IRQHandler, . - CAN0_Tx_Warning_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Rx_Warning_IRQHandler + .type CAN0_Rx_Warning_IRQHandler, %function +CAN0_Rx_Warning_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Rx_Warning_IRQHandler, . - CAN0_Rx_Warning_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_Wake_Up_IRQHandler + .type CAN0_Wake_Up_IRQHandler, %function +CAN0_Wake_Up_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_Wake_Up_IRQHandler, . - CAN0_Wake_Up_IRQHandler + + .align 1 + .thumb_func + .weak SDHC_IRQHandler + .type SDHC_IRQHandler, %function +SDHC_IRQHandler: + ldr r0,=SDHC_DriverIRQHandler + bx r0 + .size SDHC_IRQHandler, . - SDHC_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler DMA0_DriverIRQHandler + def_irq_handler DMA1_DriverIRQHandler + def_irq_handler DMA2_DriverIRQHandler + def_irq_handler DMA3_DriverIRQHandler + def_irq_handler DMA4_DriverIRQHandler + def_irq_handler DMA5_DriverIRQHandler + def_irq_handler DMA6_DriverIRQHandler + def_irq_handler DMA7_DriverIRQHandler + def_irq_handler DMA8_DriverIRQHandler + def_irq_handler DMA9_DriverIRQHandler + def_irq_handler DMA10_DriverIRQHandler + def_irq_handler DMA11_DriverIRQHandler + def_irq_handler DMA12_DriverIRQHandler + def_irq_handler DMA13_DriverIRQHandler + def_irq_handler DMA14_DriverIRQHandler + def_irq_handler DMA15_DriverIRQHandler + def_irq_handler DMA_Error_DriverIRQHandler + def_irq_handler MCM_IRQHandler + def_irq_handler FTFE_IRQHandler + def_irq_handler Read_Collision_IRQHandler + def_irq_handler LVD_LVW_IRQHandler + def_irq_handler LLWU_IRQHandler + def_irq_handler WDOG_EWM_IRQHandler + def_irq_handler RNG_IRQHandler + def_irq_handler I2C0_DriverIRQHandler + def_irq_handler I2C1_DriverIRQHandler + def_irq_handler SPI0_DriverIRQHandler + def_irq_handler SPI1_DriverIRQHandler + def_irq_handler I2S0_Tx_DriverIRQHandler + def_irq_handler I2S0_Rx_DriverIRQHandler + def_irq_handler UART0_LON_DriverIRQHandler + def_irq_handler UART0_RX_TX_DriverIRQHandler + def_irq_handler UART0_ERR_DriverIRQHandler + def_irq_handler UART1_RX_TX_DriverIRQHandler + def_irq_handler UART1_ERR_DriverIRQHandler + def_irq_handler UART2_RX_TX_DriverIRQHandler + def_irq_handler UART2_ERR_DriverIRQHandler + def_irq_handler UART3_RX_TX_DriverIRQHandler + def_irq_handler UART3_ERR_DriverIRQHandler + def_irq_handler ADC0_IRQHandler + def_irq_handler CMP0_IRQHandler + def_irq_handler CMP1_IRQHandler + def_irq_handler FTM0_IRQHandler + def_irq_handler FTM1_IRQHandler + def_irq_handler FTM2_IRQHandler + def_irq_handler CMT_IRQHandler + def_irq_handler RTC_IRQHandler + def_irq_handler RTC_Seconds_IRQHandler + def_irq_handler PIT0_IRQHandler + def_irq_handler PIT1_IRQHandler + def_irq_handler PIT2_IRQHandler + def_irq_handler PIT3_IRQHandler + def_irq_handler PDB0_IRQHandler + def_irq_handler USB0_IRQHandler + def_irq_handler USBDCD_IRQHandler + def_irq_handler Reserved71_IRQHandler + def_irq_handler DAC0_IRQHandler + def_irq_handler MCG_IRQHandler + def_irq_handler LPTMR0_IRQHandler + def_irq_handler PORTA_IRQHandler + def_irq_handler PORTB_IRQHandler + def_irq_handler PORTC_IRQHandler + def_irq_handler PORTD_IRQHandler + def_irq_handler PORTE_IRQHandler + def_irq_handler SWI_IRQHandler + def_irq_handler SPI2_DriverIRQHandler + def_irq_handler UART4_RX_TX_DriverIRQHandler + def_irq_handler UART4_ERR_DriverIRQHandler + def_irq_handler UART5_RX_TX_DriverIRQHandler + def_irq_handler UART5_ERR_DriverIRQHandler + def_irq_handler CMP2_IRQHandler + def_irq_handler FTM3_IRQHandler + def_irq_handler DAC1_IRQHandler + def_irq_handler ADC1_IRQHandler + def_irq_handler I2C2_DriverIRQHandler + def_irq_handler CAN0_DriverIRQHandler + def_irq_handler SDHC_DriverIRQHandler + def_irq_handler Reserved98_IRQHandler + def_irq_handler Reserved99_IRQHandler + def_irq_handler Reserved100_IRQHandler + def_irq_handler Reserved101_IRQHandler + + .end diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_IAR/MK24FN1M0xxx12.icf b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_IAR/MK24FN1M0xxx12.icf new file mode 100644 index 00000000000..4b753e15d1b --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_IAR/MK24FN1M0xxx12.icf @@ -0,0 +1,118 @@ +/* +** ################################################################### +** Processors: MK64FN1M0VDC12 +** MK64FN1M0VLL12 +** MK64FN1M0VLQ12 +** MK64FN1M0VMD12 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.8, 2015-02-19 +** Build: b151009 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright (c) 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ +define symbol __ram_vector_table__ = 1; + +/* Heap 1/4 of ram and stack 1/8 */ +define symbol __stack_size__=0x8000; +define symbol __heap_size__=0x10000; + +define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; +define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_flash_config_start = 0x00000400; +define symbol m_flash_config_end = 0x0000040F; + +define symbol m_text_start = 0x00000410; +define symbol m_text_end = 0x000FFFFF; + +define symbol m_interrupts_ram_start = 0x1FFF0000; +define symbol m_interrupts_ram_end = 0x1FFF0000 + __ram_vector_table_offset__; + +define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__; +define symbol m_data_end = 0x1FFFFFFF; + +define symbol m_data_2_start = 0x20000000; +define symbol m_data_2_end = 0x2002FFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__; + +define memory mem with size = 4G; +define region m_flash_config_region = mem:[from m_flash_config_start to m_flash_config_end]; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end] + | mem:[from m_data_2_start to m_data_2_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data_2_end-__size_cstack__+1 to m_data_2_end]; +define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in m_flash_config_region { section FlashConfig }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in m_interrupts_ram_region { section m_interrupts_ram }; + diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_IAR/startup_MK24F12.S b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_IAR/startup_MK24F12.S new file mode 100644 index 00000000000..f55ac1d7f93 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_IAR/startup_MK24F12.S @@ -0,0 +1,847 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MK24F12.s +; @purpose: CMSIS Cortex-M4 Core Device Startup File +; MK24F12 +; @version: 2.8 +; @date: 2016-3-21 +; @build: b170112 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2016, Freescale Semiconductor, Inc. +; Copyright 2016 - 2017 NXP +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of the copyright holder nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete + DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete + DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete + DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete + DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete + DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete + DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete + DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete + DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete + DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete + DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete + DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete + DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete + DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete + DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete + DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete + DCD DMA_Error_IRQHandler ;DMA Error Interrupt + DCD MCM_IRQHandler ;Normal Interrupt + DCD FTFE_IRQHandler ;FTFE Command complete interrupt + DCD Read_Collision_IRQHandler ;Read Collision Interrupt + DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit + DCD WDOG_EWM_IRQHandler ;WDOG Interrupt + DCD RNG_IRQHandler ;RNG Interrupt + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 Interrupt + DCD SPI1_IRQHandler ;SPI1 Interrupt + DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt + DCD UART0_LON_IRQHandler ;UART0 LON interrupt + DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt + DCD UART0_ERR_IRQHandler ;UART0 Error interrupt + DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt + DCD UART1_ERR_IRQHandler ;UART1 Error interrupt + DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt + DCD UART2_ERR_IRQHandler ;UART2 Error interrupt + DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt + DCD UART3_ERR_IRQHandler ;UART3 Error interrupt + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD CMP1_IRQHandler ;CMP1 interrupt + DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt + DCD CMT_IRQHandler ;CMT interrupt + DCD RTC_IRQHandler ;RTC interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ;PDB0 Interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD USBDCD_IRQHandler ;USBDCD Interrupt + DCD Reserved71_IRQHandler ;Reserved interrupt 71 + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD MCG_IRQHandler ;MCG Interrupt + DCD LPTMR0_IRQHandler ;LPTimer interrupt + DCD PORTA_IRQHandler ;Port A interrupt + DCD PORTB_IRQHandler ;Port B interrupt + DCD PORTC_IRQHandler ;Port C interrupt + DCD PORTD_IRQHandler ;Port D interrupt + DCD PORTE_IRQHandler ;Port E interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD SPI2_IRQHandler ;SPI2 Interrupt + DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt + DCD UART4_ERR_IRQHandler ;UART4 Error interrupt + DCD UART5_RX_TX_IRQHandler ;UART5 Receive/Transmit interrupt + DCD UART5_ERR_IRQHandler ;UART5 Error interrupt + DCD CMP2_IRQHandler ;CMP2 interrupt + DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt + DCD DAC1_IRQHandler ;DAC1 interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD I2C2_IRQHandler ;I2C2 interrupt + DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt + DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt + DCD CAN0_Error_IRQHandler ;CAN0 error interrupt + DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt + DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt + DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt + DCD SDHC_IRQHandler ;SDHC interrupt + DCD Reserved98_IRQHandler ;Reserved interrupt 98 + DCD Reserved99_IRQHandler ;Reserved interrupt 99 + DCD Reserved100_IRQHandler ;Reserved interrupt 100 + DCD Reserved101_IRQHandler ;Reserved interrupt 101 + DCD DefaultISR ;102 + DCD DefaultISR ;103 + DCD DefaultISR ;104 + DCD DefaultISR ;105 + DCD DefaultISR ;106 + DCD DefaultISR ;107 + DCD DefaultISR ;108 + DCD DefaultISR ;109 + DCD DefaultISR ;110 + DCD DefaultISR ;111 + DCD DefaultISR ;112 + DCD DefaultISR ;113 + DCD DefaultISR ;114 + DCD DefaultISR ;115 + DCD DefaultISR ;116 + DCD DefaultISR ;117 + DCD DefaultISR ;118 + DCD DefaultISR ;119 + DCD DefaultISR ;120 + DCD DefaultISR ;121 + DCD DefaultISR ;122 + DCD DefaultISR ;123 + DCD DefaultISR ;124 + DCD DefaultISR ;125 + DCD DefaultISR ;126 + DCD DefaultISR ;127 + DCD DefaultISR ;128 + DCD DefaultISR ;129 + DCD DefaultISR ;130 + DCD DefaultISR ;131 + DCD DefaultISR ;132 + DCD DefaultISR ;133 + DCD DefaultISR ;134 + DCD DefaultISR ;135 + DCD DefaultISR ;136 + DCD DefaultISR ;137 + DCD DefaultISR ;138 + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R2, [R1] + MSR MSP, R2 + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_IRQHandler + LDR R0, =DMA2_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_IRQHandler + LDR R0, =DMA3_DriverIRQHandler + BX R0 + + PUBWEAK DMA4_IRQHandler + PUBWEAK DMA4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA4_IRQHandler + LDR R0, =DMA4_DriverIRQHandler + BX R0 + + PUBWEAK DMA5_IRQHandler + PUBWEAK DMA5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA5_IRQHandler + LDR R0, =DMA5_DriverIRQHandler + BX R0 + + PUBWEAK DMA6_IRQHandler + PUBWEAK DMA6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA6_IRQHandler + LDR R0, =DMA6_DriverIRQHandler + BX R0 + + PUBWEAK DMA7_IRQHandler + PUBWEAK DMA7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA7_IRQHandler + LDR R0, =DMA7_DriverIRQHandler + BX R0 + + PUBWEAK DMA8_IRQHandler + PUBWEAK DMA8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA8_IRQHandler + LDR R0, =DMA8_DriverIRQHandler + BX R0 + + PUBWEAK DMA9_IRQHandler + PUBWEAK DMA9_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA9_IRQHandler + LDR R0, =DMA9_DriverIRQHandler + BX R0 + + PUBWEAK DMA10_IRQHandler + PUBWEAK DMA10_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA10_IRQHandler + LDR R0, =DMA10_DriverIRQHandler + BX R0 + + PUBWEAK DMA11_IRQHandler + PUBWEAK DMA11_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA11_IRQHandler + LDR R0, =DMA11_DriverIRQHandler + BX R0 + + PUBWEAK DMA12_IRQHandler + PUBWEAK DMA12_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA12_IRQHandler + LDR R0, =DMA12_DriverIRQHandler + BX R0 + + PUBWEAK DMA13_IRQHandler + PUBWEAK DMA13_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA13_IRQHandler + LDR R0, =DMA13_DriverIRQHandler + BX R0 + + PUBWEAK DMA14_IRQHandler + PUBWEAK DMA14_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA14_IRQHandler + LDR R0, =DMA14_DriverIRQHandler + BX R0 + + PUBWEAK DMA15_IRQHandler + PUBWEAK DMA15_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA15_IRQHandler + LDR R0, =DMA15_DriverIRQHandler + BX R0 + + PUBWEAK DMA_Error_IRQHandler + PUBWEAK DMA_Error_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_Error_IRQHandler + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + + PUBWEAK MCM_IRQHandler + PUBWEAK FTFE_IRQHandler + PUBWEAK Read_Collision_IRQHandler + PUBWEAK LVD_LVW_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK WDOG_EWM_IRQHandler + PUBWEAK RNG_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C0_IRQHandler + LDR R0, =I2C0_DriverIRQHandler + BX R0 + + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C1_IRQHandler + LDR R0, =I2C1_DriverIRQHandler + BX R0 + + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI0_IRQHandler + LDR R0, =SPI0_DriverIRQHandler + BX R0 + + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI1_IRQHandler + LDR R0, =SPI1_DriverIRQHandler + BX R0 + + PUBWEAK I2S0_Tx_IRQHandler + PUBWEAK I2S0_Tx_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2S0_Tx_IRQHandler + LDR R0, =I2S0_Tx_DriverIRQHandler + BX R0 + + PUBWEAK I2S0_Rx_IRQHandler + PUBWEAK I2S0_Rx_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2S0_Rx_IRQHandler + LDR R0, =I2S0_Rx_DriverIRQHandler + BX R0 + + PUBWEAK UART0_LON_IRQHandler + PUBWEAK UART0_LON_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART0_LON_IRQHandler + LDR R0, =UART0_LON_DriverIRQHandler + BX R0 + + PUBWEAK UART0_RX_TX_IRQHandler + PUBWEAK UART0_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART0_RX_TX_IRQHandler + LDR R0, =UART0_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART0_ERR_IRQHandler + PUBWEAK UART0_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART0_ERR_IRQHandler + LDR R0, =UART0_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART1_RX_TX_IRQHandler + PUBWEAK UART1_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART1_RX_TX_IRQHandler + LDR R0, =UART1_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART1_ERR_IRQHandler + PUBWEAK UART1_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART1_ERR_IRQHandler + LDR R0, =UART1_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART2_RX_TX_IRQHandler + PUBWEAK UART2_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_RX_TX_IRQHandler + LDR R0, =UART2_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART2_ERR_IRQHandler + PUBWEAK UART2_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_ERR_IRQHandler + LDR R0, =UART2_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART3_RX_TX_IRQHandler + PUBWEAK UART3_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART3_RX_TX_IRQHandler + LDR R0, =UART3_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART3_ERR_IRQHandler + PUBWEAK UART3_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART3_ERR_IRQHandler + LDR R0, =UART3_ERR_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK FTM0_IRQHandler + PUBWEAK FTM1_IRQHandler + PUBWEAK FTM2_IRQHandler + PUBWEAK CMT_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT0_IRQHandler + PUBWEAK PIT1_IRQHandler + PUBWEAK PIT2_IRQHandler + PUBWEAK PIT3_IRQHandler + PUBWEAK PDB0_IRQHandler + PUBWEAK USB0_IRQHandler + PUBWEAK USBDCD_IRQHandler + PUBWEAK Reserved71_IRQHandler + PUBWEAK DAC0_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTB_IRQHandler + PUBWEAK PORTC_IRQHandler + PUBWEAK PORTD_IRQHandler + PUBWEAK PORTE_IRQHandler + PUBWEAK SWI_IRQHandler + PUBWEAK SPI2_IRQHandler + PUBWEAK SPI2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI2_IRQHandler + LDR R0, =SPI2_DriverIRQHandler + BX R0 + + PUBWEAK UART4_RX_TX_IRQHandler + PUBWEAK UART4_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART4_RX_TX_IRQHandler + LDR R0, =UART4_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART4_ERR_IRQHandler + PUBWEAK UART4_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART4_ERR_IRQHandler + LDR R0, =UART4_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART5_RX_TX_IRQHandler + PUBWEAK UART5_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART5_RX_TX_IRQHandler + LDR R0, =UART5_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART5_ERR_IRQHandler + PUBWEAK UART5_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART5_ERR_IRQHandler + LDR R0, =UART5_ERR_DriverIRQHandler + BX R0 + + PUBWEAK CMP2_IRQHandler + PUBWEAK FTM3_IRQHandler + PUBWEAK DAC1_IRQHandler + PUBWEAK ADC1_IRQHandler + PUBWEAK I2C2_IRQHandler + PUBWEAK I2C2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C2_IRQHandler + LDR R0, =I2C2_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_ORed_Message_buffer_IRQHandler + PUBWEAK CAN0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_ORed_Message_buffer_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_Bus_Off_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_Bus_Off_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_Error_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_Error_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_Tx_Warning_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_Tx_Warning_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_Rx_Warning_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_Rx_Warning_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_Wake_Up_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_Wake_Up_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK SDHC_IRQHandler + PUBWEAK SDHC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SDHC_IRQHandler + LDR R0, =SDHC_DriverIRQHandler + BX R0 + + PUBWEAK Reserved98_IRQHandler + PUBWEAK Reserved99_IRQHandler + PUBWEAK Reserved100_IRQHandler + PUBWEAK Reserved101_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(1) +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +DMA8_DriverIRQHandler +DMA9_DriverIRQHandler +DMA10_DriverIRQHandler +DMA11_DriverIRQHandler +DMA12_DriverIRQHandler +DMA13_DriverIRQHandler +DMA14_DriverIRQHandler +DMA15_DriverIRQHandler +DMA_Error_DriverIRQHandler +MCM_IRQHandler +FTFE_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +WDOG_EWM_IRQHandler +RNG_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +I2S0_Tx_DriverIRQHandler +I2S0_Rx_DriverIRQHandler +UART0_LON_DriverIRQHandler +UART0_RX_TX_DriverIRQHandler +UART0_ERR_DriverIRQHandler +UART1_RX_TX_DriverIRQHandler +UART1_ERR_DriverIRQHandler +UART2_RX_TX_DriverIRQHandler +UART2_ERR_DriverIRQHandler +UART3_RX_TX_DriverIRQHandler +UART3_ERR_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +Reserved71_IRQHandler +DAC0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +SPI2_DriverIRQHandler +UART4_RX_TX_DriverIRQHandler +UART4_ERR_DriverIRQHandler +UART5_RX_TX_DriverIRQHandler +UART5_ERR_DriverIRQHandler +CMP2_IRQHandler +FTM3_IRQHandler +DAC1_IRQHandler +ADC1_IRQHandler +I2C2_DriverIRQHandler +CAN0_DriverIRQHandler +SDHC_DriverIRQHandler +Reserved98_IRQHandler +Reserved99_IRQHandler +Reserved100_IRQHandler +Reserved101_IRQHandler +DefaultISR + B DefaultISR + + END diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/cmsis.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/cmsis.h new file mode 100644 index 00000000000..b8ebe562ff9 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/cmsis.h @@ -0,0 +1,13 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2017 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC11U24 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "fsl_device_registers.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/cmsis_nvic.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/cmsis_nvic.c new file mode 100644 index 00000000000..0de56f35da8 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/cmsis_nvic.c @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); + +void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + InstallIRQHandler(IRQn, vector); +} + +uint32_t __NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + 16]; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/cmsis_nvic.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/cmsis_nvic.h new file mode 100644 index 00000000000..68f955d408b --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/cmsis_nvic.h @@ -0,0 +1,51 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t __NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/fsl_device_registers.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/fsl_device_registers.h new file mode 100644 index 00000000000..585944e07ce --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/fsl_device_registers.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MK24FN1M0CAJ12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || \ + defined(CPU_MK24FN1M0VLQ12)) + +#define K24F12_SERIES + +/* CMSIS-style register definitions */ +#include "MK24F12.h" +/* CPU specific feature definitions */ +#include "MK24F12_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/system_MK24F12.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/system_MK24F12.c new file mode 100644 index 00000000000..fc8c34c77ff --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/system_MK24F12.c @@ -0,0 +1,243 @@ +/* +** ################################################################### +** Processors: MK24FN1M0CAJ12 +** MK24FN1M0VDC12 +** MK24FN1M0VLL12 +** MK24FN1M0VLQ12 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: K24P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.8, 2016-03-21 +** Build: b170112 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2016 - 2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2013-08-12) +** Initial version. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** MCG - registers updated. +** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-09) +** DMA - EARS register removed. +** AIPS0, AIPS1 - MPRA register updated. +** - rev. 2.3 (2014-01-24) +** Update according to reference manual rev. 2 +** ENET, MCG, MCM, SIM, USB - registers updated +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK24F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** - rev. 2.5 (2014-08-28) +** Update of system files - default clock configuration changed. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 2.6 (2014-10-14) +** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. +** - rev. 2.7 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** - rev. 2.8 (2016-03-21) +** Added MK24FN1M0CAJ12 part. +** GPIO - renamed port instances: PTx -> GPIOx. +** +** ################################################################### +*/ + +/*! + * @file MK24F12 + * @version 2.8 + * @date 2016-03-21 + * @brief Device specific configuration file for MK24F12 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ +#if (DISABLE_WDOG) + /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */ + WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ + /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */ + WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ + /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ + WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | + WDOG_STCTRLH_WAITEN_MASK | + WDOG_STCTRLH_STOPEN_MASK | + WDOG_STCTRLH_ALLOWUPDATE_MASK | + WDOG_STCTRLH_CLKSRC_MASK | + 0x0100U; +#endif /* (DISABLE_WDOG) */ + +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */ + uint16_t Divider; + + if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) { + /* Output of FLL or PLL is selected */ + if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) { + /* FLL is selected */ + if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) { + /* External reference clock is selected */ + switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { + case 0x00U: + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + break; + case 0x01U: + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + break; + case 0x02U: + default: + MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ + break; + } + if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { + switch (MCG->C1 & MCG_C1_FRDIV_MASK) { + case 0x38U: + Divider = 1536U; + break; + case 0x30U: + Divider = 1280U; + break; + default: + Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + break; + } + } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */ + Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); + } + MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ + } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ + } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */ + /* Select correct multiplier to calculate the MCG output clock */ + switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { + case 0x00U: + MCGOUTClock *= 640U; + break; + case 0x20U: + MCGOUTClock *= 1280U; + break; + case 0x40U: + MCGOUTClock *= 1920U; + break; + case 0x60U: + MCGOUTClock *= 2560U; + break; + case 0x80U: + MCGOUTClock *= 732U; + break; + case 0xA0U: + MCGOUTClock *= 1464U; + break; + case 0xC0U: + MCGOUTClock *= 2197U; + break; + case 0xE0U: + MCGOUTClock *= 2929U; + break; + default: + break; + } + } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ + /* PLL is selected */ + Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); + MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */ + Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); + MCGOUTClock *= Divider; /* Calculate the MCG output clock */ + } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) { + /* Internal reference clock is selected */ + if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) { + MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ + } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ + Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); + MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */ + } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */ + } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) { + /* External reference clock is selected */ + switch (MCG->C7 & MCG_C7_OSCSEL_MASK) { + case 0x00U: + MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ + break; + case 0x01U: + MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */ + break; + case 0x02U: + default: + MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */ + break; + } + } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ + /* Reserved value */ + return; + } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */ + SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/system_MK24F12.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/system_MK24F12.h new file mode 100644 index 00000000000..6ce1ded2adb --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/system_MK24F12.h @@ -0,0 +1,166 @@ +/* +** ################################################################### +** Processors: MK24FN1M0CAJ12 +** MK24FN1M0VDC12 +** MK24FN1M0VLL12 +** MK24FN1M0VLQ12 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: K24P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.8, 2016-03-21 +** Build: b170112 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2016 - 2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2013-08-12) +** Initial version. +** - rev. 2.0 (2013-10-29) +** Register accessor macros added to the memory map. +** Symbols for Processor Expert memory map compatibility added to the memory map. +** Startup file for gcc has been updated according to CMSIS 3.2. +** System initialization updated. +** MCG - registers updated. +** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. +** - rev. 2.1 (2013-10-30) +** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. +** - rev. 2.2 (2013-12-09) +** DMA - EARS register removed. +** AIPS0, AIPS1 - MPRA register updated. +** - rev. 2.3 (2014-01-24) +** Update according to reference manual rev. 2 +** ENET, MCG, MCM, SIM, USB - registers updated +** - rev. 2.4 (2014-02-10) +** The declaration of clock configurations has been moved to separate header file system_MK24F12.h +** Update of SystemInit() and SystemCoreClockUpdate() functions. +** Module access macro module_BASES replaced by module_BASE_PTRS. +** - rev. 2.5 (2014-08-28) +** Update of system files - default clock configuration changed. +** Update of startup files - possibility to override DefaultISR added. +** - rev. 2.6 (2014-10-14) +** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. +** - rev. 2.7 (2015-02-19) +** Renamed interrupt vector LLW to LLWU. +** - rev. 2.8 (2016-03-21) +** Added MK24FN1M0CAJ12 part. +** GPIO - renamed port instances: PTx -> GPIOx. +** +** ################################################################### +*/ + +/*! + * @file MK24F12 + * @version 2.8 + * @date 2016-03-21 + * @brief Device specific configuration file for MK24F12 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MK24F12_H_ +#define _SYSTEM_MK24F12_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Define clock source values */ + +#define CPU_XTAL_CLK_HZ 50000000u /* Value of the external crystal or oscillator clock frequency in Hz */ +#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */ +#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ +#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ +#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */ + +/* RTC oscillator setting */ +/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */ +#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */ + +/* Low power mode enable */ +/* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */ +#define SYSTEM_SMC_PMPROT_VALUE 0x2AU /* SMC_PMPROT */ + +#define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MK24F12_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/dma_reqs.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/dma_reqs.h new file mode 100644 index 00000000000..13fbaf19528 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/dma_reqs.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DMA_REQS_H_ +#define _FSL_DMA_REQS_H_ + +#include "fsl_common.h" + +/* Array for DSPI DMA TX requests */ +#define SPI_DMA_TX_REQUEST_NUMBERS \ + { \ + kDmaRequestMux0SPI0Tx, kDmaRequestMux0SPI1, kDmaRequestMux0SPI2 \ + } + +/* Array for DSPI DMA RX requests */ +#define SPI_DMA_RX_REQUEST_NUMBERS \ + { \ + kDmaRequestMux0SPI0Rx, kDmaRequestMux0SPI1, kDmaRequestMux0SPI2 \ + } + +/* Array for UART DMA TX requests */ +#define UART_DMA_TX_REQUEST_NUMBERS \ + { \ + kDmaRequestMux0UART0Tx, kDmaRequestMux0UART1Tx, kDmaRequestMux0UART2Tx, \ + kDmaRequestMux0UART3Tx, kDmaRequestMux0UART4, kDmaRequestMux0UART5 \ + } + +/* Array for UART DMA RX requests */ +#define UART_DMA_RX_REQUEST_NUMBERS \ + { \ + kDmaRequestMux0UART0Rx, kDmaRequestMux0UART1Rx, kDmaRequestMux0UART2Rx, \ + kDmaRequestMux0UART3Rx, kDmaRequestMux0UART4, kDmaRequestMux0UART5 \ + } + +#endif /* _FSL_DMA_REQS_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_adc16.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_adc16.c new file mode 100644 index 00000000000..0af6a4443e9 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_adc16.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_adc16.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ADC16 module. + * + * @param base ADC16 peripheral base address + */ +static uint32_t ADC16_GetInstance(ADC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ADC16 bases for each instance. */ +static ADC_Type *const s_adc16Bases[] = ADC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ADC16 clocks for each instance. */ +static const clock_ip_name_t s_adc16Clocks[] = ADC16_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ADC16_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_adc16Bases); instance++) + { + if (s_adc16Bases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_adc16Bases)); + + return instance; +} + +void ADC16_Init(ADC_Type *base, const adc16_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_adc16Clocks[ADC16_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* ADCx_CFG1. */ + tmp32 = ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_MODE(config->resolution); + if (kADC16_LongSampleDisabled != config->longSampleMode) + { + tmp32 |= ADC_CFG1_ADLSMP_MASK; + } + tmp32 |= ADC_CFG1_ADIV(config->clockDivider); + if (config->enableLowPower) + { + tmp32 |= ADC_CFG1_ADLPC_MASK; + } + base->CFG1 = tmp32; + + /* ADCx_CFG2. */ + tmp32 = base->CFG2 & ~(ADC_CFG2_ADACKEN_MASK | ADC_CFG2_ADHSC_MASK | ADC_CFG2_ADLSTS_MASK); + if (kADC16_LongSampleDisabled != config->longSampleMode) + { + tmp32 |= ADC_CFG2_ADLSTS(config->longSampleMode); + } + if (config->enableHighSpeed) + { + tmp32 |= ADC_CFG2_ADHSC_MASK; + } + if (config->enableAsynchronousClock) + { + tmp32 |= ADC_CFG2_ADACKEN_MASK; + } + base->CFG2 = tmp32; + + /* ADCx_SC2. */ + tmp32 = base->SC2 & ~(ADC_SC2_REFSEL_MASK); + tmp32 |= ADC_SC2_REFSEL(config->referenceVoltageSource); + base->SC2 = tmp32; + + /* ADCx_SC3. */ + if (config->enableContinuousConversion) + { + base->SC3 |= ADC_SC3_ADCO_MASK; + } + else + { + base->SC3 &= ~ADC_SC3_ADCO_MASK; + } +} + +void ADC16_Deinit(ADC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_adc16Clocks[ADC16_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void ADC16_GetDefaultConfig(adc16_config_t *config) +{ + assert(NULL != config); + + config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; + config->clockSource = kADC16_ClockSourceAsynchronousClock; + config->enableAsynchronousClock = true; + config->clockDivider = kADC16_ClockDivider8; + config->resolution = kADC16_ResolutionSE12Bit; + config->longSampleMode = kADC16_LongSampleDisabled; + config->enableHighSpeed = false; + config->enableLowPower = false; + config->enableContinuousConversion = false; +} + +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION +status_t ADC16_DoAutoCalibration(ADC_Type *base) +{ + bool bHWTrigger = false; + volatile uint32_t tmp32; /* 'volatile' here is for the dummy read of ADCx_R[0] register. */ + status_t status = kStatus_Success; + + /* The calibration would be failed when in hardwar mode. + * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/ + if (0U != (ADC_SC2_ADTRG_MASK & base->SC2)) + { + bHWTrigger = true; + base->SC2 &= ~ADC_SC2_ADTRG_MASK; + } + + /* Clear the CALF and launch the calibration. */ + base->SC3 |= ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK; + while (0U == (kADC16_ChannelConversionDoneFlag & ADC16_GetChannelStatusFlags(base, 0U))) + { + /* Check the CALF when the calibration is active. */ + if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) + { + status = kStatus_Fail; + break; + } + } + tmp32 = base->R[0]; /* Dummy read to clear COCO caused by calibration. */ + + /* Restore the hardware trigger setting if it was enabled before. */ + if (bHWTrigger) + { + base->SC2 |= ADC_SC2_ADTRG_MASK; + } + /* Check the CALF at the end of calibration. */ + if (0U != (kADC16_CalibrationFailedFlag & ADC16_GetStatusFlags(base))) + { + status = kStatus_Fail; + } + if (kStatus_Success != status) /* Check if the calibration process is succeed. */ + { + return status; + } + + /* Calculate the calibration values. */ + tmp32 = base->CLP0 + base->CLP1 + base->CLP2 + base->CLP3 + base->CLP4 + base->CLPS; + tmp32 = 0x8000U | (tmp32 >> 1U); + base->PG = tmp32; + +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + tmp32 = base->CLM0 + base->CLM1 + base->CLM2 + base->CLM3 + base->CLM4 + base->CLMS; + tmp32 = 0x8000U | (tmp32 >> 1U); + base->MG = tmp32; +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + + return kStatus_Success; +} +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode) +{ + if (kADC16_ChannelMuxA == mode) + { + base->CFG2 &= ~ADC_CFG2_MUXSEL_MASK; + } + else /* kADC16_ChannelMuxB. */ + { + base->CFG2 |= ADC_CFG2_MUXSEL_MASK; + } +} +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config) +{ + uint32_t tmp32 = base->SC2 & ~(ADC_SC2_ACFE_MASK | ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK); + + if (!config) /* Pass "NULL" to disable the feature. */ + { + base->SC2 = tmp32; + return; + } + /* Enable the feature. */ + tmp32 |= ADC_SC2_ACFE_MASK; + + /* Select the hardware compare working mode. */ + switch (config->hardwareCompareMode) + { + case kADC16_HardwareCompareMode0: + break; + case kADC16_HardwareCompareMode1: + tmp32 |= ADC_SC2_ACFGT_MASK; + break; + case kADC16_HardwareCompareMode2: + tmp32 |= ADC_SC2_ACREN_MASK; + break; + case kADC16_HardwareCompareMode3: + tmp32 |= ADC_SC2_ACFGT_MASK | ADC_SC2_ACREN_MASK; + break; + default: + break; + } + base->SC2 = tmp32; + + /* Load the compare values. */ + base->CV1 = ADC_CV1_CV(config->value1); + base->CV2 = ADC_CV2_CV(config->value2); +} + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode) +{ + uint32_t tmp32 = base->SC3 & ~(ADC_SC3_AVGE_MASK | ADC_SC3_AVGS_MASK); + + if (kADC16_HardwareAverageDisabled != mode) + { + tmp32 |= ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(mode); + } + base->SC3 = tmp32; +} +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config) +{ + uint32_t tmp32; + + if (!config) /* Passing "NULL" is to disable the feature. */ + { + base->PGA = 0U; + return; + } + + /* Enable the PGA and set the gain value. */ + tmp32 = ADC_PGA_PGAEN_MASK | ADC_PGA_PGAG(config->pgaGain); + + /* Configure the misc features for PGA. */ + if (config->enableRunInNormalMode) + { + tmp32 |= ADC_PGA_PGALPb_MASK; + } +#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING + if (config->disablePgaChopping) + { + tmp32 |= ADC_PGA_PGACHPb_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT + if (config->enableRunInOffsetMeasurement) + { + tmp32 |= ADC_PGA_PGAOFSM_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ + base->PGA = tmp32; +} +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +uint32_t ADC16_GetStatusFlags(ADC_Type *base) +{ + uint32_t ret = 0; + + if (0U != (base->SC2 & ADC_SC2_ADACT_MASK)) + { + ret |= kADC16_ActiveFlag; + } +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + if (0U != (base->SC3 & ADC_SC3_CALF_MASK)) + { + ret |= kADC16_CalibrationFailedFlag; + } +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + return ret; +} + +void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + if (0U != (mask & kADC16_CalibrationFailedFlag)) + { + base->SC3 |= ADC_SC3_CALF_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ +} + +void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config) +{ + assert(channelGroup < ADC_SC1_COUNT); + assert(NULL != config); + + uint32_t sc1 = ADC_SC1_ADCH(config->channelNumber); /* Set the channel number. */ + +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + /* Enable the differential conversion. */ + if (config->enableDifferentialConversion) + { + sc1 |= ADC_SC1_DIFF_MASK; + } +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + /* Enable the interrupt when the conversion is done. */ + if (config->enableInterruptOnConversionCompleted) + { + sc1 |= ADC_SC1_AIEN_MASK; + } + base->SC1[channelGroup] = sc1; +} + +uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_SC1_COUNT); + + uint32_t ret = 0U; + + if (0U != (base->SC1[channelGroup] & ADC_SC1_COCO_MASK)) + { + ret |= kADC16_ChannelConversionDoneFlag; + } + return ret; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_adc16.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_adc16.h new file mode 100644 index 00000000000..ea62c55fee6 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_adc16.h @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_ADC16_H_ +#define _FSL_ADC16_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup adc16 + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief ADC16 driver version 2.0.0. */ +#define FSL_ADC16_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @brief Channel status flags. + */ +enum _adc16_channel_status_flags +{ + kADC16_ChannelConversionDoneFlag = ADC_SC1_COCO_MASK, /*!< Conversion done. */ +}; + +/*! + * @brief Converter status flags. + */ +enum _adc16_status_flags +{ + kADC16_ActiveFlag = ADC_SC2_ADACT_MASK, /*!< Converter is active. */ +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION + kADC16_CalibrationFailedFlag = ADC_SC3_CALF_MASK, /*!< Calibration is failed. */ +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ +}; + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +/*! + * @brief Channel multiplexer mode for each channel. + * + * For some ADC16 channels, there are two pin selections in channel multiplexer. For example, ADC0_SE4a and ADC0_SE4b + * are the different channels that share the same channel number. + */ +typedef enum _adc_channel_mux_mode +{ + kADC16_ChannelMuxA = 0U, /*!< For channel with channel mux a. */ + kADC16_ChannelMuxB = 1U, /*!< For channel with channel mux b. */ +} adc16_channel_mux_mode_t; +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +/*! + * @brief Clock divider for the converter. + */ +typedef enum _adc16_clock_divider +{ + kADC16_ClockDivider1 = 0U, /*!< For divider 1 from the input clock to the module. */ + kADC16_ClockDivider2 = 1U, /*!< For divider 2 from the input clock to the module. */ + kADC16_ClockDivider4 = 2U, /*!< For divider 4 from the input clock to the module. */ + kADC16_ClockDivider8 = 3U, /*!< For divider 8 from the input clock to the module. */ +} adc16_clock_divider_t; + +/*! + *@brief Converter's resolution. + */ +typedef enum _adc16_resolution +{ + /* This group of enumeration is for internal use which is related to register setting. */ + kADC16_Resolution8or9Bit = 0U, /*!< Single End 8-bit or Differential Sample 9-bit. */ + kADC16_Resolution12or13Bit = 1U, /*!< Single End 12-bit or Differential Sample 13-bit. */ + kADC16_Resolution10or11Bit = 2U, /*!< Single End 10-bit or Differential Sample 11-bit. */ + + /* This group of enumeration is for a public user. */ + kADC16_ResolutionSE8Bit = kADC16_Resolution8or9Bit, /*!< Single End 8-bit. */ + kADC16_ResolutionSE12Bit = kADC16_Resolution12or13Bit, /*!< Single End 12-bit. */ + kADC16_ResolutionSE10Bit = kADC16_Resolution10or11Bit, /*!< Single End 10-bit. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + kADC16_ResolutionDF9Bit = kADC16_Resolution8or9Bit, /*!< Differential Sample 9-bit. */ + kADC16_ResolutionDF13Bit = kADC16_Resolution12or13Bit, /*!< Differential Sample 13-bit. */ + kADC16_ResolutionDF11Bit = kADC16_Resolution10or11Bit, /*!< Differential Sample 11-bit. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + +#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U) + /* 16-bit is supported by default. */ + kADC16_Resolution16Bit = 3U, /*!< Single End 16-bit or Differential Sample 16-bit. */ + kADC16_ResolutionSE16Bit = kADC16_Resolution16Bit, /*!< Single End 16-bit. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + kADC16_ResolutionDF16Bit = kADC16_Resolution16Bit, /*!< Differential Sample 16-bit. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ +#endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U */ +} adc16_resolution_t; + +/*! + * @brief Clock source. + */ +typedef enum _adc16_clock_source +{ + kADC16_ClockSourceAlt0 = 0U, /*!< Selection 0 of the clock source. */ + kADC16_ClockSourceAlt1 = 1U, /*!< Selection 1 of the clock source. */ + kADC16_ClockSourceAlt2 = 2U, /*!< Selection 2 of the clock source. */ + kADC16_ClockSourceAlt3 = 3U, /*!< Selection 3 of the clock source. */ + + /* Chip defined clock source */ + kADC16_ClockSourceAsynchronousClock = kADC16_ClockSourceAlt3, /*!< Using internal asynchronous clock. */ +} adc16_clock_source_t; + +/*! + * @brief Long sample mode. + */ +typedef enum _adc16_long_sample_mode +{ + kADC16_LongSampleCycle24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */ + kADC16_LongSampleCycle16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */ + kADC16_LongSampleCycle10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */ + kADC16_LongSampleCycle6 = 3U, /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */ + kADC16_LongSampleDisabled = 4U, /*!< Disable the long sample feature. */ +} adc16_long_sample_mode_t; + +/*! + * @brief Reference voltage source. + */ +typedef enum _adc16_reference_voltage_source +{ + kADC16_ReferenceVoltageSourceVref = 0U, /*!< For external pins pair of VrefH and VrefL. */ + kADC16_ReferenceVoltageSourceValt = 1U, /*!< For alternate reference pair of ValtH and ValtL. */ +} adc16_reference_voltage_source_t; + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * @brief Hardware average mode. + */ +typedef enum _adc16_hardware_average_mode +{ + kADC16_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ + kADC16_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ + kADC16_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ + kADC16_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ + kADC16_HardwareAverageDisabled = 4U, /*!< Disable the hardware average feature.*/ +} adc16_hardware_average_mode_t; +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +/*! + * @brief Hardware compare mode. + */ +typedef enum _adc16_hardware_compare_mode +{ + kADC16_HardwareCompareMode0 = 0U, /*!< x < value1. */ + kADC16_HardwareCompareMode1 = 1U, /*!< x > value1. */ + kADC16_HardwareCompareMode2 = 2U, /*!< if value1 <= value2, then x < value1 || x > value2; + else, value1 > x > value2. */ + kADC16_HardwareCompareMode3 = 3U, /*!< if value1 <= value2, then value1 <= x <= value2; + else x >= value1 || x <= value2. */ +} adc16_hardware_compare_mode_t; + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief PGA's Gain mode. + */ +typedef enum _adc16_pga_gain +{ + kADC16_PGAGainValueOf1 = 0U, /*!< For amplifier gain of 1. */ + kADC16_PGAGainValueOf2 = 1U, /*!< For amplifier gain of 2. */ + kADC16_PGAGainValueOf4 = 2U, /*!< For amplifier gain of 4. */ + kADC16_PGAGainValueOf8 = 3U, /*!< For amplifier gain of 8. */ + kADC16_PGAGainValueOf16 = 4U, /*!< For amplifier gain of 16. */ + kADC16_PGAGainValueOf32 = 5U, /*!< For amplifier gain of 32. */ + kADC16_PGAGainValueOf64 = 6U, /*!< For amplifier gain of 64. */ +} adc16_pga_gain_t; +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +/*! + * @brief ADC16 converter configuration. + */ +typedef struct _adc16_config +{ + adc16_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ + adc16_clock_source_t clockSource; /*!< Select the input clock source to converter. */ + bool enableAsynchronousClock; /*!< Enable the asynchronous clock output. */ + adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock source. */ + adc16_resolution_t resolution; /*!< Select the sample resolution mode. */ + adc16_long_sample_mode_t longSampleMode; /*!< Select the long sample mode. */ + bool enableHighSpeed; /*!< Enable the high-speed mode. */ + bool enableLowPower; /*!< Enable low power. */ + bool enableContinuousConversion; /*!< Enable continuous conversion mode. */ +} adc16_config_t; + +/*! + * @brief ADC16 Hardware comparison configuration. + */ +typedef struct _adc16_hardware_compare_config +{ + adc16_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode. + See "adc16_hardware_compare_mode_t". */ + int16_t value1; /*!< Setting value1 for hardware compare mode. */ + int16_t value2; /*!< Setting value2 for hardware compare mode. */ +} adc16_hardware_compare_config_t; + +/*! + * @brief ADC16 channel conversion configuration. + */ +typedef struct _adc16_channel_config +{ + uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31. + See channel connection information for each chip in Reference + Manual document. */ + bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */ +#if defined(FSL_FEATURE_ADC16_HAS_DIFF_MODE) && FSL_FEATURE_ADC16_HAS_DIFF_MODE + bool enableDifferentialConversion; /*!< Using Differential sample mode. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ +} adc16_channel_config_t; + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief ADC16 programmable gain amplifier configuration. + */ +typedef struct _adc16_pga_config +{ + adc16_pga_gain_t pgaGain; /*!< Setting PGA gain. */ + bool enableRunInNormalMode; /*!< Enable PGA working in normal mode, or low power mode by default. */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_CHOPPING) && FSL_FEATURE_ADC16_HAS_PGA_CHOPPING + bool disablePgaChopping; /*!< Disable the PGA chopping function. + The PGA employs chopping to remove/reduce offset and 1/f noise and offers + an offset measurement configuration that aids the offset calibration. */ +#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ +#if defined(FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT) && FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT + bool enableRunInOffsetMeasurement; /*!< Enable the PGA working in offset measurement mode. + When this feature is enabled, the PGA disconnects itself from the external + inputs and auto-configures into offset measurement mode. With this field + set, run the ADC in the recommended settings and enable the maximum hardware + averaging to get the PGA offset number. The output is the + (PGA offset * (64+1)) for the given PGA setting. */ +#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ +} adc16_pga_config_t; +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the ADC16 module. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to configuration structure. See "adc16_config_t". + */ +void ADC16_Init(ADC_Type *base, const adc16_config_t *config); + +/*! + * @brief De-initializes the ADC16 module. + * + * @param base ADC16 peripheral base address. + */ +void ADC16_Deinit(ADC_Type *base); + +/*! + * @brief Gets an available pre-defined settings for the converter's configuration. + * + * This function initializes the converter configuration structure with available settings. The default values are as follows. + * @code + * config->referenceVoltageSource = kADC16_ReferenceVoltageSourceVref; + * config->clockSource = kADC16_ClockSourceAsynchronousClock; + * config->enableAsynchronousClock = true; + * config->clockDivider = kADC16_ClockDivider8; + * config->resolution = kADC16_ResolutionSE12Bit; + * config->longSampleMode = kADC16_LongSampleDisabled; + * config->enableHighSpeed = false; + * config->enableLowPower = false; + * config->enableContinuousConversion = false; + * @endcode + * @param config Pointer to the configuration structure. + */ +void ADC16_GetDefaultConfig(adc16_config_t *config); + +#if defined(FSL_FEATURE_ADC16_HAS_CALIBRATION) && FSL_FEATURE_ADC16_HAS_CALIBRATION +/*! + * @brief Automates the hardware calibration. + * + * This auto calibration helps to adjust the plus/minus side gain automatically. + * Execute the calibration before using the converter. Note that the hardware trigger should be used + * during the calibration. + * + * @param base ADC16 peripheral base address. + * + * @return Execution status. + * @retval kStatus_Success Calibration is done successfully. + * @retval kStatus_Fail Calibration has failed. + */ +status_t ADC16_DoAutoCalibration(ADC_Type *base); +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + +#if defined(FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION) && FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION +/*! + * @brief Sets the offset value for the conversion result. + * + * This offset value takes effect on the conversion result. If the offset value is not zero, the reading result + * is subtracted by it. Note, the hardware calibration fills the offset value automatically. + * + * @param base ADC16 peripheral base address. + * @param value Setting offset value. + */ +static inline void ADC16_SetOffsetValue(ADC_Type *base, int16_t value) +{ + base->OFS = (uint32_t)(value); +} +#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */ + +/* @} */ + +/*! + * @name Advanced Features + * @{ + */ + +#if defined(FSL_FEATURE_ADC16_HAS_DMA) && FSL_FEATURE_ADC16_HAS_DMA +/*! + * @brief Enables generating the DMA trigger when the conversion is complete. + * + * @param base ADC16 peripheral base address. + * @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled. + */ +static inline void ADC16_EnableDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SC2 |= ADC_SC2_DMAEN_MASK; + } + else + { + base->SC2 &= ~ADC_SC2_DMAEN_MASK; + } +} +#endif /* FSL_FEATURE_ADC16_HAS_DMA */ + +/*! + * @brief Enables the hardware trigger mode. + * + * @param base ADC16 peripheral base address. + * @param enable Switcher of the hardware trigger feature. "true" means enabled, "false" means not enabled. + */ +static inline void ADC16_EnableHardwareTrigger(ADC_Type *base, bool enable) +{ + if (enable) + { + base->SC2 |= ADC_SC2_ADTRG_MASK; + } + else + { + base->SC2 &= ~ADC_SC2_ADTRG_MASK; + } +} + +#if defined(FSL_FEATURE_ADC16_HAS_MUX_SELECT) && FSL_FEATURE_ADC16_HAS_MUX_SELECT +/*! + * @brief Sets the channel mux mode. + * + * Some sample pins share the same channel index. The channel mux mode decides which pin is used for an + * indicated channel. + * + * @param base ADC16 peripheral base address. + * @param mode Setting channel mux mode. See "adc16_channel_mux_mode_t". + */ +void ADC16_SetChannelMuxMode(ADC_Type *base, adc16_channel_mux_mode_t mode); +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +/*! + * @brief Configures the hardware compare mode. + * + * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the result + * in the compare range is available. To compare the range, see "adc16_hardware_compare_mode_t" or the appopriate reference + * manual for more information. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to the "adc16_hardware_compare_config_t" structure. Passing "NULL" disables the feature. + */ +void ADC16_SetHardwareCompareConfig(ADC_Type *base, const adc16_hardware_compare_config_t *config); + +#if defined(FSL_FEATURE_ADC16_HAS_HW_AVERAGE) && FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * @brief Sets the hardware average mode. + * + * The hardware average mode provides a way to process the conversion result automatically by using hardware. The multiple + * conversion results are accumulated and averaged internally making them easier to read. + * + * @param base ADC16 peripheral base address. + * @param mode Setting the hardware average mode. See "adc16_hardware_average_mode_t". + */ +void ADC16_SetHardwareAverage(ADC_Type *base, adc16_hardware_average_mode_t mode); +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +#if defined(FSL_FEATURE_ADC16_HAS_PGA) && FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief Configures the PGA for the converter's front end. + * + * @param base ADC16 peripheral base address. + * @param config Pointer to the "adc16_pga_config_t" structure. Passing "NULL" disables the feature. + */ +void ADC16_SetPGAConfig(ADC_Type *base, const adc16_pga_config_t *config); +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +/*! + * @brief Gets the status flags of the converter. + * + * @param base ADC16 peripheral base address. + * + * @return Flags' mask if indicated flags are asserted. See "_adc16_status_flags". + */ +uint32_t ADC16_GetStatusFlags(ADC_Type *base); + +/*! + * @brief Clears the status flags of the converter. + * + * @param base ADC16 peripheral base address. + * @param mask Mask value for the cleared flags. See "_adc16_status_flags". + */ +void ADC16_ClearStatusFlags(ADC_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Conversion Channel + * @{ + */ + +/*! + * @brief Configures the conversion channel. + * + * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API + * configures the channel while the external trigger source helps to trigger the conversion. + * + * Note that the "Channel Group" has a detailed description. + * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one + * group of status and control registers, one for each conversion. The channel group parameter indicates which group of + * registers are used, for example, channel group 0 is for Group A registers and channel group 1 is for Group B registers. The + * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of + * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and hardware + * trigger modes. Channel group 1 and greater indicates multiple channel group registers for + * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual for the + * number of SC1n registers (channel groups) specific to this device. Channel group 1 or greater are not used + * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion. + * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and + * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a + * conversion aborts the current conversion. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * @param config Pointer to the "adc16_channel_config_t" structure for the conversion channel. + */ +void ADC16_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc16_channel_config_t *config); + +/*! + * @brief Gets the conversion value. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * + * @return Conversion value. + */ +static inline uint32_t ADC16_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < ADC_R_COUNT); + + return base->R[channelGroup]; +} + +/*! + * @brief Gets the status flags of channel. + * + * @param base ADC16 peripheral base address. + * @param channelGroup Channel group index. + * + * @return Flags' mask if indicated flags are asserted. See "_adc16_channel_status_flags". + */ +uint32_t ADC16_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_ADC16_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_clock.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_clock.c new file mode 100644 index 00000000000..12048524dd9 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_clock.c @@ -0,0 +1,1793 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Macro definition remap workaround. */ +#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) +#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK +#endif +#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) +#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK +#endif +#if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK))) +#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK +#endif +#if (defined(MCG_C6_CME_MASK) && !(defined(MCG_C6_CME0_MASK))) +#define MCG_C6_CME0_MASK MCG_C6_CME_MASK +#endif + +/* PLL fixed multiplier when there is not PRDIV and VDIV. */ +#define PLL_FIXED_MULT (375U) +/* Max frequency of the reference clock used for internal clock trim. */ +#define TRIM_REF_CLK_MIN (8000000U) +/* Min frequency of the reference clock used for internal clock trim. */ +#define TRIM_REF_CLK_MAX (16000000U) +/* Max trim value of fast internal reference clock. */ +#define TRIM_FIRC_MAX (5000000U) +/* Min trim value of fast internal reference clock. */ +#define TRIM_FIRC_MIN (3000000U) +/* Max trim value of fast internal reference clock. */ +#define TRIM_SIRC_MAX (39063U) +/* Min trim value of fast internal reference clock. */ +#define TRIM_SIRC_MIN (31250U) + +#define MCG_S_IRCST_VAL ((MCG->S & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT) +#define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) +#define MCG_S_IREFST_VAL ((MCG->S & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT) +#define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT) +#define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT) +#define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT) +#define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT) +#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT) +#define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT) +#define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT) +#define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT) +#define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT) +#define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT) +#define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT) +#define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT) +#define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT) +#define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT) +#define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT) +#define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT) + +#define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK) + +#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT) +#define SIM_CLKDIV1_OUTDIV2_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) +#define SIM_CLKDIV1_OUTDIV3_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT) +#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) +#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT) +#define SIM_SOPT2_PLLFLLSEL_VAL ((SIM->SOPT2 & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT) + +/* MCG_S_CLKST definition. */ +enum _mcg_clkout_stat +{ + kMCG_ClkOutStatFll, /* FLL. */ + kMCG_ClkOutStatInt, /* Internal clock. */ + kMCG_ClkOutStatExt, /* External clock. */ + kMCG_ClkOutStatPll /* PLL. */ +}; + +/* MCG_S_PLLST definition. */ +enum _mcg_pllst +{ + kMCG_PllstFll, /* FLL is used. */ + kMCG_PllstPll /* PLL is used. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Slow internal reference clock frequency. */ +static uint32_t s_slowIrcFreq = 32768U; +/* Fast internal reference clock frequency. */ +static uint32_t s_fastIrcFreq = 4000000U; + +/* External XTAL0 (OSC0) clock frequency. */ +uint32_t g_xtal0Freq; +/* External XTAL32K clock frequency. */ +uint32_t g_xtal32Freq; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the MCG external reference clock frequency. + * + * Get the current MCG external reference clock frequency in Hz. It is + * the frequency select by MCG_C7[OSCSEL]. This is an internal function. + * + * @return MCG external reference clock frequency in Hz. + */ +static uint32_t CLOCK_GetMcgExtClkFreq(void); + +/*! + * @brief Get the MCG FLL external reference clock frequency. + * + * Get the current MCG FLL external reference clock frequency in Hz. It is + * the frequency after by MCG_C1[FRDIV]. This is an internal function. + * + * @return MCG FLL external reference clock frequency in Hz. + */ +static uint32_t CLOCK_GetFllExtRefClkFreq(void); + +/*! + * @brief Get the MCG FLL reference clock frequency. + * + * Get the current MCG FLL reference clock frequency in Hz. It is + * the frequency select by MCG_C1[IREFS]. This is an internal function. + * + * @return MCG FLL reference clock frequency in Hz. + */ +static uint32_t CLOCK_GetFllRefClkFreq(void); + +/*! + * @brief Get the frequency of clock selected by MCG_C2[IRCS]. + * + * This clock's two output: + * 1. MCGOUTCLK when MCG_S[CLKST]=0. + * 2. MCGIRCLK when MCG_C1[IRCLKEN]=1. + * + * @return The frequency in Hz. + */ +static uint32_t CLOCK_GetInternalRefClkSelectFreq(void); + +/*! + * @brief Get the MCG PLL/PLL0 reference clock frequency. + * + * Get the current MCG PLL/PLL0 reference clock frequency in Hz. + * This is an internal function. + * + * @return MCG PLL/PLL0 reference clock frequency in Hz. + */ +static uint32_t CLOCK_GetPll0RefFreq(void); + +/*! + * @brief Calculate the RANGE value base on crystal frequency. + * + * To setup external crystal oscillator, must set the register bits RANGE + * base on the crystal frequency. This function returns the RANGE base on the + * input frequency. This is an internal function. + * + * @param freq Crystal frequency in Hz. + * @return The RANGE value. + */ +static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq); + +/******************************************************************************* + * Code + ******************************************************************************/ + +#ifndef MCG_USER_CONFIG_FLL_STABLE_DELAY_EN +/*! + * @brief Delay function to wait FLL stable. + * + * Delay function to wait FLL stable in FEI mode or FEE mode, should wait at least + * 1ms. Every time changes FLL setting, should wait this time for FLL stable. + */ +void CLOCK_FllStableDelay(void) +{ + /* + Should wait at least 1ms. Because in these modes, the core clock is 100MHz + at most, so this function could obtain the 1ms delay. + */ + volatile uint32_t i = 30000U; + while (i--) + { + __NOP(); + } +} +#else /* With MCG_USER_CONFIG_FLL_STABLE_DELAY_EN defined. */ +/* Once user defines the MCG_USER_CONFIG_FLL_STABLE_DELAY_EN to use their own delay function, he has to + * create his own CLOCK_FllStableDelay() function in application code. Since the clock functions in this + * file would call the CLOCK_FllStableDelay() regardness how it is defined. + */ +extern void CLOCK_FllStableDelay(void); +#endif /* MCG_USER_CONFIG_FLL_STABLE_DELAY_EN */ + +static uint32_t CLOCK_GetMcgExtClkFreq(void) +{ + uint32_t freq; + + switch (MCG_C7_OSCSEL_VAL) + { + case 0U: + /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ + assert(g_xtal0Freq); + freq = g_xtal0Freq; + break; + case 1U: + /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ + assert(g_xtal32Freq); + freq = g_xtal32Freq; + break; + case 2U: + freq = MCG_INTERNAL_IRC_48M; + break; + default: + freq = 0U; + break; + } + + return freq; +} + +static uint32_t CLOCK_GetFllExtRefClkFreq(void) +{ + /* FllExtRef = McgExtRef / FllExtRefDiv */ + uint8_t frdiv; + uint8_t range; + uint8_t oscsel; + + uint32_t freq = CLOCK_GetMcgExtClkFreq(); + + if (!freq) + { + return freq; + } + + frdiv = MCG_C1_FRDIV_VAL; + freq >>= frdiv; + + range = MCG_C2_RANGE_VAL; + oscsel = MCG_C7_OSCSEL_VAL; + + /* + When should use divider 32, 64, 128, 256, 512, 1024, 1280, 1536. + 1. MCG_C7[OSCSEL] selects IRC48M. + 2. MCG_C7[OSCSEL] selects OSC0 and MCG_C2[RANGE] is not 0. + */ + if (((0U != range) && (kMCG_OscselOsc == oscsel)) || (kMCG_OscselIrc == oscsel)) + { + switch (frdiv) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + freq >>= 5u; + break; + case 6: + /* 64*20=1280 */ + freq /= 20u; + break; + case 7: + /* 128*12=1536 */ + freq /= 12u; + break; + default: + freq = 0u; + break; + } + } + + return freq; +} + +static uint32_t CLOCK_GetInternalRefClkSelectFreq(void) +{ + if (kMCG_IrcSlow == MCG_S_IRCST_VAL) + { + /* Slow internal reference clock selected*/ + return s_slowIrcFreq; + } + else + { + /* Fast internal reference clock selected*/ + return s_fastIrcFreq >> MCG_SC_FCRDIV_VAL; + } +} + +static uint32_t CLOCK_GetFllRefClkFreq(void) +{ + /* If use external reference clock. */ + if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) + { + return CLOCK_GetFllExtRefClkFreq(); + } + /* If use internal reference clock. */ + else + { + return s_slowIrcFreq; + } +} + +static uint32_t CLOCK_GetPll0RefFreq(void) +{ + /* MCG external reference clock. */ + return CLOCK_GetMcgExtClkFreq(); +} + +static uint8_t CLOCK_GetOscRangeFromFreq(uint32_t freq) +{ + uint8_t range; + + if (freq <= 39063U) + { + range = 0U; + } + else if (freq <= 8000000U) + { + range = 1U; + } + else + { + range = 2U; + } + + return range; +} + +uint32_t CLOCK_GetOsc0ErClkFreq(void) +{ + if (OSC0->CR & OSC_CR_ERCLKEN_MASK) + { + /* Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. */ + assert(g_xtal0Freq); + return g_xtal0Freq; + } + else + { + return 0U; + } +} + +/* Function Name : CLOCK_GetEr32kClkFreq */ +uint32_t CLOCK_GetEr32kClkFreq(void) +{ + uint32_t freq; + + switch (SIM_SOPT1_OSC32KSEL_VAL) + { + case 0U: /* OSC 32k clock */ + freq = (CLOCK_GetOsc0ErClkFreq() == 32768U) ? 32768U : 0U; + break; + case 2U: /* RTC 32k clock */ + /* Please call CLOCK_SetXtal32Freq base on board setting before using XTAL32K/RTC_CLKIN clock. */ + assert(g_xtal32Freq); + freq = g_xtal32Freq; + break; + case 3U: /* LPO clock */ + freq = LPO_CLK_FREQ; + break; + default: + freq = 0U; + break; + } + return freq; +} + +uint32_t CLOCK_GetPllFllSelClkFreq(void) +{ + uint32_t freq; + + switch (SIM_SOPT2_PLLFLLSEL_VAL) + { + case 0U: /* FLL. */ + freq = CLOCK_GetFllFreq(); + break; + case 1U: /* PLL. */ + freq = CLOCK_GetPll0Freq(); + break; + case 3U: /* MCG IRC48M. */ + freq = MCG_INTERNAL_IRC_48M; + break; + default: + freq = 0U; + break; + } + + return freq; +} + +uint32_t CLOCK_GetFlashClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1); +} + +uint32_t CLOCK_GetFlexBusClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1); +} + +uint32_t CLOCK_GetBusClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1); +} + +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + return CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); +} + +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV1_VAL + 1); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV2_VAL + 1); + break; + case kCLOCK_FlexBusClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV3_VAL + 1); + break; + case kCLOCK_FlashClk: + freq = CLOCK_GetOutClkFreq() / (SIM_CLKDIV1_OUTDIV4_VAL + 1); + break; + case kCLOCK_PllFllSelClk: + freq = CLOCK_GetPllFllSelClkFreq(); + break; + case kCLOCK_Er32kClk: + freq = CLOCK_GetEr32kClkFreq(); + break; + case kCLOCK_McgFixedFreqClk: + freq = CLOCK_GetFixedFreqClkFreq(); + break; + case kCLOCK_McgInternalRefClk: + freq = CLOCK_GetInternalRefClkFreq(); + break; + case kCLOCK_McgFllClk: + freq = CLOCK_GetFllFreq(); + break; + case kCLOCK_McgPll0Clk: + freq = CLOCK_GetPll0Freq(); + break; + case kCLOCK_McgIrc48MClk: + freq = MCG_INTERNAL_IRC_48M; + break; + case kCLOCK_LpoClk: + freq = LPO_CLK_FREQ; + break; + case kCLOCK_Osc0ErClk: + freq = CLOCK_GetOsc0ErClkFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +void CLOCK_SetSimConfig(sim_clock_config_t const *config) +{ + SIM->CLKDIV1 = config->clkdiv1; + CLOCK_SetPllFllSelClock(config->pllFllSel); + CLOCK_SetEr32kClock(config->er32kSrc); +} + +bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbfs0); + + if (kCLOCK_UsbSrcExt == src) + { + SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK; + } + else + { + switch (freq) + { + case 120000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1); + break; + case 96000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0); + break; + case 72000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1); + break; + case 48000000U: + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0); + break; + default: + ret = false; + break; + } + + SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src); + } + + CLOCK_EnableClock(kCLOCK_Usbfs0); + + if (kCLOCK_UsbSrcIrc48M == src) + { + USB0->CLK_RECOVER_IRC_EN = 0x03U; + USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK; + } + return ret; +} + +uint32_t CLOCK_GetOutClkFreq(void) +{ + uint32_t mcgoutclk; + uint32_t clkst = MCG_S_CLKST_VAL; + + switch (clkst) + { + case kMCG_ClkOutStatPll: + mcgoutclk = CLOCK_GetPll0Freq(); + break; + case kMCG_ClkOutStatFll: + mcgoutclk = CLOCK_GetFllFreq(); + break; + case kMCG_ClkOutStatInt: + mcgoutclk = CLOCK_GetInternalRefClkSelectFreq(); + break; + case kMCG_ClkOutStatExt: + mcgoutclk = CLOCK_GetMcgExtClkFreq(); + break; + default: + mcgoutclk = 0U; + break; + } + return mcgoutclk; +} + +uint32_t CLOCK_GetFllFreq(void) +{ + static const uint16_t fllFactorTable[4][2] = {{640, 732}, {1280, 1464}, {1920, 2197}, {2560, 2929}}; + + uint8_t drs, dmx32; + uint32_t freq; + + /* If FLL is not enabled currently, then return 0U. */ + if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK)) + { + return 0U; + } + + /* Get FLL reference clock frequency. */ + freq = CLOCK_GetFllRefClkFreq(); + if (!freq) + { + return freq; + } + + drs = MCG_C4_DRST_DRS_VAL; + dmx32 = MCG_C4_DMX32_VAL; + + return freq * fllFactorTable[drs][dmx32]; +} + +uint32_t CLOCK_GetInternalRefClkFreq(void) +{ + /* If MCGIRCLK is gated. */ + if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK)) + { + return 0U; + } + + return CLOCK_GetInternalRefClkSelectFreq(); +} + +uint32_t CLOCK_GetFixedFreqClkFreq(void) +{ + uint32_t freq = CLOCK_GetFllRefClkFreq(); + + /* MCGFFCLK must be no more than MCGOUTCLK/8. */ + if ((freq) && (freq <= (CLOCK_GetOutClkFreq() / 8U))) + { + return freq; + } + else + { + return 0U; + } +} + +uint32_t CLOCK_GetPll0Freq(void) +{ + uint32_t mcgpll0clk; + + /* If PLL0 is not enabled, return 0. */ + if (!(MCG->S & MCG_S_LOCK0_MASK)) + { + return 0U; + } + + mcgpll0clk = CLOCK_GetPll0RefFreq(); + + /* + * Please call CLOCK_SetXtal0Freq base on board setting before using OSC0 clock. + * Please call CLOCK_SetXtal1Freq base on board setting before using OSC1 clock. + */ + assert(mcgpll0clk); + + mcgpll0clk /= (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_C5_PRDIV0_VAL); + mcgpll0clk *= (FSL_FEATURE_MCG_PLL_VDIV_BASE + MCG_C6_VDIV0_VAL); + + return mcgpll0clk; +} + +status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel) +{ + bool needDelay; + uint32_t i; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + /* If change MCG_C7[OSCSEL] and external reference clock is system clock source, return error. */ + if ((MCG_C7_OSCSEL_VAL != oscsel) && (!(MCG->S & MCG_S_IREFST_MASK))) + { + return kStatus_MCG_SourceUsed; + } +#endif /* MCG_CONFIG_CHECK_PARAM */ + + if (MCG_C7_OSCSEL_VAL != oscsel) + { + /* If change OSCSEL, need to delay, ERR009878. */ + needDelay = true; + } + else + { + needDelay = false; + } + + MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel); + if (needDelay) + { + /* ERR009878 Delay at least 50 micro-seconds for external clock change valid. */ + i = 1500U; + while (i--) + { + __NOP(); + } + } + + return kStatus_Success; +} + +status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv) +{ + uint32_t mcgOutClkState = MCG_S_CLKST_VAL; + mcg_irc_mode_t curIrcs = (mcg_irc_mode_t)MCG_S_IRCST_VAL; + uint8_t curFcrdiv = MCG_SC_FCRDIV_VAL; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + /* If MCGIRCLK is used as system clock source. */ + if (kMCG_ClkOutStatInt == mcgOutClkState) + { + /* If need to change MCGIRCLK source or driver, return error. */ + if (((kMCG_IrcFast == curIrcs) && (fcrdiv != curFcrdiv)) || (ircs != curIrcs)) + { + return kStatus_MCG_SourceUsed; + } + } +#endif + + /* If need to update the FCRDIV. */ + if (fcrdiv != curFcrdiv) + { + /* If fast IRC is in use currently, change to slow IRC. */ + if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCLKEN_MASK))) + { + MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow))); + while (MCG_S_IRCST_VAL != kMCG_IrcSlow) + { + } + } + /* Update FCRDIV. */ + MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv); + } + + /* Set internal reference clock selection. */ + MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs)); + MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode; + + /* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */ + if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable)) + { + while (MCG_S_IRCST_VAL != ircs) + { + } + } + + return kStatus_Success; +} + +uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv) +{ + uint8_t ret_prdiv; /* PRDIV to return. */ + uint8_t ret_vdiv; /* VDIV to return. */ + uint8_t prdiv_min; /* Min PRDIV value to make reference clock in allowed range. */ + uint8_t prdiv_max; /* Max PRDIV value to make reference clock in allowed range. */ + uint8_t prdiv_cur; /* PRDIV value for iteration. */ + uint8_t vdiv_cur; /* VDIV value for iteration. */ + uint32_t ret_freq = 0U; /* PLL output fequency to return. */ + uint32_t diff = 0xFFFFFFFFU; /* Difference between desireFreq and return frequency. */ + uint32_t ref_div; /* Reference frequency after PRDIV. */ + + /* + Steps: + 1. Get allowed prdiv with such rules: + 1). refFreq / prdiv >= FSL_FEATURE_MCG_PLL_REF_MIN. + 2). refFreq / prdiv <= FSL_FEATURE_MCG_PLL_REF_MAX. + 2. For each allowed prdiv, there are two candidate vdiv values: + 1). (desireFreq / (refFreq / prdiv)). + 2). (desireFreq / (refFreq / prdiv)) + 1. + If could get the precise desired frequency, return current prdiv and + vdiv directly. Otherwise choose the one which is closer to desired + frequency. + */ + + /* Reference frequency is out of range. */ + if ((refFreq < FSL_FEATURE_MCG_PLL_REF_MIN) || + (refFreq > (FSL_FEATURE_MCG_PLL_REF_MAX * (FSL_FEATURE_MCG_PLL_PRDIV_MAX + FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) + { + return 0U; + } + + /* refFreq/PRDIV must in a range. First get the allowed PRDIV range. */ + prdiv_max = refFreq / FSL_FEATURE_MCG_PLL_REF_MIN; + prdiv_min = (refFreq + FSL_FEATURE_MCG_PLL_REF_MAX - 1U) / FSL_FEATURE_MCG_PLL_REF_MAX; + + /* PRDIV traversal. */ + for (prdiv_cur = prdiv_max; prdiv_cur >= prdiv_min; prdiv_cur--) + { + /* Reference frequency after PRDIV. */ + ref_div = refFreq / prdiv_cur; + + vdiv_cur = desireFreq / ref_div; + + if ((vdiv_cur < FSL_FEATURE_MCG_PLL_VDIV_BASE - 1U) || (vdiv_cur > FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) + { + /* No VDIV is available with this PRDIV. */ + continue; + } + + ret_freq = vdiv_cur * ref_div; + + if (vdiv_cur >= FSL_FEATURE_MCG_PLL_VDIV_BASE) + { + if (ret_freq == desireFreq) /* If desire frequency is got. */ + { + *prdiv = prdiv_cur - FSL_FEATURE_MCG_PLL_PRDIV_BASE; + *vdiv = vdiv_cur - FSL_FEATURE_MCG_PLL_VDIV_BASE; + return ret_freq; + } + /* New PRDIV/VDIV is closer. */ + if (diff > desireFreq - ret_freq) + { + diff = desireFreq - ret_freq; + ret_prdiv = prdiv_cur; + ret_vdiv = vdiv_cur; + } + } + vdiv_cur++; + if (vdiv_cur <= (FSL_FEATURE_MCG_PLL_VDIV_BASE + 31U)) + { + ret_freq += ref_div; + /* New PRDIV/VDIV is closer. */ + if (diff > ret_freq - desireFreq) + { + diff = ret_freq - desireFreq; + ret_prdiv = prdiv_cur; + ret_vdiv = vdiv_cur; + } + } + } + + if (0xFFFFFFFFU != diff) + { + /* PRDIV/VDIV found. */ + *prdiv = ret_prdiv - FSL_FEATURE_MCG_PLL_PRDIV_BASE; + *vdiv = ret_vdiv - FSL_FEATURE_MCG_PLL_VDIV_BASE; + ret_freq = (refFreq / ret_prdiv) * ret_vdiv; + return ret_freq; + } + else + { + /* No proper PRDIV/VDIV found. */ + return 0U; + } +} + +void CLOCK_EnablePll0(mcg_pll_config_t const *config) +{ + assert(config); + + uint8_t mcg_c5 = 0U; + + mcg_c5 |= MCG_C5_PRDIV0(config->prdiv); + MCG->C5 = mcg_c5; /* Disable the PLL first. */ + + MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv); + + /* Set enable mode. */ + MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode); + + /* Wait for PLL lock. */ + while (!(MCG->S & MCG_S_LOCK0_MASK)) + { + } +} + +void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode) +{ + /* Clear the previous flag, MCG_SC[LOCS0]. */ + MCG->SC &= ~MCG_SC_ATMF_MASK; + + if (kMCG_MonitorNone == mode) + { + MCG->C6 &= ~MCG_C6_CME0_MASK; + } + else + { + if (kMCG_MonitorInt == mode) + { + MCG->C2 &= ~MCG_C2_LOCRE0_MASK; + } + else + { + MCG->C2 |= MCG_C2_LOCRE0_MASK; + } + MCG->C6 |= MCG_C6_CME0_MASK; + } +} + +void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode) +{ + uint8_t mcg_c8 = MCG->C8; + + mcg_c8 &= ~(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK); + + if (kMCG_MonitorNone != mode) + { + if (kMCG_MonitorReset == mode) + { + mcg_c8 |= MCG_C8_LOCRE1_MASK; + } + mcg_c8 |= MCG_C8_CME1_MASK; + } + MCG->C8 = mcg_c8; +} + +void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode) +{ + uint8_t mcg_c8; + + /* Clear previous flag. */ + MCG->S = MCG_S_LOLS0_MASK; + + if (kMCG_MonitorNone == mode) + { + MCG->C6 &= ~MCG_C6_LOLIE0_MASK; + } + else + { + mcg_c8 = MCG->C8; + + mcg_c8 &= ~MCG_C8_LOCS1_MASK; + + if (kMCG_MonitorInt == mode) + { + mcg_c8 &= ~MCG_C8_LOLRE_MASK; + } + else + { + mcg_c8 |= MCG_C8_LOLRE_MASK; + } + MCG->C8 = mcg_c8; + MCG->C6 |= MCG_C6_LOLIE0_MASK; + } +} + +uint32_t CLOCK_GetStatusFlags(void) +{ + uint32_t ret = 0U; + uint8_t mcg_s = MCG->S; + + if (MCG->SC & MCG_SC_LOCS0_MASK) + { + ret |= kMCG_Osc0LostFlag; + } + if (mcg_s & MCG_S_OSCINIT0_MASK) + { + ret |= kMCG_Osc0InitFlag; + } + if (MCG->C8 & MCG_C8_LOCS1_MASK) + { + ret |= kMCG_RtcOscLostFlag; + } + if (mcg_s & MCG_S_LOLS0_MASK) + { + ret |= kMCG_Pll0LostFlag; + } + if (mcg_s & MCG_S_LOCK0_MASK) + { + ret |= kMCG_Pll0LockFlag; + } + return ret; +} + +void CLOCK_ClearStatusFlags(uint32_t mask) +{ + uint8_t reg; + + if (mask & kMCG_Osc0LostFlag) + { + MCG->SC &= ~MCG_SC_ATMF_MASK; + } + if (mask & kMCG_RtcOscLostFlag) + { + reg = MCG->C8; + MCG->C8 = reg; + } + if (mask & kMCG_Pll0LostFlag) + { + MCG->S = MCG_S_LOLS0_MASK; + } +} + +void CLOCK_InitOsc0(osc_config_t const *config) +{ + uint8_t range = CLOCK_GetOscRangeFromFreq(config->freq); + + OSC_SetCapLoad(OSC0, config->capLoad); + OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig); + + MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode); + + if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK)) + { + /* Wait for stable. */ + while (!(MCG->S & MCG_S_OSCINIT0_MASK)) + { + } + } +} + +void CLOCK_DeinitOsc0(void) +{ + OSC0->CR = 0U; + MCG->C2 &= ~OSC_MODE_MASK; +} + +status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms) +{ + uint32_t multi; /* extFreq / desireFreq */ + uint32_t actv; /* Auto trim value. */ + uint8_t mcg_sc; + + static const uint32_t trimRange[2][2] = { + /* Min Max */ + {TRIM_SIRC_MIN, TRIM_SIRC_MAX}, /* Slow IRC. */ + {TRIM_FIRC_MIN, TRIM_FIRC_MAX} /* Fast IRC. */ + }; + + if ((extFreq > TRIM_REF_CLK_MAX) || (extFreq < TRIM_REF_CLK_MIN)) + { + return kStatus_MCG_AtmBusClockInvalid; + } + + /* Check desired frequency range. */ + if ((desireFreq < trimRange[atms][0]) || (desireFreq > trimRange[atms][1])) + { + return kStatus_MCG_AtmDesiredFreqInvalid; + } + + /* + Make sure internal reference clock is not used to generate bus clock. + Here only need to check (MCG_S_IREFST == 1). + */ + if (MCG_S_IREFST(kMCG_FllSrcInternal) == (MCG->S & MCG_S_IREFST_MASK)) + { + return kStatus_MCG_AtmIrcUsed; + } + + multi = extFreq / desireFreq; + actv = multi * 21U; + + if (kMCG_AtmSel4m == atms) + { + actv *= 128U; + } + + /* Now begin to start trim. */ + MCG->ATCVL = (uint8_t)actv; + MCG->ATCVH = (uint8_t)(actv >> 8U); + + mcg_sc = MCG->SC; + mcg_sc &= ~(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK); + mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms)); + MCG->SC = (mcg_sc | MCG_SC_ATME_MASK); + + /* Wait for finished. */ + while (MCG->SC & MCG_SC_ATME_MASK) + { + } + + /* Error occurs? */ + if (MCG->SC & MCG_SC_ATMF_MASK) + { + /* Clear the failed flag. */ + MCG->SC = mcg_sc; + return kStatus_MCG_AtmHardwareFail; + } + + *actualFreq = extFreq / multi; + + if (kMCG_AtmSel4m == atms) + { + s_fastIrcFreq = *actualFreq; + } + else + { + s_slowIrcFreq = *actualFreq; + } + + return kStatus_Success; +} + +mcg_mode_t CLOCK_GetMode(void) +{ + mcg_mode_t mode = kMCG_ModeError; + uint32_t clkst = MCG_S_CLKST_VAL; + uint32_t irefst = MCG_S_IREFST_VAL; + uint32_t lp = MCG_C2_LP_VAL; + uint32_t pllst = MCG_S_PLLST_VAL; + + /*------------------------------------------------------------------ + Mode and Registers + ____________________________________________________________________ + + Mode | CLKST | IREFST | PLLST | LP + ____________________________________________________________________ + + FEI | 00(FLL) | 1(INT) | 0(FLL) | X + ____________________________________________________________________ + + FEE | 00(FLL) | 0(EXT) | 0(FLL) | X + ____________________________________________________________________ + + FBE | 10(EXT) | 0(EXT) | 0(FLL) | 0(NORMAL) + ____________________________________________________________________ + + FBI | 01(INT) | 1(INT) | 0(FLL) | 0(NORMAL) + ____________________________________________________________________ + + BLPI | 01(INT) | 1(INT) | 0(FLL) | 1(LOW POWER) + ____________________________________________________________________ + + BLPE | 10(EXT) | 0(EXT) | X | 1(LOW POWER) + ____________________________________________________________________ + + PEE | 11(PLL) | 0(EXT) | 1(PLL) | X + ____________________________________________________________________ + + PBE | 10(EXT) | 0(EXT) | 1(PLL) | O(NORMAL) + ____________________________________________________________________ + + PBI | 01(INT) | 1(INT) | 1(PLL) | 0(NORMAL) + ____________________________________________________________________ + + PEI | 11(PLL) | 1(INT) | 1(PLL) | X + ____________________________________________________________________ + + ----------------------------------------------------------------------*/ + + switch (clkst) + { + case kMCG_ClkOutStatFll: + if (kMCG_FllSrcExternal == irefst) + { + mode = kMCG_ModeFEE; + } + else + { + mode = kMCG_ModeFEI; + } + break; + case kMCG_ClkOutStatInt: + if (lp) + { + mode = kMCG_ModeBLPI; + } + else + { + { + mode = kMCG_ModeFBI; + } + } + break; + case kMCG_ClkOutStatExt: + if (lp) + { + mode = kMCG_ModeBLPE; + } + else + { + if (kMCG_PllstPll == pllst) + { + mode = kMCG_ModePBE; + } + else + { + mode = kMCG_ModeFBE; + } + } + break; + case kMCG_ClkOutStatPll: + { + mode = kMCG_ModePEE; + } + break; + default: + break; + } + + return mode; +} + +status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + uint8_t mcg_c4; + bool change_drs = false; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + if (!((kMCG_ModeFEI == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEE == mode))) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + mcg_c4 = MCG->C4; + + /* + Errata: ERR007993 + Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before + reference clock source changes, then reset to previous value after + reference clock changes. + */ + if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) + { + change_drs = true; + /* Change the LSB of DRST_DRS. */ + MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); + } + + /* Set CLKS and IREFS. */ + MCG->C1 = + ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ + | MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */ + + /* Wait and check status. */ + while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL) + { + } + + /* Errata: ERR007993 */ + if (change_drs) + { + MCG->C4 = mcg_c4; + } + + /* In FEI mode, the MCG_C4[DMX32] is set to 0U. */ + MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)); + + /* Check MCG_S[CLKST] */ + while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) + { + } + + /* Wait for FLL stable time. */ + if (fllStableDelay) + { + fllStableDelay(); + } + + return kStatus_Success; +} + +status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + uint8_t mcg_c4; + bool change_drs = false; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode))) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + mcg_c4 = MCG->C4; + + /* + Errata: ERR007993 + Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before + reference clock source changes, then reset to previous value after + reference clock changes. + */ + if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL) + { + change_drs = true; + /* Change the LSB of DRST_DRS. */ + MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); + } + + /* Set CLKS and IREFS. */ + MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */ + | MCG_C1_FRDIV(frdiv) /* FRDIV */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + + /* If use external crystal as clock source, wait for it stable. */ + if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) + { + if (MCG->C2 & MCG_C2_EREFS_MASK) + { + while (!(MCG->S & MCG_S_OSCINIT0_MASK)) + { + } + } + } + + /* Wait and check status. */ + while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL) + { + } + + /* Errata: ERR007993 */ + if (change_drs) + { + MCG->C4 = mcg_c4; + } + + /* Set DRS and DMX32. */ + mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + MCG->C4 = mcg_c4; + + /* Wait for DRST_DRS update. */ + while (MCG->C4 != mcg_c4) + { + } + + /* Check MCG_S[CLKST] */ + while (kMCG_ClkOutStatFll != MCG_S_CLKST_VAL) + { + } + + /* Wait for FLL stable time. */ + if (fllStableDelay) + { + fllStableDelay(); + } + + return kStatus_Success; +} + +status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + uint8_t mcg_c4; + bool change_drs = false; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + + if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || + (kMCG_ModeBLPI == mode))) + + { + return kStatus_MCG_ModeUnreachable; + } +#endif + + mcg_c4 = MCG->C4; + + MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ + + /* + Errata: ERR007993 + Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before + reference clock source changes, then reset to previous value after + reference clock changes. + */ + if (kMCG_FllSrcExternal == MCG_S_IREFST_VAL) + { + change_drs = true; + /* Change the LSB of DRST_DRS. */ + MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); + } + + /* Set CLKS and IREFS. */ + MCG->C1 = + ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */ + | MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */ + + /* Wait and check status. */ + while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL) + { + } + + /* Errata: ERR007993 */ + if (change_drs) + { + MCG->C4 = mcg_c4; + } + + while (kMCG_ClkOutStatInt != MCG_S_CLKST_VAL) + { + } + + MCG->C4 = (mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs)); + + /* Wait for FLL stable time. */ + if (fllStableDelay) + { + fllStableDelay(); + } + + return kStatus_Success; +} + +status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + uint8_t mcg_c4; + bool change_drs = false; + +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + if (!((kMCG_ModeFEE == mode) || (kMCG_ModeFBI == mode) || (kMCG_ModeFBE == mode) || (kMCG_ModeFEI == mode) || + (kMCG_ModePBE == mode) || (kMCG_ModeBLPE == mode))) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + + /* Change to FLL mode. */ + MCG->C6 &= ~MCG_C6_PLLS_MASK; + while (MCG->S & MCG_S_PLLST_MASK) + { + } + + /* Set LP bit to enable the FLL */ + MCG->C2 &= ~MCG_C2_LP_MASK; + + mcg_c4 = MCG->C4; + + /* + Errata: ERR007993 + Workaround: Invert MCG_C4[DMX32] or change MCG_C4[DRST_DRS] before + reference clock source changes, then reset to previous value after + reference clock changes. + */ + if (kMCG_FllSrcInternal == MCG_S_IREFST_VAL) + { + change_drs = true; + /* Change the LSB of DRST_DRS. */ + MCG->C4 ^= (1U << MCG_C4_DRST_DRS_SHIFT); + } + + /* Set CLKS and IREFS. */ + MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) | + (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ + | MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + + /* If use external crystal as clock source, wait for it stable. */ + if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) + { + if (MCG->C2 & MCG_C2_EREFS_MASK) + { + while (!(MCG->S & MCG_S_OSCINIT0_MASK)) + { + } + } + } + + /* Wait for Reference clock Status bit to clear */ + while (kMCG_FllSrcExternal != MCG_S_IREFST_VAL) + { + } + + /* Errata: ERR007993 */ + if (change_drs) + { + MCG->C4 = mcg_c4; + } + + /* Set DRST_DRS and DMX32. */ + mcg_c4 = ((mcg_c4 & ~(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) | (MCG_C4_DMX32(dmx32) | MCG_C4_DRST_DRS(drs))); + + /* Wait for clock status bits to show clock source is ext ref clk */ + while (kMCG_ClkOutStatExt != MCG_S_CLKST_VAL) + { + } + + /* Wait for fll stable time. */ + if (fllStableDelay) + { + fllStableDelay(); + } + + return kStatus_Success; +} + +status_t CLOCK_SetBlpiMode(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + if (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) + { + return kStatus_MCG_ModeUnreachable; + } +#endif /* MCG_CONFIG_CHECK_PARAM */ + + /* Set LP. */ + MCG->C2 |= MCG_C2_LP_MASK; + + return kStatus_Success; +} + +status_t CLOCK_SetBlpeMode(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + if (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + + /* Set LP bit to enter BLPE mode. */ + MCG->C2 |= MCG_C2_LP_MASK; + + return kStatus_Success; +} + +status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) +{ + assert(config); + + /* + This function is designed to change MCG to PBE mode from PEE/BLPE/FBE, + but with this workflow, the source mode could be all modes except PEI/PBI. + */ + MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ + + /* Change to use external clock first. */ + MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + + /* Wait for CLKST clock status bits to show clock source is ext ref clk */ + while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != + (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) + { + } + + /* Disable PLL first, then configure PLL. */ + MCG->C6 &= ~MCG_C6_PLLS_MASK; + while (MCG->S & MCG_S_PLLST_MASK) + { + } + + /* Configure the PLL. */ + { + CLOCK_EnablePll0(config); + } + + /* Change to PLL mode. */ + MCG->C6 |= MCG_C6_PLLS_MASK; + + /* Wait for PLL mode changed. */ + while (!(MCG->S & MCG_S_PLLST_MASK)) + { + } + + return kStatus_Success; +} + +status_t CLOCK_SetPeeMode(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + mcg_mode_t mode = CLOCK_GetMode(); + if (kMCG_ModePBE != mode) + { + return kStatus_MCG_ModeUnreachable; + } +#endif + + /* Change to use PLL/FLL output clock first. */ + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); + + /* Wait for clock status bits to update */ + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll) + { + } + + return kStatus_Success; +} + +status_t CLOCK_ExternalModeToFbeModeQuick(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + if (MCG->S & MCG_S_IREFST_MASK) + { + return kStatus_MCG_ModeInvalid; + } +#endif /* MCG_CONFIG_CHECK_PARAM */ + + /* Disable low power */ + MCG->C2 &= ~MCG_C2_LP_MASK; + + MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) + { + } + + /* Disable PLL. */ + MCG->C6 &= ~MCG_C6_PLLS_MASK; + while (MCG->S & MCG_S_PLLST_MASK) + { + } + + return kStatus_Success; +} + +status_t CLOCK_InternalModeToFbiModeQuick(void) +{ +#if (defined(MCG_CONFIG_CHECK_PARAM) && MCG_CONFIG_CHECK_PARAM) + if (!(MCG->S & MCG_S_IREFST_MASK)) + { + return kStatus_MCG_ModeInvalid; + } +#endif + + /* Disable low power */ + MCG->C2 &= ~MCG_C2_LP_MASK; + + MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal)); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) + { + } + + return kStatus_Success; +} + +status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + return CLOCK_SetFeiMode(dmx32, drs, fllStableDelay); +} + +status_t CLOCK_BootToFeeMode( + mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)) +{ + CLOCK_SetExternalRefClkConfig(oscsel); + + return CLOCK_SetFeeMode(frdiv, dmx32, drs, fllStableDelay); +} + +status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode) +{ + /* If reset mode is FEI mode, set MCGIRCLK and always success. */ + CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv); + + /* If reset mode is not BLPI, first enter FBI mode. */ + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt) + { + } + + /* Enter BLPI mode. */ + MCG->C2 |= MCG_C2_LP_MASK; + + return kStatus_Success; +} + +status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel) +{ + CLOCK_SetExternalRefClkConfig(oscsel); + + /* Set to FBE mode. */ + MCG->C1 = + ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */ + | MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */ + + /* If use external crystal as clock source, wait for it stable. */ + if (MCG_C7_OSCSEL(kMCG_OscselOsc) == (MCG->C7 & MCG_C7_OSCSEL_MASK)) + { + if (MCG->C2 & MCG_C2_EREFS_MASK) + { + while (!(MCG->S & MCG_S_OSCINIT0_MASK)) + { + } + } + } + + /* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */ + while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) != + (MCG_S_IREFST(kMCG_FllSrcExternal) | MCG_S_CLKST(kMCG_ClkOutStatExt))) + { + } + + /* In FBE now, start to enter BLPE. */ + MCG->C2 |= MCG_C2_LP_MASK; + + return kStatus_Success; +} + +status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config) +{ + assert(config); + + CLOCK_SetExternalRefClkConfig(oscsel); + + CLOCK_SetPbeMode(pllcs, config); + + /* Change to use PLL output clock. */ + MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll) + { + } + + return kStatus_Success; +} + +/* + The transaction matrix. It defines the path for mode switch, the row is for + current mode and the column is target mode. + For example, switch from FEI to PEE: + 1. Current mode FEI, next mode is mcgModeMatrix[FEI][PEE] = FBE, so swith to FBE. + 2. Current mode FBE, next mode is mcgModeMatrix[FBE][PEE] = PBE, so swith to PBE. + 3. Current mode PBE, next mode is mcgModeMatrix[PBE][PEE] = PEE, so swith to PEE. + Thus the MCG mode has changed from FEI to PEE. + */ +static const mcg_mode_t mcgModeMatrix[8][8] = { + {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, + kMCG_ModeFBE}, /* FEI */ + {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, + kMCG_ModeFBE}, /* FBI */ + {kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeBLPI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFBI, + kMCG_ModeFBI}, /* BLPI */ + {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, + kMCG_ModeFBE}, /* FEE */ + {kMCG_ModeFEI, kMCG_ModeFBI, kMCG_ModeFBI, kMCG_ModeFEE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, + kMCG_ModePBE}, /* FBE */ + {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, + kMCG_ModePBE}, /* BLPE */ + {kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeFBE, kMCG_ModeBLPE, kMCG_ModePBE, + kMCG_ModePEE}, /* PBE */ + {kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, kMCG_ModePBE, + kMCG_ModePBE} /* PEE */ + /* FEI FBI BLPI FEE FBE BLPE PBE PEE */ +}; + +status_t CLOCK_SetMcgConfig(const mcg_config_t *config) +{ + mcg_mode_t next_mode; + status_t status = kStatus_Success; + + mcg_pll_clk_select_t pllcs = kMCG_PllClkSelPll0; + + /* If need to change external clock, MCG_C7[OSCSEL]. */ + if (MCG_C7_OSCSEL_VAL != config->oscsel) + { + /* If external clock is in use, change to FEI first. */ + if (!(MCG->S & MCG_S_IRCST_MASK)) + { + CLOCK_ExternalModeToFbeModeQuick(); + CLOCK_SetFeiMode(config->dmx32, config->drs, (void (*)(void))0); + } + + CLOCK_SetExternalRefClkConfig(config->oscsel); + } + + /* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */ + if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt) + { + MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */ + + { + CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay); + } + } + + /* Configure MCGIRCLK. */ + CLOCK_SetInternalRefClkConfig(config->irclkEnableMode, config->ircs, config->fcrdiv); + + next_mode = CLOCK_GetMode(); + + do + { + next_mode = mcgModeMatrix[next_mode][config->mcgMode]; + + switch (next_mode) + { + case kMCG_ModeFEI: + status = CLOCK_SetFeiMode(config->dmx32, config->drs, CLOCK_FllStableDelay); + break; + case kMCG_ModeFEE: + status = CLOCK_SetFeeMode(config->frdiv, config->dmx32, config->drs, CLOCK_FllStableDelay); + break; + case kMCG_ModeFBI: + status = CLOCK_SetFbiMode(config->dmx32, config->drs, (void (*)(void))0); + break; + case kMCG_ModeFBE: + status = CLOCK_SetFbeMode(config->frdiv, config->dmx32, config->drs, (void (*)(void))0); + break; + case kMCG_ModeBLPI: + status = CLOCK_SetBlpiMode(); + break; + case kMCG_ModeBLPE: + status = CLOCK_SetBlpeMode(); + break; + case kMCG_ModePBE: + /* If target mode is not PBE or PEE, then only need to set CLKS = EXT here. */ + if ((kMCG_ModePEE == config->mcgMode) || (kMCG_ModePBE == config->mcgMode)) + { + { + status = CLOCK_SetPbeMode(pllcs, &config->pll0Config); + } + } + else + { + MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal)); + while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt) + { + } + } + break; + case kMCG_ModePEE: + status = CLOCK_SetPeeMode(); + break; + default: + break; + } + if (kStatus_Success != status) + { + return status; + } + } while (next_mode != config->mcgMode); + + if (config->pll0Config.enableMode & kMCG_PllEnableIndependent) + { + CLOCK_EnablePll0(&config->pll0Config); + } + else + { + MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent; + } + return kStatus_Success; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_clock.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_clock.h new file mode 100644 index 00000000000..f08000c33f5 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_clock.h @@ -0,0 +1,1533 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright (c) 2016 - 2017 , NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Configures whether to check a parameter in a function. + * + * Some MCG settings must be changed with conditions, for example: + * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when + * MCGIRCLK is used as a system clock source. + * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used + * as a system clock source. For example, in FBE/BLPE/PBE modes. + * 3. The users should only switch between the supported clock modes. + * + * MCG functions check the parameter and MCG status before setting, if not allowed + * to change, the functions return error. The parameter checking increases code size, + * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to + * disable parameter checking. + */ +#ifndef MCG_CONFIG_CHECK_PARAM +#define MCG_CONFIG_CHECK_PARAM 0U +#endif + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could contol the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.2.1. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +/*@}*/ + +/*! @brief External XTAL0 (OSC0) clock frequency. + * + * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the + * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example, + * if XTAL0 is 8 MHz: + * @code + * CLOCK_InitOsc0(...); // Set up the OSC0 + * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to the clock driver. + * @endcode + * + * This is important for the multicore platforms where only one core needs to set up the + * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq + * to get a valid clock frequency. + */ +extern uint32_t g_xtal0Freq; + +/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency. + * + * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the + * function CLOCK_SetXtal32Freq to set the value in the clock driver. + * + * This is important for the multicore platforms where only one core needs to set up + * the clock. All other cores need to call the CLOCK_SetXtal32Freq + * to get a valid clock frequency. + */ +extern uint32_t g_xtal32Freq; + +/*! @brief IRC48M clock frequency in Hz. */ +#define MCG_INTERNAL_IRC_48M 48000000U + +#if (defined(OSC) && !(defined(OSC0))) +#define OSC0 OSC +#endif + +/*! @brief Clock ip name array for DMAMUX. */ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dmamux0 \ + } + +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc0 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_Sai0 \ + } + +/*! @brief Clock ip name array for FLEXBUS. */ +#define FLEXBUS_CLOCKS \ + { \ + kCLOCK_Flexbus0 \ + } + +/*! @brief Clock ip name array for PORT. */ +#define PORT_CLOCKS \ + { \ + kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \ + } + +/*! @brief Clock ip name array for EWM. */ +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } + +/*! @brief Clock ip name array for PIT. */ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit0 \ + } + +/*! @brief Clock ip name array for SDHC. */ +#define SDHC_CLOCKS \ + { \ + kCLOCK_Sdhc0 \ + } + +/*! @brief Clock ip name array for DSPI. */ +#define DSPI_CLOCKS \ + { \ + kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \ + } + +/*! @brief Clock ip name array for LPTMR. */ +#define LPTMR_CLOCKS \ + { \ + kCLOCK_Lptmr0 \ + } + +/*! @brief Clock ip name array for FTM. */ +#define FTM_CLOCKS \ + { \ + kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \ + } + +/*! @brief Clock ip name array for EDMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma0 \ + } + +/*! @brief Clock ip name array for MPU. */ +#define SYSMPU_CLOCKS \ + { \ + kCLOCK_Sysmpu0 \ + } + +/*! @brief Clock ip name array for DAC. */ +#define DAC_CLOCKS \ + { \ + kCLOCK_Dac0, kCLOCK_Dac1 \ + } + +/*! @brief Clock ip name array for ADC16. */ +#define ADC16_CLOCKS \ + { \ + kCLOCK_Adc0, kCLOCK_Adc1 \ + } + +/*! @brief Clock ip name array for VREF. */ +#define VREF_CLOCKS \ + { \ + kCLOCK_Vref0 \ + } + +/*! @brief Clock ip name array for CMT. */ +#define CMT_CLOCKS \ + { \ + kCLOCK_Cmt0 \ + } + +/*! @brief Clock ip name array for UART. */ +#define UART_CLOCKS \ + { \ + kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, kCLOCK_Uart5 \ + } + +/*! @brief Clock ip name array for RNGA. */ +#define RNGA_CLOCKS \ + { \ + kCLOCK_Rnga0 \ + } + +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc0 \ + } + +/*! @brief Clock ip name array for I2C. */ +#define I2C_CLOCKS \ + { \ + kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2 \ + } + +/*! @brief Clock ip name array for PDB. */ +#define PDB_CLOCKS \ + { \ + kCLOCK_Pdb0 \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_Flexcan0 \ + } + +/*! @brief Clock ip name array for FTF. */ +#define FTF_CLOCKS \ + { \ + kCLOCK_Ftf0 \ + } + +/*! @brief Clock ip name array for CMP. */ +#define CMP_CLOCKS \ + { \ + kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \ + } + +/*! + * @brief LPO clock frequency. + */ +#define LPO_CLK_FREQ 1000U + +/*! @brief Peripherals clock source definition. */ +#define SYS_CLK kCLOCK_CoreSysClk +#define BUS_CLK kCLOCK_BusClk + +#define I2C0_CLK_SRC BUS_CLK +#define I2C1_CLK_SRC BUS_CLK +#define I2C2_CLK_SRC BUS_CLK +#define DSPI0_CLK_SRC BUS_CLK +#define DSPI1_CLK_SRC BUS_CLK +#define DSPI2_CLK_SRC BUS_CLK +#define UART0_CLK_SRC SYS_CLK +#define UART1_CLK_SRC SYS_CLK +#define UART2_CLK_SRC BUS_CLK +#define UART3_CLK_SRC BUS_CLK +#define UART4_CLK_SRC BUS_CLK +#define UART5_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + + /* ----------------------------- System layer clock -------------------------------*/ + kCLOCK_CoreSysClk, /*!< Core/system clock */ + kCLOCK_PlatClk, /*!< Platform clock */ + kCLOCK_BusClk, /*!< Bus clock */ + kCLOCK_FlexBusClk, /*!< FlexBus clock */ + kCLOCK_FlashClk, /*!< Flash clock */ + kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */ + kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */ + + /* ---------------------------------- OSC clock -----------------------------------*/ + kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */ + kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */ + kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */ + kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */ + + /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/ + kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */ + kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */ + kCLOCK_McgFllClk, /*!< MCGFLLCLK */ + kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */ + kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */ + kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */ + kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */ + kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */ + + /* --------------------------------- Other clock ----------------------------------*/ + kCLOCK_LpoClk, /*!< LPO clock */ + +} clock_name_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */ + kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */ + kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */ +} clock_usb_src_t; +/*------------------------------------------------------------------------------ + + clock_gate_t definition: + + 31 16 0 + ----------------------------------------------------------------- + | SIM_SCGC register offset | control bit offset in SCGC | + ----------------------------------------------------------------- + + For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the + SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as + + kCLOCK_GateSdhc0 = (0x1030 << 16) | 17; + +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 16U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, + kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U), + kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U), + kCLOCK_Uart5 = CLK_GATE_DEFINE(0x1028U, 11U), + + kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U), + kCLOCK_Dac1 = CLK_GATE_DEFINE(0x102CU, 13U), + + kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U), + kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U), + kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U), + kCLOCK_Adc1 = CLK_GATE_DEFINE(0x1030U, 27U), + + kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U), + kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U), + kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U), + kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U), + kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U), + kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U), + kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U), + kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U), + kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U), + kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U), + kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U), + kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U), + kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U), + + kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U), + kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U), + kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U), + kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U), + kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U), + kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U), + + kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U), + kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U), + kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U), + kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x103CU, 9U), + kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U), + kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U), + kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U), + kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U), + kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U), + kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U), + kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U), + kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U), + kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U), + kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U), + kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U), + kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U), + + kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U), + kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U), + kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U), +} clock_ip_name_t; + +/*!@brief SIM configuration structure for clock setting. */ +typedef struct _sim_clock_config +{ + uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */ + uint8_t er32kSrc; /*!< ERCLK32K source selection. */ + uint32_t clkdiv1; /*!< SIM_CLKDIV1. */ +} sim_clock_config_t; + +/*! @brief OSC work mode. */ +typedef enum _osc_mode +{ + kOSC_ModeExt = 0U, /*!< Use an external clock. */ +#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) + kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */ +#else + kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */ +#endif + kOSC_ModeOscHighGain = 0U +#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK))) + | + MCG_C2_EREFS_MASK +#else + | + MCG_C2_EREFS0_MASK +#endif +#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK))) + | + MCG_C2_HGO_MASK, /*!< Oscillator high gain. */ +#else + | + MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */ +#endif +} osc_mode_t; + +/*! @brief Oscillator capacitor load setting.*/ +enum _osc_cap_load +{ + kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ + kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ + kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ + kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */ +}; + +/*! @brief OSCERCLK enable mode. */ +enum _oscer_enable_mode +{ + kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */ + kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */ +}; + +/*! @brief OSC configuration for OSCERCLK. */ +typedef struct _oscer_config +{ + uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */ + +} oscer_config_t; + +/*! + * @brief OSC Initialization Configuration Structure + * + * Defines the configuration data structure to initialize the OSC. + * When porting to a new board, set the following members + * according to the board setting: + * 1. freq: The external frequency. + * 2. workMode: The OSC module mode. + */ +typedef struct _osc_config +{ + uint32_t freq; /*!< External clock frequency. */ + uint8_t capLoad; /*!< Capacitor load setting. */ + osc_mode_t workMode; /*!< OSC work mode setting. */ + oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */ +} osc_config_t; + +/*! @brief MCG FLL reference clock source select. */ +typedef enum _mcg_fll_src +{ + kMCG_FllSrcExternal, /*!< External reference clock is selected */ + kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */ +} mcg_fll_src_t; + +/*! @brief MCG internal reference clock select */ +typedef enum _mcg_irc_mode +{ + kMCG_IrcSlow, /*!< Slow internal reference clock selected */ + kMCG_IrcFast /*!< Fast internal reference clock selected */ +} mcg_irc_mode_t; + +/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */ +typedef enum _mcg_dmx32 +{ + kMCG_Dmx32Default, /*!< DCO has a default range of 25% */ + kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ +} mcg_dmx32_t; + +/*! @brief MCG DCO range select */ +typedef enum _mcg_drs +{ + kMCG_DrsLow, /*!< Low frequency range */ + kMCG_DrsMid, /*!< Mid frequency range */ + kMCG_DrsMidHigh, /*!< Mid-High frequency range */ + kMCG_DrsHigh /*!< High frequency range */ +} mcg_drs_t; + +/*! @brief MCG PLL reference clock select */ +typedef enum _mcg_pll_ref_src +{ + kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */ + kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */ +} mcg_pll_ref_src_t; + +/*! @brief MCGOUT clock source. */ +typedef enum _mcg_clkout_src +{ + kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */ + kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */ + kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */ +} mcg_clkout_src_t; + +/*! @brief MCG Automatic Trim Machine Select */ +typedef enum _mcg_atm_select +{ + kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */ + kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */ +} mcg_atm_select_t; + +/*! @brief MCG OSC Clock Select */ +typedef enum _mcg_oscsel +{ + kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */ + kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */ + kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */ +} mcg_oscsel_t; + +/*! @brief MCG PLLCS select */ +typedef enum _mcg_pll_clk_select +{ + kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */ + kMCG_PllClkSelPll1 /* PLL1 output clock is selected */ +} mcg_pll_clk_select_t; + +/*! @brief MCG clock monitor mode. */ +typedef enum _mcg_monitor_mode +{ + kMCG_MonitorNone, /*!< Clock monitor is disabled. */ + kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */ + kMCG_MonitorReset /*!< System reset when clock lost. */ +} mcg_monitor_mode_t; + +/*! @brief MCG status. */ +enum _mcg_status +{ + kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */ + kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific + function. */ + kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */ + kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */ + kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */ + kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */ + kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because + it is in use. */ +}; + +/*! @brief MCG status flags. */ +enum _mcg_status_flags_t +{ + kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */ + kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */ + kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */ + kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */ + kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */ +}; + +/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */ +enum _mcg_irclk_enable_mode +{ + kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */ + kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */ +}; + +/*! @brief MCG PLL clock enable mode definition. */ +enum _mcg_pll_enable_mode +{ + kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the + MCG clock mode. Generally, the PLL + is disabled in FLL modes + (FEI/FBI/FEE/FBE). Setting the PLL clock + enable independent, enables the + PLL in the FLL modes. */ + kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */ +}; + +/*! @brief MCG mode definitions */ +typedef enum _mcg_mode +{ + kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */ + kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */ + kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */ + kMCG_ModeFEE, /*!< FEE - FLL Engaged External */ + kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */ + kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */ + kMCG_ModePBE, /*!< PBE - PLL Bypassed External */ + kMCG_ModePEE, /*!< PEE - PLL Engaged External */ + kMCG_ModeError /*!< Unknown mode */ +} mcg_mode_t; + +/*! @brief MCG PLL configuration. */ +typedef struct _mcg_pll_config +{ + uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */ + uint8_t prdiv; /*!< Reference divider PRDIV. */ + uint8_t vdiv; /*!< VCO divider VDIV. */ +} mcg_pll_config_t; + +/*! @brief MCG mode change configuration structure + * + * When porting to a new board, set the following members + * according to the board setting: + * 1. frdiv: If the FLL uses the external reference clock, set this + * value to ensure that the external reference clock divided by frdiv is + * in the 31.25 kHz to 39.0625 kHz range. + * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after + * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to + * FSL_FEATURE_MCG_PLL_REF_MAX range. + */ +typedef struct _mcg_config +{ + mcg_mode_t mcgMode; /*!< MCG mode. */ + + /* ----------------------- MCGIRCCLK settings ------------------------ */ + uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */ + mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */ + uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */ + + /* ------------------------ MCG FLL settings ------------------------- */ + uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */ + mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */ + mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */ + mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */ + + /* ------------------------ MCG PLL settings ------------------------- */ + mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */ + +} mcg_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); + (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); + (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)); +} + +/*! + * @brief Set ERCLK32K source. + * + * @param src The value to set ERCLK32K clock source. + */ +static inline void CLOCK_SetEr32kClock(uint32_t src) +{ + SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src)); +} + +/*! + * @brief Set debug trace clock source. + * + * @param src The value to set debug trace clock source. + */ +static inline void CLOCK_SetTraceClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src)); +} + +/*! + * @brief Set SDHC0 clock source. + * + * @param src The value to set SDHC0 clock source. + */ +static inline void CLOCK_SetSdhc0Clock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src)); +} + +/*! + * @brief Set PLLFLLSEL clock source. + * + * @param src The value to set PLLFLLSEL clock source. + */ +static inline void CLOCK_SetPllFllSelClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src)); +} + +/*! + * @brief Set CLKOUT source. + * + * @param src The value to set CLKOUT source. + */ +static inline void CLOCK_SetClkOutClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src)); +} + +/*! + * @brief Set RTC_CLKOUT source. + * + * @param src The value to set RTC_CLKOUT source. + */ +static inline void CLOCK_SetRtcClkOutClock(uint32_t src) +{ + SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src)); +} + +/*! @brief Enable USB FS clock. + * + * @param src USB FS clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB FS clock. + */ +bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Disable USB FS clock. + * + * Disable USB FS clock. + */ +static inline void CLOCK_DisableUsbfs0Clock(void) +{ + CLOCK_DisableClock(kCLOCK_Usbfs0); +} + +/*! + * @brief System clock divider + * + * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4]. + * + * @param outdiv1 Clock 1 output divider value. + * + * @param outdiv2 Clock 2 output divider value. + * + * @param outdiv3 Clock 3 output divider value. + * + * @param outdiv4 Clock 4 output divider value. + */ +static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4) +{ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) | + SIM_CLKDIV1_OUTDIV4(outdiv4); +} + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * The MCG must be properly configured before using this function. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in Hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! + * @brief Get the core clock or system clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); + +/*! + * @brief Get the bus clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetBusClkFreq(void); + +/*! + * @brief Get the flexbus clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetFlexBusClkFreq(void); + +/*! + * @brief Get the flash clock frequency. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetFlashClkFreq(void); + +/*! + * @brief Get the output clock frequency selected by SIM[PLLFLLSEL]. + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetPllFllSelClkFreq(void); + +/*! + * @brief Get the external reference 32K clock frequency (ERCLK32K). + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetEr32kClkFreq(void); + +/*! + * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK). + * + * @return Clock frequency in Hz. + */ +uint32_t CLOCK_GetOsc0ErClkFreq(void); + +/*! + * @brief Set the clock configure in SIM module. + * + * This function sets system layer clock settings in SIM module. + * + * @param config Pointer to the configure structure. + */ +void CLOCK_SetSimConfig(sim_clock_config_t const *config); + +/*! + * @brief Set the system clock dividers in SIM to safe value. + * + * The system level clocks (core clock, bus clock, flexbus clock and flash clock) + * must be in allowed ranges. During MCG clock mode switch, the MCG output clock + * changes then the system level clocks may be out of range. This function could + * be used before MCG mode change, to make sure system level clocks are in allowed + * range. + * + * @param config Pointer to the configure structure. + */ +static inline void CLOCK_SetSimSafeDivs(void) +{ + SIM->CLKDIV1 = 0x01040000U; +} + +/*! @name MCG frequency functions. */ +/*@{*/ + +/*! + * @brief Gets the MCG output clock (MCGOUTCLK) frequency. + * + * This function gets the MCG output clock frequency in Hz based on the current MCG + * register value. + * + * @return The frequency of MCGOUTCLK. + */ +uint32_t CLOCK_GetOutClkFreq(void); + +/*! + * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency. + * + * This function gets the MCG FLL clock frequency in Hz based on the current MCG + * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and + * disabled in low power state in other modes. + * + * @return The frequency of MCGFLLCLK. + */ +uint32_t CLOCK_GetFllFreq(void); + +/*! + * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency. + * + * This function gets the MCG internal reference clock frequency in Hz based + * on the current MCG register value. + * + * @return The frequency of MCGIRCLK. + */ +uint32_t CLOCK_GetInternalRefClkFreq(void); + +/*! + * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency. + * + * This function gets the MCG fixed frequency clock frequency in Hz based + * on the current MCG register value. + * + * @return The frequency of MCGFFCLK. + */ +uint32_t CLOCK_GetFixedFreqClkFreq(void); + +/*! + * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency. + * + * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG + * register value. + * + * @return The frequency of MCGPLL0CLK. + */ +uint32_t CLOCK_GetPll0Freq(void); + +/*@}*/ + +/*! @name MCG clock configuration. */ +/*@{*/ + +/*! + * @brief Enables or disables the MCG low power. + * + * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words, + * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and + * PBI modes, enabling low power sets the MCG to BLPI mode. + * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings. + * + * @param enable True to enable MCG low power, false to disable MCG low power. + */ +static inline void CLOCK_SetLowPowerEnable(bool enable) +{ + if (enable) + { + MCG->C2 |= MCG_C2_LP_MASK; + } + else + { + MCG->C2 &= ~MCG_C2_LP_MASK; + } +} + +/*! + * @brief Configures the Internal Reference clock (MCGIRCLK). + * + * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC + * source. If the fast IRC is used, this function sets the fast IRC divider. + * This function also sets whether the \c MCGIRCLK is enabled in stop mode. + * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result, + * using the function in these modes it is not allowed. + * + * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. + * @param ircs MCGIRCLK clock source, choose fast or slow. + * @param fcrdiv Fast IRC divider setting (\c FCRDIV). + * @retval kStatus_MCG_SourceUsed Because the internall reference clock is used as a clock source, + * the confuration should not be changed. Otherwise, a glitch occurs. + * @retval kStatus_Success MCGIRCLK configuration finished successfully. + */ +status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv); + +/*! + * @brief Selects the MCG external reference clock. + * + * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL], + * and waits for the clock source to be stable. Because the external reference + * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes. + * + * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL]. + * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source, + * the confuration should not be changed. Otherwise, a glitch occurs. + * @retval kStatus_Success External reference clock set successfully. + */ +status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel); + +/*! + * @brief Set the FLL external reference clock divider value. + * + * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV]. + * + * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV]. + */ +static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv) +{ + MCG->C1 = (MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv); +} + +/*! + * @brief Enables the PLL0 in FLL mode. + * + * This function sets us the PLL0 in FLL mode and reconfigures + * the PLL0. Ensure that the PLL reference + * clock is enabled before calling this function and that the PLL0 is not used as a clock source. + * The function CLOCK_CalcPllDiv gets the correct PLL + * divider values. + * + * @param config Pointer to the configuration structure. + */ +void CLOCK_EnablePll0(mcg_pll_config_t const *config); + +/*! + * @brief Disables the PLL0 in FLL mode. + * + * This function disables the PLL0 in FLL mode. It should be used together with the + * @ref CLOCK_EnablePll0. + */ +static inline void CLOCK_DisablePll0(void) +{ + MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK); +} + +/*! + * @brief Calculates the PLL divider setting for a desired output frequency. + * + * This function calculates the correct reference clock divider (\c PRDIV) and + * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the + * closest frequency match with the corresponding \c PRDIV/VDIV + * returned from parameters. If a desired frequency is not valid, this function + * returns 0. + * + * @param refFreq PLL reference clock frequency. + * @param desireFreq Desired PLL output frequency. + * @param prdiv PRDIV value to generate desired PLL frequency. + * @param vdiv VDIV value to generate desired PLL frequency. + * @return Closest frequency match that the PLL was able generate. + */ +uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv); + +/*@}*/ + +/*! @name MCG clock lock monitor functions. */ +/*@{*/ + +/*! + * @brief Sets the OSC0 clock monitor mode. + * + * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode); + +/*! + * @brief Sets the RTC OSC clock monitor mode. + * + * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode); + +/*! + * @brief Sets the PLL0 clock monitor mode. + * + * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode); + +/*! + * @brief Gets the MCG status flags. + * + * This function gets the MCG clock status flags. All status flags are + * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To + * check a specific flag, compare the return value with the flag. + * + * Example: + * @code + // To check the clock lost lock status of OSC0 and PLL0. + uint32_t mcgFlags; + + mcgFlags = CLOCK_GetStatusFlags(); + + if (mcgFlags & kMCG_Osc0LostFlag) + { + // OSC0 clock lock lost. Do something. + } + if (mcgFlags & kMCG_Pll0LostFlag) + { + // PLL0 clock lock lost. Do something. + } + @endcode + * + * @return Logical OR value of the @ref _mcg_status_flags_t. + */ +uint32_t CLOCK_GetStatusFlags(void); + +/*! + * @brief Clears the MCG status flags. + * + * This function clears the MCG clock lock lost status. The parameter is a logical + * OR value of the flags to clear. See @ref _mcg_status_flags_t. + * + * Example: + * @code + // To clear the clock lost lock status flags of OSC0 and PLL0. + + CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag); + @endcode + * + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration @ref _mcg_status_flags_t. + */ +void CLOCK_ClearStatusFlags(uint32_t mask); + +/*@}*/ + +/*! + * @name OSC configuration + * @{ + */ + +/*! + * @brief Configures the OSC external reference clock (OSCERCLK). + * + * This function configures the OSC external reference clock (OSCERCLK). + * This is an example to enable the OSCERCLK in normal and stop modes and also set + * the output divider to 1: + * + @code + oscer_config_t config = + { + .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop, + .erclkDiv = 1U, + }; + + OSC_SetExtRefClkConfig(OSC, &config); + @endcode + * + * @param base OSC peripheral address. + * @param config Pointer to the configuration structure. + */ +static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config) +{ + uint8_t reg = base->CR; + + reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK); + reg |= config->enableMode; + + base->CR = reg; +} + +/*! + * @brief Sets the capacitor load configuration for the oscillator. + * + * This function sets the specified capacitors configuration for the oscillator. + * This should be done in the early system level initialization function call + * based on the system configuration. + * + * @param base OSC peripheral address. + * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load. + * + * Example: + @code + // To enable only 2 pF and 8 pF capacitor load, please use like this. + OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P); + @endcode + */ +static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad) +{ + uint8_t reg = base->CR; + + reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK); + reg |= capLoad; + + base->CR = reg; +} + +/*! + * @brief Initializes the OSC0. + * + * This function initializes the OSC0 according to the board configuration. + * + * @param config Pointer to the OSC0 configuration structure. + */ +void CLOCK_InitOsc0(osc_config_t const *config); + +/*! + * @brief Deinitializes the OSC0. + * + * This function deinitializes the OSC0. + */ +void CLOCK_DeinitOsc0(void); + +/* @} */ + +/*! + * @name External clock frequency + * @{ + */ + +/*! + * @brief Sets the XTAL0 frequency based on board settings. + * + * @param freq The XTAL0/EXTAL0 input clock frequency in Hz. + */ +static inline void CLOCK_SetXtal0Freq(uint32_t freq) +{ + g_xtal0Freq = freq; +} + +/*! + * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings. + * + * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz. + */ +static inline void CLOCK_SetXtal32Freq(uint32_t freq) +{ + g_xtal32Freq = freq; +} +/* @} */ + +/*! + * @name MCG auto-trim machine. + * @{ + */ + +/*! + * @brief Auto trims the internal reference clock. + * + * This function trims the internal reference clock by using the external clock. If + * successful, it returns the kStatus_Success and the frequency after + * trimming is received in the parameter @p actualFreq. If an error occurs, + * the error code is returned. + * + * @param extFreq External clock frequency, which should be a bus clock. + * @param desireFreq Frequency to trim to. + * @param actualFreq Actual frequency after trimming. + * @param atms Trim fast or slow internal reference clock. + * @retval kStatus_Success ATM success. + * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM. + * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency. + * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source. + * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming. + */ +status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms); +/* @} */ + +/*! @name MCG mode functions. */ +/*@{*/ + +/*! + * @brief Gets the current MCG mode. + * + * This function checks the MCG registers and determines the current MCG mode. + * + * @return Current MCG mode or error code; See @ref mcg_mode_t. + */ +mcg_mode_t CLOCK_GetMode(void); + +/*! + * @brief Sets the MCG to FEI mode. + * + * This function sets the MCG to FEI mode. If setting to FEI mode fails + * from the current mode, this function returns an error. + * + * @param dmx32 DMX32 in FEI mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing + * NULL does not cause a delay. + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switched to the target mode successfully. + * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed + * to a frequency above 32768 Hz. + */ +status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Sets the MCG to FEE mode. + * + * This function sets the MCG to FEE mode. If setting to FEE mode fails + * from the current mode, this function returns an error. + * + * @param frdiv FLL reference clock divider setting, FRDIV. + * @param dmx32 DMX32 in FEE mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. Passing + * NULL does not cause a delay. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switched to the target mode successfully. + */ +status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Sets the MCG to FBI mode. + * + * This function sets the MCG to FBI mode. If setting to FBI mode fails + * from the current mode, this function returns an error. + * + * @param dmx32 DMX32 in FBI mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL + * is not used in FBI mode, this parameter can be NULL. Passing + * NULL does not cause a delay. + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switched to the target mode successfully. + * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed + * to frequency above 32768 Hz. + */ +status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Sets the MCG to FBE mode. + * + * This function sets the MCG to FBE mode. If setting to FBE mode fails + * from the current mode, this function returns an error. + * + * @param frdiv FLL reference clock divider setting, FRDIV. + * @param dmx32 DMX32 in FBE mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL + * is not used in FBE mode, this parameter can be NULL. Passing NULL + * does not cause a delay. + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switched to the target mode successfully. + */ +status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Sets the MCG to BLPI mode. + * + * This function sets the MCG to BLPI mode. If setting to BLPI mode fails + * from the current mode, this function returns an error. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switched to the target mode successfully. + */ +status_t CLOCK_SetBlpiMode(void); + +/*! + * @brief Sets the MCG to BLPE mode. + * + * This function sets the MCG to BLPE mode. If setting to BLPE mode fails + * from the current mode, this function returns an error. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switched to the target mode successfully. + */ +status_t CLOCK_SetBlpeMode(void); + +/*! + * @brief Sets the MCG to PBE mode. + * + * This function sets the MCG to PBE mode. If setting to PBE mode fails + * from the current mode, this function returns an error. + * + * @param pllcs The PLL selection, PLLCS. + * @param config Pointer to the PLL configuration. + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switched to the target mode successfully. + * + * @note + * 1. The parameter \c pllcs selects the PLL. For platforms with + * only one PLL, the parameter pllcs is kept for interface compatibility. + * 2. The parameter \c config is the PLL configuration structure. On some + * platforms, it is possible to choose the external PLL directly, which renders the + * configuration structure not necessary. In this case, pass in NULL. + * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL); + */ +status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); + +/*! + * @brief Sets the MCG to PEE mode. + * + * This function sets the MCG to PEE mode. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switched to the target mode successfully. + * + * @note This function only changes the CLKS to use the PLL/FLL output. If the + * PRDIV/VDIV are different than in the PBE mode, set them up + * in PBE mode and wait. When the clock is stable, switch to PEE mode. + */ +status_t CLOCK_SetPeeMode(void); + +/*! + * @brief Switches the MCG to FBE mode from the external mode. + * + * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly. + * The external clock is used as the system clock souce and PLL is disabled. However, + * the FLL settings are not configured. This is a lite function with a small code size, which is useful + * during the mode switch. For example, to switch from PEE mode to FEI mode: + * + * @code + * CLOCK_ExternalModeToFbeModeQuick(); + * CLOCK_SetFeiMode(...); + * @endcode + * + * @retval kStatus_Success Switched successfully. + * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function. + */ +status_t CLOCK_ExternalModeToFbeModeQuick(void); + +/*! + * @brief Switches the MCG to FBI mode from internal modes. + * + * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly. + * The MCGIRCLK is used as the system clock souce and PLL is disabled. However, + * FLL settings are not configured. This is a lite function with a small code size, which is useful + * during the mode switch. For example, to switch from PEI mode to FEE mode: + * + * @code + * CLOCK_InternalModeToFbiModeQuick(); + * CLOCK_SetFeeMode(...); + * @endcode + * + * @retval kStatus_Success Switched successfully. + * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function. + */ +status_t CLOCK_InternalModeToFbiModeQuick(void); + +/*! + * @brief Sets the MCG to FEI mode during system boot up. + * + * This function sets the MCG to FEI mode from the reset mode. It can also be used to + * set up MCG during system boot up. + * + * @param dmx32 DMX32 in FEI mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to ensure that the FLL is stable. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switched to the target mode successfully. + * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed + * to frequency above 32768 Hz. + */ +status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Sets the MCG to FEE mode during system bootup. + * + * This function sets MCG to FEE mode from the reset mode. It can also be used to + * set up the MCG during system boot up. + * + * @param oscsel OSC clock select, OSCSEL. + * @param frdiv FLL reference clock divider setting, FRDIV. + * @param dmx32 DMX32 in FEE mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to ensure that the FLL is stable. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switched to the target mode successfully. + */ +status_t CLOCK_BootToFeeMode( + mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void)); + +/*! + * @brief Sets the MCG to BLPI mode during system boot up. + * + * This function sets the MCG to BLPI mode from the reset mode. It can also be used to + * set up the MCG during sytem boot up. + * + * @param fcrdiv Fast IRC divider, FCRDIV. + * @param ircs The internal reference clock to select, IRCS. + * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode. + * + * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting. + * @retval kStatus_Success Switched to the target mode successfully. + */ +status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode); + +/*! + * @brief Sets the MCG to BLPE mode during sytem boot up. + * + * This function sets the MCG to BLPE mode from the reset mode. It can also be used to + * set up the MCG during sytem boot up. + * + * @param oscsel OSC clock select, MCG_C7[OSCSEL]. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switched to the target mode successfully. + */ +status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel); + +/*! + * @brief Sets the MCG to PEE mode during system boot up. + * + * This function sets the MCG to PEE mode from reset mode. It can also be used to + * set up the MCG during system boot up. + * + * @param oscsel OSC clock select, MCG_C7[OSCSEL]. + * @param pllcs The PLL selection, PLLCS. + * @param config Pointer to the PLL configuration. + * + * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode. + * @retval kStatus_Success Switched to the target mode successfully. + */ +status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config); + +/*! + * @brief Sets the MCG to a target mode. + * + * This function sets MCG to a target mode defined by the configuration + * structure. If switching to the target mode fails, this function + * chooses the correct path. + * + * @param config Pointer to the target MCG mode configuration structure. + * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status. + * + * @note If the external clock is used in the target mode, ensure that it is + * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this + * function. + */ +status_t CLOCK_SetMcgConfig(mcg_config_t const *config); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_cmp.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_cmp.c new file mode 100644 index 00000000000..6a5f15a75b1 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_cmp.c @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_cmp.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for CMP module. + * + * @param base CMP peripheral base address + */ +static uint32_t CMP_GetInstance(CMP_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to CMP bases for each instance. */ +static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to CMP clocks for each instance. */ +static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t CMP_GetInstance(CMP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_cmpBases); instance++) + { + if (s_cmpBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_cmpBases)); + + return instance; +} + +void CMP_Init(CMP_Type *base, const cmp_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure. */ + CMP_Enable(base, false); /* Disable the CMP module during configuring. */ + /* CMPx_CR1. */ + tmp8 = base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK); + if (config->enableHighSpeed) + { + tmp8 |= CMP_CR1_PMODE_MASK; + } + if (config->enableInvertOutput) + { + tmp8 |= CMP_CR1_INV_MASK; + } + if (config->useUnfilteredOutput) + { + tmp8 |= CMP_CR1_COS_MASK; + } + if (config->enablePinOut) + { + tmp8 |= CMP_CR1_OPE_MASK; + } +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + if (config->enableTriggerMode) + { + tmp8 |= CMP_CR1_TRIGM_MASK; + } + else + { + tmp8 &= ~CMP_CR1_TRIGM_MASK; + } +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ + base->CR1 = tmp8; + + /* CMPx_CR0. */ + tmp8 = base->CR0 & ~CMP_CR0_HYSTCTR_MASK; + tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode); + base->CR0 = tmp8; + + CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ +} + +void CMP_Deinit(CMP_Type *base) +{ + /* Disable the CMP module. */ + CMP_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void CMP_GetDefaultConfig(cmp_config_t *config) +{ + assert(NULL != config); + + config->enableCmp = true; /* Enable the CMP module after initialization. */ + config->hysteresisMode = kCMP_HysteresisLevel0; + config->enableHighSpeed = false; + config->enableInvertOutput = false; + config->useUnfilteredOutput = false; + config->enablePinOut = false; +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + config->enableTriggerMode = false; +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ +} + +void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) +{ + uint8_t tmp8 = base->MUXCR; + + tmp8 &= ~(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); + tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel); + base->MUXCR = tmp8; +} + +#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +void CMP_EnableDMA(CMP_Type *base, bool enable) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (enable) + { + tmp8 |= CMP_SCR_DMAEN_MASK; + } + else + { + tmp8 &= ~CMP_SCR_DMAEN_MASK; + } + base->SCR = tmp8; +} +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + +void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + +#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT + /* Choose the clock source for sampling. */ + if (config->enableSample) + { + base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ + } + else + { + base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */ + } +#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ + /* Set the filter count. */ + tmp8 = base->CR0 & ~CMP_CR0_FILTER_CNT_MASK; + tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount); + base->CR0 = tmp8; + /* Set the filter period. It is used as the divider to bus clock. */ + base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); +} + +void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) +{ + uint8_t tmp8 = 0U; + + if (NULL == config) + { + /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/ + base->DACCR = 0U; + return; + } + /* CMPx_DACCR. */ + tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ + if (kCMP_VrefSourceVin2 == config->referenceVoltageSource) + { + tmp8 |= CMP_DACCR_VRSEL_MASK; + } + tmp8 |= CMP_DACCR_VOSEL(config->DACValue); + + base->DACCR = tmp8; +} + +void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingInterruptEnable & mask)) + { + tmp8 |= CMP_SCR_IER_MASK; + } + if (0U != (kCMP_OutputFallingInterruptEnable & mask)) + { + tmp8 |= CMP_SCR_IEF_MASK; + } + base->SCR = tmp8; +} + +void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingInterruptEnable & mask)) + { + tmp8 &= ~CMP_SCR_IER_MASK; + } + if (0U != (kCMP_OutputFallingInterruptEnable & mask)) + { + tmp8 &= ~CMP_SCR_IEF_MASK; + } + base->SCR = tmp8; +} + +uint32_t CMP_GetStatusFlags(CMP_Type *base) +{ + uint32_t ret32 = 0U; + + if (0U != (CMP_SCR_CFR_MASK & base->SCR)) + { + ret32 |= kCMP_OutputRisingEventFlag; + } + if (0U != (CMP_SCR_CFF_MASK & base->SCR)) + { + ret32 |= kCMP_OutputFallingEventFlag; + } + if (0U != (CMP_SCR_COUT_MASK & base->SCR)) + { + ret32 |= kCMP_OutputAssertEventFlag; + } + return ret32; +} + +void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK); /* To avoid change the w1c bits. */ + + if (0U != (kCMP_OutputRisingEventFlag & mask)) + { + tmp8 |= CMP_SCR_CFR_MASK; + } + if (0U != (kCMP_OutputFallingEventFlag & mask)) + { + tmp8 |= CMP_SCR_CFF_MASK; + } + base->SCR = tmp8; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_cmp.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_cmp.h new file mode 100644 index 00000000000..5d16bf08de4 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_cmp.h @@ -0,0 +1,343 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CMP_H_ +#define _FSL_CMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cmp + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CMP driver version 2.0.0. */ +#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! +* @brief Interrupt enable/disable mask. +*/ +enum _cmp_interrupt_enable +{ + kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */ + kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */ +}; + +/*! + * @brief Status flags' mask. + */ +enum _cmp_status_flags +{ + kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ + kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ + kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */ +}; + +/*! + * @brief CMP Hysteresis mode. + */ +typedef enum _cmp_hysteresis_mode +{ + kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */ + kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */ + kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */ + kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */ +} cmp_hysteresis_mode_t; + +/*! + * @brief CMP Voltage Reference source. + */ +typedef enum _cmp_reference_voltage_source +{ + kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as a resistor ladder network supply reference Vin. */ + kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as a resistor ladder network supply reference Vin. */ +} cmp_reference_voltage_source_t; + +/*! + * @brief Configures the comparator. + */ +typedef struct _cmp_config +{ + bool enableCmp; /*!< Enable the CMP module. */ + cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */ + bool enableHighSpeed; /*!< Enable High-speed (HS) comparison mode. */ + bool enableInvertOutput; /*!< Enable the inverted comparator output. */ + bool useUnfilteredOutput; /*!< Set the compare output(COUT) to equal COUTA(true) or COUT(false). */ + bool enablePinOut; /*!< The comparator output is available on the associated pin. */ +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + bool enableTriggerMode; /*!< Enable the trigger mode. */ +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ +} cmp_config_t; + +/*! + * @brief Configures the filter. + */ +typedef struct _cmp_filter_config +{ +#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT + bool enableSample; /*!< Using the external SAMPLE as a sampling clock input or using a divided bus clock. */ +#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ + uint8_t filterCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter.*/ + uint8_t filterPeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. */ +} cmp_filter_config_t; + +/*! + * @brief Configures the internal DAC. + */ +typedef struct _cmp_dac_config +{ + cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */ + uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/ +} cmp_dac_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the CMP. + * + * This function initializes the CMP module. The operations included are as follows. + * - Enabling the clock for CMP module. + * - Configuring the comparator. + * - Enabling the CMP module. + * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for + * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP. + * + * @param base CMP peripheral base address. + * @param config Pointer to the configuration structure. + */ +void CMP_Init(CMP_Type *base, const cmp_config_t *config); + +/*! + * @brief De-initializes the CMP module. + * + * This function de-initializes the CMP module. The operations included are as follows. + * - Disabling the CMP module. + * - Disabling the clock for CMP module. + * + * This function disables the clock for the CMP. + * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the + * clock for the CMP, ensure that all the CMP instances are not used. + * + * @param base CMP peripheral base address. + */ +void CMP_Deinit(CMP_Type *base); + +/*! + * @brief Enables/disables the CMP module. + * + * @param base CMP peripheral base address. + * @param enable Enables or disables the module. + */ +static inline void CMP_Enable(CMP_Type *base, bool enable) +{ + if (enable) + { + base->CR1 |= CMP_CR1_EN_MASK; + } + else + { + base->CR1 &= ~CMP_CR1_EN_MASK; + } +} + +/*! +* @brief Initializes the CMP user configuration structure. +* +* This function initializes the user configuration structure to these default values. +* @code +* config->enableCmp = true; +* config->hysteresisMode = kCMP_HysteresisLevel0; +* config->enableHighSpeed = false; +* config->enableInvertOutput = false; +* config->useUnfilteredOutput = false; +* config->enablePinOut = false; +* config->enableTriggerMode = false; +* @endcode +* @param config Pointer to the configuration structure. +*/ +void CMP_GetDefaultConfig(cmp_config_t *config); + +/*! + * @brief Sets the input channels for the comparator. + * + * This function sets the input channels for the comparator. + * Note that two input channels cannot be set the same way in the application. When the user selects the same input + * from the analog mux to the positive and negative port, the comparator is disabled automatically. + * + * @param base CMP peripheral base address. + * @param positiveChannel Positive side input channel number. Available range is 0-7. + * @param negativeChannel Negative side input channel number. Available range is 0-7. + */ +void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel); + +/* @} */ + +/*! + * @name Advanced Features + * @{ + */ + +#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +/*! + * @brief Enables/disables the DMA request for rising/falling events. + * + * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of + * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from the CMP + * if the DMA is disabled. + * + * @param base CMP peripheral base address. + * @param enable Enables or disables the feature. + */ +void CMP_EnableDMA(CMP_Type *base, bool enable); +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + +#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE +/*! + * @brief Enables/disables the window mode. + * + * @param base CMP peripheral base address. + * @param enable Enables or disables the feature. + */ +static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable) +{ + if (enable) + { + base->CR1 |= CMP_CR1_WE_MASK; + } + else + { + base->CR1 &= ~CMP_CR1_WE_MASK; + } +} +#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */ + +#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE +/*! + * @brief Enables/disables the pass through mode. + * + * @param base CMP peripheral base address. + * @param enable Enables or disables the feature. + */ +static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable) +{ + if (enable) + { + base->MUXCR |= CMP_MUXCR_PSTM_MASK; + } + else + { + base->MUXCR &= ~CMP_MUXCR_PSTM_MASK; + } +} +#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */ + +/*! + * @brief Configures the filter. + * + * @param base CMP peripheral base address. + * @param config Pointer to the configuration structure. + */ +void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config); + +/*! + * @brief Configures the internal DAC. + * + * @param base CMP peripheral base address. + * @param config Pointer to the configuration structure. "NULL" disables the feature. + */ +void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config); + +/*! + * @brief Enables the interrupts. + * + * @param base CMP peripheral base address. + * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask); + +/*! + * @brief Disables the interrupts. + * + * @param base CMP peripheral base address. + * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Results + * @{ + */ + +/*! + * @brief Gets the status flags. + * + * @param base CMP peripheral base address. + * + * @return Mask value for the asserted flags. See "_cmp_status_flags". + */ +uint32_t CMP_GetStatusFlags(CMP_Type *base); + +/*! + * @brief Clears the status flags. + * + * @param base CMP peripheral base address. + * @param mask Mask value for the flags. See "_cmp_status_flags". + */ +void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask); + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_CMP_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_cmt.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_cmt.c new file mode 100644 index 00000000000..8cf72bc7e7d --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_cmt.c @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_cmt.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* The standard intermediate frequency (IF). */ +#define CMT_INTERMEDIATEFREQUENCY_8MHZ (8000000U) +/* CMT data modulate mask. */ +#define CMT_MODULATE_COUNT_WIDTH (8U) +/* CMT diver 1. */ +#define CMT_CMTDIV_ONE (1) +/* CMT diver 2. */ +#define CMT_CMTDIV_TWO (2) +/* CMT diver 4. */ +#define CMT_CMTDIV_FOUR (4) +/* CMT diver 8. */ +#define CMT_CMTDIV_EIGHT (8) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for CMT module. + * + * @param base CMT peripheral base address. + */ +static uint32_t CMT_GetInstance(CMT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to cmt clocks for each instance. */ +static const clock_ip_name_t s_cmtClock[FSL_FEATURE_SOC_CMT_COUNT] = CMT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to cmt bases for each instance. */ +static CMT_Type *const s_cmtBases[] = CMT_BASE_PTRS; + +/*! @brief Pointers to cmt IRQ number for each instance. */ +static const IRQn_Type s_cmtIrqs[] = CMT_IRQS; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static uint32_t CMT_GetInstance(CMT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_cmtBases); instance++) + { + if (s_cmtBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_cmtBases)); + + return instance; +} + +void CMT_GetDefaultConfig(cmt_config_t *config) +{ + assert(config); + + /* Default infrared output is enabled and set with high active, the divider is set to 1. */ + config->isInterruptEnabled = false; + config->isIroEnabled = true; + config->iroPolarity = kCMT_IROActiveHigh; + config->divider = kCMT_SecondClkDiv1; +} + +void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz) +{ + assert(config); + assert(busClock_Hz >= CMT_INTERMEDIATEFREQUENCY_8MHZ); + + uint8_t divider; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate clock. */ + CLOCK_EnableClock(s_cmtClock[CMT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Sets clock divider. The divider set in pps should be set + to make sycClock_Hz/divder = 8MHz */ + base->PPS = CMT_PPS_PPSDIV(busClock_Hz / CMT_INTERMEDIATEFREQUENCY_8MHZ - 1); + divider = base->MSC; + divider &= ~CMT_MSC_CMTDIV_MASK; + divider |= CMT_MSC_CMTDIV(config->divider); + base->MSC = divider; + + /* Set the IRO signal. */ + base->OC = CMT_OC_CMTPOL(config->iroPolarity) | CMT_OC_IROPEN(config->isIroEnabled); + + /* Set interrupt. */ + if (config->isInterruptEnabled) + { + CMT_EnableInterrupts(base, kCMT_EndOfCycleInterruptEnable); + EnableIRQ(s_cmtIrqs[CMT_GetInstance(base)]); + } +} + +void CMT_Deinit(CMT_Type *base) +{ + /*Disable the CMT modulator. */ + base->MSC = 0; + + /* Disable the interrupt. */ + CMT_DisableInterrupts(base, kCMT_EndOfCycleInterruptEnable); + DisableIRQ(s_cmtIrqs[CMT_GetInstance(base)]); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the clock. */ + CLOCK_DisableClock(s_cmtClock[CMT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig) +{ + uint8_t mscReg = base->MSC; + + /* Judge the mode. */ + if (mode != kCMT_DirectIROCtl) + { + assert(modulateConfig); + + /* Set carrier generator. */ + CMT_SetCarrirGenerateCountOne(base, modulateConfig->highCount1, modulateConfig->lowCount1); + if (mode == kCMT_FSKMode) + { + CMT_SetCarrirGenerateCountTwo(base, modulateConfig->highCount2, modulateConfig->lowCount2); + } + + /* Set carrier modulator. */ + CMT_SetModulateMarkSpace(base, modulateConfig->markCount, modulateConfig->spaceCount); + mscReg &= ~ (CMT_MSC_FSK_MASK | CMT_MSC_BASE_MASK); + mscReg |= mode; + } + else + { + mscReg &= ~CMT_MSC_MCGEN_MASK; + } + /* Set the CMT mode. */ + base->MSC = mscReg; +} + +cmt_mode_t CMT_GetMode(CMT_Type *base) +{ + uint8_t mode = base->MSC; + + if (!(mode & CMT_MSC_MCGEN_MASK)) + { /* Carrier modulator disabled and the IRO signal is in direct software control. */ + return kCMT_DirectIROCtl; + } + else + { + /* Carrier modulator is enabled. */ + if (mode & CMT_MSC_BASE_MASK) + { + /* Base band mode. */ + return kCMT_BasebandMode; + } + else if (mode & CMT_MSC_FSK_MASK) + { + /* FSK mode. */ + return kCMT_FSKMode; + } + else + { + /* Time mode. */ + return kCMT_TimeMode; + } + } +} + +uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz) +{ + uint32_t frequency; + uint32_t divider; + + /* Get intermediate frequency. */ + frequency = busClock_Hz / ((base->PPS & CMT_PPS_PPSDIV_MASK) + 1); + + /* Get the second divider. */ + divider = ((base->MSC & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT); + /* Get CMT frequency. */ + switch ((cmt_second_clkdiv_t)divider) + { + case kCMT_SecondClkDiv1: + frequency = frequency / CMT_CMTDIV_ONE; + break; + case kCMT_SecondClkDiv2: + frequency = frequency / CMT_CMTDIV_TWO; + break; + case kCMT_SecondClkDiv4: + frequency = frequency / CMT_CMTDIV_FOUR; + break; + case kCMT_SecondClkDiv8: + frequency = frequency / CMT_CMTDIV_EIGHT; + break; + default: + frequency = frequency / CMT_CMTDIV_ONE; + break; + } + + return frequency; +} + +void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount) +{ + /* Set modulate mark. */ + base->CMD1 = (markCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD1_MB_MASK; + base->CMD2 = (markCount & CMT_CMD2_MB_MASK); + /* Set modulate space. */ + base->CMD3 = (spaceCount >> CMT_MODULATE_COUNT_WIDTH) & CMT_CMD3_SB_MASK; + base->CMD4 = spaceCount & CMT_CMD4_SB_MASK; +} + +void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state) +{ + uint8_t ocReg = base->OC; + + ocReg &= ~CMT_OC_IROL_MASK; + ocReg |= CMT_OC_IROL(state); + + /* Set the infrared output signal control. */ + base->OC = ocReg; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_cmt.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_cmt.h new file mode 100644 index 00000000000..3d81f8a9a4a --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_cmt.h @@ -0,0 +1,401 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_CMT_H_ +#define _FSL_CMT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cmt + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CMT driver version 2.0.1. */ +#define FSL_CMT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief The modes of CMT. + */ +typedef enum _cmt_mode +{ + kCMT_DirectIROCtl = 0x00U, /*!< Carrier modulator is disabled and the IRO signal is directly in software control */ + kCMT_TimeMode = 0x01U, /*!< Carrier modulator is enabled in time mode. */ + kCMT_FSKMode = 0x05U, /*!< Carrier modulator is enabled in FSK mode. */ + kCMT_BasebandMode = 0x09U /*!< Carrier modulator is enabled in baseband mode. */ +} cmt_mode_t; + +/*! + * @brief The CMT clock divide primary prescaler. + * The primary clock divider is used to divider the bus clock to + * get the intermediate frequency to approximately equal to 8 MHZ. + * When the bus clock is 8 MHZ, set primary prescaler to "kCMT_PrimaryClkDiv1". + */ +typedef enum _cmt_primary_clkdiv +{ + kCMT_PrimaryClkDiv1 = 0U, /*!< The intermediate frequency is the bus clock divided by 1. */ + kCMT_PrimaryClkDiv2 = 1U, /*!< The intermediate frequency is the bus clock divided by 2. */ + kCMT_PrimaryClkDiv3 = 2U, /*!< The intermediate frequency is the bus clock divided by 3. */ + kCMT_PrimaryClkDiv4 = 3U, /*!< The intermediate frequency is the bus clock divided by 4. */ + kCMT_PrimaryClkDiv5 = 4U, /*!< The intermediate frequency is the bus clock divided by 5. */ + kCMT_PrimaryClkDiv6 = 5U, /*!< The intermediate frequency is the bus clock divided by 6. */ + kCMT_PrimaryClkDiv7 = 6U, /*!< The intermediate frequency is the bus clock divided by 7. */ + kCMT_PrimaryClkDiv8 = 7U, /*!< The intermediate frequency is the bus clock divided by 8. */ + kCMT_PrimaryClkDiv9 = 8U, /*!< The intermediate frequency is the bus clock divided by 9. */ + kCMT_PrimaryClkDiv10 = 9U, /*!< The intermediate frequency is the bus clock divided by 10. */ + kCMT_PrimaryClkDiv11 = 10U, /*!< The intermediate frequency is the bus clock divided by 11. */ + kCMT_PrimaryClkDiv12 = 11U, /*!< The intermediate frequency is the bus clock divided by 12. */ + kCMT_PrimaryClkDiv13 = 12U, /*!< The intermediate frequency is the bus clock divided by 13. */ + kCMT_PrimaryClkDiv14 = 13U, /*!< The intermediate frequency is the bus clock divided by 14. */ + kCMT_PrimaryClkDiv15 = 14U, /*!< The intermediate frequency is the bus clock divided by 15. */ + kCMT_PrimaryClkDiv16 = 15U /*!< The intermediate frequency is the bus clock divided by 16. */ +} cmt_primary_clkdiv_t; + +/*! + * @brief The CMT clock divide secondary prescaler. + * The second prescaler can be used to divide the 8 MHZ CMT clock + * by 1, 2, 4, or 8 according to the specification. + */ +typedef enum _cmt_second_clkdiv +{ + kCMT_SecondClkDiv1 = 0U, /*!< The CMT clock is the intermediate frequency frequency divided by 1. */ + kCMT_SecondClkDiv2 = 1U, /*!< The CMT clock is the intermediate frequency frequency divided by 2. */ + kCMT_SecondClkDiv4 = 2U, /*!< The CMT clock is the intermediate frequency frequency divided by 4. */ + kCMT_SecondClkDiv8 = 3U /*!< The CMT clock is the intermediate frequency frequency divided by 8. */ +} cmt_second_clkdiv_t; + +/*! + * @brief The CMT infrared output polarity. + */ +typedef enum _cmt_infrared_output_polarity +{ + kCMT_IROActiveLow = 0U, /*!< The CMT infrared output signal polarity is active-low. */ + kCMT_IROActiveHigh = 1U /*!< The CMT infrared output signal polarity is active-high. */ +} cmt_infrared_output_polarity_t; + +/*! + * @brief The CMT infrared output signal state control. + */ +typedef enum _cmt_infrared_output_state +{ + kCMT_IROCtlLow = 0U, /*!< The CMT Infrared output signal state is controlled to low. */ + kCMT_IROCtlHigh = 1U /*!< The CMT Infrared output signal state is controlled to high. */ +} cmt_infrared_output_state_t; + +/*! + * @brief CMT interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the CMT interrupt configurations. + */ +enum _cmt_interrupt_enable +{ + kCMT_EndOfCycleInterruptEnable = CMT_MSC_EOCIE_MASK, /*!< CMT end of cycle interrupt. */ +}; + +/*! + * @brief CMT carrier generator and modulator configuration structure + * + */ +typedef struct _cmt_modulate_config +{ + uint8_t highCount1; /*!< The high-time for carrier generator first register. */ + uint8_t lowCount1; /*!< The low-time for carrier generator first register. */ + uint8_t highCount2; /*!< The high-time for carrier generator second register for FSK mode. */ + uint8_t lowCount2; /*!< The low-time for carrier generator second register for FSK mode. */ + uint16_t markCount; /*!< The mark time for the modulator gate. */ + uint16_t spaceCount; /*!< The space time for the modulator gate. */ +} cmt_modulate_config_t; + +/*! @brief CMT basic configuration structure. */ +typedef struct _cmt_config +{ + bool isInterruptEnabled; /*!< Timer interrupt 0-disable, 1-enable. */ + bool isIroEnabled; /*!< The IRO output 0-disabled, 1-enabled. */ + cmt_infrared_output_polarity_t iroPolarity; /*!< The IRO polarity. */ + cmt_second_clkdiv_t divider; /*!< The CMT clock divide prescaler. */ +} cmt_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Gets the CMT default configuration structure. This API + * gets the default configuration structure for the CMT_Init(). + * Use the initialized structure unchanged in CMT_Init() or modify + * fields of the structure before calling the CMT_Init(). + * + * @param config The CMT configuration structure pointer. + */ +void CMT_GetDefaultConfig(cmt_config_t *config); + +/*! + * @brief Initializes the CMT module. + * + * This function ungates the module clock and sets the CMT internal clock, + * interrupt, and infrared output signal for the CMT module. + * + * @param base CMT peripheral base address. + * @param config The CMT basic configuration structure. + * @param busClock_Hz The CMT module input clock - bus clock frequency. + */ +void CMT_Init(CMT_Type *base, const cmt_config_t *config, uint32_t busClock_Hz); + +/*! + * @brief Disables the CMT module and gate control. + * + * This function disables CMT modulator, interrupts, and gates the + * CMT clock control. CMT_Init must be called to use the CMT again. + * + * @param base CMT peripheral base address. + */ +void CMT_Deinit(CMT_Type *base); + +/*! @}*/ + +/*! + * @name Basic Control Operations + * @{ + */ + +/*! + * @brief Selects the mode for CMT. + * + * @param base CMT peripheral base address. + * @param mode The CMT feature mode enumeration. See "cmt_mode_t". + * @param modulateConfig The carrier generation and modulator configuration. + */ +void CMT_SetMode(CMT_Type *base, cmt_mode_t mode, cmt_modulate_config_t *modulateConfig); + +/*! + * @brief Gets the mode of the CMT module. + * + * @param base CMT peripheral base address. + * @return The CMT mode. + * kCMT_DirectIROCtl Carrier modulator is disabled; the IRO signal is directly in software control. + * kCMT_TimeMode Carrier modulator is enabled in time mode. + * kCMT_FSKMode Carrier modulator is enabled in FSK mode. + * kCMT_BasebandMode Carrier modulator is enabled in baseband mode. + */ +cmt_mode_t CMT_GetMode(CMT_Type *base); + +/*! + * @brief Gets the actual CMT clock frequency. + * + * @param base CMT peripheral base address. + * @param busClock_Hz CMT module input clock - bus clock frequency. + * @return The CMT clock frequency. + */ +uint32_t CMT_GetCMTFrequency(CMT_Type *base, uint32_t busClock_Hz); + +/*! + * @brief Sets the primary data set for the CMT carrier generator counter. + * + * This function sets the high-time and low-time of the primary data set for the + * CMT carrier generator counter to control the period and the duty cycle of the + * output carrier signal. + * If the CMT clock period is Tcmt, the period of the carrier generator signal equals + * (highCount + lowCount) * Tcmt. The duty cycle equals to highCount / (highCount + lowCount). + * + * @param base CMT peripheral base address. + * @param highCount The number of CMT clocks for carrier generator signal high time, + * integer in the range of 1 ~ 0xFF. + * @param lowCount The number of CMT clocks for carrier generator signal low time, + * integer in the range of 1 ~ 0xFF. + */ +static inline void CMT_SetCarrirGenerateCountOne(CMT_Type *base, uint32_t highCount, uint32_t lowCount) +{ + assert(highCount <= CMT_CGH1_PH_MASK); + assert(highCount); + assert(lowCount <= CMT_CGL1_PL_MASK); + assert(lowCount); + + base->CGH1 = highCount; + base->CGL1 = lowCount; +} + +/*! + * @brief Sets the secondary data set for the CMT carrier generator counter. + * + * This function is used for FSK mode setting the high-time and low-time of the secondary + * data set CMT carrier generator counter to control the period and the duty cycle + * of the output carrier signal. + * If the CMT clock period is Tcmt, the period of the carrier generator signal equals + * (highCount + lowCount) * Tcmt. The duty cycle equals highCount / (highCount + lowCount). + * + * @param base CMT peripheral base address. + * @param highCount The number of CMT clocks for carrier generator signal high time, + * integer in the range of 1 ~ 0xFF. + * @param lowCount The number of CMT clocks for carrier generator signal low time, + * integer in the range of 1 ~ 0xFF. + */ +static inline void CMT_SetCarrirGenerateCountTwo(CMT_Type *base, uint32_t highCount, uint32_t lowCount) +{ + assert(highCount <= CMT_CGH2_SH_MASK); + assert(highCount); + assert(lowCount <= CMT_CGL2_SL_MASK); + assert(lowCount); + + base->CGH2 = highCount; + base->CGL2 = lowCount; +} + +/*! + * @brief Sets the modulation mark and space time period for the CMT modulator. + * + * This function sets the mark time period of the CMT modulator counter + * to control the mark time of the output modulated signal from the carrier generator output signal. + * If the CMT clock frequency is Fcmt and the carrier out signal frequency is fcg: + * - In Time and Baseband mode: The mark period of the generated signal equals (markCount + 1) / (Fcmt/8). + * The space period of the generated signal equals spaceCount / (Fcmt/8). + * - In FSK mode: The mark period of the generated signal equals (markCount + 1)/fcg. + * The space period of the generated signal equals spaceCount / fcg. + * + * @param base Base address for current CMT instance. + * @param markCount The number of clock period for CMT modulator signal mark period, + * in the range of 0 ~ 0xFFFF. + * @param spaceCount The number of clock period for CMT modulator signal space period, + * in the range of the 0 ~ 0xFFFF. + */ +void CMT_SetModulateMarkSpace(CMT_Type *base, uint32_t markCount, uint32_t spaceCount); + +/*! + * @brief Enables or disables the extended space operation. + * + * This function is used to make the space period longer + * for time, baseband, and FSK modes. + * + * @param base CMT peripheral base address. + * @param enable True enable the extended space, false disable the extended space. + */ +static inline void CMT_EnableExtendedSpace(CMT_Type *base, bool enable) +{ + if (enable) + { + base->MSC |= CMT_MSC_EXSPC_MASK; + } + else + { + base->MSC &= ~CMT_MSC_EXSPC_MASK; + } +} + +/*! + * @brief Sets the IRO (infrared output) signal state. + * + * Changes the states of the IRO signal when the kCMT_DirectIROMode mode is set + * and the IRO signal is enabled. + * + * @param base CMT peripheral base address. + * @param state The control of the IRO signal. See "cmt_infrared_output_state_t" + */ +void CMT_SetIroState(CMT_Type *base, cmt_infrared_output_state_t state); + +/*! + * @brief Enables the CMT interrupt. + * + * This function enables the CMT interrupts according to the provided mask if enabled. + * The CMT only has the end of the cycle interrupt - an interrupt occurs at the end + * of the modulator cycle. This interrupt provides a means for the user + * to reload the new mark/space values into the CMT modulator data registers + * and verify the modulator mark and space. + * For example, to enable the end of cycle, do the following. + * @code + * CMT_EnableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable); + * @endcode + * @param base CMT peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _cmt_interrupt_enable. + */ +static inline void CMT_EnableInterrupts(CMT_Type *base, uint32_t mask) +{ + base->MSC |= mask; +} + +/*! + * @brief Disables the CMT interrupt. + * + * This function disables the CMT interrupts according to the provided maskIf enabled. + * The CMT only has the end of the cycle interrupt. + * For example, to disable the end of cycle, do the following. + * @code + * CMT_DisableInterrupts(CMT, kCMT_EndOfCycleInterruptEnable); + * @endcode + * + * @param base CMT peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _cmt_interrupt_enable. + */ +static inline void CMT_DisableInterrupts(CMT_Type *base, uint32_t mask) +{ + base->MSC &= ~mask; +} + +/*! + * @brief Gets the end of the cycle status flag. + * + * The flag is set: + * - When the modulator is not currently active and carrier and modulator + * are set to start the initial CMT transmission. + * - At the end of each modulation cycle when the counter is reloaded and + * the carrier and modulator are enabled. + * @param base CMT peripheral base address. + * @return Current status of the end of cycle status flag + * @arg non-zero: End-of-cycle has occurred. + * @arg zero: End-of-cycle has not yet occurred since the flag last cleared. + */ +static inline uint32_t CMT_GetStatusFlags(CMT_Type *base) +{ + return base->MSC & CMT_MSC_EOCF_MASK; +} + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CMT_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_common.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_common.c new file mode 100644 index 00000000000..b719fafbc04 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_common.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_common.h" +/* This is not needed for mbed */ +#if 0 +#include "fsl_debug_console.h" + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); + for (;;) + { + __BKPT(0); + } +} +#elif(defined(__REDLIB__)) + +#if SDK_DEBUGCONSOLE +void __assertion_failed(char *_Expr) +{ + PRINTF("%s\n", _Expr); + for (;;) + { + __asm("bkpt #0"); + } +} +#endif + +#elif(defined(__GNUC__)) +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); + for (;;) + { + __BKPT(0); + } +} +#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */ +#endif /* NDEBUG */ +#endif /* This was not needed for mbed */ + +#ifndef __GIC_PRIO_BITS +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + + return ret; +} +#endif + +#ifndef CPU_QN908X +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t index = 0; + uint32_t intNumber = (uint32_t)interrupt; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1u << intNumber; + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t index = 0; + uint32_t intNumber = (uint32_t)interrupt; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + SYSCON->STARTERCLR[index] = 1u << intNumber; +} +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ +#else +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t index = 0; + uint32_t intNumber = (uint32_t)interrupt; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + /* SYSCON->STARTERSET[index] = 1u << intNumber; */ + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t index = 0; + uint32_t intNumber = (uint32_t)interrupt; + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + /* SYSCON->STARTERCLR[index] = 1u << intNumber; */ +} +#endif /*CPU_QN908X */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_common.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_common.h new file mode 100644 index 00000000000..f20c09027e9 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_common.h @@ -0,0 +1,348 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enable specific interrupt. + * + * Enable the interrupt not routed from intmux. + * + * @param interrupt The IRQ number. + */ +static inline void EnableIRQ(IRQn_Type interrupt) +{ + if (NotAvail_IRQn == interrupt) + { + return; + } + +#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) + if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) +#endif + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } +} + +/*! + * @brief Disable specific interrupt. + * + * Disable the interrupt not routed from intmux. + * + * @param interrupt The IRQ number. + */ +static inline void DisableIRQ(IRQn_Type interrupt) +{ + if (NotAvail_IRQn == interrupt) + { + return; + } + +#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0) + if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX) +#endif + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +} + +/*! + * @brief Enaable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +} + +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) +/*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ +void EnableDeepSleepIRQ(IRQn_Type interrupt); + +/*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally). + * + * @param interrupt The IRQ number. + */ +void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_crc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_crc.c new file mode 100644 index 00000000000..dba1db8c463 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_crc.c @@ -0,0 +1,282 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_crc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @internal @brief Has data register with name CRC. */ +#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG +#define DATA CRC +#define DATALL CRCLL +#endif + +#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT +/* @brief Default user configuration structure for CRC-16-CCITT */ +#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U +/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */ +#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU +/*< Default initial checksum */ +#define CRC_DRIVER_DEFAULT_REFLECT_IN false +/*< Default is no transpose */ +#define CRC_DRIVER_DEFAULT_REFLECT_OUT false +/*< Default is transpose bytes */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false +/*< Default is without complement of CRC data register read data */ +#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16 +/*< Default is 16-bit CRC protocol */ +#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum +/*< Default is resutl type is final checksum */ +#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */ + +/*! @brief CRC type of transpose of read write data */ +typedef enum _crc_transpose_type +{ + kCrcTransposeNone = 0U, /*! No transpose */ + kCrcTransposeBits = 1U, /*! Tranpose bits in bytes */ + kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */ + kCrcTransposeBytes = 3U, /*! Transpose bytes */ +} crc_transpose_type_t; + +/*! +* @brief CRC module configuration. +* +* This structure holds the configuration for the CRC module. +*/ +typedef struct _crc_module_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first.@n + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + crc_transpose_type_t readTranspose; /*!< Type of transpose when reading CRC result. */ + crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ +} crc_module_config_t; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Returns transpose type for CRC protocol reflect in parameter. + * + * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter. + */ +static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectIn(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes); +} + +/*! + * @brief Returns transpose type for CRC protocol reflect out parameter. + * + * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter. + */ +static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectOut(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone); +} + +/*! + * @brief Starts checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts the checksum computation by writing the seed value + * + * @param base CRC peripheral address. + * @param config Pointer to protocol configuration structure. + */ +static void CRC_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config) +{ + uint32_t crcControl; + + /* pre-compute value for CRC control registger based on user configuraton without WAS field */ + crcControl = 0 | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) | + CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits); + + /* make sure the control register is clear - WAS is deasserted, and protocol is set */ + base->CTRL = crcControl; + + /* write polynomial register */ + base->GPOLY = config->polynomial; + + /* write pre-computed control register value along with WAS to start checksum computation */ + base->CTRL = crcControl | CRC_CTRL_WAS(true); + + /* write seed (initial checksum) */ + base->DATA = config->seed; + + /* deassert WAS by writing pre-computed CRC control register value */ + base->CTRL = crcControl; +} + +/*! + * @brief Starts final checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts final checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum + * (output reflection and xor functions are applied). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void CRC_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for final checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = CRC_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut); + moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = protocolConfig->complementChecksum; + moduleConfig.crcBits = protocolConfig->crcBits; + + CRC_ConfigureAndStart(base, &moduleConfig); +} + +/*! + * @brief Starts intermediate checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts intermediate checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void CRC_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = + kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */ + moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */ + moduleConfig.crcBits = protocolConfig->crcBits; + + CRC_ConfigureAndStart(base, &moduleConfig); +} + +void CRC_Init(CRC_Type *base, const crc_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* ungate clock */ + CLOCK_EnableClock(kCLOCK_Crc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* configure CRC module and write the seed */ + if (config->crcResult == kCrcFinalChecksum) + { + CRC_SetProtocolConfig(base, config); + } + else + { + CRC_SetRawProtocolConfig(base, config); + } +} + +void CRC_GetDefaultConfig(crc_config_t *config) +{ + static const crc_config_t crc16ccit = { + CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED, + CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT, + CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS, + CRC_DRIVER_DEFAULT_CRC_RESULT, + }; + + *config = crc16ccit; +} + +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) +{ + const uint32_t *data32; + + /* 8-bit reads and writes till source address is aligned 4 bytes */ + while ((dataSize) && ((uint32_t)data & 3U)) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } + + /* use 32-bit reads and writes as long as possible */ + data32 = (const uint32_t *)data; + while (dataSize >= sizeof(uint32_t)) + { + base->DATA = *data32; + data32++; + dataSize -= sizeof(uint32_t); + } + + data = (const uint8_t *)data32; + + /* 8-bit reads and writes till end of data buffer */ + while (dataSize) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } +} + +uint32_t CRC_Get32bitResult(CRC_Type *base) +{ + return base->DATA; +} + +uint16_t CRC_Get16bitResult(CRC_Type *base) +{ + uint32_t retval; + uint32_t totr; /* type of transpose read bitfield */ + + retval = base->DATA; + totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT; + + /* check transpose type to get 16-bit out of 32-bit register */ + if (totr >= 2U) + { + /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */ + retval &= 0xFFFF0000U; + retval = retval >> 16U; + } + else + { + /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */ + retval &= 0x0000FFFFU; + } + return (uint16_t)retval; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_crc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_crc.h new file mode 100644 index 00000000000..247a9bac781 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_crc.h @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_CRC_H_ +#define _FSL_CRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup crc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CRC driver version. Version 2.0.1. + * + * Current version: 2.0.1 + * + * Change log: + * - Version 2.0.1 + * - move DATA and DATALL macro definition from header file to source file + */ +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +#ifndef CRC_DRIVER_CUSTOM_DEFAULTS +/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */ +#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1 +#endif + +/*! @brief CRC bit width */ +typedef enum _crc_bits +{ + kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */ + kCrcBits32 = 1U /*!< Generate 32-bit CRC code */ +} crc_bits_t; + +/*! @brief CRC result type */ +typedef enum _crc_result +{ + kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum. + Reflect out and final xor protocol features are applied. */ + kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value). + Reflect out and final xor protocol feature are not applied. + Intermediate checksum can be used as a seed for CRC_Init() + to continue adding data to this checksum. */ +} crc_result_t; + +/*! +* @brief CRC protocol configuration. +* +* This structure holds the configuration for the CRC protocol. +* +*/ +typedef struct _crc_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first. + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + bool reflectIn; /*!< Reflect bits on input. */ + bool reflectOut; /*!< Reflect bits on output. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ + crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or + CRC_Get32bitResult() */ +} crc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enables and configures the CRC peripheral module. + * + * This function enables the clock gate in the SIM module for the CRC peripheral. + * It also configures the CRC module and starts a checksum computation by writing the seed. + * + * @param base CRC peripheral address. + * @param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config); + +/*! + * @brief Disables the CRC peripheral module. + * + * This function disables the clock gate in the SIM module for the CRC peripheral. + * + * @param base CRC peripheral address. + */ +static inline void CRC_Deinit(CRC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* gate clock */ + CLOCK_DisableClock(kCLOCK_Crc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Loads default values to the CRC protocol configuration structure. + * + * Loads default values to the CRC protocol configuration structure. The default values are as follows. + * @code + * config->polynomial = 0x1021; + * config->seed = 0xFFFF; + * config->reflectIn = false; + * config->reflectOut = false; + * config->complementChecksum = false; + * config->crcBits = kCrcBits16; + * config->crcResult = kCrcFinalChecksum; + * @endcode + * + * @param config CRC protocol configuration structure. + */ +void CRC_GetDefaultConfig(crc_config_t *config); + +/*! + * @brief Writes data to the CRC module. + * + * Writes input data buffer bytes to the CRC data register. + * The configured type of transpose is applied. + * + * @param base CRC peripheral address. + * @param data Input data stream, MSByte in data[0]. + * @param dataSize Size in bytes of the input data buffer. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); + +/*! + * @brief Reads the 32-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * @param base CRC peripheral address. + * @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations. + */ +uint32_t CRC_Get32bitResult(CRC_Type *base); + +/*! + * @brief Reads a 16-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * @param base CRC peripheral address. + * @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations. + */ +uint16_t CRC_Get16bitResult(CRC_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_CRC_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dac.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dac.c new file mode 100644 index 00000000000..8d13d622835 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dac.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dac.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for DAC module. + * + * @param base DAC peripheral base address + */ +static uint32_t DAC_GetInstance(DAC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to DAC bases for each instance. */ +static DAC_Type *const s_dacBases[] = DAC_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to DAC clocks for each instance. */ +static const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t DAC_GetInstance(DAC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dacBases); instance++) + { + if (s_dacBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_dacBases)); + + return instance; +} + +void DAC_Init(DAC_Type *base, const dac_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure. */ + /* DACx_C0. */ + tmp8 = base->C0 & ~(DAC_C0_DACRFS_MASK | DAC_C0_LPEN_MASK); + if (kDAC_ReferenceVoltageSourceVref2 == config->referenceVoltageSource) + { + tmp8 |= DAC_C0_DACRFS_MASK; + } + if (config->enableLowPowerMode) + { + tmp8 |= DAC_C0_LPEN_MASK; + } + base->C0 = tmp8; + + /* DAC_Enable(base, true); */ + /* Tip: The DAC output can be enabled till then after user sets their own available data in application. */ +} + +void DAC_Deinit(DAC_Type *base) +{ + DAC_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void DAC_GetDefaultConfig(dac_config_t *config) +{ + assert(NULL != config); + + config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2; + config->enableLowPowerMode = false; +} + +void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + + /* DACx_C0. */ + tmp8 = base->C0 & ~(DAC_C0_DACTRGSEL_MASK); + if (kDAC_BufferTriggerBySoftwareMode == config->triggerMode) + { + tmp8 |= DAC_C0_DACTRGSEL_MASK; + } + base->C0 = tmp8; + + /* DACx_C1. */ + tmp8 = base->C1 & + ~( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + DAC_C1_DACBFWM_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + DAC_C1_DACBFMD_MASK); +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + tmp8 |= DAC_C1_DACBFWM(config->watermark); +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + tmp8 |= DAC_C1_DACBFMD(config->workMode); + base->C1 = tmp8; + + /* DACx_C2. */ + tmp8 = base->C2 & ~DAC_C2_DACBFUP_MASK; + tmp8 |= DAC_C2_DACBFUP(config->upperLimit); + base->C2 = tmp8; +} + +void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config) +{ + assert(NULL != config); + + config->triggerMode = kDAC_BufferTriggerBySoftwareMode; +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + config->watermark = kDAC_BufferWatermark1Word; +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + config->workMode = kDAC_BufferWorkAsNormalMode; + config->upperLimit = DAC_DATL_COUNT - 1U; +} + +void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value) +{ + assert(index < DAC_DATL_COUNT); + + base->DAT[index].DATL = (uint8_t)(0xFFU & value); /* Low 8-bit. */ + base->DAT[index].DATH = (uint8_t)((0xF00U & value) >> 8); /* High 4-bit. */ +} + +void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index) +{ + assert(index < DAC_DATL_COUNT); + + uint8_t tmp8 = base->C2 & ~DAC_C2_DACBFRP_MASK; + + tmp8 |= DAC_C2_DACBFRP(index); + base->C2 = tmp8; +} + +void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask) +{ + mask &= ( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + DAC_C0_DACBWIEN_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK); + base->C0 |= ((uint8_t)mask); /* Write 1 to enable. */ +} + +void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask) +{ + mask &= ( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + DAC_C0_DACBWIEN_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + DAC_C0_DACBTIEN_MASK | DAC_C0_DACBBIEN_MASK); + base->C0 &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to disable. */ +} + +uint32_t DAC_GetBufferStatusFlags(DAC_Type *base) +{ + return (uint32_t)(base->SR & ( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + DAC_SR_DACBFWMF_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK)); +} + +void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask) +{ + mask &= ( +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + DAC_SR_DACBFWMF_MASK | +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + DAC_SR_DACBFRPTF_MASK | DAC_SR_DACBFRPBF_MASK); + base->SR &= (uint8_t)(~((uint8_t)mask)); /* Write 0 to clear flags. */ +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dac.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dac.h new file mode 100644 index 00000000000..b71febf3bc3 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dac.h @@ -0,0 +1,378 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DAC_H_ +#define _FSL_DAC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dac + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DAC driver version 2.0.1. */ +#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief DAC buffer flags. + */ +enum _dac_buffer_status_flags +{ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + kDAC_BufferWatermarkFlag = DAC_SR_DACBFWMF_MASK, /*!< DAC Buffer Watermark Flag. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + kDAC_BufferReadPointerTopPositionFlag = DAC_SR_DACBFRPTF_MASK, /*!< DAC Buffer Read Pointer Top Position Flag. */ + kDAC_BufferReadPointerBottomPositionFlag = DAC_SR_DACBFRPBF_MASK, /*!< DAC Buffer Read Pointer Bottom Position + Flag. */ +}; + +/*! + * @brief DAC buffer interrupts. + */ +enum _dac_buffer_interrupt_enable +{ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION + kDAC_BufferWatermarkInterruptEnable = DAC_C0_DACBWIEN_MASK, /*!< DAC Buffer Watermark Interrupt Enable. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION */ + kDAC_BufferReadPointerTopInterruptEnable = DAC_C0_DACBTIEN_MASK, /*!< DAC Buffer Read Pointer Top Flag Interrupt + Enable. */ + kDAC_BufferReadPointerBottomInterruptEnable = DAC_C0_DACBBIEN_MASK, /*!< DAC Buffer Read Pointer Bottom Flag + Interrupt Enable */ +}; + +/*! + * @brief DAC reference voltage source. + */ +typedef enum _dac_reference_voltage_source +{ + kDAC_ReferenceVoltageSourceVref1 = 0U, /*!< The DAC selects DACREF_1 as the reference voltage. */ + kDAC_ReferenceVoltageSourceVref2 = 1U, /*!< The DAC selects DACREF_2 as the reference voltage. */ +} dac_reference_voltage_source_t; + +/*! + * @brief DAC buffer trigger mode. + */ +typedef enum _dac_buffer_trigger_mode +{ + kDAC_BufferTriggerByHardwareMode = 0U, /*!< The DAC hardware trigger is selected. */ + kDAC_BufferTriggerBySoftwareMode = 1U, /*!< The DAC software trigger is selected. */ +} dac_buffer_trigger_mode_t; + +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION +/*! + * @brief DAC buffer watermark. + */ +typedef enum _dac_buffer_watermark +{ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD) && FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD + kDAC_BufferWatermark1Word = 0U, /*!< 1 word away from the upper limit. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD */ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS + kDAC_BufferWatermark2Word = 1U, /*!< 2 words away from the upper limit. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS */ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS + kDAC_BufferWatermark3Word = 2U, /*!< 3 words away from the upper limit. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS */ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS) && FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS + kDAC_BufferWatermark4Word = 3U, /*!< 4 words away from the upper limit. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS */ +} dac_buffer_watermark_t; +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + +/*! + * @brief DAC buffer work mode. + */ +typedef enum _dac_buffer_work_mode +{ + kDAC_BufferWorkAsNormalMode = 0U, /*!< Normal mode. */ +#if defined(FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE + kDAC_BufferWorkAsSwingMode, /*!< Swing mode. */ +#endif /* FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE */ + kDAC_BufferWorkAsOneTimeScanMode, /*!< One-Time Scan mode. */ +#if defined(FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE) && FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE + kDAC_BufferWorkAsFIFOMode, /*!< FIFO mode. */ +#endif /* FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE */ +} dac_buffer_work_mode_t; + +/*! + * @brief DAC module configuration. + */ +typedef struct _dac_config +{ + dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the DAC reference voltage source. */ + bool enableLowPowerMode; /*!< Enable the low-power mode. */ +} dac_config_t; + +/*! + * @brief DAC buffer configuration. + */ +typedef struct _dac_buffer_config +{ + dac_buffer_trigger_mode_t triggerMode; /*!< Select the buffer's trigger mode. */ +#if defined(FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION) && FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + dac_buffer_watermark_t watermark; /*!< Select the buffer's watermark. */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + dac_buffer_work_mode_t workMode; /*!< Select the buffer's work mode. */ + uint8_t upperLimit; /*!< Set the upper limit for the buffer index. + Normally, 0-15 is available for a buffer with 16 items. */ +} dac_buffer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the DAC module. + * + * This function initializes the DAC module including the following operations. + * - Enabling the clock for DAC module. + * - Configuring the DAC converter with a user configuration. + * - Enabling the DAC module. + * + * @param base DAC peripheral base address. + * @param config Pointer to the configuration structure. See "dac_config_t". + */ +void DAC_Init(DAC_Type *base, const dac_config_t *config); + +/*! + * @brief De-initializes the DAC module. + * + * This function de-initializes the DAC module including the following operations. + * - Disabling the DAC module. + * - Disabling the clock for the DAC module. + * + * @param base DAC peripheral base address. + */ +void DAC_Deinit(DAC_Type *base); + +/*! + * @brief Initializes the DAC user configuration structure. + * + * This function initializes the user configuration structure to a default value. The default values are as follows. + * @code + * config->referenceVoltageSource = kDAC_ReferenceVoltageSourceVref2; + * config->enableLowPowerMode = false; + * @endcode + * @param config Pointer to the configuration structure. See "dac_config_t". + */ +void DAC_GetDefaultConfig(dac_config_t *config); + +/*! + * @brief Enables the DAC module. + * + * @param base DAC peripheral base address. + * @param enable Enables or disables the feature. + */ +static inline void DAC_Enable(DAC_Type *base, bool enable) +{ + if (enable) + { + base->C0 |= DAC_C0_DACEN_MASK; + } + else + { + base->C0 &= ~DAC_C0_DACEN_MASK; + } +} + +/* @} */ + +/*! + * @name Buffer + * @{ + */ + +/*! + * @brief Enables the DAC buffer. + * + * @param base DAC peripheral base address. + * @param enable Enables or disables the feature. + */ +static inline void DAC_EnableBuffer(DAC_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= DAC_C1_DACBFEN_MASK; + } + else + { + base->C1 &= ~DAC_C1_DACBFEN_MASK; + } +} + +/*! + * @brief Configures the CMP buffer. + * + * @param base DAC peripheral base address. + * @param config Pointer to the configuration structure. See "dac_buffer_config_t". + */ +void DAC_SetBufferConfig(DAC_Type *base, const dac_buffer_config_t *config); + +/*! + * @brief Initializes the DAC buffer configuration structure. + * + * This function initializes the DAC buffer configuration structure to default values. The default values are as follows. + * @code + * config->triggerMode = kDAC_BufferTriggerBySoftwareMode; + * config->watermark = kDAC_BufferWatermark1Word; + * config->workMode = kDAC_BufferWorkAsNormalMode; + * config->upperLimit = DAC_DATL_COUNT - 1U; + * @endcode + * @param config Pointer to the configuration structure. See "dac_buffer_config_t". + */ +void DAC_GetDefaultBufferConfig(dac_buffer_config_t *config); + +/*! + * @brief Enables the DMA for DAC buffer. + * + * @param base DAC peripheral base address. + * @param enable Enables or disables the feature. + */ +static inline void DAC_EnableBufferDMA(DAC_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= DAC_C1_DMAEN_MASK; + } + else + { + base->C1 &= ~DAC_C1_DMAEN_MASK; + } +} + +/*! + * @brief Sets the value for items in the buffer. + * + * @param base DAC peripheral base address. + * @param index Setting the index for items in the buffer. The available index should not exceed the size of the DAC buffer. + * @param value Setting the value for items in the buffer. 12-bits are available. + */ +void DAC_SetBufferValue(DAC_Type *base, uint8_t index, uint16_t value); + +/*! + * @brief Triggers the buffer using software and updates the read pointer of the DAC buffer. + * + * This function triggers the function using software. The read pointer of the DAC buffer is updated with one step + * after this function is called. Changing the read pointer depends on the buffer's work mode. + * + * @param base DAC peripheral base address. + */ +static inline void DAC_DoSoftwareTriggerBuffer(DAC_Type *base) +{ + base->C0 |= DAC_C0_DACSWTRG_MASK; +} + +/*! + * @brief Gets the current read pointer of the DAC buffer. + * + * This function gets the current read pointer of the DAC buffer. + * The current output value depends on the item indexed by the read pointer. It is updated either + * by a software trigger or a hardware trigger. + * + * @param base DAC peripheral base address. + * + * @return The current read pointer of the DAC buffer. + */ +static inline uint8_t DAC_GetBufferReadPointer(DAC_Type *base) +{ + return ((base->C2 & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT); +} + +/*! + * @brief Sets the current read pointer of the DAC buffer. + * + * This function sets the current read pointer of the DAC buffer. + * The current output value depends on the item indexed by the read pointer. It is updated either by a + * software trigger or a hardware trigger. After the read pointer changes, the DAC output value also changes. + * + * @param base DAC peripheral base address. + * @param index Setting an index value for the pointer. + */ +void DAC_SetBufferReadPointer(DAC_Type *base, uint8_t index); + +/*! + * @brief Enables interrupts for the DAC buffer. + * + * @param base DAC peripheral base address. + * @param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable". + */ +void DAC_EnableBufferInterrupts(DAC_Type *base, uint32_t mask); + +/*! + * @brief Disables interrupts for the DAC buffer. + * + * @param base DAC peripheral base address. + * @param mask Mask value for interrupts. See "_dac_buffer_interrupt_enable". + */ +void DAC_DisableBufferInterrupts(DAC_Type *base, uint32_t mask); + +/*! + * @brief Gets the flags of events for the DAC buffer. + * + * @param base DAC peripheral base address. + * + * @return Mask value for the asserted flags. See "_dac_buffer_status_flags". + */ +uint32_t DAC_GetBufferStatusFlags(DAC_Type *base); + +/*! + * @brief Clears the flags of events for the DAC buffer. + * + * @param base DAC peripheral base address. + * @param mask Mask value for flags. See "_dac_buffer_status_flags_t". + */ +void DAC_ClearBufferStatusFlags(DAC_Type *base, uint32_t mask); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_DAC_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dmamux.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dmamux.c new file mode 100644 index 00000000000..39ce9cfbead --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dmamux.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMAMUX. + * + * @param base DMAMUX peripheral base address. + */ +static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMAMUX instance number to base pointer. */ +static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map DMAMUX instance number to clock name. */ +static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmamuxBases); instance++) + { + if (s_dmamuxBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_dmamuxBases)); + + return instance; +} + +void DMAMUX_Init(DMAMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void DMAMUX_Deinit(DMAMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dmamux.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dmamux.h new file mode 100644 index 00000000000..071348b2c25 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dmamux.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DMAMUX_H_ +#define _FSL_DMAMUX_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dmamux + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMAMUX driver version 2.0.2. */ +#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMAMUX Initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the DMAMUX peripheral. + * + * This function ungates the DMAMUX clock. + * + * @param base DMAMUX peripheral base address. + * + */ +void DMAMUX_Init(DMAMUX_Type *base); + +/*! + * @brief Deinitializes the DMAMUX peripheral. + * + * This function gates the DMAMUX clock. + * + * @param base DMAMUX peripheral base address. + */ +void DMAMUX_Deinit(DMAMUX_Type *base); + +/* @} */ +/*! + * @name DMAMUX Channel Operation + * @{ + */ + +/*! + * @brief Enables the DMAMUX channel. + * + * This function enables the DMAMUX channel. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; +} + +/*! + * @brief Disables the DMAMUX channel. + * + * This function disables the DMAMUX channel. + * + * @note The user must disable the DMAMUX channel before configuring it. + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; +} + +/*! + * @brief Configures the DMAMUX channel source. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + * @param source Channel source, which is used to trigger the DMA transfer. + */ +static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] = ((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); +} + +#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U +/*! + * @brief Enables the DMAMUX period trigger. + * + * This function enables the DMAMUX period trigger feature. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK; +} + +/*! + * @brief Disables the DMAMUX period trigger. + * + * This function disables the DMAMUX period trigger. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] &= ~DMAMUX_CHCFG_TRIG_MASK; +} +#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */ + +#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON) +/*! + * @brief Enables the DMA channel to be always ON. + * + * This function enables the DMAMUX channel always ON feature. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + * @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled. + */ +static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + if (enable) + { + base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK; + } + else + { + base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK; + } +} +#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /* _FSL_DMAMUX_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dspi.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dspi.c new file mode 100644 index 00000000000..e2b90ba56a9 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dspi.c @@ -0,0 +1,1669 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dspi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Typedef for master interrupt handler. */ +typedef void (*dspi_master_isr_t)(SPI_Type *base, dspi_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*dspi_slave_isr_t)(SPI_Type *base, dspi_slave_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for DSPI module. + * + * @param base DSPI peripheral base address. + */ +uint32_t DSPI_GetInstance(SPI_Type *base); + +/*! + * @brief Configures the DSPI peripheral chip select polarity. + * + * This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and + * configures the Pcs signal to operate with the desired characteristic. + * + * @param base DSPI peripheral address. + * @param pcs The particular peripheral chip select (parameter value is of type dspi_which_pcs_t) for which we wish to + * apply the active high or active low characteristic. + * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of + * type dspi_pcs_polarity_config_t. + */ +static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh); + +/*! + * @brief Master fill up the TX FIFO with data. + * This is not a public API. + */ +static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle); + +/*! + * @brief Master finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API. + */ +static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle); + +/*! + * @brief Slave fill up the TX FIFO with data. + * This is not a public API. + */ +static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle); + +/*! + * @brief Slave finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API. + */ +static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle); + +/*! + * @brief DSPI common interrupt handler. + * + * @param base DSPI peripheral address. + * @param handle pointer to g_dspiHandle which stores the transfer state. + */ +static void DSPI_CommonIRQHandler(SPI_Type *base, void *param); + +/*! + * @brief Master prepare the transfer. + * Basically it set up dspi_master_handle . + * This is not a public API. + */ +static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ +static const uint32_t s_baudratePrescaler[] = {2, 3, 5, 7}; +static const uint32_t s_baudrateScaler[] = {2, 4, 6, 8, 16, 32, 64, 128, + 256, 512, 1024, 2048, 4096, 8192, 16384, 32768}; + +static const uint32_t s_delayPrescaler[] = {1, 3, 5, 7}; +static const uint32_t s_delayScaler[] = {2, 4, 8, 16, 32, 64, 128, 256, + 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536}; + +/*! @brief Pointers to dspi bases for each instance. */ +static SPI_Type *const s_dspiBases[] = SPI_BASE_PTRS; + +/*! @brief Pointers to dspi IRQ number for each instance. */ +static IRQn_Type const s_dspiIRQ[] = SPI_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to dspi clocks for each instance. */ +static clock_ip_name_t const s_dspiClock[] = DSPI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to dspi handles for each instance. */ +static void *g_dspiHandle[ARRAY_SIZE(s_dspiBases)]; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static dspi_master_isr_t s_dspiMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static dspi_slave_isr_t s_dspiSlaveIsr; + +/********************************************************************************************************************** +* Code +*********************************************************************************************************************/ +uint32_t DSPI_GetInstance(SPI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dspiBases); instance++) + { + if (s_dspiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_dspiBases)); + + return instance; +} + +void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(masterConfig); + + uint32_t temp; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* enable DSPI clock */ + CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + DSPI_Enable(base, true); + DSPI_StopTransfer(base); + + DSPI_SetMasterSlaveMode(base, kDSPI_Master); + + temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK | + SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK)); + + base->MCR = temp | SPI_MCR_CONT_SCKE(masterConfig->enableContinuousSCK) | + SPI_MCR_MTFE(masterConfig->enableModifiedTimingFormat) | + SPI_MCR_ROOE(masterConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(masterConfig->samplePoint) | + SPI_MCR_DIS_TXF(false) | SPI_MCR_DIS_RXF(false); + + DSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow); + + if (0 == DSPI_MasterSetBaudRate(base, masterConfig->whichCtar, masterConfig->ctarConfig.baudRate, srcClock_Hz)) + { + assert(false); + } + + temp = base->CTAR[masterConfig->whichCtar] & + ~(SPI_CTAR_FMSZ_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_LSBFE_MASK); + + base->CTAR[masterConfig->whichCtar] = + temp | SPI_CTAR_FMSZ(masterConfig->ctarConfig.bitsPerFrame - 1) | SPI_CTAR_CPOL(masterConfig->ctarConfig.cpol) | + SPI_CTAR_CPHA(masterConfig->ctarConfig.cpha) | SPI_CTAR_LSBFE(masterConfig->ctarConfig.direction); + + DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_PcsToSck, srcClock_Hz, + masterConfig->ctarConfig.pcsToSckDelayInNanoSec); + DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_LastSckToPcs, srcClock_Hz, + masterConfig->ctarConfig.lastSckToPcsDelayInNanoSec); + DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_BetweenTransfer, srcClock_Hz, + masterConfig->ctarConfig.betweenTransferDelayInNanoSec); + + DSPI_StartTransfer(base); +} + +void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig) +{ + assert(masterConfig); + + masterConfig->whichCtar = kDSPI_Ctar0; + masterConfig->ctarConfig.baudRate = 500000; + masterConfig->ctarConfig.bitsPerFrame = 8; + masterConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + masterConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + masterConfig->ctarConfig.direction = kDSPI_MsbFirst; + + masterConfig->ctarConfig.pcsToSckDelayInNanoSec = 1000; + masterConfig->ctarConfig.lastSckToPcsDelayInNanoSec = 1000; + masterConfig->ctarConfig.betweenTransferDelayInNanoSec = 1000; + + masterConfig->whichPcs = kDSPI_Pcs0; + masterConfig->pcsActiveHighOrLow = kDSPI_PcsActiveLow; + + masterConfig->enableContinuousSCK = false; + masterConfig->enableRxFifoOverWrite = false; + masterConfig->enableModifiedTimingFormat = false; + masterConfig->samplePoint = kDSPI_SckToSin0Clock; +} + +void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + uint32_t temp = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* enable DSPI clock */ + CLOCK_EnableClock(s_dspiClock[DSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + DSPI_Enable(base, true); + DSPI_StopTransfer(base); + + DSPI_SetMasterSlaveMode(base, kDSPI_Slave); + + temp = base->MCR & (~(SPI_MCR_CONT_SCKE_MASK | SPI_MCR_MTFE_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_SMPL_PT_MASK | + SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK)); + + base->MCR = temp | SPI_MCR_CONT_SCKE(slaveConfig->enableContinuousSCK) | + SPI_MCR_MTFE(slaveConfig->enableModifiedTimingFormat) | + SPI_MCR_ROOE(slaveConfig->enableRxFifoOverWrite) | SPI_MCR_SMPL_PT(slaveConfig->samplePoint) | + SPI_MCR_DIS_TXF(false) | SPI_MCR_DIS_RXF(false); + + DSPI_SetOnePcsPolarity(base, kDSPI_Pcs0, kDSPI_PcsActiveLow); + + temp = base->CTAR[slaveConfig->whichCtar] & + ~(SPI_CTAR_FMSZ_MASK | SPI_CTAR_CPOL_MASK | SPI_CTAR_CPHA_MASK | SPI_CTAR_LSBFE_MASK); + + base->CTAR[slaveConfig->whichCtar] = temp | SPI_CTAR_SLAVE_FMSZ(slaveConfig->ctarConfig.bitsPerFrame - 1) | + SPI_CTAR_SLAVE_CPOL(slaveConfig->ctarConfig.cpol) | + SPI_CTAR_SLAVE_CPHA(slaveConfig->ctarConfig.cpha); + + DSPI_StartTransfer(base); +} + +void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + slaveConfig->whichCtar = kDSPI_Ctar0; + slaveConfig->ctarConfig.bitsPerFrame = 8; + slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + + slaveConfig->enableContinuousSCK = false; + slaveConfig->enableRxFifoOverWrite = false; + slaveConfig->enableModifiedTimingFormat = false; + slaveConfig->samplePoint = kDSPI_SckToSin0Clock; +} + +void DSPI_Deinit(SPI_Type *base) +{ + DSPI_StopTransfer(base); + DSPI_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* disable DSPI clock */ + CLOCK_DisableClock(s_dspiClock[DSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pcs_polarity_config_t activeLowOrHigh) +{ + uint32_t temp; + + temp = base->MCR; + + if (activeLowOrHigh == kDSPI_PcsActiveLow) + { + temp |= SPI_MCR_PCSIS(pcs); + } + else + { + temp &= ~SPI_MCR_PCSIS(pcs); + } + + base->MCR = temp; +} + +uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, + dspi_ctar_selection_t whichCtar, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz) +{ + /* for master mode configuration, if slave mode detected, return 0*/ + if (!DSPI_IsMaster(base)) + { + return 0; + } + uint32_t temp; + uint32_t prescaler, bestPrescaler; + uint32_t scaler, bestScaler; + uint32_t dbr, bestDbr; + uint32_t realBaudrate, bestBaudrate; + uint32_t diff, min_diff; + uint32_t baudrate = baudRate_Bps; + + /* find combination of prescaler and scaler resulting in baudrate closest to the requested value */ + min_diff = 0xFFFFFFFFU; + bestPrescaler = 0; + bestScaler = 0; + bestDbr = 1; + bestBaudrate = 0; /* required to avoid compilation warning */ + + /* In all for loops, if min_diff = 0, the exit for loop*/ + for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++) + { + for (scaler = 0; (scaler < 16) && min_diff; scaler++) + { + for (dbr = 1; (dbr < 3) && min_diff; dbr++) + { + realBaudrate = ((srcClock_Hz * dbr) / (s_baudratePrescaler[prescaler] * (s_baudrateScaler[scaler]))); + + /* calculate the baud rate difference based on the conditional statement that states that the calculated + * baud rate must not exceed the desired baud rate. + */ + if (baudrate >= realBaudrate) + { + diff = baudrate - realBaudrate; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestPrescaler = prescaler; + bestScaler = scaler; + bestBaudrate = realBaudrate; + bestDbr = dbr; + } + } + } + } + } + + /* write the best dbr, prescalar, and baud rate scalar to the CTAR */ + temp = base->CTAR[whichCtar] & ~(SPI_CTAR_DBR_MASK | SPI_CTAR_PBR_MASK | SPI_CTAR_BR_MASK); + + base->CTAR[whichCtar] = temp | ((bestDbr - 1) << SPI_CTAR_DBR_SHIFT) | (bestPrescaler << SPI_CTAR_PBR_SHIFT) | + (bestScaler << SPI_CTAR_BR_SHIFT); + + /* return the actual calculated baud rate */ + return bestBaudrate; +} + +void DSPI_MasterSetDelayScaler( + SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay) +{ + /* these settings are only relevant in master mode */ + if (DSPI_IsMaster(base)) + { + switch (whichDelay) + { + case kDSPI_PcsToSck: + base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PCSSCK_MASK) & (~SPI_CTAR_CSSCK_MASK)) | + SPI_CTAR_PCSSCK(prescaler) | SPI_CTAR_CSSCK(scaler); + break; + case kDSPI_LastSckToPcs: + base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PASC_MASK) & (~SPI_CTAR_ASC_MASK)) | + SPI_CTAR_PASC(prescaler) | SPI_CTAR_ASC(scaler); + break; + case kDSPI_BetweenTransfer: + base->CTAR[whichCtar] = (base->CTAR[whichCtar] & (~SPI_CTAR_PDT_MASK) & (~SPI_CTAR_DT_MASK)) | + SPI_CTAR_PDT(prescaler) | SPI_CTAR_DT(scaler); + break; + default: + break; + } + } +} + +uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, + dspi_ctar_selection_t whichCtar, + dspi_delay_type_t whichDelay, + uint32_t srcClock_Hz, + uint32_t delayTimeInNanoSec) +{ + /* for master mode configuration, if slave mode detected, return 0 */ + if (!DSPI_IsMaster(base)) + { + return 0; + } + + uint32_t prescaler, bestPrescaler; + uint32_t scaler, bestScaler; + uint32_t realDelay, bestDelay; + uint32_t diff, min_diff; + uint32_t initialDelayNanoSec; + + /* find combination of prescaler and scaler resulting in the delay closest to the + * requested value + */ + min_diff = 0xFFFFFFFFU; + /* Initialize prescaler and scaler to their max values to generate the max delay */ + bestPrescaler = 0x3; + bestScaler = 0xF; + bestDelay = (((1000000000U * 4) / srcClock_Hz) * s_delayPrescaler[bestPrescaler] * s_delayScaler[bestScaler]) / 4; + + /* First calculate the initial, default delay */ + initialDelayNanoSec = 1000000000U / srcClock_Hz * 2; + + /* If the initial, default delay is already greater than the desired delay, then + * set the delays to their initial value (0) and return the delay. In other words, + * there is no way to decrease the delay value further. + */ + if (initialDelayNanoSec >= delayTimeInNanoSec) + { + DSPI_MasterSetDelayScaler(base, whichCtar, 0, 0, whichDelay); + return initialDelayNanoSec; + } + + /* In all for loops, if min_diff = 0, the exit for loop */ + for (prescaler = 0; (prescaler < 4) && min_diff; prescaler++) + { + for (scaler = 0; (scaler < 16) && min_diff; scaler++) + { + realDelay = ((4000000000U / srcClock_Hz) * s_delayPrescaler[prescaler] * s_delayScaler[scaler]) / 4; + + /* calculate the delay difference based on the conditional statement + * that states that the calculated delay must not be less then the desired delay + */ + if (realDelay >= delayTimeInNanoSec) + { + diff = realDelay - delayTimeInNanoSec; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestPrescaler = prescaler; + bestScaler = scaler; + bestDelay = realDelay; + } + } + } + } + + /* write the best dbr, prescalar, and baud rate scalar to the CTAR */ + DSPI_MasterSetDelayScaler(base, whichCtar, bestPrescaler, bestScaler, whichDelay); + + /* return the actual calculated baud rate */ + return bestDelay; +} + +void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command) +{ + assert(command); + + command->isPcsContinuous = false; + command->whichCtar = kDSPI_Ctar0; + command->whichPcs = kDSPI_Pcs0; + command->isEndOfQueue = false; + command->clearTransferCount = false; +} + +void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data) +{ + assert(command); + + /* First, clear Transmit Complete Flag (TCF) */ + DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | + SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | + SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data); + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + /* Wait till TCF sets */ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) + { + } +} + +void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data) +{ + /* First, clear Transmit Complete Flag (TCF) */ + DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + base->PUSHR = data; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + /* Wait till TCF sets */ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) + { + } +} + +void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data) +{ + /* First, clear Transmit Complete Flag (TCF) */ + DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag); + + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + base->PUSHR_SLAVE = data; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + /* Wait till TCF sets */ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxCompleteFlag)) + { + } +} + +void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask) +{ + if (mask & SPI_RSER_TFFF_RE_MASK) + { + base->RSER &= ~SPI_RSER_TFFF_DIRS_MASK; + } + if (mask & SPI_RSER_RFDF_RE_MASK) + { + base->RSER &= ~SPI_RSER_RFDF_DIRS_MASK; + } + base->RSER |= mask; +} + +/*Transactional APIs -- Master*/ + +void DSPI_MasterTransferCreateHandle(SPI_Type *base, + dspi_master_handle_t *handle, + dspi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + g_dspiHandle[DSPI_GetInstance(base)] = handle; + + handle->callback = callback; + handle->userData = userData; +} + +status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer) +{ + assert(transfer); + + uint16_t wordToSend = 0; + uint16_t wordReceived = 0; + uint8_t dummyData = DSPI_DUMMY_DATA; + uint8_t bitsPerFrame; + + uint32_t command; + uint32_t lastCommand; + + uint8_t *txData; + uint8_t *rxData; + uint32_t remainingSendByteCount; + uint32_t remainingReceiveByteCount; + + uint32_t fifoSize; + dspi_command_data_config_t commandStruct; + + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + DSPI_StopTransfer(base); + DSPI_DisableInterrupts(base, kDSPI_AllInterruptEnable); + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + /*Calculate the command and lastCommand*/ + commandStruct.whichPcs = + (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); + commandStruct.isEndOfQueue = false; + commandStruct.clearTransferCount = false; + commandStruct.whichCtar = + (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous); + + command = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + commandStruct.isEndOfQueue = true; + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer); + lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + /*Calculate the bitsPerFrame*/ + bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1; + + txData = transfer->txData; + rxData = transfer->rxData; + remainingSendByteCount = transfer->dataSize; + remainingReceiveByteCount = transfer->dataSize; + + if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK)) + { + fifoSize = 1; + } + else + { + fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); + } + + DSPI_StartTransfer(base); + + if (bitsPerFrame <= 8) + { + while (remainingSendByteCount > 0) + { + if (remainingSendByteCount == 1) + { + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + if (txData != NULL) + { + base->PUSHR = (*txData) | (lastCommand); + txData++; + } + else + { + base->PUSHR = (lastCommand) | (dummyData); + } + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + remainingSendByteCount--; + + while (remainingReceiveByteCount > 0) + { + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + if (rxData != NULL) + { + /* Read data from POPR*/ + *(rxData) = DSPI_ReadData(base); + rxData++; + } + else + { + DSPI_ReadData(base); + } + remainingReceiveByteCount--; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + } + else + { + /*Wait until Tx Fifo is not full*/ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + if (txData != NULL) + { + base->PUSHR = command | (uint16_t)(*txData); + txData++; + } + else + { + base->PUSHR = command | dummyData; + } + remainingSendByteCount--; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + while ((remainingReceiveByteCount - remainingSendByteCount) >= fifoSize) + { + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + if (rxData != NULL) + { + *(rxData) = DSPI_ReadData(base); + rxData++; + } + else + { + DSPI_ReadData(base); + } + remainingReceiveByteCount--; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + } + } + } + else + { + while (remainingSendByteCount > 0) + { + if (remainingSendByteCount <= 2) + { + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + if (txData != NULL) + { + wordToSend = *(txData); + ++txData; + + if (remainingSendByteCount > 1) + { + wordToSend |= (unsigned)(*(txData)) << 8U; + ++txData; + } + } + else + { + wordToSend = dummyData; + } + + base->PUSHR = lastCommand | wordToSend; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + remainingSendByteCount = 0; + + while (remainingReceiveByteCount > 0) + { + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + + if (remainingReceiveByteCount != 1) + { + if (rxData != NULL) + { + *(rxData) = wordReceived; + ++rxData; + *(rxData) = wordReceived >> 8; + ++rxData; + } + remainingReceiveByteCount -= 2; + } + else + { + if (rxData != NULL) + { + *(rxData) = wordReceived; + ++rxData; + } + remainingReceiveByteCount--; + } + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + } + else + { + /*Wait until Tx Fifo is not full*/ + while (!(DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } + + if (txData != NULL) + { + wordToSend = *(txData); + ++txData; + wordToSend |= (unsigned)(*(txData)) << 8U; + ++txData; + } + else + { + wordToSend = dummyData; + } + base->PUSHR = command | wordToSend; + remainingSendByteCount -= 2; + + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + while (((remainingReceiveByteCount - remainingSendByteCount) / 2) >= fifoSize) + { + if (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + + if (rxData != NULL) + { + *rxData = wordReceived; + ++rxData; + *rxData = wordReceived >> 8; + ++rxData; + } + remainingReceiveByteCount -= 2; + + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + } + } + } + } + } + + return kStatus_Success; +} + +static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + dspi_command_data_config_t commandStruct; + + DSPI_StopTransfer(base); + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + commandStruct.whichPcs = + (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); + commandStruct.isEndOfQueue = false; + commandStruct.clearTransferCount = false; + commandStruct.whichCtar = + (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous); + handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + commandStruct.isEndOfQueue = true; + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer); + handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1; + + if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK)) + { + handle->fifoSize = 1; + } + else + { + handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); + } + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->remainingSendByteCount = transfer->dataSize; + handle->remainingReceiveByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; +} + +status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kDSPI_Busy) + { + return kStatus_DSPI_Busy; + } + + handle->state = kDSPI_Busy; + + DSPI_MasterTransferPrepare(base, handle, transfer); + DSPI_StartTransfer(base); + + /* Enable the NVIC for DSPI peripheral. */ + EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); + + DSPI_MasterTransferFillUpTxFifo(base, handle); + + /* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt + * Since SPI is a synchronous interface, we only need to enable the RX interrupt. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + s_dspiMasterIsr = DSPI_MasterTransferHandleIRQ; + + DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable); + + return kStatus_Success; +} + +status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kDSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->totalByteCount - handle->remainingReceiveByteCount; + return kStatus_Success; +} + +static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt requests*/ + DSPI_DisableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable); + + status_t status = 0; + if (handle->state == kDSPI_Error) + { + status = kStatus_DSPI_Error; + } + else + { + status = kStatus_Success; + } + + handle->state = kDSPI_Idle; + + if (handle->callback) + { + handle->callback(base, handle, status, handle->userData); + } +} + +static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle) +{ + assert(handle); + + uint16_t wordToSend = 0; + uint8_t dummyData = DSPI_DUMMY_DATA; + + /* If bits/frame is greater than one byte */ + if (handle->bitsPerFrame > 8) + { + /* Fill the fifo until it is full or until the send word count is 0 or until the difference + * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth. + * The reason for checking the difference is to ensure we only send as much as the + * RX FIFO can receive. + * For this case where bitsPerFrame > 8, each entry in the FIFO contains 2 bytes of the + * send data, hence the difference between the remainingReceiveByteCount and + * remainingSendByteCount must be divided by 2 to convert this difference into a + * 16-bit (2 byte) value. + */ + while ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) && + ((handle->remainingReceiveByteCount - handle->remainingSendByteCount) / 2 < handle->fifoSize)) + { + if (handle->remainingSendByteCount <= 2) + { + if (handle->txData) + { + if (handle->remainingSendByteCount == 1) + { + wordToSend = *(handle->txData); + } + else + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data byte */ + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + } + } + else + { + wordToSend = dummyData; + } + handle->remainingSendByteCount = 0; + base->PUSHR = handle->lastCommand | wordToSend; + } + /* For all words except the last word */ + else + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data byte */ + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + ++handle->txData; /* increment to next data byte */ + } + else + { + wordToSend = dummyData; + } + handle->remainingSendByteCount -= 2; /* decrement remainingSendByteCount by 2 */ + base->PUSHR = handle->command | wordToSend; + } + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + /* exit loop if send count is zero, else update local variables for next loop */ + if (handle->remainingSendByteCount == 0) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + /* Optimized for bits/frame less than or equal to one byte. */ + else + { + /* Fill the fifo until it is full or until the send word count is 0 or until the difference + * between the remainingReceiveByteCount and remainingSendByteCount equals the FIFO depth. + * The reason for checking the difference is to ensure we only send as much as the + * RX FIFO can receive. + */ + while ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) && + ((handle->remainingReceiveByteCount - handle->remainingSendByteCount) < handle->fifoSize)) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; + } + else + { + wordToSend = dummyData; + } + + if (handle->remainingSendByteCount == 1) + { + base->PUSHR = handle->lastCommand | wordToSend; + } + else + { + base->PUSHR = handle->command | wordToSend; + } + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + --handle->remainingSendByteCount; + + /* exit loop if send count is zero, else update local variables for next loop */ + if (handle->remainingSendByteCount == 0) + { + break; + } + } + } +} + +void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle) +{ + assert(handle); + + DSPI_StopTransfer(base); + + /* Disable interrupt requests*/ + DSPI_DisableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable); + + handle->state = kDSPI_Idle; +} + +void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle) +{ + assert(handle); + + /* RECEIVE IRQ handler: Check read buffer only if there are remaining bytes to read. */ + if (handle->remainingReceiveByteCount) + { + /* Check read buffer.*/ + uint16_t wordReceived; /* Maximum supported data bit length in master mode is 16-bits */ + + /* If bits/frame is greater than one byte */ + if (handle->bitsPerFrame > 8) + { + while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + /* clear the rx fifo drain request, needed for non-DMA applications as this flag + * will remain set even if the rx fifo is empty. By manually clearing this flag, it + * either remain clear if no more data is in the fifo, or it will set if there is + * more data in the fifo. + */ + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + + /* Store read bytes into rx buffer only if a buffer pointer was provided */ + if (handle->rxData) + { + /* For the last word received, if there is an extra byte due to the odd transfer + * byte count, only save the the last byte and discard the upper byte + */ + if (handle->remainingReceiveByteCount == 1) + { + *handle->rxData = wordReceived; /* Write first data byte */ + --handle->remainingReceiveByteCount; + } + else + { + *handle->rxData = wordReceived; /* Write first data byte */ + ++handle->rxData; /* increment to next data byte */ + *handle->rxData = wordReceived >> 8; /* Write second data byte */ + ++handle->rxData; /* increment to next data byte */ + handle->remainingReceiveByteCount -= 2; + } + } + else + { + if (handle->remainingReceiveByteCount == 1) + { + --handle->remainingReceiveByteCount; + } + else + { + handle->remainingReceiveByteCount -= 2; + } + } + if (handle->remainingReceiveByteCount == 0) + { + break; + } + } /* End of RX FIFO drain while loop */ + } + /* Optimized for bits/frame less than or equal to one byte. */ + else + { + while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + wordReceived = DSPI_ReadData(base); + /* clear the rx fifo drain request, needed for non-DMA applications as this flag + * will remain set even if the rx fifo is empty. By manually clearing this flag, it + * either remain clear if no more data is in the fifo, or it will set if there is + * more data in the fifo. + */ + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + + /* Store read bytes into rx buffer only if a buffer pointer was provided */ + if (handle->rxData) + { + *handle->rxData = wordReceived; + ++handle->rxData; + } + + --handle->remainingReceiveByteCount; + + if (handle->remainingReceiveByteCount == 0) + { + break; + } + } /* End of RX FIFO drain while loop */ + } + } + + /* Check write buffer. We always have to send a word in order to keep the transfer + * moving. So if the caller didn't provide a send buffer, we just send a zero. + */ + if (handle->remainingSendByteCount) + { + DSPI_MasterTransferFillUpTxFifo(base, handle); + } + + /* Check if we're done with this transfer.*/ + if ((handle->remainingSendByteCount == 0) && (handle->remainingReceiveByteCount == 0)) + { + /* Complete the transfer and disable the interrupts */ + DSPI_MasterTransferComplete(base, handle); + } +} + +/*Transactional APIs -- Slave*/ +void DSPI_SlaveTransferCreateHandle(SPI_Type *base, + dspi_slave_handle_t *handle, + dspi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + g_dspiHandle[DSPI_GetInstance(base)] = handle; + + handle->callback = callback; + handle->userData = userData; +} + +status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + /* If receive length is zero */ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + /* If both send buffer and receive buffer is null */ + if ((!(transfer->txData)) && (!(transfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kDSPI_Busy) + { + return kStatus_DSPI_Busy; + } + handle->state = kDSPI_Busy; + + /* Enable the NVIC for DSPI peripheral. */ + EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]); + + /* Store transfer information */ + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->remainingSendByteCount = transfer->dataSize; + handle->remainingReceiveByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + handle->errorCount = 0; + + uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT; + handle->bitsPerFrame = + (((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1; + + DSPI_StopTransfer(base); + + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + DSPI_StartTransfer(base); + + /* Prepare data to transmit */ + DSPI_SlaveTransferFillUpTxFifo(base, handle); + + s_dspiSlaveIsr = DSPI_SlaveTransferHandleIRQ; + + /* Enable RX FIFO drain request, the slave only use this interrupt */ + DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable); + + if (handle->rxData) + { + /* RX FIFO overflow request enable */ + DSPI_EnableInterrupts(base, kDSPI_RxFifoOverflowInterruptEnable); + } + if (handle->txData) + { + /* TX FIFO underflow request enable */ + DSPI_EnableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable); + } + + return kStatus_Success; +} + +status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kDSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->totalByteCount - handle->remainingReceiveByteCount; + return kStatus_Success; +} + +static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle) +{ + assert(handle); + + uint16_t transmitData = 0; + uint8_t dummyPattern = DSPI_DUMMY_DATA; + + /* Service the transmitter, if transmit buffer provided, transmit the data, + * else transmit dummy pattern + */ + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + /* Transmit data */ + if (handle->remainingSendByteCount > 0) + { + /* Have data to transmit, update the transmit data and push to FIFO */ + if (handle->bitsPerFrame <= 8) + { + /* bits/frame is 1 byte */ + if (handle->txData) + { + /* Update transmit data and transmit pointer */ + transmitData = *handle->txData; + handle->txData++; + } + else + { + transmitData = dummyPattern; + } + + /* Decrease remaining dataSize */ + --handle->remainingSendByteCount; + } + /* bits/frame is 2 bytes */ + else + { + /* With multibytes per frame transmission, the transmit frame contains data from + * transmit buffer until sent dataSize matches user request. Other bytes will set to + * dummy pattern value. + */ + if (handle->txData) + { + /* Update first byte of transmit data and transmit pointer */ + transmitData = *handle->txData; + handle->txData++; + + if (handle->remainingSendByteCount == 1) + { + /* Decrease remaining dataSize */ + --handle->remainingSendByteCount; + /* Update second byte of transmit data to second byte of dummy pattern */ + transmitData = transmitData | (uint16_t)(((uint16_t)dummyPattern) << 8); + } + else + { + /* Update second byte of transmit data and transmit pointer */ + transmitData = transmitData | (uint16_t)((uint16_t)(*handle->txData) << 8); + handle->txData++; + handle->remainingSendByteCount -= 2; + } + } + else + { + if (handle->remainingSendByteCount == 1) + { + --handle->remainingSendByteCount; + } + else + { + handle->remainingSendByteCount -= 2; + } + transmitData = (uint16_t)((uint16_t)(dummyPattern) << 8) | dummyPattern; + } + } + } + else + { + break; + } + + /* Write the data to the DSPI data register */ + base->PUSHR_SLAVE = transmitData; + + /* Try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + } +} + +static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt requests */ + DSPI_DisableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable | + kDSPI_RxFifoOverflowInterruptEnable | kDSPI_RxFifoDrainRequestInterruptEnable); + + /* The transfer is complete. */ + handle->txData = NULL; + handle->rxData = NULL; + handle->remainingReceiveByteCount = 0; + handle->remainingSendByteCount = 0; + + status_t status = 0; + if (handle->state == kDSPI_Error) + { + status = kStatus_DSPI_Error; + } + else + { + status = kStatus_Success; + } + + handle->state = kDSPI_Idle; + + if (handle->callback) + { + handle->callback(base, handle, status, handle->userData); + } +} + +void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle) +{ + assert(handle); + + DSPI_StopTransfer(base); + + /* Disable interrupt requests */ + DSPI_DisableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable | kDSPI_TxFifoFillRequestInterruptEnable | + kDSPI_RxFifoOverflowInterruptEnable | kDSPI_RxFifoDrainRequestInterruptEnable); + + handle->state = kDSPI_Idle; + handle->remainingSendByteCount = 0; + handle->remainingReceiveByteCount = 0; +} + +void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle) +{ + assert(handle); + + uint8_t dummyPattern = DSPI_DUMMY_DATA; + uint32_t dataReceived; + uint32_t dataSend = 0; + + /* Because SPI protocol is synchronous, the number of bytes that that slave received from the + * master is the actual number of bytes that the slave transmitted to the master. So we only + * monitor the received dataSize to know when the transfer is complete. + */ + if (handle->remainingReceiveByteCount > 0) + { + while (DSPI_GetStatusFlags(base) & kDSPI_RxFifoDrainRequestFlag) + { + /* Have received data in the buffer. */ + dataReceived = base->POPR; + /*Clear the rx fifo drain request, needed for non-DMA applications as this flag + * will remain set even if the rx fifo is empty. By manually clearing this flag, it + * either remain clear if no more data is in the fifo, or it will set if there is + * more data in the fifo. + */ + DSPI_ClearStatusFlags(base, kDSPI_RxFifoDrainRequestFlag); + + /* If bits/frame is one byte */ + if (handle->bitsPerFrame <= 8) + { + if (handle->rxData) + { + /* Receive buffer is not null, store data into it */ + *handle->rxData = dataReceived; + ++handle->rxData; + } + /* Descrease remaining receive byte count */ + --handle->remainingReceiveByteCount; + + if (handle->remainingSendByteCount > 0) + { + if (handle->txData) + { + dataSend = *handle->txData; + ++handle->txData; + } + else + { + dataSend = dummyPattern; + } + + --handle->remainingSendByteCount; + /* Write the data to the DSPI data register */ + base->PUSHR_SLAVE = dataSend; + } + } + else /* If bits/frame is 2 bytes */ + { + /* With multibytes frame receiving, we only receive till the received dataSize + * matches user request. Other bytes will be ignored. + */ + if (handle->rxData) + { + /* Receive buffer is not null, store first byte into it */ + *handle->rxData = dataReceived; + ++handle->rxData; + + if (handle->remainingReceiveByteCount == 1) + { + /* Decrease remaining receive byte count */ + --handle->remainingReceiveByteCount; + } + else + { + /* Receive buffer is not null, store second byte into it */ + *handle->rxData = dataReceived >> 8; + ++handle->rxData; + handle->remainingReceiveByteCount -= 2; + } + } + /* If no handle->rxData*/ + else + { + if (handle->remainingReceiveByteCount == 1) + { + /* Decrease remaining receive byte count */ + --handle->remainingReceiveByteCount; + } + else + { + handle->remainingReceiveByteCount -= 2; + } + } + + if (handle->remainingSendByteCount > 0) + { + if (handle->txData) + { + dataSend = *handle->txData; + ++handle->txData; + + if (handle->remainingSendByteCount == 1) + { + --handle->remainingSendByteCount; + dataSend |= (uint16_t)((uint16_t)(dummyPattern) << 8); + } + else + { + dataSend |= (uint32_t)(*handle->txData) << 8; + ++handle->txData; + handle->remainingSendByteCount -= 2; + } + } + /* If no handle->txData*/ + else + { + if (handle->remainingSendByteCount == 1) + { + --handle->remainingSendByteCount; + } + else + { + handle->remainingSendByteCount -= 2; + } + dataSend = (uint16_t)((uint16_t)(dummyPattern) << 8) | dummyPattern; + } + /* Write the data to the DSPI data register */ + base->PUSHR_SLAVE = dataSend; + } + } + /* Try to clear TFFF by writing a one to it; it will not clear if TX FIFO not full */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + if (handle->remainingReceiveByteCount == 0) + { + break; + } + } + } + /* Check if remaining receive byte count matches user request */ + if ((handle->remainingReceiveByteCount == 0) || (handle->state == kDSPI_Error)) + { + /* Other cases, stop the transfer. */ + DSPI_SlaveTransferComplete(base, handle); + return; + } + + /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */ + if ((DSPI_GetStatusFlags(base) & kDSPI_TxFifoUnderflowFlag) && (base->RSER & SPI_RSER_TFUF_RE_MASK)) + { + DSPI_ClearStatusFlags(base, kDSPI_TxFifoUnderflowFlag); + /* Change state to error and clear flag */ + if (handle->txData) + { + handle->state = kDSPI_Error; + } + handle->errorCount++; + } + /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ + if ((DSPI_GetStatusFlags(base) & kDSPI_RxFifoOverflowFlag) && (base->RSER & SPI_RSER_RFOF_RE_MASK)) + { + DSPI_ClearStatusFlags(base, kDSPI_RxFifoOverflowFlag); + /* Change state to error and clear flag */ + if (handle->txData) + { + handle->state = kDSPI_Error; + } + handle->errorCount++; + } +} + +static void DSPI_CommonIRQHandler(SPI_Type *base, void *param) +{ + if (DSPI_IsMaster(base)) + { + s_dspiMasterIsr(base, (dspi_master_handle_t *)param); + } + else + { + s_dspiSlaveIsr(base, (dspi_slave_handle_t *)param); + } +} + +#if defined(SPI0) +void SPI0_DriverIRQHandler(void) +{ + assert(g_dspiHandle[0]); + DSPI_CommonIRQHandler(SPI0, g_dspiHandle[0]); +} +#endif + +#if defined(SPI1) +void SPI1_DriverIRQHandler(void) +{ + assert(g_dspiHandle[1]); + DSPI_CommonIRQHandler(SPI1, g_dspiHandle[1]); +} +#endif + +#if defined(SPI2) +void SPI2_DriverIRQHandler(void) +{ + assert(g_dspiHandle[2]); + DSPI_CommonIRQHandler(SPI2, g_dspiHandle[2]); +} +#endif + +#if defined(SPI3) +void SPI3_DriverIRQHandler(void) +{ + assert(g_dspiHandle[3]); + DSPI_CommonIRQHandler(SPI3, g_dspiHandle[3]); +} +#endif + +#if defined(SPI4) +void SPI4_DriverIRQHandler(void) +{ + assert(g_dspiHandle[4]); + DSPI_CommonIRQHandler(SPI4, g_dspiHandle[4]); +} +#endif + +#if defined(SPI5) +void SPI5_DriverIRQHandler(void) +{ + assert(g_dspiHandle[5]); + DSPI_CommonIRQHandler(SPI5, g_dspiHandle[5]); +} +#endif + +#if (FSL_FEATURE_SOC_DSPI_COUNT > 6) +#error "Should write the SPIx_DriverIRQHandler function that instance greater than 5 !" +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dspi.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dspi.h new file mode 100644 index 00000000000..5dd96afcbe0 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dspi.h @@ -0,0 +1,1180 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_DSPI_H_ +#define _FSL_DSPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dspi_driver + * @{ + */ + + +/********************************************************************************************************************** + * Definitions + *********************************************************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DSPI driver version 2.1.4. */ +#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*@}*/ + +#ifndef DSPI_DUMMY_DATA +/*! @brief DSPI dummy data if there is no Tx data.*/ +#define DSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for Tx if there is no txData. */ +#endif + +/*! @brief Status for the DSPI driver.*/ +enum _dspi_status +{ + kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0), /*!< DSPI transfer is busy.*/ + kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1), /*!< DSPI driver error. */ + kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2), /*!< DSPI is idle.*/ + kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out of range. */ +}; + +/*! @brief DSPI status flags in SPIx_SR register.*/ +enum _dspi_flags +{ + kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK, /*!< Transfer Complete Flag. */ + kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK, /*!< End of Queue Flag.*/ + kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK, /*!< Transmit FIFO Underflow Flag.*/ + kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /*!< Transmit FIFO Fill Flag.*/ + kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK, /*!< Receive FIFO Overflow Flag.*/ + kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/ + kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK, /*!< The module is in Stopped/Running state.*/ + kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK | + SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All statuses above.*/ +}; + +/*! @brief DSPI interrupt source.*/ +enum _dspi_interrupt_enable +{ + kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK, /*!< TCF interrupt enable.*/ + kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK, /*!< EOQF interrupt enable.*/ + kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK, /*!< TFUF interrupt enable.*/ + kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /*!< TFFF interrupt enable, DMA disable.*/ + kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK, /*!< RFOF interrupt enable.*/ + kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /*!< RFDF interrupt enable, DMA disable.*/ + kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK | + SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK + /*!< All above interrupts enable.*/ +}; + +/*! @brief DSPI DMA source.*/ +enum _dspi_dma_enable +{ + kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DMA requests. + No Tx interrupt request. */ + kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK) /*!< RFDF flag generates DMA requests. + No Rx interrupt request. */ +}; + +/*! @brief DSPI master or slave mode configuration.*/ +typedef enum _dspi_master_slave_mode +{ + kDSPI_Master = 1U, /*!< DSPI peripheral operates in master mode.*/ + kDSPI_Slave = 0U /*!< DSPI peripheral operates in slave mode.*/ +} dspi_master_slave_mode_t; + +/*! + * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is valid + * only when the CPHA bit in the CTAR register is 0. + */ +typedef enum _dspi_master_sample_point +{ + kDSPI_SckToSin0Clock = 0U, /*!< 0 system clocks between SCK edge and SIN sample.*/ + kDSPI_SckToSin1Clock = 1U, /*!< 1 system clock between SCK edge and SIN sample.*/ + kDSPI_SckToSin2Clock = 2U /*!< 2 system clocks between SCK edge and SIN sample.*/ +} dspi_master_sample_point_t; + +/*! @brief DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure).*/ +typedef enum _dspi_which_pcs_config +{ + kDSPI_Pcs0 = 1U << 0, /*!< Pcs[0] */ + kDSPI_Pcs1 = 1U << 1, /*!< Pcs[1] */ + kDSPI_Pcs2 = 1U << 2, /*!< Pcs[2] */ + kDSPI_Pcs3 = 1U << 3, /*!< Pcs[3] */ + kDSPI_Pcs4 = 1U << 4, /*!< Pcs[4] */ + kDSPI_Pcs5 = 1U << 5 /*!< Pcs[5] */ +} dspi_which_pcs_t; + +/*! @brief DSPI Peripheral Chip Select (Pcs) Polarity configuration.*/ +typedef enum _dspi_pcs_polarity_config +{ + kDSPI_PcsActiveHigh = 0U, /*!< Pcs Active High (idles low). */ + kDSPI_PcsActiveLow = 1U /*!< Pcs Active Low (idles high). */ +} dspi_pcs_polarity_config_t; + +/*! @brief DSPI Peripheral Chip Select (Pcs) Polarity.*/ +enum _dspi_pcs_polarity +{ + kDSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ + kDSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ + kDSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ + kDSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ + kDSPI_Pcs4ActiveLow = 1U << 4, /*!< Pcs4 Active Low (idles high). */ + kDSPI_Pcs5ActiveLow = 1U << 5, /*!< Pcs5 Active Low (idles high). */ + kDSPI_PcsAllActiveLow = 0xFFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ +}; + +/*! @brief DSPI clock polarity configuration for a given CTAR.*/ +typedef enum _dspi_clock_polarity +{ + kDSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high DSPI clock (idles low).*/ + kDSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low DSPI clock (idles high).*/ +} dspi_clock_polarity_t; + +/*! @brief DSPI clock phase configuration for a given CTAR.*/ +typedef enum _dspi_clock_phase +{ + kDSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the + following edge.*/ + kDSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the + following edge.*/ +} dspi_clock_phase_t; + +/*! @brief DSPI data shifter direction options for a given CTAR.*/ +typedef enum _dspi_shift_direction +{ + kDSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ + kDSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. + Shifting out of LSB is not supported for slave */ +} dspi_shift_direction_t; + +/*! @brief DSPI delay type selection.*/ +typedef enum _dspi_delay_type +{ + kDSPI_PcsToSck = 1U, /*!< Pcs-to-SCK delay. */ + kDSPI_LastSckToPcs, /*!< The last SCK edge to Pcs delay. */ + kDSPI_BetweenTransfer /*!< Delay between transfers. */ +} dspi_delay_type_t; + +/*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection.*/ +typedef enum _dspi_ctar_selection +{ + kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode; note that CTAR0 and CTAR0_SLAVE are the + same register address. */ + kDSPI_Ctar1 = 1U, /*!< CTAR1 selection option for master mode only. */ + kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only; note that some devices do not support CTAR2. */ + kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only; note that some devices do not support CTAR3. */ + kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only; note that some devices do not support CTAR4. */ + kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only; note that some devices do not support CTAR5. */ + kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only; note that some devices do not support CTAR6. */ + kDSPI_Ctar7 = 7U /*!< CTAR7 selection option for master mode only; note that some devices do not support CTAR7. */ +} dspi_ctar_selection_t; + +#define DSPI_MASTER_CTAR_SHIFT (0U) /*!< DSPI master CTAR shift macro; used internally. */ +#define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro; used internally. */ +#define DSPI_MASTER_PCS_SHIFT (4U) /*!< DSPI master PCS shift macro; used internally. */ +#define DSPI_MASTER_PCS_MASK (0xF0U) /*!< DSPI master PCS mask macro; used internally. */ +/*! @brief Use this enumeration for the DSPI master transfer configFlags. */ +enum _dspi_transfer_config_flag_for_master +{ + kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */ + kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR1 setting. */ + kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR2 setting. */ + kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR3 setting. */ + kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR4 setting. */ + kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR5 setting. */ + kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR6 setting. */ + kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR7 setting. */ + + kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS0 signal. */ + kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS1 signal. */ + kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS2 signal.*/ + kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS3 signal. */ + kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */ + kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */ + + kDSPI_MasterPcsContinuous = 1U << 20, /*!< Indicates whether the PCS signal is continuous. */ + kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/ +}; + +#define DSPI_SLAVE_CTAR_SHIFT (0U) /*!< DSPI slave CTAR shift macro; used internally. */ +#define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro; used internally. */ +/*! @brief Use this enumeration for the DSPI slave transfer configFlags. */ +enum _dspi_transfer_config_flag_for_slave +{ + kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /*!< DSPI slave transfer use CTAR0 setting. */ + /*!< DSPI slave can only use PCS0. */ +}; + +/*! @brief DSPI transfer state, which is used for DSPI transactional API state machine. */ +enum _dspi_transfer_state +{ + kDSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ + kDSPI_Busy, /*!< Transfer queue is not finished. */ + kDSPI_Error /*!< Transfer error. */ +}; + +/*! @brief DSPI master command date configuration used for the SPIx_PUSHR.*/ +typedef struct _dspi_command_data_config +{ + bool isPcsContinuous; /*!< Option to enable the continuous assertion of the chip select between transfers.*/ + dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes + Register (CTAR) to use for CTAS.*/ + dspi_which_pcs_t whichPcs; /*!< The desired PCS signal to use for the data transfer.*/ + bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue.*/ + bool clearTransferCount; /*!< Clears the SPI Transfer Counter (SPI_TCNT) before transmission starts.*/ +} dspi_command_data_config_t; + +/*! @brief DSPI master ctar configuration structure.*/ +typedef struct _dspi_master_ctar_config +{ + uint32_t baudRate; /*!< Baud Rate for DSPI. */ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/ + dspi_clock_polarity_t cpol; /*!< Clock polarity. */ + dspi_clock_phase_t cpha; /*!< Clock phase. */ + dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum + delay. It also sets the boundary value if out of range.*/ + uint32_t lastSckToPcsDelayInNanoSec; /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the + minimum delay. It also sets the boundary value if out of range.*/ + + uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time in nanoseconds; setting to 0 sets the minimum + delay. It also sets the boundary value if out of range.*/ +} dspi_master_ctar_config_t; + +/*! @brief DSPI master configuration structure.*/ +typedef struct _dspi_master_config +{ + dspi_ctar_selection_t whichCtar; /*!< The desired CTAR to use. */ + dspi_master_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */ + + dspi_which_pcs_t whichPcs; /*!< The desired Peripheral Chip Select (pcs). */ + dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< The desired PCS active high or low. */ + + bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only + supported for CPHA = 1.*/ + bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming + data is ignored and the data from the transfer that generated the overflow + is also ignored. If ROOE = 1, the incoming data is shifted to the + shift register. */ + + bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if true.*/ + dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer + Format. It's valid only when CPHA=0. */ +} dspi_master_config_t; + +/*! @brief DSPI slave ctar configuration structure.*/ +typedef struct _dspi_slave_ctar_config +{ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/ + dspi_clock_polarity_t cpol; /*!< Clock polarity. */ + dspi_clock_phase_t cpha; /*!< Clock phase. */ + /*!< Slave only supports MSB and does not support LSB.*/ +} dspi_slave_ctar_config_t; + +/*! @brief DSPI slave configuration structure.*/ +typedef struct _dspi_slave_config +{ + dspi_ctar_selection_t whichCtar; /*!< The desired CTAR to use. */ + dspi_slave_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */ + + bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only + supported for CPHA = 1.*/ + bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming + data is ignored and the data from the transfer that generated the overflow + is also ignored. If ROOE = 1, the incoming data is shifted to the + shift register. */ + bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if true.*/ + dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer + Format. It's valid only when CPHA=0. */ +} dspi_slave_config_t; + +/*! +* @brief Forward declaration of the _dspi_master_handle typedefs. +*/ +typedef struct _dspi_master_handle dspi_master_handle_t; + +/*! +* @brief Forward declaration of the _dspi_slave_handle typedefs. +*/ +typedef struct _dspi_slave_handle dspi_slave_handle_t; + +/*! + * @brief Completion callback function pointer type. + * + * @param base DSPI peripheral address. + * @param handle Pointer to the handle for the DSPI master. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*dspi_master_transfer_callback_t)(SPI_Type *base, + dspi_master_handle_t *handle, + status_t status, + void *userData); +/*! + * @brief Completion callback function pointer type. + * + * @param base DSPI peripheral address. + * @param handle Pointer to the handle for the DSPI slave. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*dspi_slave_transfer_callback_t)(SPI_Type *base, + dspi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief DSPI master/slave transfer structure.*/ +typedef struct _dspi_transfer +{ + uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + volatile size_t dataSize; /*!< Transfer bytes. */ + + uint32_t + configFlags; /*!< Transfer transfer configuration flags; set from _dspi_transfer_config_flag_for_master if the + transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer + is used for slave.*/ +} dspi_transfer_t; + +/*! @brief DSPI master transfer handle structure used for transactional API. */ +struct _dspi_master_handle +{ + uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */ + volatile uint32_t command; /*!< The desired data command. */ + volatile uint32_t lastCommand; /*!< The desired last data command. */ + + uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile bool isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal is active after the last frame transfer.*/ + volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/ + volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/ + size_t totalByteCount; /*!< A number of transfer bytes*/ + + volatile uint8_t state; /*!< DSPI transfer state, see _dspi_transfer_state.*/ + + dspi_master_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/*! @brief DSPI slave transfer handle structure used for the transactional API. */ +struct _dspi_slave_handle +{ + uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */ + volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/ + volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/ + size_t totalByteCount; /*!< A number of transfer bytes*/ + + volatile uint8_t state; /*!< DSPI transfer state.*/ + + volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ + + dspi_slave_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/********************************************************************************************************************** + * API + *********************************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the DSPI master. + * + * This function initializes the DSPI master configuration. This is an example use case. + * @code + * dspi_master_config_t masterConfig; + * masterConfig.whichCtar = kDSPI_Ctar0; + * masterConfig.ctarConfig.baudRate = 500000000U; + * masterConfig.ctarConfig.bitsPerFrame = 8; + * masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + * masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + * masterConfig.ctarConfig.direction = kDSPI_MsbFirst; + * masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; + * masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; + * masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; + * masterConfig.whichPcs = kDSPI_Pcs0; + * masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow; + * masterConfig.enableContinuousSCK = false; + * masterConfig.enableRxFifoOverWrite = false; + * masterConfig.enableModifiedTimingFormat = false; + * masterConfig.samplePoint = kDSPI_SckToSin0Clock; + * DSPI_MasterInit(base, &masterConfig, srcClock_Hz); + * @endcode + * + * @param base DSPI peripheral address. + * @param masterConfig Pointer to the structure dspi_master_config_t. + * @param srcClock_Hz Module source input clock in Hertz. + */ +void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Sets the dspi_master_config_t structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit(). + * Users may use the initialized structure unchanged in the DSPI_MasterInit() or modify the structure + * before calling the DSPI_MasterInit(). + * Example: + * @code + * dspi_master_config_t masterConfig; + * DSPI_MasterGetDefaultConfig(&masterConfig); + * @endcode + * @param masterConfig pointer to dspi_master_config_t structure + */ +void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig); + +/*! + * @brief DSPI slave configuration. + * + * This function initializes the DSPI slave configuration. This is an example use case. + * @code + * dspi_slave_config_t slaveConfig; + * slaveConfig->whichCtar = kDSPI_Ctar0; + * slaveConfig->ctarConfig.bitsPerFrame = 8; + * slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + * slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; + * slaveConfig->enableContinuousSCK = false; + * slaveConfig->enableRxFifoOverWrite = false; + * slaveConfig->enableModifiedTimingFormat = false; + * slaveConfig->samplePoint = kDSPI_SckToSin0Clock; + * DSPI_SlaveInit(base, &slaveConfig); + * @endcode + * + * @param base DSPI peripheral address. + * @param slaveConfig Pointer to the structure dspi_master_config_t. + */ +void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig); + +/*! + * @brief Sets the dspi_slave_config_t structure to a default value. + * + * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit(). + * Users may use the initialized structure unchanged in the DSPI_SlaveInit() or modify the structure + * before calling the DSPI_SlaveInit(). + * This is an example. + * @code + * dspi_slave_config_t slaveConfig; + * DSPI_SlaveGetDefaultConfig(&slaveConfig); + * @endcode + * @param slaveConfig Pointer to the dspi_slave_config_t structure. + */ +void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock. + * @param base DSPI peripheral address. + */ +void DSPI_Deinit(SPI_Type *base); + +/*! + * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0. + * + * @param base DSPI peripheral address. + * @param enable Pass true to enable module, false to disable module. + */ +static inline void DSPI_Enable(SPI_Type *base, bool enable) +{ + if (enable) + { + base->MCR &= ~SPI_MCR_MDIS_MASK; + } + else + { + base->MCR |= SPI_MCR_MDIS_MASK; + } +} + +/*! + *@} +*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the DSPI status flag state. + * @param base DSPI peripheral address. + * @return DSPI status (in SR register). + */ +static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base) +{ + return (base->SR); +} + +/*! + * @brief Clears the DSPI status flag. + * + * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the + * desired status bit to clear. The list of status bits is defined in the dspi_status_and_interrupt_request_t. The + * function uses these bit positions in its algorithm to clear the desired flag state. + * This is an example. + * @code + * DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag|kDSPI_EndOfQueueFlag); + * @endcode + * + * @param base DSPI peripheral address. + * @param statusFlags The status flag used from the type dspi_flags. + */ +static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags) +{ + base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ +} + +/*! + *@} +*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the DSPI interrupts. + * + * This function configures the various interrupt masks of the DSPI. The parameters are a base and an interrupt mask. + * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request. + * + * @code + * DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); + * @endcode + * + * @param base DSPI peripheral address. + * @param mask The interrupt mask; use the enum _dspi_interrupt_enable. + */ +void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask); + +/*! + * @brief Disables the DSPI interrupts. + * + * @code + * DSPI_DisableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); + * @endcode + * + * @param base DSPI peripheral address. + * @param mask The interrupt mask; use the enum _dspi_interrupt_enable. + */ +static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask) +{ + base->RSER &= ~mask; +} + +/*! + *@} +*/ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the DSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask. + * @code + * DSPI_EnableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable); + * @endcode + * + * @param base DSPI peripheral address. + * @param mask The interrupt mask; use the enum dspi_dma_enable. + */ +static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask) +{ + base->RSER |= mask; +} + +/*! + * @brief Disables the DSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask. + * @code + * SPI_DisableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable); + * @endcode + * + * @param base DSPI peripheral address. + * @param mask The interrupt mask; use the enum dspi_dma_enable. + */ +static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask) +{ + base->RSER &= ~mask; +} + +/*! + * @brief Gets the DSPI master PUSHR data register address for the DMA operation. + * + * This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation. + * + * @param base DSPI peripheral address. + * @return The DSPI master PUSHR data register address. + */ +static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base) +{ + return (uint32_t) & (base->PUSHR); +} + +/*! + * @brief Gets the DSPI slave PUSHR data register address for the DMA operation. + * + * This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation. + * + * @param base DSPI peripheral address. + * @return The DSPI slave PUSHR data register address. + */ +static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base) +{ + return (uint32_t) & (base->PUSHR_SLAVE); +} + +/*! + * @brief Gets the DSPI POPR data register address for the DMA operation. + * + * This function gets the DSPI POPR data register address as this value is needed for the DMA operation. + * + * @param base DSPI peripheral address. + * @return The DSPI POPR data register address. + */ +static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base) +{ + return (uint32_t) & (base->POPR); +} + +/*! + *@} +*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the DSPI for master or slave. + * + * @param base DSPI peripheral address. + * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t. + */ +static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode) +{ + base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) | SPI_MCR_MSTR(mode); +} + +/*! + * @brief Returns whether the DSPI module is in master mode. + * + * @param base DSPI peripheral address. + * @return Returns true if the module is in master mode or false if the module is in slave mode. + */ +static inline bool DSPI_IsMaster(SPI_Type *base) +{ + return (bool)((base->MCR) & SPI_MCR_MSTR_MASK); +} +/*! + * @brief Starts the DSPI transfers and clears HALT bit in MCR. + * + * This function sets the module to start data transfer in either master or slave mode. + * + * @param base DSPI peripheral address. + */ +static inline void DSPI_StartTransfer(SPI_Type *base) +{ + base->MCR &= ~SPI_MCR_HALT_MASK; +} +/*! + * @brief Stops DSPI transfers and sets the HALT bit in MCR. + * + * This function stops data transfers in either master or slave modes. + * + * @param base DSPI peripheral address. + */ +static inline void DSPI_StopTransfer(SPI_Type *base) +{ + base->MCR |= SPI_MCR_HALT_MASK; +} + +/*! + * @brief Enables or disables the DSPI FIFOs. + * + * This function allows the caller to disable/enable the Tx and Rx FIFOs independently. + * Note that to disable, pass in a logic 0 (false) for the particular FIFO configuration. To enable, + * pass in a logic 1 (true). + * + * @param base DSPI peripheral address. + * @param enableTxFifo Disables (false) the TX FIFO; Otherwise, enables (true) the TX FIFO + * @param enableRxFifo Disables (false) the RX FIFO; Otherwise, enables (true) the RX FIFO + */ +static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo) +{ + base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK))) | SPI_MCR_DIS_TXF(!enableTxFifo) | + SPI_MCR_DIS_RXF(!enableRxFifo); +} + +/*! + * @brief Flushes the DSPI FIFOs. + * + * @param base DSPI peripheral address. + * @param flushTxFifo Flushes (true) the Tx FIFO; Otherwise, does not flush (false) the Tx FIFO + * @param flushRxFifo Flushes (true) the Rx FIFO; Otherwise, does not flush (false) the Rx FIFO + */ +static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo) +{ + base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK))) | SPI_MCR_CLR_TXF(flushTxFifo) | + SPI_MCR_CLR_RXF(flushRxFifo); +} + +/*! + * @brief Configures the DSPI peripheral chip select polarity simultaneously. + * For example, PCS0 and PCS1 are set to active low and other PCS is set to active high. Note that the number of + * PCSs is specific to the device. + * @code + * DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow | kDSPI_Pcs1ActiveLow); + @endcode + * @param base DSPI peripheral address. + * @param mask The PCS polarity mask; use the enum _dspi_pcs_polarity. + */ +static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask) +{ + base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) | SPI_MCR_PCSIS(mask); +} + +/*! + * @brief Sets the DSPI baud rate in bits per second. + * + * This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without + * exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the + * caller also provide the frequency of the module source clock (in Hertz). + * + * @param base DSPI peripheral address. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t + * @param baudRate_Bps The desired baud rate in bits per second + * @param srcClock_Hz Module source input clock in Hertz + * @return The actual calculated baud rate + */ +uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, + dspi_ctar_selection_t whichCtar, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz); + +/*! + * @brief Manually configures the delay prescaler and scaler for a particular CTAR. + * + * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar + * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT) and scalar (DT). + * + * These delay names are available in the type dspi_delay_type_t. + * + * The user passes the delay to the configuration along with the prescaler and scaler value. + * This allows the user to directly set the prescaler/scaler values if pre-calculated or + * to manually increment either value. + * + * @param base DSPI peripheral address. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. + * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3). + * @param scaler The scaler delay value (can be any integer between 0 to 15). + * @param whichDelay The desired delay to configure; must be of type dspi_delay_type_t + */ +void DSPI_MasterSetDelayScaler( + SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay); + +/*! + * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds. + * + * This function calculates the values for the following. + * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or + * After SCK delay pre-scalar (PASC) and scalar (ASC), or + * Delay after transfer pre-scalar (PDT) and scalar (DT). + * + * These delay names are available in the type dspi_delay_type_t. + * + * The user passes which delay to configure along with the desired delay value in nanoseconds. The function + * calculates the values needed for the prescaler and scaler. Note that returning the calculated delay as an exact + * delay match may not be possible. In this case, the closest match is calculated without going below the desired + * delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum + * supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay + * input. + * + * @param base DSPI peripheral address. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. + * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t + * @param srcClock_Hz Module source input clock in Hertz + * @param delayTimeInNanoSec The desired delay value in nanoseconds. + * @return The actual calculated delay value. + */ +uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, + dspi_ctar_selection_t whichCtar, + dspi_delay_type_t whichDelay, + uint32_t srcClock_Hz, + uint32_t delayTimeInNanoSec); + +/*! + * @brief Writes data into the data buffer for master mode. + * + * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion + * provides characteristics of the data, such as the optional continuous chip select + * operation between transfers, the desired Clock and Transfer Attributes register to use for the + * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current + * transfer is the last in the queue, and whether to clear the transfer count (normally needed when + * sending the first frame of a data packet). This is an example. + * @code + * dspi_command_data_config_t commandConfig; + * commandConfig.isPcsContinuous = true; + * commandConfig.whichCtar = kDSPICtar0; + * commandConfig.whichPcs = kDSPIPcs0; + * commandConfig.clearTransferCount = false; + * commandConfig.isEndOfQueue = false; + * DSPI_MasterWriteData(base, &commandConfig, dataWord); + @endcode + * + * @param base DSPI peripheral address. + * @param command Pointer to the command structure. + * @param data The data word to be sent. + */ +static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data) +{ + base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | + SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | + SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data); +} + +/*! + * @brief Sets the dspi_command_data_config_t structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx(). + * Users may use the initialized structure unchanged in the DSPI_MasterWrite_xx() or modify the structure + * before calling the DSPI_MasterWrite_xx(). + * This is an example. + * @code + * dspi_command_data_config_t command; + * DSPI_GetDefaultDataCommandConfig(&command); + * @endcode + * @param command Pointer to the dspi_command_data_config_t structure. + */ +void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command); + +/*! + * @brief Writes data into the data buffer master mode and waits till complete to return. + * + * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion + * provides characteristics of the data, such as the optional continuous chip select + * operation between transfers, the desired Clock and Transfer Attributes register to use for the + * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current + * transfer is the last in the queue, and whether to clear the transfer count (normally needed when + * sending the first frame of a data packet). This is an example. + * @code + * dspi_command_config_t commandConfig; + * commandConfig.isPcsContinuous = true; + * commandConfig.whichCtar = kDSPICtar0; + * commandConfig.whichPcs = kDSPIPcs1; + * commandConfig.clearTransferCount = false; + * commandConfig.isEndOfQueue = false; + * DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord); + * @endcode + * + * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be + * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol, + * the received data is available when the transmit completes. + * + * @param base DSPI peripheral address. + * @param command Pointer to the command structure. + * @param data The data word to be sent. + */ +void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data); + +/*! + * @brief Returns the DSPI command word formatted to the PUSHR data register bit field. + * + * This function allows the caller to pass in the data command structure and returns the command word formatted + * according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the + * desired data to send and use the function DSPI_HAL_WriteCommandDataMastermode or + * DSPI_HAL_WriteCommandDataMastermodeBlocking to write the entire 32-bit command data word to the PUSHR. This helps + * improve performance in cases where the command structure is constant. For example, the user calls this function + * before starting a transfer to generate the command word. When they are ready to transmit the data, they OR + * this formatted command word with the desired data to transmit. This process increases transmit performance when + * compared to calling send functions, such as DSPI_HAL_WriteDataMastermode, which format the command word each time a + * data word is to be sent. + * + * @param command Pointer to the command structure. + * @return The command word formatted to the PUSHR data register bit field. + */ +static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command) +{ + /* Format the 16-bit command word according to the PUSHR data register bit field*/ + return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | + SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | + SPI_PUSHR_CTCNT(command->clearTransferCount)); +} + +/*! + * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data + * buffer master mode and waits till complete to return. + * + * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total 32-bit word + * as the data to send. + * The command portion provides characteristics of the data, such as the optional continuous chip select operation + * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS + * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the + * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for + * appending this command with the data to send. This is an example: + * @code + * dataWord = <16-bit command> | <16-bit data>; + * DSPI_MasterWriteCommandDataBlocking(base, dataWord); + * @endcode + * + * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be + * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). + * Because the SPI is a synchronous protocol, the received data is available when the transmit completes. + * + * For a blocking polling transfer, see methods below. + * Option 1: +* uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command); +* uint32_t data0 = command_to_send | data_need_to_send_0; +* uint32_t data1 = command_to_send | data_need_to_send_1; +* uint32_t data2 = command_to_send | data_need_to_send_2; +* +* DSPI_MasterWriteCommandDataBlocking(base,data0); +* DSPI_MasterWriteCommandDataBlocking(base,data1); +* DSPI_MasterWriteCommandDataBlocking(base,data2); +* +* Option 2: +* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0); +* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1); +* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2); +* + * @param base DSPI peripheral address. + * @param data The data word (command and data combined) to be sent. + */ +void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data); + +/*! + * @brief Writes data into the data buffer in slave mode. + * + * In slave mode, up to 16-bit words may be written. + * + * @param base DSPI peripheral address. + * @param data The data to send. + */ +static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data) +{ + base->PUSHR_SLAVE = data; +} + +/*! + * @brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns. + * + * In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data + * into data register, and finally waits until the data is transmitted. + * + * @param base DSPI peripheral address. + * @param data The data to send. + */ +void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data); + +/*! + * @brief Reads data from the data buffer. + * + * @param base DSPI peripheral address. + * @return The data from the read data buffer. + */ +static inline uint32_t DSPI_ReadData(SPI_Type *base) +{ + return (base->POPR); +} + +/*! + *@} +*/ + +/*! + * @name Transactional + * @{ + */ +/*Transactional APIs*/ + +/*! + * @brief Initializes the DSPI master handle. + * + * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a + * specified DSPI instance, call this API once to get the initialized handle. + * + * @param base DSPI peripheral base address. + * @param handle DSPI handle pointer to dspi_master_handle_t. + * @param callback DSPI callback. + * @param userData Callback function parameter. + */ +void DSPI_MasterTransferCreateHandle(SPI_Type *base, + dspi_master_handle_t *handle, + dspi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief DSPI master transfer data using polling. + * + * This function transfers data using polling. This is a blocking function, which does not return until all transfers + * have been completed. + * + * @param base DSPI peripheral base address. + * @param transfer Pointer to the dspi_transfer_t structure. + * @return status of status_t. + */ +status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer); + +/*! + * @brief DSPI master transfer data using interrupts. + * + * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all + * data is transferred, the callback function is called. + + * @param base DSPI peripheral base address. + * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. + * @param transfer Pointer to the dspi_transfer_t structure. + * @return status of status_t. + */ +status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer); + +/*! + * @brief Gets the master transfer count. + * + * This function gets the master transfer count. + * + * @param base DSPI peripheral base address. + * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count); + +/*! + * @brief DSPI master aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base DSPI peripheral base address. + * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. + */ +void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle); + +/*! + * @brief DSPI Master IRQ handler function. + * + * This function processes the DSPI transmit and receive IRQ. + + * @param base DSPI peripheral base address. + * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. + */ +void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle); + +/*! + * @brief Initializes the DSPI slave handle. + * + * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a + * specified DSPI instance, call this API once to get the initialized handle. + * + * @param handle DSPI handle pointer to the dspi_slave_handle_t. + * @param base DSPI peripheral base address. + * @param callback DSPI callback. + * @param userData Callback function parameter. + */ +void DSPI_SlaveTransferCreateHandle(SPI_Type *base, + dspi_slave_handle_t *handle, + dspi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief DSPI slave transfers data using an interrupt. + * + * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all + * data is transferred, the callback function is called. + * + * @param base DSPI peripheral base address. + * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. + * @param transfer Pointer to the dspi_transfer_t structure. + * @return status of status_t. + */ +status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer); + +/*! + * @brief Gets the slave transfer count. + * + * This function gets the slave transfer count. + * + * @param base DSPI peripheral base address. + * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. + * @param count The number of bytes transferred by using the non-blocking transaction. + * @return status of status_t. + */ +status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count); + +/*! + * @brief DSPI slave aborts a transfer using an interrupt. + * + * This function aborts a transfer using an interrupt. + * + * @param base DSPI peripheral base address. + * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. + */ +void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle); + +/*! + * @brief DSPI Master IRQ handler function. + * + * This function processes the DSPI transmit and receive IRQ. + * + * @param base DSPI peripheral base address. + * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. + */ +void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle); + +/*! + *@} +*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + /*! + *@} + */ + +#endif /*_FSL_DSPI_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dspi_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dspi_edma.c new file mode 100644 index 00000000000..ef0d15174f5 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dspi_edma.c @@ -0,0 +1,1248 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_dspi_edma.h" + +/*********************************************************************************************************************** +* Definitons +***********************************************************************************************************************/ + +/*! +* @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. +*/ +typedef struct _dspi_master_edma_private_handle +{ + SPI_Type *base; /*!< DSPI peripheral base address. */ + dspi_master_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */ +} dspi_master_edma_private_handle_t; + +/*! +* @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. +*/ +typedef struct _dspi_slave_edma_private_handle +{ + SPI_Type *base; /*!< DSPI peripheral base address. */ + dspi_slave_edma_handle_t *handle; /*!< dspi_master_edma_handle_t handle */ +} dspi_slave_edma_private_handle_t; + +/*********************************************************************************************************************** +* Prototypes +***********************************************************************************************************************/ +/*! +* @brief EDMA_DspiMasterCallback after the DSPI master transfer completed by using EDMA. +* This is not a public API. +*/ +static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle, + void *g_dspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +/*! +* @brief EDMA_DspiSlaveCallback after the DSPI slave transfer completed by using EDMA. +* This is not a public API. +*/ +static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_dspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); +/*! +* @brief Get instance number for DSPI module. +* +* This is not a public API and it's extern from fsl_dspi.c. +* +* @param base DSPI peripheral base address +*/ +extern uint32_t DSPI_GetInstance(SPI_Type *base); + +/*********************************************************************************************************************** +* Variables +***********************************************************************************************************************/ + +/*! @brief Pointers to dspi edma handles for each instance. */ +static dspi_master_edma_private_handle_t s_dspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT]; +static dspi_slave_edma_private_handle_t s_dspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT]; + +/*********************************************************************************************************************** +* Code +***********************************************************************************************************************/ + +void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base, + dspi_master_edma_handle_t *handle, + dspi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToIntermediaryHandle, + edma_handle_t *edmaIntermediaryToTxRegHandle) +{ + assert(handle); + assert(edmaRxRegToRxDataHandle); + assert(edmaTxDataToIntermediaryHandle); + assert(edmaIntermediaryToTxRegHandle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + uint32_t instance = DSPI_GetInstance(base); + + s_dspiMasterEdmaPrivateHandle[instance].base = base; + s_dspiMasterEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToIntermediaryHandle = edmaTxDataToIntermediaryHandle; + handle->edmaIntermediaryToTxRegHandle = edmaIntermediaryToTxRegHandle; +} + +status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + /* If both send buffer and receive buffer is null */ + if ((!(transfer->txData)) && (!(transfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kDSPI_Busy) + { + return kStatus_DSPI_Busy; + } + + handle->state = kDSPI_Busy; + + uint32_t instance = DSPI_GetInstance(base); + uint16_t wordToSend = 0; + uint8_t dummyData = DSPI_DUMMY_DATA; + uint8_t dataAlreadyFed = 0; + uint8_t dataFedMax = 2; + + uint32_t rxAddr = DSPI_GetRxRegisterAddress(base); + uint32_t txAddr = DSPI_MasterGetTxRegisterAddress(base); + + edma_tcd_t *softwareTCD = (edma_tcd_t *)((uint32_t)(&handle->dspiSoftwareTCD[1]) & (~0x1FU)); + + edma_transfer_config_t transferConfigA; + edma_transfer_config_t transferConfigB; + edma_transfer_config_t transferConfigC; + + handle->txBuffIfNull = ((uint32_t)DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA; + + dspi_command_data_config_t commandStruct; + DSPI_StopTransfer(base); + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + commandStruct.whichPcs = + (dspi_which_pcs_t)(1U << ((transfer->configFlags & DSPI_MASTER_PCS_MASK) >> DSPI_MASTER_PCS_SHIFT)); + commandStruct.isEndOfQueue = false; + commandStruct.clearTransferCount = false; + commandStruct.whichCtar = + (dspi_ctar_selection_t)((transfer->configFlags & DSPI_MASTER_CTAR_MASK) >> DSPI_MASTER_CTAR_SHIFT); + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterPcsContinuous); + handle->command = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + commandStruct.isEndOfQueue = true; + commandStruct.isPcsContinuous = (bool)(transfer->configFlags & kDSPI_MasterActiveAfterTransfer); + handle->lastCommand = DSPI_MasterGetFormattedCommand(&(commandStruct)); + + handle->bitsPerFrame = ((base->CTAR[commandStruct.whichCtar] & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT) + 1; + + if ((base->MCR & SPI_MCR_DIS_RXF_MASK) || (base->MCR & SPI_MCR_DIS_TXF_MASK)) + { + handle->fifoSize = 1; + } + else + { + handle->fifoSize = FSL_FEATURE_DSPI_FIFO_SIZEn(base); + } + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->remainingSendByteCount = transfer->dataSize; + handle->remainingReceiveByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer + * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame + */ + uint32_t limited_size = 0; + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + limited_size = 32767u; + } + else + { + limited_size = 511u; + } + + if (handle->bitsPerFrame > 8) + { + if (transfer->dataSize > (limited_size << 1u)) + { + handle->state = kDSPI_Idle; + return kStatus_DSPI_OutOfRange; + } + } + else + { + if (transfer->dataSize > limited_size) + { + handle->state = kDSPI_Idle; + return kStatus_DSPI_OutOfRange; + } + } + + /*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */ + if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1)) + { + handle->state = kDSPI_Idle; + return kStatus_InvalidArgument; + } + + DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback, + &s_dspiMasterEdmaPrivateHandle[instance]); + + /* + (1)For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C. + channel_A minor link to channel_B , channel_B minor link to channel_C. + + Already pushed 1 or 2 data in SPI_PUSHR , then start the DMA tansfer. + channel_A:SPI_POPR to rxData, + channel_B:next txData to handle->command (low 16 bits), + channel_C:handle->command (32 bits) to SPI_PUSHR, and use the scatter/gather to transfer the last data + (handle->lastCommand to SPI_PUSHR). + + (2)For DSPI instances with separate RX and TX DMA requests: + Rx DMA request -> channel_A + Tx DMA request -> channel_C -> channel_B . + channel_C major link to channel_B. + So need prepare the first data in "intermediary" before the DMA + transfer and then channel_B is used to prepare the next data to "intermediary" + + channel_A:SPI_POPR to rxData, + channel_C: handle->command (32 bits) to SPI_PUSHR, + channel_B: next txData to handle->command (low 16 bits), and use the scatter/gather to prepare the last data + (handle->lastCommand to handle->Command). + */ + + /*If dspi has separate dma request , prepare the first data in "intermediary" . + else (dspi has shared dma request) , send first 2 data if there is fifo or send first 1 data if there is no fifo*/ + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /* For DSPI instances with separate RX/TX DMA requests, we'll use the TX DMA request to + * trigger the TX DMA channel and RX DMA request to trigger the RX DMA channel + */ + + /*Prepare the firt data*/ + if (handle->bitsPerFrame > 8) + { + /* If it's the last word */ + if (handle->remainingSendByteCount <= 2) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data byte */ + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; + handle->command = handle->lastCommand; + } + else /* For all words except the last word , frame > 8bits */ + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data byte */ + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + ++handle->txData; /* increment to next data byte */ + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->command = (handle->command & 0xffff0000U) | wordToSend; + } + } + else /* Optimized for bits/frame less than or equal to one byte. */ + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* increment to next data word*/ + } + else + { + wordToSend = dummyData; + } + + if (handle->remainingSendByteCount == 1) + { + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; + handle->command = handle->lastCommand; + } + else + { + handle->command = (handle->command & 0xffff0000U) | wordToSend; + } + } + } + + else /*dspi has shared dma request*/ + + { + /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to + * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. + */ + + /* If bits/frame is greater than one byte */ + if (handle->bitsPerFrame > 8) + { + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + if (handle->remainingSendByteCount <= 2) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->remainingSendByteCount = 0; + base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + /* For all words except the last word */ + else + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + ++handle->txData; + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->remainingSendByteCount -= 2; + base->PUSHR = (handle->command & 0xffff0000U) | wordToSend; + } + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + dataAlreadyFed += 2; + + /* exit loop if send count is zero, else update local variables for next loop */ + if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == (dataFedMax * 2))) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + else /* Optimized for bits/frame less than or equal to one byte. */ + { + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; + } + else + { + wordToSend = dummyData; + } + + if (handle->remainingSendByteCount == 1) + { + base->PUSHR = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + else + { + base->PUSHR = (handle->command & 0xffff0000U) | wordToSend; + } + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + --handle->remainingSendByteCount; + + dataAlreadyFed++; + + /* exit loop if send count is zero, else update local variables for next loop */ + if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == dataFedMax)) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + } + + /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer(rxData)*/ + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + transferConfigA.srcAddr = (uint32_t)rxAddr; + transferConfigA.srcOffset = 0; + + if (handle->rxData) + { + transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigA.destOffset = 1; + } + else + { + transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigA.destOffset = 0; + } + + transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigA.minorLoopBytes = 1; + transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount; + } + else + { + transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigA.minorLoopBytes = 2; + transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2; + } + + /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ + handle->nbytes = transferConfigA.minorLoopBytes; + + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigA, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MajorInterruptEnable); + + /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should + write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the + SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */ + + EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel); + + /*Calculate the last data : handle->lastCommand*/ + if (((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) || + ((((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) || + ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) && + (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))) + { + if (handle->txData) + { + uint32_t bufferIndex = 0; + + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + if (handle->bitsPerFrame <= 8) + { + bufferIndex = handle->remainingSendByteCount - 1; + } + else + { + bufferIndex = handle->remainingSendByteCount - 2; + } + } + else + { + bufferIndex = handle->remainingSendByteCount; + } + + if (handle->bitsPerFrame <= 8) + { + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | handle->txData[bufferIndex - 1]; + } + else + { + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | + ((uint32_t)handle->txData[bufferIndex - 1] << 8) | + handle->txData[bufferIndex - 2]; + } + } + else + { + if (handle->bitsPerFrame <= 8) + { + wordToSend = dummyData; + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend; + } + } + + /*For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data + * (handle->lastCommand) to handle->Command*/ + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand); + transferConfigB.destAddr = (uint32_t) & (handle->command); + transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigB.srcOffset = 0; + transferConfigB.destOffset = 0; + transferConfigB.minorLoopBytes = 4; + transferConfigB.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD); + EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigB, NULL); + } + + /*User_Send_Buffer(txData) to intermediary(handle->command)*/ + if (((((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame <= 8)) || + ((handle->remainingSendByteCount > 4) && (handle->bitsPerFrame > 8))) && + (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) || + (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) + { + if (handle->txData) + { + transferConfigB.srcAddr = (uint32_t)(handle->txData); + transferConfigB.srcOffset = 1; + } + else + { + transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigB.srcOffset = 0; + } + + transferConfigB.destAddr = (uint32_t)(&handle->command); + transferConfigB.destOffset = 0; + + transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigB.minorLoopBytes = 1; + + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 2; + } + else + { + /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is + majorlink , the majorlink would not trigger the channel_C*/ + transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1; + } + } + else + { + transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigB.minorLoopBytes = 2; + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 2; + } + else + { + /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is + * majorlink*/ + transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 + 1; + } + } + + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, softwareTCD); + EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, false); + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL); + } + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL); + } + + /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to + handle the last data */ + + EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel); + + /*For DSPI instances with shared RX/TX DMA requests: use the scatter/gather to prepare the last data + * (handle->lastCommand) to SPI_PUSHR*/ + if (((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0))) + { + transferConfigC.srcAddr = (uint32_t) & (handle->lastCommand); + transferConfigC.destAddr = (uint32_t)txAddr; + transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.srcOffset = 0; + transferConfigC.destOffset = 0; + transferConfigC.minorLoopBytes = 4; + transferConfigC.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD); + EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigC, NULL); + } + + if (((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) || + ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8)) || + (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) + { + transferConfigC.srcAddr = (uint32_t)(&(handle->command)); + transferConfigC.destAddr = (uint32_t)txAddr; + + transferConfigC.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigC.srcOffset = 0; + transferConfigC.destOffset = 0; + transferConfigC.minorLoopBytes = 4; + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + if (handle->bitsPerFrame <= 8) + { + transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1; + } + else + { + transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1; + } + + EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD); + } + else + { + transferConfigC.majorLoopCounts = 1; + + EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL); + } + + EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, false); + } + else + { + EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL); + } + + /*Start the EDMA channel_A , channel_B , channel_C transfer*/ + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_StartTransfer(handle->edmaTxDataToIntermediaryHandle); + EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle); + + /*Set channel priority*/ + uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel; + uint8_t channelPriorityMid = handle->edmaTxDataToIntermediaryHandle->channel; + uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel; + uint8_t t = 0; + if (channelPriorityLow > channelPriorityMid) + { + t = channelPriorityLow; + channelPriorityLow = channelPriorityMid; + channelPriorityMid = t; + } + + if (channelPriorityLow > channelPriorityHigh) + { + t = channelPriorityLow; + channelPriorityLow = channelPriorityHigh; + channelPriorityHigh = t; + } + + if (channelPriorityMid > channelPriorityHigh) + { + t = channelPriorityMid; + channelPriorityMid = channelPriorityHigh; + channelPriorityHigh = t; + } + edma_channel_Preemption_config_t preemption_config_t; + preemption_config_t.enableChannelPreemption = true; + preemption_config_t.enablePreemptAbility = true; + preemption_config_t.channelPriority = channelPriorityLow; + + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityMid; + EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t); + } + else + { + EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityMid; + EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + } + + /*Set the channel link.*/ + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /*if there is Tx DMA request , carry the 32bits data (handle->command) to PUSHR first , then link to channelB + to prepare the next 32bits data (txData to handle->command) */ + if (handle->remainingSendByteCount > 1) + { + EDMA_SetChannelLink(handle->edmaIntermediaryToTxRegHandle->base, + handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MajorLink, + handle->edmaTxDataToIntermediaryHandle->channel); + } + + DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + } + else + { + if (handle->remainingSendByteCount > 0) + { + EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MinorLink, handle->edmaTxDataToIntermediaryHandle->channel); + + EDMA_SetChannelLink(handle->edmaTxDataToIntermediaryHandle->base, + handle->edmaTxDataToIntermediaryHandle->channel, kEDMA_MinorLink, + handle->edmaIntermediaryToTxRegHandle->channel); + } + + DSPI_EnableDMA(base, kDSPI_RxDmaEnable); + } + + DSPI_StartTransfer(base); + + return kStatus_Success; +} + +static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle, + void *g_dspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + assert(edmaHandle); + assert(g_dspiEdmaPrivateHandle); + + dspi_master_edma_private_handle_t *dspiEdmaPrivateHandle; + + dspiEdmaPrivateHandle = (dspi_master_edma_private_handle_t *)g_dspiEdmaPrivateHandle; + + DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + dspiEdmaPrivateHandle->handle->state = kDSPI_Idle; + + if (dspiEdmaPrivateHandle->handle->callback) + { + dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle, + kStatus_Success, dspiEdmaPrivateHandle->handle->userData); + } +} + +void DSPI_MasterTransferAbortEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle) +{ + assert(handle); + + DSPI_StopTransfer(base); + + DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToIntermediaryHandle); + EDMA_AbortTransfer(handle->edmaIntermediaryToTxRegHandle); + + handle->state = kDSPI_Idle; +} + +status_t DSPI_MasterTransferGetCountEDMA(SPI_Type *base, dspi_master_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kDSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t bytes; + + bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, + handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - bytes; + + return kStatus_Success; +} + +void DSPI_SlaveTransferCreateHandleEDMA(SPI_Type *base, + dspi_slave_edma_handle_t *handle, + dspi_slave_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle); + assert(edmaRxRegToRxDataHandle); + assert(edmaTxDataToTxRegHandle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + uint32_t instance = DSPI_GetInstance(base); + + s_dspiSlaveEdmaPrivateHandle[instance].base = base; + s_dspiSlaveEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, dspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + /* If send/receive length is zero */ + if (transfer->dataSize == 0) + { + return kStatus_InvalidArgument; + } + + /* If both send buffer and receive buffer is null */ + if ((!(transfer->txData)) && (!(transfer->rxData))) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kDSPI_Busy) + { + return kStatus_DSPI_Busy; + } + + handle->state = kDSPI_Busy; + + uint32_t instance = DSPI_GetInstance(base); + uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT; + handle->bitsPerFrame = + (((base->CTAR_SLAVE[whichCtar]) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT) + 1; + + /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer + * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame + */ + uint32_t limited_size = 0; + if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + limited_size = 32767u; + } + else + { + limited_size = 511u; + } + + if (handle->bitsPerFrame > 8) + { + if (transfer->dataSize > (limited_size << 1u)) + { + handle->state = kDSPI_Idle; + return kStatus_DSPI_OutOfRange; + } + } + else + { + if (transfer->dataSize > limited_size) + { + handle->state = kDSPI_Idle; + return kStatus_DSPI_OutOfRange; + } + } + + /*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */ + if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1)) + { + handle->state = kDSPI_Idle; + return kStatus_InvalidArgument; + } + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]); + + /* Store transfer information */ + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->remainingSendByteCount = transfer->dataSize; + handle->remainingReceiveByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + uint16_t wordToSend = 0; + uint8_t dummyData = DSPI_DUMMY_DATA; + uint8_t dataAlreadyFed = 0; + uint8_t dataFedMax = 2; + + uint32_t rxAddr = DSPI_GetRxRegisterAddress(base); + uint32_t txAddr = DSPI_SlaveGetTxRegisterAddress(base); + + edma_transfer_config_t transferConfigA; + edma_transfer_config_t transferConfigC; + + DSPI_StopTransfer(base); + + DSPI_FlushFifo(base, true, true); + DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag); + + DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + DSPI_StartTransfer(base); + + /*if dspi has separate dma request , need not prepare data first . + else (dspi has shared dma request) , send first 2 data into fifo if there is fifo or send first 1 data to + slaveGetTxRegister if there is no fifo*/ + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to + * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel. + */ + /* If bits/frame is greater than one byte */ + if (handle->bitsPerFrame > 8) + { + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + ++handle->txData; /* Increment to next data byte */ + + wordToSend |= (unsigned)(*(handle->txData)) << 8U; + ++handle->txData; /* Increment to next data byte */ + } + else + { + wordToSend = ((uint32_t)dummyData << 8) | dummyData; + } + handle->remainingSendByteCount -= 2; /* decrement remainingSendByteCount by 2 */ + base->PUSHR_SLAVE = wordToSend; + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + + dataAlreadyFed += 2; + + /* Exit loop if send count is zero, else update local variables for next loop */ + if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == (dataFedMax * 2))) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + else /* Optimized for bits/frame less than or equal to one byte. */ + { + while (DSPI_GetStatusFlags(base) & kDSPI_TxFifoFillRequestFlag) + { + if (handle->txData) + { + wordToSend = *(handle->txData); + /* Increment to next data word*/ + ++handle->txData; + } + else + { + wordToSend = dummyData; + } + + base->PUSHR_SLAVE = wordToSend; + + /* Try to clear the TFFF; if the TX FIFO is full this will clear */ + DSPI_ClearStatusFlags(base, kDSPI_TxFifoFillRequestFlag); + /* Decrement remainingSendByteCount*/ + --handle->remainingSendByteCount; + + dataAlreadyFed++; + + /* Exit loop if send count is zero, else update local variables for next loop */ + if ((handle->remainingSendByteCount == 0) || (dataAlreadyFed == dataFedMax)) + { + break; + } + } /* End of TX FIFO fill while loop */ + } + } + + /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/ + if (handle->remainingReceiveByteCount > 0) + { + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + transferConfigA.srcAddr = (uint32_t)rxAddr; + transferConfigA.srcOffset = 0; + + if (handle->rxData) + { + transferConfigA.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigA.destOffset = 1; + } + else + { + transferConfigA.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigA.destOffset = 0; + } + + transferConfigA.destTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigA.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigA.minorLoopBytes = 1; + transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount; + } + else + { + transferConfigA.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigA.minorLoopBytes = 2; + transferConfigA.majorLoopCounts = handle->remainingReceiveByteCount / 2; + } + + /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ + handle->nbytes = transferConfigA.minorLoopBytes; + + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigA, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MajorInterruptEnable); + } + + if (handle->remainingSendByteCount > 0) + { + /***channel_C *** used for carry the data from User_Send_Buffer to Tx_Data_Register(PUSHR_SLAVE)*/ + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + + transferConfigC.destAddr = (uint32_t)txAddr; + transferConfigC.destOffset = 0; + + if (handle->txData) + { + transferConfigC.srcAddr = (uint32_t)(&(handle->txData[0])); + transferConfigC.srcOffset = 1; + } + else + { + transferConfigC.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigC.srcOffset = 0; + if (handle->bitsPerFrame <= 8) + { + handle->txBuffIfNull = DSPI_DUMMY_DATA; + } + else + { + handle->txBuffIfNull = (DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA; + } + } + + transferConfigC.srcTransferSize = kEDMA_TransferSize1Bytes; + + if (handle->bitsPerFrame <= 8) + { + transferConfigC.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigC.minorLoopBytes = 1; + transferConfigC.majorLoopCounts = handle->remainingSendByteCount; + } + else + { + transferConfigC.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigC.minorLoopBytes = 2; + transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2; + } + + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigC, NULL); + + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + } + + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + + /*Set channel priority*/ + uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel; + uint8_t channelPriorityHigh = handle->edmaTxDataToTxRegHandle->channel; + uint8_t t = 0; + + if (channelPriorityLow > channelPriorityHigh) + { + t = channelPriorityLow; + channelPriorityLow = channelPriorityHigh; + channelPriorityHigh = t; + } + + edma_channel_Preemption_config_t preemption_config_t; + preemption_config_t.enableChannelPreemption = true; + preemption_config_t.enablePreemptAbility = true; + preemption_config_t.channelPriority = channelPriorityLow; + + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &preemption_config_t); + } + else + { + EDMA_SetChannelPreemptionConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &preemption_config_t); + + preemption_config_t.channelPriority = channelPriorityHigh; + EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &preemption_config_t); + } + + /*Set the channel link. + For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_C. + For DSPI instances with separate RX and TX DMA requests: + Rx DMA request -> channel_A + Tx DMA request -> channel_C */ + if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + if (handle->remainingSendByteCount > 0) + { + EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MinorLink, handle->edmaTxDataToTxRegHandle->channel); + } + DSPI_EnableDMA(base, kDSPI_RxDmaEnable); + } + else + { + DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + } + + return kStatus_Success; +} + +static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_dspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + assert(edmaHandle); + assert(g_dspiEdmaPrivateHandle); + + dspi_slave_edma_private_handle_t *dspiEdmaPrivateHandle; + + dspiEdmaPrivateHandle = (dspi_slave_edma_private_handle_t *)g_dspiEdmaPrivateHandle; + + DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + dspiEdmaPrivateHandle->handle->state = kDSPI_Idle; + + if (dspiEdmaPrivateHandle->handle->callback) + { + dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle, + kStatus_Success, dspiEdmaPrivateHandle->handle->userData); + } +} + +void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle) +{ + assert(handle); + + DSPI_StopTransfer(base); + + DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = kDSPI_Idle; +} + +status_t DSPI_SlaveTransferGetCountEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kDSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t bytes; + + bytes = (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, + handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - bytes; + + return kStatus_Success; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dspi_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dspi_edma.h new file mode 100644 index 00000000000..23e29ce2983 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_dspi_edma.h @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_DSPI_EDMA_H_ +#define _FSL_DSPI_EDMA_H_ + +#include "fsl_dspi.h" +#include "fsl_edma.h" +/*! + * @addtogroup dspi_edma_driver + * @{ + */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! +* @brief Forward declaration of the DSPI eDMA master handle typedefs. +*/ +typedef struct _dspi_master_edma_handle dspi_master_edma_handle_t; + +/*! +* @brief Forward declaration of the DSPI eDMA slave handle typedefs. +*/ +typedef struct _dspi_slave_edma_handle dspi_slave_edma_handle_t; + +/*! + * @brief Completion callback function pointer type. + * + * @param base DSPI peripheral base address. + * @param handle A pointer to the handle for the DSPI master. + * @param status Success or error code describing whether the transfer completed. + * @param userData An arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*dspi_master_edma_transfer_callback_t)(SPI_Type *base, + dspi_master_edma_handle_t *handle, + status_t status, + void *userData); +/*! + * @brief Completion callback function pointer type. + * + * @param base DSPI peripheral base address. + * @param handle A pointer to the handle for the DSPI slave. + * @param status Success or error code describing whether the transfer completed. + * @param userData An arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*dspi_slave_edma_transfer_callback_t)(SPI_Type *base, + dspi_slave_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief DSPI master eDMA transfer handle structure used for the transactional API. */ +struct _dspi_master_edma_handle +{ + uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */ + volatile uint32_t command; /*!< The desired data command. */ + volatile uint32_t lastCommand; /*!< The desired last data command. */ + + uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile bool + isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal keeps active after the last frame transfer.*/ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + volatile uint8_t state; /*!< DSPI transfer state , _dspi_transfer_state.*/ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/ + volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/ + size_t totalByteCount; /*!< A number of transfer bytes*/ + + uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/ + uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/ + + dspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ + + edma_handle_t *edmaRxRegToRxDataHandle; /*!TCD[channel].SADDR = tcd->SADDR; + base->TCD[channel].SOFF = tcd->SOFF; + base->TCD[channel].ATTR = tcd->ATTR; + base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; + base->TCD[channel].SLAST = tcd->SLAST; + base->TCD[channel].DADDR = tcd->DADDR; + base->TCD[channel].DOFF = tcd->DOFF; + base->TCD[channel].CITER_ELINKNO = tcd->CITER; + base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA; + /* Clear DONE bit first, otherwise ESG cannot be set */ + base->TCD[channel].CSR = 0; + base->TCD[channel].CSR = tcd->CSR; + base->TCD[channel].BITER_ELINKNO = tcd->BITER; +} + +void EDMA_Init(DMA_Type *base, const edma_config_t *config) +{ + assert(config != NULL); + + uint32_t tmpreg; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate EDMA periphral clock */ + CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Configure EDMA peripheral according to the configuration structure. */ + tmpreg = base->CR; + tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); + tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | + DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true)); + base->CR = tmpreg; +} + +void EDMA_Deinit(DMA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate EDMA periphral clock */ + CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void EDMA_GetDefaultConfig(edma_config_t *config) +{ + assert(config != NULL); + + config->enableRoundRobinArbitration = false; + config->enableHaltOnError = true; + config->enableContinuousLinkMode = false; + config->enableDebugMode = false; +} + +void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]); +} + +void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + assert(((uint32_t)nextTcd & 0x1FU) == 0); + + EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd); +} + +void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + + uint32_t tmpreg; + + tmpreg = base->TCD[channel].NBYTES_MLOFFYES; + tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + base->TCD[channel].NBYTES_MLOFFYES = tmpreg; +} + +void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel); +} + +void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); +} + +void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t tmpreg; + + tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Enable error interrupt */ + if (mask & kEDMA_ErrorInterruptEnable) + { + base->EEI |= (0x1U << channel); + } + + /* Enable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; + } +} + +void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Disable error interrupt */ + if (mask & kEDMA_ErrorInterruptEnable) + { + base->EEI &= ~(0x1U << channel); + } + + /* Disable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK; + } +} + +void EDMA_TcdReset(edma_tcd_t *tcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + /* Reset channel TCD */ + tcd->SADDR = 0U; + tcd->SOFF = 0U; + tcd->ATTR = 0U; + tcd->NBYTES = 0U; + tcd->SLAST = 0U; + tcd->DADDR = 0U; + tcd->DOFF = 0U; + tcd->CITER = 0U; + tcd->DLAST_SGA = 0U; + /* Enable auto disable request feature */ + tcd->CSR = DMA_CSR_DREQ(true); + tcd->BITER = 0U; +} + +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + assert(config != NULL); + assert(((uint32_t)nextTcd & 0x1FU) == 0); + + /* source address */ + tcd->SADDR = config->srcAddr; + /* destination address */ + tcd->DADDR = config->destAddr; + /* Source data and destination data transfer size */ + tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize); + /* Source address signed offset */ + tcd->SOFF = config->srcOffset; + /* Destination address signed offset */ + tcd->DOFF = config->destOffset; + /* Minor byte transfer count */ + tcd->NBYTES = config->minorLoopBytes; + /* Current major iteration count */ + tcd->CITER = config->majorLoopCounts; + /* Starting major iteration count */ + tcd->BITER = config->majorLoopCounts; + /* Enable scatter/gather processing */ + if (nextTcd != NULL) + { + tcd->DLAST_SGA = (uint32_t)nextTcd; + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + } +} + +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + uint32_t tmpreg; + + tmpreg = tcd->NBYTES & + ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + tcd->NBYTES = tmpreg; +} + +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + if (type == kEDMA_MinorLink) /* Minor link config */ + { + uint32_t tmpreg; + + /* Enable minor link */ + tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set likned channel */ + tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); + tcd->CITER = tmpreg; + tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); + tcd->BITER = tmpreg; + } + else if (type == kEDMA_MajorLink) /* Major link config */ + { + uint32_t tmpreg; + + /* Enable major link */ + tcd->CSR |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK); + tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); + } + else /* Link none */ + { + tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK; + tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK; + } +} + +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + uint32_t tmpreg; + + tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Enable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + tcd->CSR |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + tcd->CSR |= DMA_CSR_INTHALF_MASK; + } +} + +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Disable Major interrupt */ + if (mask & kEDMA_MajorInterruptEnable) + { + tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (mask & kEDMA_HalfInterruptEnable) + { + tcd->CSR &= ~DMA_CSR_INTHALF_MASK; + } +} + +uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t remainingCount = 0; + + if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR) + { + remainingCount = 0; + } + else + { + /* Calculate the unfinished bytes */ + if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK) + { + remainingCount = + (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT; + } + else + { + remainingCount = + (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT; + } + } + + return remainingCount; +} + +uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t retval = 0; + + /* Get DONE bit flag */ + retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT); + /* Get ERROR bit flag */ + retval |= (((base->ERR >> channel) & 0x1U) << 1U); + /* Get INT bit flag */ + retval |= (((base->INT >> channel) & 0x1U) << 2U); + + return retval; +} + +void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Clear DONE bit flag */ + if (mask & kEDMA_DoneFlag) + { + base->CDNE = channel; + } + /* Clear ERROR bit flag */ + if (mask & kEDMA_ErrorFlag) + { + base->CERR = channel; + } + /* Clear INT bit flag */ + if (mask & kEDMA_InterruptFlag) + { + base->CINT = channel; + } +} + +void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) +{ + assert(handle != NULL); + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t edmaInstance; + uint32_t channelIndex; + edma_tcd_t *tcdRegs; + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + handle->base = base; + handle->channel = channel; + /* Get the DMA instance number */ + edmaInstance = EDMA_GetInstance(base); + channelIndex = (edmaInstance * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel; + s_EDMAHandle[channelIndex] = handle; + + /* Enable NVIC interrupt */ + EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); + + /* + Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), + CSR will be 0. Because in order to suit EDMA busy check mechanism in + EDMA_SubmitTransfer, CSR must be set 0. + */ + tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + tcdRegs->SADDR = 0; + tcdRegs->SOFF = 0; + tcdRegs->ATTR = 0; + tcdRegs->NBYTES = 0; + tcdRegs->SLAST = 0; + tcdRegs->DADDR = 0; + tcdRegs->DOFF = 0; + tcdRegs->CITER = 0; + tcdRegs->DLAST_SGA = 0; + tcdRegs->CSR = 0; + tcdRegs->BITER = 0; +} + +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) +{ + assert(handle != NULL); + assert(((uint32_t)tcdPool & 0x1FU) == 0); + + /* Initialize tcd queue attibute. */ + handle->header = 0; + handle->tail = 0; + handle->tcdUsed = 0; + handle->tcdSize = tcdSize; + handle->flags = 0; + handle->tcdPool = tcdPool; +} + +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type) +{ + assert(config != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); + assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U)); + assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U)); + assert(transferBytes % bytesEachRequest == 0); + + config->destAddr = (uint32_t)destAddr; + config->srcAddr = (uint32_t)srcAddr; + config->minorLoopBytes = bytesEachRequest; + config->majorLoopCounts = transferBytes / bytesEachRequest; + switch (srcWidth) + { + case 1U: + config->srcTransferSize = kEDMA_TransferSize1Bytes; + break; + case 2U: + config->srcTransferSize = kEDMA_TransferSize2Bytes; + break; + case 4U: + config->srcTransferSize = kEDMA_TransferSize4Bytes; + break; + case 16U: + config->srcTransferSize = kEDMA_TransferSize16Bytes; + break; + case 32U: + config->srcTransferSize = kEDMA_TransferSize32Bytes; + break; + default: + break; + } + switch (destWidth) + { + case 1U: + config->destTransferSize = kEDMA_TransferSize1Bytes; + break; + case 2U: + config->destTransferSize = kEDMA_TransferSize2Bytes; + break; + case 4U: + config->destTransferSize = kEDMA_TransferSize4Bytes; + break; + case 16U: + config->destTransferSize = kEDMA_TransferSize16Bytes; + break; + case 32U: + config->destTransferSize = kEDMA_TransferSize32Bytes; + break; + default: + break; + } + switch (type) + { + case kEDMA_MemoryToMemory: + config->destOffset = destWidth; + config->srcOffset = srcWidth; + break; + case kEDMA_MemoryToPeripheral: + config->destOffset = 0U; + config->srcOffset = srcWidth; + break; + case kEDMA_PeripheralToMemory: + config->destOffset = destWidth; + config->srcOffset = 0U; + break; + default: + break; + } +} + +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + + edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + + if (handle->tcdPool == NULL) + { + /* + Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because + if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit + this check mechanism, EDMA_CreatHandle will clear CSR register. + */ + if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0)) + { + return kStatus_EDMA_Busy; + } + else + { + EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL); + /* Enable auto disable request feature */ + handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK; + /* Enable major interrupt */ + handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK; + + return kStatus_Success; + } + } + else /* Use the TCD queue. */ + { + uint32_t primask; + uint32_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + if (handle->tcdUsed >= handle->tcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1U; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0U; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U; + /* Configure current TCD block. */ + EDMA_TcdReset(&handle->tcdPool[currentTcd]); + EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); + /* Enable major interrupt */ + handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; + /* Link current TCD with next TCD for identification of current TCD */ + handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { + /* Enable scatter/gather feature in the previous TCD block. */ + csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + handle->tcdPool[previousTcd].CSR = csr; + /* + Check if the TCD blcok in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) + { + /* Enable scatter/gather also in the TCD registers. */ + csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + tcdRegs->CSR = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic + link succeed. + */ + if (tcdRegs->CSR & DMA_CSR_ESG_MASK) + { + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (tcdRegs->DLAST_SGA != 0) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + /* Enable channel request again. */ + if (handle->flags & EDMA_TRANSFER_ENABLED_MASK) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + + return kStatus_Success; + } +} + +void EDMA_StartTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + + if (handle->tcdPool == NULL) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + else /* Use the TCD queue. */ + { + uint32_t primask; + edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + + handle->flags |= EDMA_TRANSFER_ENABLED_MASK; + + /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */ + if (tcdRegs->DLAST_SGA != 0U) + { + primask = DisableGlobalIRQ(); + /* Check if channel request is actually disable. */ + if ((handle->base->ERQ & (1U << handle->channel)) == 0U) + { + /* Check if transfer is paused. */ + if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK)) + { + /* + Re-enable channel request must be as soon as possible, so must put it into + critical section to avoid task switching or interrupt service routine. + */ + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + } + EnableGlobalIRQ(primask); + } + } +} + +void EDMA_StopTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + + handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK); + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); +} + +void EDMA_AbortTransfer(edma_handle_t *handle) +{ + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); + /* + Clear CSR to release channel. Because if the given channel started transfer, + CSR will be not zero. Because if it is the last transfer, DREQ will be set. + If not, ESG will be set. + */ + handle->base->TCD[handle->channel].CSR = 0; + /* Cancel all next TCD transfer. */ + handle->base->TCD[handle->channel].DLAST_SGA = 0; +} + +void EDMA_HandleIRQ(edma_handle_t *handle) +{ + assert(handle != NULL); + + /* Clear EDMA interrupt flag */ + handle->base->CINT = handle->channel; + if ((handle->tcdPool == NULL) && (handle->callback != NULL)) + { + (handle->callback)(handle, handle->userData, true, 0); + } + else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */ + { + uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA; + uint32_t sga_index; + int32_t tcds_done; + uint8_t new_header; + bool transfer_done; + + /* Check if transfer is already finished. */ + transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0); + /* Get the offset of the next transfer TCD blcoks to be loaded into the eDMA engine. */ + sga -= (uint32_t)handle->tcdPool; + /* Get the index of the next transfer TCD blcoks to be loaded into the eDMA engine. */ + sga_index = sga / sizeof(edma_tcd_t); + /* Adjust header positions. */ + if (transfer_done) + { + /* New header shall point to the next TCD to be loaded (current one is already finished) */ + new_header = sga_index; + } + else + { + /* New header shall point to this descriptor currently loaded (not finished yet) */ + new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U; + } + /* Calculate the number of finished TCDs */ + if (new_header == handle->header) + { + if (handle->tcdUsed == handle->tcdSize) + { + tcds_done = handle->tcdUsed; + } + else + { + /* No TCD in the memory are going to be loaded or internal error occurs. */ + tcds_done = 0; + } + } + else + { + tcds_done = new_header - handle->header; + if (tcds_done < 0) + { + tcds_done += handle->tcdSize; + } + } + /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */ + handle->header = new_header; + /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */ + handle->tcdUsed -= tcds_done; + /* Invoke callback function. */ + if (handle->callback) + { + (handle->callback)(handle, handle->userData, transfer_done, tcds_done); + } + } +} + +/* 8 channels (Shared): kl28 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U + +void DMA0_04_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } +} + +void DMA0_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } +} + +void DMA0_26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } +} + +void DMA0_37_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } +} + +#if defined(DMA1) +void DMA1_04_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } +} + +void DMA1_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } +} + +void DMA1_26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } +} + +void DMA1_37_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } +} +#endif +#endif /* 8 channels (Shared) */ + +/* 16 channels (Shared): K32H844P */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U + +void DMA0_08_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } +} + +void DMA0_19_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } +} + +void DMA0_210_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } +} + +void DMA0_311_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } +} + +void DMA0_412_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } +} + +void DMA0_513_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } +} + +void DMA0_614_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } +} + +void DMA0_715_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } +} + +#if defined(DMA1) +void DMA1_08_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[16]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[24]); + } +} + +void DMA1_19_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[17]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[25]); + } +} + +void DMA1_210_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[18]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[26]); + } +} + +void DMA1_311_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[19]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[27]); + } +} + +void DMA1_412_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[20]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[28]); + } +} + +void DMA1_513_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[21]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[29]); + } +} + +void DMA1_614_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[22]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[30]); + } +} + +void DMA1_715_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[23]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[31]); + } +} +#endif +#endif /* 16 channels (Shared) */ + +/* 32 channels (Shared): k80 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U + +void DMA0_DMA16_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[16]); + } +} + +void DMA1_DMA17_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[17]); + } +} + +void DMA2_DMA18_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[18]); + } +} + +void DMA3_DMA19_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[19]); + } +} + +void DMA4_DMA20_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[20]); + } +} + +void DMA5_DMA21_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[21]); + } +} + +void DMA6_DMA22_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[22]); + } +} + +void DMA7_DMA23_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[23]); + } +} + +void DMA8_DMA24_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[24]); + } +} + +void DMA9_DMA25_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[25]); + } +} + +void DMA10_DMA26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[26]); + } +} + +void DMA11_DMA27_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[27]); + } +} + +void DMA12_DMA28_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[28]); + } +} + +void DMA13_DMA29_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[29]); + } +} + +void DMA14_DMA30_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[30]); + } +} + +void DMA15_DMA31_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[31]); + } +} +#endif /* 32 channels (Shared) */ + +/* 32 channels (Shared): MCIMX7U5_M4 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U + +void DMA0_0_4_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } +} + +void DMA0_1_5_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } +} + +void DMA0_2_6_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } +} + +void DMA0_3_7_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } +} + +void DMA0_8_12_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } +} + +void DMA0_9_13_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } +} + +void DMA0_10_14_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } +} + +void DMA0_11_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } +} + +void DMA0_16_20_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[16]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[20]); + } +} + +void DMA0_17_21_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[17]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[21]); + } +} + +void DMA0_18_22_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[18]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[22]); + } +} + +void DMA0_19_23_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[19]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[23]); + } +} + +void DMA0_24_28_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[24]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[28]); + } +} + +void DMA0_25_29_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[25]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[29]); + } +} + +void DMA0_26_30_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[26]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[30]); + } +} + +void DMA0_27_31_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[27]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[31]); + } +} +#endif /* 32 channels (Shared): MCIMX7U5 */ + +/* 4 channels (No Shared): kv10 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0 + +void DMA0_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[0]); +} + +void DMA1_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[1]); +} + +void DMA2_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[2]); +} + +void DMA3_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[3]); +} + +/* 8 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U + +void DMA4_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[4]); +} + +void DMA5_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[5]); +} + +void DMA6_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[6]); +} + +void DMA7_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[7]); +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */ + +/* 16 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U + +void DMA8_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[8]); +} + +void DMA9_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[9]); +} + +void DMA10_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[10]); +} + +void DMA11_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[11]); +} + +void DMA12_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[12]); +} + +void DMA13_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[13]); +} + +void DMA14_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[14]); +} + +void DMA15_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[15]); +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */ + +/* 32 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U + +void DMA16_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[16]); +} + +void DMA17_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[17]); +} + +void DMA18_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[18]); +} + +void DMA19_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[19]); +} + +void DMA20_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[20]); +} + +void DMA21_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[21]); +} + +void DMA22_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[22]); +} + +void DMA23_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[23]); +} + +void DMA24_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[24]); +} + +void DMA25_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[25]); +} + +void DMA26_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[26]); +} + +void DMA27_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[27]); +} + +void DMA28_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[28]); +} + +void DMA29_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[29]); +} + +void DMA30_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[30]); +} + +void DMA31_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[31]); +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */ + +#endif /* 4/8/16/32 channels (No Shared) */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_edma.h new file mode 100644 index 00000000000..a97622d7e1e --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_edma.h @@ -0,0 +1,910 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_EDMA_H_ +#define _FSL_EDMA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup edma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief eDMA driver version */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */ +/*@}*/ + +/*! @brief Compute the offset unit from DCHPRI3 */ +#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U))) + +/*! @brief Get the pointer of DCHPRIn */ +#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)] + +/*! @brief eDMA transfer configuration */ +typedef enum _edma_transfer_size +{ + kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ + kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ + kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ + kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ + kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ +} edma_transfer_size_t; + +/*! @brief eDMA modulo configuration */ +typedef enum _edma_modulo +{ + kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */ + kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */ + kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */ + kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */ + kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */ + kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */ + kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */ + kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */ + kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */ + kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */ + kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1 K bytes. */ + kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2 K bytes. */ + kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4 K bytes. */ + kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8 K bytes. */ + kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16 K bytes. */ + kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32 K bytes. */ + kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64 K bytes. */ + kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128 K bytes. */ + kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256 K bytes. */ + kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512 K bytes. */ + kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1 M bytes. */ + kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2 M bytes. */ + kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4 M bytes. */ + kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8 M bytes. */ + kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16 M bytes. */ + kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32 M bytes. */ + kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64 M bytes. */ + kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128 M bytes. */ + kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256 M bytes. */ + kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512 M bytes. */ + kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1 G bytes. */ + kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2 G bytes. */ +} edma_modulo_t; + +/*! @brief Bandwidth control */ +typedef enum _edma_bandwidth +{ + kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ + kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ + kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ +} edma_bandwidth_t; + +/*! @brief Channel link type */ +typedef enum _edma_channel_link_type +{ + kEDMA_LinkNone = 0x0U, /*!< No channel link */ + kEDMA_MinorLink, /*!< Channel link after each minor loop */ + kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */ +} edma_channel_link_type_t; + +/*!@brief eDMA channel status flags. */ +enum _edma_channel_status_flags +{ + kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ + kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ + kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ +}; + +/*! @brief eDMA channel error status flags. */ +enum _edma_error_status_flags +{ + kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */ + kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */ + kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ + kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */ + kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */ + kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */ + kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */ + kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/ + kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */ + kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */ + kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */ +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1 + kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ +#endif + kEDMA_ValidFlag = DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ +}; + +/*! @brief eDMA interrupt source */ +typedef enum _edma_interrupt_enable +{ + kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ + kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ + kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ +} edma_interrupt_enable_t; + +/*! @brief eDMA transfer type */ +typedef enum _edma_transfer_type +{ + kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */ + kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */ + kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */ +} edma_transfer_type_t; + +/*! @brief eDMA transfer status */ +enum _edma_transfer_status +{ + kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ + kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief eDMA global configuration structure.*/ +typedef struct _edma_config +{ + bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel + activates again if that channel has a minor loop channel link enabled and + the link channel is itself. */ + bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. + Subsequently, all service requests are ignored until the HALT bit is cleared.*/ + bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method or fixed priority + arbitration is used for channel selection */ + bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of + a new channel. Executing channels are allowed to complete. */ +} edma_config_t; + +/*! + * @brief eDMA transfer configuration + * + * This structure configures the source/destination transfer attribute. + * This figure shows the eDMA's transfer model: + * _________________________________________________ + * | Transfer Size | | + * Minor Loop |_______________| Major loop Count 1 | + * Bytes | Transfer Size | | + * ____________|_______________|____________________|--> Minor loop complete + * ____________________________________ + * | | | + * |_______________| Major Loop Count 2 | + * | | | + * |_______________|____________________|--> Minor loop Complete + * + * ---------------------------------------------------------> Transfer complete + */ +typedef struct _edma_transfer_config +{ + uint32_t srcAddr; /*!< Source data address. */ + uint32_t destAddr; /*!< Destination data address. */ + edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ + edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ + int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to + form the next-state value as each source read is completed. */ + int16_t destOffset; /*!< Sign-extended offset applied to the current destination address to + form the next-state value as each destination write is completed. */ + uint32_t minorLoopBytes; /*!< Bytes to transfer in a minor loop*/ + uint32_t majorLoopCounts; /*!< Major loop iteration count. */ +} edma_transfer_config_t; + +/*! @brief eDMA channel priority configuration */ +typedef struct _edma_channel_Preemption_config +{ + bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */ + bool enablePreemptAbility; /*!< If true: a channel can suspend other channel with low priority */ + uint8_t channelPriority; /*!< Channel priority */ +} edma_channel_Preemption_config_t; + +/*! @brief eDMA minor offset configuration */ +typedef struct _edma_minor_offset_config +{ + bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */ + bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */ + uint32_t minorOffset; /*!< Offset for a minor loop mapping. */ +} edma_minor_offset_config_t; + +/*! + * @brief eDMA TCD. + * + * This structure is same as TCD register which is described in reference manual, + * and is used to configure the scatter/gather feature as a next hardware TCD. + */ +typedef struct _edma_tcd +{ + __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ + __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ + __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ + __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ + __IO uint32_t SLAST; /*!< SLAST register */ + __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ + __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ + __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ + __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next stcd address used in scatter-gather mode */ + __IO uint16_t CSR; /*!< CSR register, for TCD control status */ + __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ +} edma_tcd_t; + +/*! @brief Callback for eDMA */ +struct _edma_handle; + +/*! @brief Define callback function for eDMA. */ +typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); + +/*! @brief eDMA transfer handle structure */ +typedef struct _edma_handle +{ + edma_callback callback; /*!< Callback function for major count exhausted. */ + void *userData; /*!< Callback function parameter. */ + DMA_Type *base; /*!< eDMA peripheral base address. */ + edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ + uint8_t channel; /*!< eDMA channel number. */ + volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */ + volatile int8_t tail; /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */ + volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in + the memory. */ + volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */ + uint8_t flags; /*!< The status of the current channel. */ +} edma_handle_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name eDMA initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the eDMA peripheral. + * + * This function ungates the eDMA clock and configures the eDMA peripheral according + * to the configuration structure. + * + * @param base eDMA peripheral base address. + * @param config A pointer to the configuration structure, see "edma_config_t". + * @note This function enables the minor loop map feature. + */ +void EDMA_Init(DMA_Type *base, const edma_config_t *config); + +/*! + * @brief Deinitializes the eDMA peripheral. + * + * This function gates the eDMA clock. + * + * @param base eDMA peripheral base address. + */ +void EDMA_Deinit(DMA_Type *base); + +/*! + * @brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * @code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * @endcode + * + * @param config A pointer to the eDMA configuration structure. + */ +void EDMA_GetDefaultConfig(edma_config_t *config); + +/* @} */ +/*! + * @name eDMA Channel Operation + * @{ + */ + +/*! + * @brief Sets all TCD registers to default values. + * + * This function sets TCD registers for this channel to default values. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @note This function must not be called while the channel transfer is ongoing + * or it causes unpredictable results. + * @note This function enables the auto stop request feature. + */ +void EDMA_ResetChannel(DMA_Type *base, uint32_t channel); + +/*! + * @brief Configures the eDMA transfer attribute. + * + * This function configures the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * @code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * @endcode + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Point to TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note If nextTcd is not NULL, it means scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the eDMA_ResetChannel. + */ +void EDMA_SetTransferConfig(DMA_Type *base, + uint32_t channel, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA minor offset feature. + * + * The minor offset means that the signed-extended value is added to the source address or destination + * address after each minor loop. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config); + +/*! + * @brief Configures the eDMA channel preemption feature. + * + * This function configures the channel preemption attribute and the priority of the channel. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number + * @param config A pointer to the channel preemption configuration structure. + */ +static inline void EDMA_SetChannelPreemptionConfig(DMA_Type *base, + uint32_t channel, + const edma_channel_Preemption_config_t *config) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + + DMA_DCHPRIn(base, channel) = + (DMA_DCHPRI0_DPA(!config->enablePreemptAbility) | DMA_DCHPRI0_ECP(config->enableChannelPreemption) | + DMA_DCHPRI0_CHPRI(config->channelPriority)); +} + +/*! + * @brief Sets the channel link for the eDMA transfer. + * + * This function configures either the minor link or the major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param type A channel link type, which can be one of the following: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + */ +void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); + +/*! + * @brief Sets the bandwidth for the eDMA transfer. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth); + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT +/*! + * @brief Enables an async request for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->EARS = (base->EARS & (~(1U << channel))) | ((uint32_t)enable << channel); +} +#endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */ + +/*! + * @brief Enables an auto stop request for the eDMA transfer. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); +} + +/*! + * @brief Enables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of the interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); + +/* @} */ +/*! + * @name eDMA TCD Operation + * @{ + */ + +/*! + * @brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * @param tcd Pointer to the TCD structure. + * @note This function enables the auto stop request feature. + */ +void EDMA_TcdReset(edma_tcd_t *tcd); + +/*! + * @brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The STCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * @code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * @endcode + * + * @param tcd Pointer to the TCD structure. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note TCD address should be 32 bytes aligned or it causes an eDMA error. + * @note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * @param tcd A point to the TCD structure. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config); + +/*! + * @brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * @param tcd Point to the TCD structure. + * @param type Channel link type, it can be one of: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); + +/*! + * @brief Sets the bandwidth for the eDMA TCD. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * @param tcd A pointer to the TCD structure. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + tcd->CSR = (tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth); +} + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param tcd A pointer to the TCD structure. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +/*! + * @brief Sets the auto stop request for the eDMA TCD. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param tcd A pointer to the TCD structure. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0); + + tcd->CSR = (tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ(enable); +} + +/*! + * @brief Enables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Channel Transfer Operation + * @{ + */ + +/*! + * @brief Enables the eDMA hardware channel request. + * + * This function enables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->SERQ = DMA_SERQ_SERQ(channel); +} + +/*! + * @brief Disables the eDMA hardware channel request. + * + * This function disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CERQ = DMA_CERQ_CERQ(channel); +} + +/*! + * @brief Starts the eDMA transfer by using the software trigger. + * + * This function starts a minor loop transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->SSRT = DMA_SSRT_SSRT(channel); +} + +/*! @} */ +/*! + * @name eDMA Channel Status Operation + * @{ + */ + +/*! + * @brief Gets the remaining major loop count from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the the number of major loop count that has not finished. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return Major loop count which has not been transferred yet for the current TCD. + * @note 1. This function can only be used to get unfinished major loop count of transfer without + * the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while + * the channel is running. + * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO + * register is needed while the eDMA IP does not support getting it while a channel is active. + * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine + * is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example + * copied before enabling the channel) is needed. The formula to calculate it is shown below: + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + */ +uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel); + +/*! + * @brief Gets the eDMA channel error status flags. + * + * @param base eDMA peripheral base address. + * @return The mask of error status flags. Users need to use the +* _edma_error_status_flags type to decode the return variables. + */ +static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base) +{ + return base->ES; +} + +/*! + * @brief Gets the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return The mask of channel status flags. Users need to use the + * _edma_channel_status_flags type to decode the return variables. + */ +uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel); + +/*! + * @brief Clears the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of channel status to be cleared. Users need to use + * the defined _edma_channel_status_flags type. + */ +void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Transactional Operation + */ + +/*! + * @brief Creates the eDMA handle. + * + * This function is called if using the transactional API for eDMA. This function + * initializes the internal state of the eDMA handle. + * + * @param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel); + +/*! + * @brief Installs the TCDs memory pool into the eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. + * + * @param handle eDMA handle pointer. + * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. + * @param tcdSize The number of TCD slots. + */ +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize); + +/*! + * @brief Installs a callback function for the eDMA transfer. + * + * This callback is called in the eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. + * + * @param handle eDMA handle pointer. + * @param callback eDMA callback function pointer. + * @param userData A parameter for the callback function. + */ +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData); + +/*! + * @brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type edma_transfer_t. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @param type eDMA transfer type. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type); + +/*! + * @brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * If submitting the transfer request repeatedly, this function packs an unprocessed request as + * a TCD and enables scatter/gather feature to process it in the next time. + * + * @param handle eDMA handle pointer. + * @param config Pointer to eDMA transfer configuration structure. + * @retval kStatus_EDMA_Success It means submit transfer request succeed. + * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config); + +/*! + * @brief eDMA starts transfer. + * + * This function enables the channel request. Users can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StartTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA stops transfer. + * + * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() + * again to resume the transfer. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StopTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA aborts transfer. + * + * This function disables the channel request and clear transfer status bits. + * Users can submit another transfer after calling this API. + * + * @param handle DMA handle pointer. + */ +void EDMA_AbortTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA IRQ handler for the current major loop transfer completion. + * + * This function clears the channel major interrupt flag and calls + * the callback function if it is not NULL. + * + * Note: + * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. + * These include the final address adjustments and reloading of the BITER field into the CITER. + * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from + * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). + * + * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. + * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index + * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be + * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have + * been loaded into the eDMA engine at this point already.). + * + * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not + * load a new TCD) from the memory pool to the eDMA engine when major loop completes. + * Therefore, ensure that the header and tcdUsed updated are identical for them. + * tcdUsed are both 0 in this case as no TCD to be loaded. + * + * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for + * further details. + * + * @param handle eDMA handle pointer. + */ +void EDMA_HandleIRQ(edma_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_EDMA_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_ewm.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_ewm.c new file mode 100644 index 00000000000..f22eff941e9 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_ewm.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_ewm.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +void EWM_Init(EWM_Type *base, const ewm_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + +#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ + (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Ewm0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif + value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) | + EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt); +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + base->CLKPRESCALER = config->prescaler; +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + base->CLKCTRL = config->clockSource; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ + + base->CMPL = config->compareLowValue; + base->CMPH = config->compareHighValue; + base->CTRL = value; +} + +void EWM_Deinit(EWM_Type *base) +{ + EWM_DisableInterrupts(base, kEWM_InterruptEnable); +#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ + (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Ewm0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */ +} + +void EWM_GetDefaultConfig(ewm_config_t *config) +{ + assert(config); + + config->enableEwm = true; + config->enableEwmInput = false; + config->setInputAssertLogic = false; + config->enableInterrupt = false; +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + config->clockSource = kEWM_LpoClockSource0; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + config->prescaler = 0U; +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + config->compareLowValue = 0U; + config->compareHighValue = 0xFEU; +} + +void EWM_Refresh(EWM_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->SERV = (uint8_t)0xB4U; + base->SERV = (uint8_t)0x2CU; + EnableGlobalIRQ(primaskValue); +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_ewm.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_ewm.h new file mode 100644 index 00000000000..aa32ed3c713 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_ewm.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_EWM_H_ +#define _FSL_EWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ewm + * @{ + */ + + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief EWM driver version 2.0.1. */ +#define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief Describes EWM clock source. */ +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT +typedef enum _ewm_lpo_clock_source +{ + kEWM_LpoClockSource0 = 0U, /*!< EWM clock sourced from lpo_clk[0]*/ + kEWM_LpoClockSource1 = 1U, /*!< EWM clock sourced from lpo_clk[1]*/ + kEWM_LpoClockSource2 = 2U, /*!< EWM clock sourced from lpo_clk[2]*/ + kEWM_LpoClockSource3 = 3U, /*!< EWM clock sourced from lpo_clk[3]*/ +} ewm_lpo_clock_source_t; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ + +/*! +* @brief Data structure for EWM configuration. +* +* This structure is used to configure the EWM. +*/ +typedef struct _ewm_config +{ + bool enableEwm; /*!< Enable EWM module */ + bool enableEwmInput; /*!< Enable EWM_in input */ + bool setInputAssertLogic; /*!< EWM_in signal assertion state */ + bool enableInterrupt; /*!< Enable EWM interrupt */ +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + ewm_lpo_clock_source_t clockSource; /*!< Clock source select */ +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + uint8_t prescaler; /*!< Clock prescaler value */ +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + uint8_t compareLowValue; /*!< Compare low-register value */ + uint8_t compareHighValue; /*!< Compare high-register value */ +} ewm_config_t; + +/*! + * @brief EWM interrupt configuration structure with default settings all disabled. + * + * This structure contains the settings for all of EWM interrupt configurations. + */ +enum _ewm_interrupt_enable_t +{ + kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable the EWM to generate an interrupt*/ +}; + +/*! + * @brief EWM status flags. + * + * This structure contains the constants for the EWM status flags for use in the EWM functions. + */ +enum _ewm_status_flags_t +{ + kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when EWM is enabled*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name EWM initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the EWM peripheral. + * + * This function is used to initialize the EWM. After calling, the EWM + * runs immediately according to the configuration. + * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a + * CPU reset. Modifying them more than once generates a bus transfer error. + * + * This is an example. + * @code + * ewm_config_t config; + * EWM_GetDefaultConfig(&config); + * config.compareHighValue = 0xAAU; + * EWM_Init(ewm_base,&config); + * @endcode + * + * @param base EWM peripheral base address + * @param config The configuration of the EWM +*/ +void EWM_Init(EWM_Type *base, const ewm_config_t *config); + +/*! + * @brief Deinitializes the EWM peripheral. + * + * This function is used to shut down the EWM. + * + * @param base EWM peripheral base address +*/ +void EWM_Deinit(EWM_Type *base); + +/*! + * @brief Initializes the EWM configuration structure. + * + * This function initializes the EWM configuration structure to default values. The default + * values are as follows. + * @code + * ewmConfig->enableEwm = true; + * ewmConfig->enableEwmInput = false; + * ewmConfig->setInputAssertLogic = false; + * ewmConfig->enableInterrupt = false; + * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; + * ewmConfig->prescaler = 0; + * ewmConfig->compareLowValue = 0; + * ewmConfig->compareHighValue = 0xFEU; + * @endcode + * + * @param config Pointer to the EWM configuration structure. + * @see ewm_config_t + */ +void EWM_GetDefaultConfig(ewm_config_t *config); + +/* @} */ + +/*! + * @name EWM functional Operation + * @{ + */ + +/*! + * @brief Enables the EWM interrupt. + * + * This function enables the EWM interrupt. + * + * @param base EWM peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined + * @arg kEWM_InterruptEnable + */ +static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask) +{ + base->CTRL |= mask; +} + +/*! + * @brief Disables the EWM interrupt. + * + * This function enables the EWM interrupt. + * + * @param base EWM peripheral base address + * @param mask The interrupts to disable + * The parameter can be combination of the following source if defined + * @arg kEWM_InterruptEnable + */ +static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask) +{ + base->CTRL &= ~mask; +} + +/*! + * @brief Gets all status flags. + * + * This function gets all status flags. + * + * This is an example for getting the running flag. + * @code + * uint32_t status; + * status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag; + * @endcode + * @param base EWM peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _ewm_status_flags_t + * - True: a related status flag has been set. + * - False: a related status flag is not set. + */ +static inline uint32_t EWM_GetStatusFlags(EWM_Type *base) +{ + return (base->CTRL & EWM_CTRL_EWMEN_MASK); +} + +/*! + * @brief Services the EWM. + * + * This function resets the EWM counter to zero. + * + * @param base EWM peripheral base address +*/ +void EWM_Refresh(EWM_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_EWM_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flash.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flash.c new file mode 100644 index 00000000000..f63e6c98145 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flash.c @@ -0,0 +1,3432 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flash.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name Misc utility defines + * @{ + */ +/*! @brief Alignment utility. */ +#ifndef ALIGN_DOWN +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif +#ifndef ALIGN_UP +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +/*! @brief Join bytes to word utility. */ +#define B1P4(b) (((uint32_t)(b)&0xFFU) << 24) +#define B1P3(b) (((uint32_t)(b)&0xFFU) << 16) +#define B1P2(b) (((uint32_t)(b)&0xFFU) << 8) +#define B1P1(b) ((uint32_t)(b)&0xFFU) +#define B2P3(b) (((uint32_t)(b)&0xFFFFU) << 16) +#define B2P2(b) (((uint32_t)(b)&0xFFFFU) << 8) +#define B2P1(b) ((uint32_t)(b)&0xFFFFU) +#define B3P2(b) (((uint32_t)(b)&0xFFFFFFU) << 8) +#define B3P1(b) ((uint32_t)(b)&0xFFFFFFU) +#define BYTES_JOIN_TO_WORD_1_3(x, y) (B1P4(x) | B3P1(y)) +#define BYTES_JOIN_TO_WORD_2_2(x, y) (B2P3(x) | B2P1(y)) +#define BYTES_JOIN_TO_WORD_3_1(x, y) (B3P2(x) | B1P1(y)) +#define BYTES_JOIN_TO_WORD_1_1_2(x, y, z) (B1P4(x) | B1P3(y) | B2P1(z)) +#define BYTES_JOIN_TO_WORD_1_2_1(x, y, z) (B1P4(x) | B2P2(y) | B1P1(z)) +#define BYTES_JOIN_TO_WORD_2_1_1(x, y, z) (B2P3(x) | B1P2(y) | B1P1(z)) +#define BYTES_JOIN_TO_WORD_1_1_1_1(x, y, z, w) (B1P4(x) | B1P3(y) | B1P2(z) | B1P1(w)) +/*@}*/ + +/*! + * @name Secondary flash configuration + * @{ + */ +/*! @brief Indicates whether the secondary flash has its own protection register in flash module. */ +#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FPROTS_PROTS_MASK) +#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (1) +#else +#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER (0) +#endif + +/*! @brief Indicates whether the secondary flash has its own Execute-Only access register in flash module. */ +#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) && defined(FTFE_FACSSS_SGSIZE_S_MASK) +#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (1) +#else +#define FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER (0) +#endif +/*@}*/ + +/*! + * @name Flash cache ands speculation control defines + * @{ + */ +#if defined(MCM_PLACR_CFCC_MASK) || defined(MCM_CPCR2_CCBC_MASK) +#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (1) +#else +#define FLASH_CACHE_IS_CONTROLLED_BY_MCM (0) +#endif +#if defined(FMC_PFB0CR_CINV_WAY_MASK) || defined(FMC_PFB01CR_CINV_WAY_MASK) +#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (1) +#else +#define FLASH_CACHE_IS_CONTROLLED_BY_FMC (0) +#endif +#if defined(MCM_PLACR_DFCS_MASK) +#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (1) +#else +#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM (0) +#endif +#if defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR_OCMC1_MASK) +#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (1) +#else +#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM (0) +#endif +#if defined(FMC_PFB0CR_S_INV_MASK) || defined(FMC_PFB0CR_S_B_INV_MASK) || defined(FMC_PFB01CR_S_INV_MASK) || \ + defined(FMC_PFB01CR_S_B_INV_MASK) +#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (1) +#else +#define FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC (0) +#endif +/*@}*/ + +/*! @brief Data flash IFR map Field*/ +#if defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8003F8U +#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ +#define DFLASH_IFR_READRESOURCE_START_ADDRESS 0x8000F8U +#endif + +/*! + * @name Reserved FlexNVM size (For a variety of purposes) defines + * @{ + */ +#define FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED 0xFFFFFFFFU +#define FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED 0xFFFFU +/*@}*/ + +/*! + * @name Flash Program Once Field defines + * @{ + */ +#if defined(FSL_FEATURE_FLASH_IS_FTFA) && FSL_FEATURE_FLASH_IS_FTFA +/* FTFA parts(eg. K80, KL80, L5K) support both 4-bytes and 8-bytes unit size */ +#define FLASH_PROGRAM_ONCE_MIN_ID_8BYTES \ + 0x10U /* Minimum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ +#define FLASH_PROGRAM_ONCE_MAX_ID_8BYTES \ + 0x13U /* Maximum Index indcating one of Progam Once Fields which is accessed in 8-byte records */ +#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 +#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 +#elif defined(FSL_FEATURE_FLASH_IS_FTFE) && FSL_FEATURE_FLASH_IS_FTFE +/* FTFE parts(eg. K65, KE18) only support 8-bytes unit size */ +#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 0 +#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 1 +#elif defined(FSL_FEATURE_FLASH_IS_FTFL) && FSL_FEATURE_FLASH_IS_FTFL +/* FTFL parts(eg. K20) only support 4-bytes unit size */ +#define FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT 1 +#define FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT 0 +#endif +/*@}*/ + +/*! + * @name Flash security status defines + * @{ + */ +#define FLASH_SECURITY_STATE_KEYEN 0x80U +#define FLASH_SECURITY_STATE_UNSECURED 0x02U +#define FLASH_NOT_SECURE 0x01U +#define FLASH_SECURE_BACKDOOR_ENABLED 0x02U +#define FLASH_SECURE_BACKDOOR_DISABLED 0x04U +/*@}*/ + +/*! + * @name Flash controller command numbers + * @{ + */ +#define FTFx_VERIFY_BLOCK 0x00U /*!< RD1BLK*/ +#define FTFx_VERIFY_SECTION 0x01U /*!< RD1SEC*/ +#define FTFx_PROGRAM_CHECK 0x02U /*!< PGMCHK*/ +#define FTFx_READ_RESOURCE 0x03U /*!< RDRSRC*/ +#define FTFx_PROGRAM_LONGWORD 0x06U /*!< PGM4*/ +#define FTFx_PROGRAM_PHRASE 0x07U /*!< PGM8*/ +#define FTFx_ERASE_BLOCK 0x08U /*!< ERSBLK*/ +#define FTFx_ERASE_SECTOR 0x09U /*!< ERSSCR*/ +#define FTFx_PROGRAM_SECTION 0x0BU /*!< PGMSEC*/ +#define FTFx_GENERATE_CRC 0x0CU /*!< CRCGEN*/ +#define FTFx_VERIFY_ALL_BLOCK 0x40U /*!< RD1ALL*/ +#define FTFx_READ_ONCE 0x41U /*!< RDONCE or RDINDEX*/ +#define FTFx_PROGRAM_ONCE 0x43U /*!< PGMONCE or PGMINDEX*/ +#define FTFx_ERASE_ALL_BLOCK 0x44U /*!< ERSALL*/ +#define FTFx_SECURITY_BY_PASS 0x45U /*!< VFYKEY*/ +#define FTFx_SWAP_CONTROL 0x46U /*!< SWAP*/ +#define FTFx_ERASE_ALL_BLOCK_UNSECURE 0x49U /*!< ERSALLU*/ +#define FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT 0x4AU /*!< RD1XA*/ +#define FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT 0x4BU /*!< ERSXA*/ +#define FTFx_PROGRAM_PARTITION 0x80U /*!< PGMPART)*/ +#define FTFx_SET_FLEXRAM_FUNCTION 0x81U /*!< SETRAM*/ + /*@}*/ + +/*! + * @name Common flash register info defines + * @{ + */ +#if defined(FTFA) +#define FTFx FTFA +#define FTFx_BASE FTFA_BASE +#define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#elif defined(FTFE) +#define FTFx FTFE +#define FTFx_BASE FTFE_BASE +#define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#elif defined(FTFL) +#define FTFx FTFL +#define FTFx_BASE FTFL_BASE +#define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK +#define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK +#define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK +#define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK +#define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK +#define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK +#define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM +#define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ +#if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM +#define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK +#endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ +#else +#error "Unknown flash controller" +#endif +/*@}*/ + +/*! + * @name Common flash register access info defines + * @{ + */ +#define FTFx_FCCOB3_REG (FTFx->FCCOB3) +#define FTFx_FCCOB5_REG (FTFx->FCCOB5) +#define FTFx_FCCOB6_REG (FTFx->FCCOB6) +#define FTFx_FCCOB7_REG (FTFx->FCCOB7) + +#if defined(FTFA_FPROTH0_PROT_MASK) || defined(FTFE_FPROTH0_PROT_MASK) || defined(FTFL_FPROTH0_PROT_MASK) +#define FTFx_FPROT_HIGH_REG (FTFx->FPROTH3) +#define FTFx_FPROTH3_REG (FTFx->FPROTH3) +#define FTFx_FPROTH2_REG (FTFx->FPROTH2) +#define FTFx_FPROTH1_REG (FTFx->FPROTH1) +#define FTFx_FPROTH0_REG (FTFx->FPROTH0) +#endif + +#if defined(FTFA_FPROTL0_PROT_MASK) || defined(FTFE_FPROTL0_PROT_MASK) || defined(FTFL_FPROTL0_PROT_MASK) +#define FTFx_FPROT_LOW_REG (FTFx->FPROTL3) +#define FTFx_FPROTL3_REG (FTFx->FPROTL3) +#define FTFx_FPROTL2_REG (FTFx->FPROTL2) +#define FTFx_FPROTL1_REG (FTFx->FPROTL1) +#define FTFx_FPROTL0_REG (FTFx->FPROTL0) +#elif defined(FTFA_FPROT0_PROT_MASK) || defined(FTFE_FPROT0_PROT_MASK) || defined(FTFL_FPROT0_PROT_MASK) +#define FTFx_FPROT_LOW_REG (FTFx->FPROT3) +#define FTFx_FPROTL3_REG (FTFx->FPROT3) +#define FTFx_FPROTL2_REG (FTFx->FPROT2) +#define FTFx_FPROTL1_REG (FTFx->FPROT1) +#define FTFx_FPROTL0_REG (FTFx->FPROT0) +#endif + +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER +#define FTFx_FPROTSH_REG (FTFx->FPROTSH) +#define FTFx_FPROTSL_REG (FTFx->FPROTSL) +#endif + +#define FTFx_XACCH3_REG (FTFx->XACCH3) +#define FTFx_XACCL3_REG (FTFx->XACCL3) + +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER +#define FTFx_XACCSH_REG (FTFx->XACCSH) +#define FTFx_XACCSL_REG (FTFx->XACCSL) +#endif +/*@}*/ + +/*! + * @brief Enumeration for access segment property. + */ +enum _flash_access_segment_property +{ + kFLASH_AccessSegmentBase = 256UL, +}; + +/*! + * @brief Enumeration for flash config area. + */ +enum _flash_config_area_range +{ + kFLASH_ConfigAreaStart = 0x400U, + kFLASH_ConfigAreaEnd = 0x40FU +}; + +/*! + * @name Flash register access type defines + * @{ + */ +#define FTFx_REG8_ACCESS_TYPE volatile uint8_t * +#define FTFx_REG32_ACCESS_TYPE volatile uint32_t * +/*@}*/ + +/*! + * @brief MCM cache register access info defines. + */ +#if defined(MCM_PLACR_CFCC_MASK) +#define MCM_CACHE_CLEAR_MASK MCM_PLACR_CFCC_MASK +#define MCM_CACHE_CLEAR_SHIFT MCM_PLACR_CFCC_SHIFT +#if defined(MCM) +#define MCM0_CACHE_REG MCM->PLACR +#elif defined(MCM0) +#define MCM0_CACHE_REG MCM0->PLACR +#endif +#if defined(MCM1) +#define MCM1_CACHE_REG MCM1->PLACR +#endif +#elif defined(MCM_CPCR2_CCBC_MASK) +#define MCM_CACHE_CLEAR_MASK MCM_CPCR2_CCBC_MASK +#define MCM_CACHE_CLEAR_SHIFT MCM_CPCR2_CCBC_SHIFT +#if defined(MCM) +#define MCM0_CACHE_REG MCM->CPCR2 +#elif defined(MCM0) +#define MCM0_CACHE_REG MCM0->CPCR2 +#endif +#if defined(MCM1) +#define MCM1_CACHE_REG MCM1->CPCR2 +#endif +#endif + +/*! + * @brief MSCM cache register access info defines. + */ +#if defined(MSCM_OCMDR_OCM1_MASK) +#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR_OCM1_MASK +#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR_OCM1_SHIFT +#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR_OCM1(x) +#elif defined(MSCM_OCMDR_OCMC1_MASK) +#define MSCM_SPECULATION_DISABLE_MASK MSCM_OCMDR_OCMC1_MASK +#define MSCM_SPECULATION_DISABLE_SHIFT MSCM_OCMDR_OCMC1_SHIFT +#define MSCM_SPECULATION_DISABLE(x) MSCM_OCMDR_OCMC1(x) +#endif + +/*! + * @brief MSCM prefetch speculation defines. + */ +#define MSCM_OCMDR_OCMC1_DFDS_MASK (0x10U) +#define MSCM_OCMDR_OCMC1_DFCS_MASK (0x20U) + +#define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U) +#define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U) + +/*! + * @brief Flash size encoding rule. + */ +#define FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2 (0x00U) +#define FLASH_MEMORY_SIZE_ENCODING_RULE_K3 (0x01U) + +#if defined(K32W042S1M2_M0P_SERIES) || defined(K32W042S1M2_M4_SERIES) +#define FLASH_MEMORY_SIZE_ENCODING_RULE (FLASH_MEMORY_SIZE_ENCODING_RULE_K3) +#else +#define FLASH_MEMORY_SIZE_ENCODING_RULE (FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2) +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! @brief Copy flash_run_command() to RAM*/ +static void copy_flash_run_command(uint32_t *flashRunCommand); +/*! @brief Copy flash_cache_clear_command() to RAM*/ +static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation); +/*! @brief Check whether flash execute-in-ram functions are ready*/ +static status_t flash_check_execute_in_ram_function_info(flash_config_t *config); +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! @brief Internal function Flash command sequence. Called by driver APIs only*/ +static status_t flash_command_sequence(flash_config_t *config); + +/*! @brief Perform the cache clear to the flash*/ +void flash_cache_clear(flash_config_t *config); + +/*! @brief Process the cache to the flash*/ +static void flash_cache_clear_process(flash_config_t *config, flash_cache_clear_process_t process); + +/*! @brief Validates the range and alignment of the given address range.*/ +static status_t flash_check_range(flash_config_t *config, + uint32_t startAddress, + uint32_t lengthInBytes, + uint32_t alignmentBaseline); +/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ +static status_t flash_get_matched_operation_info(flash_config_t *config, + uint32_t address, + flash_operation_config_t *info); +/*! @brief Validates the given user key for flash erase APIs.*/ +static status_t flash_check_user_key(uint32_t key); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ +static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config); +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +/*! @brief Validates the range of the given resource address.*/ +static status_t flash_check_resource_range(uint32_t start, + uint32_t lengthInBytes, + uint32_t alignmentBaseline, + flash_read_resource_option_t option); +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +/*! @brief Validates the gived swap control option.*/ +static status_t flash_check_swap_control_option(flash_swap_control_option_t option); +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ +static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address); +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +/*! @brief Validates the gived flexram function option.*/ +static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option); +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + +/*! @brief Gets the flash protection information (region size, region count).*/ +static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info); + +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL +/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/ +static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info); +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + +#if FLASH_CACHE_IS_CONTROLLED_BY_MCM +/*! @brief Performs the cache clear to the flash by MCM.*/ +void mcm_flash_cache_clear(flash_config_t *config); +#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */ + +#if FLASH_CACHE_IS_CONTROLLED_BY_FMC +/*! @brief Performs the cache clear to the flash by FMC.*/ +void fmc_flash_cache_clear(void); +#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */ + +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM +/*! @brief Sets the prefetch speculation buffer to the flash by MSCM.*/ +void mscm_flash_prefetch_speculation_enable(bool enable); +#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */ + +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC +/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/ +void fmc_flash_prefetch_speculation_clear(void); +#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Access to FTFx->FCCOB */ +volatile uint32_t *const kFCCOBx = (volatile uint32_t *)&FTFx_FCCOB3_REG; +/*! @brief Access to FTFx->FPROT */ +volatile uint32_t *const kFPROTL = (volatile uint32_t *)&FTFx_FPROT_LOW_REG; +#if defined(FTFx_FPROT_HIGH_REG) +volatile uint32_t *const kFPROTH = (volatile uint32_t *)&FTFx_FPROT_HIGH_REG; +#endif + +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER +volatile uint8_t *const kFPROTSL = (volatile uint8_t *)&FTFx_FPROTSL_REG; +volatile uint8_t *const kFPROTSH = (volatile uint8_t *)&FTFx_FPROTSH_REG; +#endif + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! @brief A function pointer used to point to relocated flash_run_command() */ +static void (*callFlashRunCommand)(FTFx_REG8_ACCESS_TYPE ftfx_fstat); +/*! @brief A function pointer used to point to relocated flash_common_bit_operation() */ +static void (*callFlashCommonBitOperation)(FTFx_REG32_ACCESS_TYPE base, + uint32_t bitMask, + uint32_t bitShift, + uint32_t bitValue); + +/*! + * @brief Position independent code of flash_run_command() + * + * Note1: The prototype of C function is shown as below: + * @code + * void flash_run_command(FTFx_REG8_ACCESS_TYPE ftfx_fstat) + * { + * // clear CCIF bit + * *ftfx_fstat = FTFx_FSTAT_CCIF_MASK; + * + * // Check CCIF bit of the flash status register, wait till it is set. + * // IP team indicates that this loop will always complete. + * while (!((*ftfx_fstat) & FTFx_FSTAT_CCIF_MASK)) + * { + * } + * } + * @endcode + * Note2: The binary code is generated by IAR 7.70.1 + */ +const static uint16_t s_flashRunCommandFunctionCode[] = { + 0x2180, /* MOVS R1, #128 ; 0x80 */ + 0x7001, /* STRB R1, [R0] */ + /* @4: */ + 0x7802, /* LDRB R2, [R0] */ + 0x420a, /* TST R2, R1 */ + 0xd0fc, /* BEQ.N @4 */ + 0x4770 /* BX LR */ +}; + +/*! + * @brief Position independent code of flash_common_bit_operation() + * + * Note1: The prototype of C function is shown as below: + * @code + * void flash_common_bit_operation(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, uint32_t + * bitValue) + * { + * if (bitMask) + * { + * uint32_t value = (((uint32_t)(((uint32_t)(bitValue)) << bitShift)) & bitMask); + * *base = (*base & (~bitMask)) | value; + * } + * + * __ISB(); + * __DSB(); + * } + * @endcode + * Note2: The binary code is generated by IAR 7.70.1 + */ +const static uint16_t s_flashCommonBitOperationFunctionCode[] = { + 0xb510, /* PUSH {R4, LR} */ + 0x2900, /* CMP R1, #0 */ + 0xd005, /* BEQ.N @12 */ + 0x6804, /* LDR R4, [R0] */ + 0x438c, /* BICS R4, R4, R1 */ + 0x4093, /* LSLS R3, R3, R2 */ + 0x4019, /* ANDS R1, R1, R3 */ + 0x4321, /* ORRS R1, R1, R4 */ + 0x6001, /* STR R1, [R0] */ + /* @12: */ + 0xf3bf, 0x8f6f, /* ISB */ + 0xf3bf, 0x8f4f, /* DSB */ + 0xbd10 /* POP {R4, PC} */ +}; +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) +/*! @brief A static buffer used to hold flash_run_command() */ +static uint32_t s_flashRunCommand[kFLASH_ExecuteInRamFunctionMaxSizeInWords]; +/*! @brief A static buffer used to hold flash_common_bit_operation() */ +static uint32_t s_flashCommonBitOperation[kFLASH_ExecuteInRamFunctionMaxSizeInWords]; +/*! @brief Flash execute-in-ram function information */ +static flash_execute_in_ram_function_config_t s_flashExecuteInRamFunctionInfo; +#endif + +/*! + * @brief Table of pflash sizes. + * + * The index into this table is the value of the SIM_FCFG1.PFSIZE bitfield. + * + * The values in this table have been right shifted 10 bits so that they will all fit within + * an 16-bit integer. To get the actual flash density, you must left shift the looked up value + * by 10 bits. + * + * Elements of this table have a value of 0 in cases where the PFSIZE bitfield value is + * reserved. + * + * Code to use the table: + * @code + * uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; + * flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; + * @endcode + */ +#if (FLASH_MEMORY_SIZE_ENCODING_RULE == FLASH_MEMORY_SIZE_ENCODING_RULE_K1_2) +const uint16_t kPFlashDensities[] = { + 8, /* 0x0 - 8192, 8KB */ + 16, /* 0x1 - 16384, 16KB */ + 24, /* 0x2 - 24576, 24KB */ + 32, /* 0x3 - 32768, 32KB */ + 48, /* 0x4 - 49152, 48KB */ + 64, /* 0x5 - 65536, 64KB */ + 96, /* 0x6 - 98304, 96KB */ + 128, /* 0x7 - 131072, 128KB */ + 192, /* 0x8 - 196608, 192KB */ + 256, /* 0x9 - 262144, 256KB */ + 384, /* 0xa - 393216, 384KB */ + 512, /* 0xb - 524288, 512KB */ + 768, /* 0xc - 786432, 768KB */ + 1024, /* 0xd - 1048576, 1MB */ + 1536, /* 0xe - 1572864, 1.5MB */ + /* 2048, 0xf - 2097152, 2MB */ +}; +#elif(FLASH_MEMORY_SIZE_ENCODING_RULE == FLASH_MEMORY_SIZE_ENCODING_RULE_K3) +const uint16_t kPFlashDensities[] = { + 0, /* 0x0 - undefined */ + 0, /* 0x1 - undefined */ + 0, /* 0x2 - undefined */ + 0, /* 0x3 - undefined */ + 0, /* 0x4 - undefined */ + 0, /* 0x5 - undefined */ + 0, /* 0x6 - undefined */ + 0, /* 0x7 - undefined */ + 0, /* 0x8 - undefined */ + 0, /* 0x9 - undefined */ + 256, /* 0xa - 262144, 256KB */ + 0, /* 0xb - undefined */ + 1024, /* 0xc - 1048576, 1MB */ + 0, /* 0xd - undefined */ + 0, /* 0xe - undefined */ + 0, /* 0xf - undefined */ +}; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t FLASH_Init(flash_config_t *config) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED + if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) + { +/* calculate the flash density from SIM_FCFG1.PFSIZE */ +#if defined(SIM_FCFG1_CORE1_PFSIZE_MASK) + uint32_t flashDensity; + uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE1_PFSIZE_MASK) >> SIM_FCFG1_CORE1_PFSIZE_SHIFT; + if (pfsize == 0xf) + { + flashDensity = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; + } + else + { + flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; + } + config->PFlashTotalSize = flashDensity; +#else + /* Unused code to solve MISRA-C issue*/ + config->PFlashBlockBase = kPFlashDensities[0]; + config->PFlashTotalSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; +#endif + config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS; + config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT; + config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE; + } + else +#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */ + { + uint32_t flashDensity; + +/* calculate the flash density from SIM_FCFG1.PFSIZE */ +#if defined(SIM_FCFG1_CORE0_PFSIZE_MASK) + uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_CORE0_PFSIZE_MASK) >> SIM_FCFG1_CORE0_PFSIZE_SHIFT; +#elif defined(SIM_FCFG1_PFSIZE_MASK) + uint8_t pfsize = (SIM->FCFG1 & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT; +#else +#error "Unknown flash size" +#endif + /* PFSIZE=0xf means that on customer parts the IFR was not correctly programmed. + * We just use the pre-defined flash size in feature file here to support pre-production parts */ + if (pfsize == 0xf) + { + flashDensity = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE; + } + else + { + flashDensity = ((uint32_t)kPFlashDensities[pfsize]) << 10; + } + + /* fill out a few of the structure members */ + config->PFlashBlockBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS; + config->PFlashTotalSize = flashDensity; + config->PFlashBlockCount = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; + config->PFlashSectorSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE; + } + + { +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER + if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) + { + config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSSS; + config->PFlashAccessSegmentCount = FTFx->FACSNS; + } + else +#endif + { + config->PFlashAccessSegmentSize = kFLASH_AccessSegmentBase << FTFx->FACSS; + config->PFlashAccessSegmentCount = FTFx->FACSN; + } +#else + config->PFlashAccessSegmentSize = 0; + config->PFlashAccessSegmentCount = 0; +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + } + + config->PFlashCallback = NULL; + +/* copy required flash commands to RAM */ +#if (FLASH_DRIVER_IS_FLASH_RESIDENT && !FLASH_DRIVER_IS_EXPORTED) + if (kStatus_FLASH_Success != flash_check_execute_in_ram_function_info(config)) + { + s_flashExecuteInRamFunctionInfo.activeFunctionCount = 0; + s_flashExecuteInRamFunctionInfo.flashRunCommand = s_flashRunCommand; + s_flashExecuteInRamFunctionInfo.flashCommonBitOperation = s_flashCommonBitOperation; + config->flashExecuteInRamFunctionInfo = &s_flashExecuteInRamFunctionInfo.activeFunctionCount; + FLASH_PrepareExecuteInRamFunctions(config); + } +#endif + + config->FlexRAMBlockBase = FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS; + config->FlexRAMTotalSize = FSL_FEATURE_FLASH_FLEX_RAM_SIZE; + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + { + status_t returnCode; + config->DFlashBlockBase = FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS; + returnCode = flash_update_flexnvm_memory_partition_status(config); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + } +#endif + + return kStatus_FLASH_Success; +} + +status_t FLASH_SetCallback(flash_config_t *config, flash_callback_t callback) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + config->PFlashCallback = callback; + + return kStatus_FLASH_Success; +} + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +status_t FLASH_PrepareExecuteInRamFunctions(flash_config_t *config) +{ + flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; + + copy_flash_run_command(flashExecuteInRamFunctionInfo->flashRunCommand); + copy_flash_common_bit_operation(flashExecuteInRamFunctionInfo->flashCommonBitOperation); + flashExecuteInRamFunctionInfo->activeFunctionCount = kFLASH_ExecuteInRamFunctionTotalNum; + + return kStatus_FLASH_Success; +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +status_t FLASH_EraseAll(flash_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to erase all flash blocks */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + /* Data flash IFR will be erased by erase all command, so we need to + * update FlexNVM memory partition status synchronously */ + if (returnCode == kStatus_FLASH_Success) + { + returnCode = flash_update_flexnvm_memory_partition_status(config); + } +#endif + + return returnCode; +} + +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + uint32_t sectorSize; + flash_operation_config_t flashOperationInfo; + uint32_t endAddress; /* storing end address */ + uint32_t numberOfSectors; /* number of sectors calculated by endAddress */ + status_t returnCode; + + flash_get_matched_operation_info(config, start, &flashOperationInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectorCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + start = flashOperationInfo.convertedAddress; + sectorSize = flashOperationInfo.activeSectorSize; + + /* calculating Flash end address */ + endAddress = start + lengthInBytes - 1; + + /* re-calculate the endAddress and align it to the start of the next sector + * which will be used in the comparison below */ + if (endAddress % sectorSize) + { + numberOfSectors = endAddress / sectorSize + 1; + endAddress = numberOfSectors * sectorSize - 1; + } + + flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); + + /* the start address will increment to the next sector address + * until it reaches the endAdddress */ + while (start <= endAddress) + { + /* preparing passing parameter to erase a flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_SECTOR, start); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + /* calling flash callback function if it is available */ + if (config->PFlashCallback) + { + config->PFlashCallback(); + } + + /* checking the success of command execution */ + if (kStatus_FLASH_Success != returnCode) + { + break; + } + else + { + /* Increment to the next sector */ + start += sectorSize; + } + } + + flash_cache_clear(config); + + return (returnCode); +} + +#if defined(FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD) && FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD +status_t FLASH_EraseAllUnsecure(flash_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Prepare passing parameter to erase all flash blocks (unsecure). */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_BLOCK_UNSECURE, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + /* Data flash IFR will be erased by erase all unsecure command, so we need to + * update FlexNVM memory partition status synchronously */ + if (returnCode == kStatus_FLASH_Success) + { + returnCode = flash_update_flexnvm_memory_partition_status(config); + } +#endif + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD */ + +status_t FLASH_EraseAllExecuteOnlySegments(flash_config_t *config, uint32_t key) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to erase all execute-only segments + * 1st element for the FCCOB register */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_ERASE_ALL_EXECUTE_ONLY_SEGMENT, 0xFFFFFFU); + + /* Validate the user key */ + returnCode = flash_check_user_key(key); + if (returnCode) + { + return returnCode; + } + + flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + + return returnCode; +} + +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + flash_operation_config_t flashOperationInfo; + + if (src == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashOperationInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.blockWriteUnitSize); + if (returnCode) + { + return returnCode; + } + + start = flashOperationInfo.convertedAddress; + + flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); + + while (lengthInBytes > 0) + { + /* preparing passing parameter to program the flash block */ + kFCCOBx[1] = *src++; + if (4 == flashOperationInfo.blockWriteUnitSize) + { + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_LONGWORD, start); + } + else if (8 == flashOperationInfo.blockWriteUnitSize) + { + kFCCOBx[2] = *src++; + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_PHRASE, start); + } + else + { + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + /* calling flash callback function if it is available */ + if (config->PFlashCallback) + { + config->PFlashCallback(); + } + + /* checking for the success of command execution */ + if (kStatus_FLASH_Success != returnCode) + { + break; + } + else + { + /* update start address for next iteration */ + start += flashOperationInfo.blockWriteUnitSize; + + /* update lengthInBytes for next iteration */ + lengthInBytes -= flashOperationInfo.blockWriteUnitSize; + } + } + + flash_cache_clear(config); + + return (returnCode); +} + +status_t FLASH_ProgramOnce(flash_config_t *config, uint32_t index, uint32_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + + if ((config == NULL) || (src == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* pass paramters to FTFx */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_PROGRAM_ONCE, index, 0xFFFFU); + + kFCCOBx[1] = *src; + +/* Note: Have to seperate the first index from the rest if it equals 0 + * to avoid a pointless comparison of unsigned int to 0 compiler warning */ +#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT +#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT + if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || + /* Range check */ + ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && + (lengthInBytes == 8)) +#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ + { + kFCCOBx[2] = *(src + 1); + } +#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ + + flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + + return returnCode; +} + +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD +status_t FLASH_ProgramSection(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + uint32_t sectorSize; + flash_operation_config_t flashOperationInfo; +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + bool needSwitchFlexRamMode = false; +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + if (src == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashOperationInfo); + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + start = flashOperationInfo.convertedAddress; + sectorSize = flashOperationInfo.activeSectorSize; + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /* Switch function of FlexRAM if needed */ + if (!(FTFx->FCNFG & FTFx_FCNFG_RAMRDY_MASK)) + { + needSwitchFlexRamMode = true; + + returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_SetFlexramAsRamError; + } + } +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); + + while (lengthInBytes > 0) + { + /* Make sure the write operation doesn't span two sectors */ + uint32_t endAddressOfCurrentSector = ALIGN_UP(start, sectorSize); + uint32_t lengthTobeProgrammedOfCurrentSector; + uint32_t currentOffset = 0; + + if (endAddressOfCurrentSector == start) + { + endAddressOfCurrentSector += sectorSize; + } + + if (lengthInBytes + start > endAddressOfCurrentSector) + { + lengthTobeProgrammedOfCurrentSector = endAddressOfCurrentSector - start; + } + else + { + lengthTobeProgrammedOfCurrentSector = lengthInBytes; + } + + /* Program Current Sector */ + while (lengthTobeProgrammedOfCurrentSector > 0) + { + /* Make sure the program size doesn't exceeds Acceleration RAM size */ + uint32_t programSizeOfCurrentPass; + uint32_t numberOfPhases; + + if (lengthTobeProgrammedOfCurrentSector > kFLASH_AccelerationRamSize) + { + programSizeOfCurrentPass = kFLASH_AccelerationRamSize; + } + else + { + programSizeOfCurrentPass = lengthTobeProgrammedOfCurrentSector; + } + + /* Copy data to FlexRAM */ + memcpy((void *)FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS, src + currentOffset / 4, programSizeOfCurrentPass); + /* Set start address of the data to be programmed */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_SECTION, start + currentOffset); + /* Set program size in terms of FEATURE_FLASH_SECTION_CMD_ADDRESS_ALIGMENT */ + numberOfPhases = programSizeOfCurrentPass / flashOperationInfo.sectionCmdAddressAligment; + + kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_2(numberOfPhases, 0xFFFFU); + + /* Peform command sequence */ + returnCode = flash_command_sequence(config); + + /* calling flash callback function if it is available */ + if (config->PFlashCallback) + { + config->PFlashCallback(); + } + + if (returnCode != kStatus_FLASH_Success) + { + flash_cache_clear(config); + return returnCode; + } + + lengthTobeProgrammedOfCurrentSector -= programSizeOfCurrentPass; + currentOffset += programSizeOfCurrentPass; + } + + src += currentOffset / 4; + start += currentOffset; + lengthInBytes -= currentOffset; + } + + flash_cache_clear(config); + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD + /* Restore function of FlexRAM if needed. */ + if (needSwitchFlexRamMode) + { + returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_RecoverFlexramAsEepromError; + } + } +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromWrite(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + status_t returnCode; + bool needSwitchFlexRamMode = false; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Validates the range of the given address */ + if ((start < config->FlexRAMBlockBase) || + ((start + lengthInBytes) > (config->FlexRAMBlockBase + config->EEpromTotalSize))) + { + return kStatus_FLASH_AddressError; + } + + returnCode = kStatus_FLASH_Success; + + /* Switch function of FlexRAM if needed */ + if (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) + { + needSwitchFlexRamMode = true; + + returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableForEeprom); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_SetFlexramAsEepromError; + } + } + + /* Write data to FlexRAM when it is used as EEPROM emulator */ + while (lengthInBytes > 0) + { + if ((!(start & 0x3U)) && (lengthInBytes >= 4)) + { + *(uint32_t *)start = *(uint32_t *)src; + start += 4; + src += 4; + lengthInBytes -= 4; + } + else if ((!(start & 0x1U)) && (lengthInBytes >= 2)) + { + *(uint16_t *)start = *(uint16_t *)src; + start += 2; + src += 2; + lengthInBytes -= 2; + } + else + { + *(uint8_t *)start = *src; + start += 1; + src += 1; + lengthInBytes -= 1; + } + /* Wait till EEERDY bit is set */ + while (!(FTFx->FCNFG & FTFx_FCNFG_EEERDY_MASK)) + { + } + + /* Check for protection violation error */ + if (FTFx->FSTAT & FTFx_FSTAT_FPVIOL_MASK) + { + return kStatus_FLASH_ProtectionViolation; + } + } + + /* Switch function of FlexRAM if needed */ + if (needSwitchFlexRamMode) + { + returnCode = FLASH_SetFlexramFunction(config, kFLASH_FlexramFunctionOptionAvailableAsRam); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_RecoverFlexramAsRamError; + } + } + + return returnCode; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +status_t FLASH_ReadResource( + flash_config_t *config, uint32_t start, uint32_t *dst, uint32_t lengthInBytes, flash_read_resource_option_t option) +{ + status_t returnCode; + flash_operation_config_t flashOperationInfo; + + if ((config == NULL) || (dst == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashOperationInfo); + + /* Check the supplied address range. */ + returnCode = + flash_check_resource_range(start, lengthInBytes, flashOperationInfo.resourceCmdAddressAligment, option); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + + while (lengthInBytes > 0) + { + /* preparing passing parameter */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_READ_RESOURCE, start); + if (flashOperationInfo.resourceCmdAddressAligment == 4) + { + kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); + } + else if (flashOperationInfo.resourceCmdAddressAligment == 8) + { + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); + } + else + { + } + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + if (kStatus_FLASH_Success != returnCode) + { + break; + } + + /* fetch data */ + *dst++ = kFCCOBx[1]; + if (flashOperationInfo.resourceCmdAddressAligment == 8) + { + *dst++ = kFCCOBx[2]; + } + /* update start address for next iteration */ + start += flashOperationInfo.resourceCmdAddressAligment; + /* update lengthInBytes for next iteration */ + lengthInBytes -= flashOperationInfo.resourceCmdAddressAligment; + } + + return (returnCode); +} +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +status_t FLASH_ReadOnce(flash_config_t *config, uint32_t index, uint32_t *dst, uint32_t lengthInBytes) +{ + status_t returnCode; + + if ((config == NULL) || (dst == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* pass paramters to FTFx */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_READ_ONCE, index, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + if (kStatus_FLASH_Success == returnCode) + { + *dst = kFCCOBx[1]; +/* Note: Have to seperate the first index from the rest if it equals 0 + * to avoid a pointless comparison of unsigned int to 0 compiler warning */ +#if FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT +#if FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT + if (((index == FLASH_PROGRAM_ONCE_MIN_ID_8BYTES) || + /* Range check */ + ((index >= FLASH_PROGRAM_ONCE_MIN_ID_8BYTES + 1) && (index <= FLASH_PROGRAM_ONCE_MAX_ID_8BYTES))) && + (lengthInBytes == 8)) +#endif /* FLASH_PROGRAM_ONCE_IS_4BYTES_UNIT_SUPPORT */ + { + *(dst + 1) = kFCCOBx[2]; + } +#endif /* FLASH_PROGRAM_ONCE_IS_8BYTES_UNIT_SUPPORT */ + } + + return returnCode; +} + +status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state) +{ + /* store data read from flash register */ + uint8_t registerValue; + + if ((config == NULL) || (state == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Get flash security register value */ + registerValue = FTFx->FSEC; + + /* check the status of the flash security bits in the security register */ + if (FLASH_SECURITY_STATE_UNSECURED == (registerValue & FTFx_FSEC_SEC_MASK)) + { + /* Flash in unsecured state */ + *state = kFLASH_SecurityStateNotSecure; + } + else + { + /* Flash in secured state + * check for backdoor key security enable bit */ + if (FLASH_SECURITY_STATE_KEYEN == (registerValue & FTFx_FSEC_KEYEN_MASK)) + { + /* Backdoor key security enabled */ + *state = kFLASH_SecurityStateBackdoorEnabled; + } + else + { + /* Backdoor key security disabled */ + *state = kFLASH_SecurityStateBackdoorDisabled; + } + } + + return (kStatus_FLASH_Success); +} + +status_t FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey) +{ + uint8_t registerValue; /* registerValue */ + status_t returnCode; /* return code variable */ + + if ((config == NULL) || (backdoorKey == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + /* set the default return code as kStatus_Success */ + returnCode = kStatus_FLASH_Success; + + /* Get flash security register value */ + registerValue = FTFx->FSEC; + + /* Check to see if flash is in secure state (any state other than 0x2) + * If not, then skip this since flash is not secure */ + if (0x02 != (registerValue & 0x03)) + { + /* preparing passing parameter to erase a flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SECURITY_BY_PASS, 0xFFFFFFU); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[0], backdoorKey[1], backdoorKey[2], backdoorKey[3]); + kFCCOBx[2] = BYTES_JOIN_TO_WORD_1_1_1_1(backdoorKey[4], backdoorKey[5], backdoorKey[6], backdoorKey[7]); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + } + + return (returnCode); +} + +status_t FLASH_VerifyEraseAll(flash_config_t *config, flash_margin_value_t margin) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to verify all block command */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_BLOCK, margin, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return flash_command_sequence(config); +} + +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, flash_margin_value_t margin) +{ + /* Check arguments. */ + uint32_t blockSize; + flash_operation_config_t flashOperationInfo; + uint32_t nextBlockStartAddress; + uint32_t remainingBytes; + status_t returnCode; + + flash_get_matched_operation_info(config, start, &flashOperationInfo); + + returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.sectionCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + flash_get_matched_operation_info(config, start, &flashOperationInfo); + start = flashOperationInfo.convertedAddress; + blockSize = flashOperationInfo.activeBlockSize; + + nextBlockStartAddress = ALIGN_UP(start, blockSize); + if (nextBlockStartAddress == start) + { + nextBlockStartAddress += blockSize; + } + + remainingBytes = lengthInBytes; + + while (remainingBytes) + { + uint32_t numberOfPhrases; + uint32_t verifyLength = nextBlockStartAddress - start; + if (verifyLength > remainingBytes) + { + verifyLength = remainingBytes; + } + + numberOfPhrases = verifyLength / flashOperationInfo.sectionCmdAddressAligment; + + /* Fill in verify section command parameters. */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_VERIFY_SECTION, start); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_2_1_1(numberOfPhrases, margin, 0xFFU); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + if (returnCode) + { + return returnCode; + } + + remainingBytes -= verifyLength; + start += verifyLength; + nextBlockStartAddress += blockSize; + } + + return kStatus_FLASH_Success; +} + +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint32_t *expectedData, + flash_margin_value_t margin, + uint32_t *failedAddress, + uint32_t *failedData) +{ + status_t returnCode; + flash_operation_config_t flashOperationInfo; + + if (expectedData == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flash_get_matched_operation_info(config, start, &flashOperationInfo); + + returnCode = flash_check_range(config, start, lengthInBytes, flashOperationInfo.checkCmdAddressAligment); + if (returnCode) + { + return returnCode; + } + + start = flashOperationInfo.convertedAddress; + + while (lengthInBytes) + { + /* preparing passing parameter to program check the flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_PROGRAM_CHECK, start); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(margin, 0xFFFFFFU); + kFCCOBx[2] = *expectedData; + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + /* checking for the success of command execution */ + if (kStatus_FLASH_Success != returnCode) + { + if (failedAddress) + { + *failedAddress = start; + } + if (failedData) + { + *failedData = 0; + } + break; + } + + lengthInBytes -= flashOperationInfo.checkCmdAddressAligment; + expectedData += flashOperationInfo.checkCmdAddressAligment / sizeof(*expectedData); + start += flashOperationInfo.checkCmdAddressAligment; + } + + return (returnCode); +} + +status_t FLASH_VerifyEraseAllExecuteOnlySegments(flash_config_t *config, flash_margin_value_t margin) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* preparing passing parameter to verify erase all execute-only segments command */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_VERIFY_ALL_EXECUTE_ONLY_SEGMENT, margin, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return flash_command_sequence(config); +} + +status_t FLASH_IsProtected(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_protection_state_t *protection_state) +{ + uint32_t endAddress; /* end address for protection check */ + uint32_t regionCheckedCounter; /* increments each time the flash address was checked for + * protection status */ + uint32_t regionCounter; /* incrementing variable used to increment through the flash + * protection regions */ + uint32_t protectStatusCounter; /* increments each time a flash region was detected as protected */ + + uint8_t flashRegionProtectStatus[FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT]; /* array of the protection + * status for each + * protection region */ + uint32_t flashRegionAddress[FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT + + 1]; /* array of the start addresses for each flash + * protection region. Note this is REGION_COUNT+1 + * due to requiring the next start address after + * the end of flash for loop-check purposes below */ + flash_protection_config_t flashProtectionInfo; /* flash protection information */ + status_t returnCode; + + if (protection_state == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); + if (returnCode) + { + return returnCode; + } + + /* Get necessary flash protection information. */ + returnCode = flash_get_protection_info(config, &flashProtectionInfo); + if (returnCode) + { + return returnCode; + } + + /* calculating Flash end address */ + endAddress = start + lengthInBytes; + + /* populate the flashRegionAddress array with the start address of each flash region */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + + /* populate up to 33rd element of array, this is the next address after end of flash array */ + while (regionCounter <= flashProtectionInfo.regionCount) + { + flashRegionAddress[regionCounter] = + flashProtectionInfo.regionBase + flashProtectionInfo.regionSize * regionCounter; + regionCounter++; + } + + /* populate flashRegionProtectStatus array with status information + * Protection status for each region is stored in the FPROT[3:0] registers + * Each bit represents one region of flash + * 4 registers * 8-bits-per-register = 32-bits (32-regions) + * The convention is: + * FPROT3[bit 0] is the first protection region (start of flash memory) + * FPROT0[bit 7] is the last protection region (end of flash memory) + * regionCounter is used to determine which FPROT[3:0] register to check for protection status + * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + while (regionCounter < flashProtectionInfo.regionCount) + { +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER + if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) + { + if (regionCounter < 8) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSL_REG >> regionCounter) & (0x01u); + } + else if ((regionCounter >= 8) && (regionCounter < 16)) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTSH_REG >> (regionCounter - 8)) & (0x01u); + } + else + { + break; + } + } + else +#endif + { + /* Note: So far protection region count may be 16/20/24/32/64 */ + if (regionCounter < 8) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL3_REG >> regionCounter) & (0x01u); + } + else if ((regionCounter >= 8) && (regionCounter < 16)) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL2_REG >> (regionCounter - 8)) & (0x01u); + } +#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT > 16) +#if (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 20) + else if ((regionCounter >= 16) && (regionCounter < 20)) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u); + } +#else + else if ((regionCounter >= 16) && (regionCounter < 24)) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL1_REG >> (regionCounter - 16)) & (0x01u); + } +#endif /* (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 20) */ +#endif +#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT > 24) + else if ((regionCounter >= 24) && (regionCounter < 32)) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTL0_REG >> (regionCounter - 24)) & (0x01u); + } +#endif +#if defined(FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT) && \ + (FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT == 64) + else if (regionCounter < 40) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH3_REG >> (regionCounter - 32)) & (0x01u); + } + else if (regionCounter < 48) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH2_REG >> (regionCounter - 40)) & (0x01u); + } + else if (regionCounter < 56) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH1_REG >> (regionCounter - 48)) & (0x01u); + } + else if (regionCounter < 64) + { + flashRegionProtectStatus[regionCounter] = (FTFx_FPROTH0_REG >> (regionCounter - 56)) & (0x01u); + } +#endif + else + { + break; + } + } + + regionCounter++; + } + + /* loop through the flash regions and check + * desired flash address range for protection status + * loop stops when it is detected that start has exceeded the endAddress */ + regionCounter = 0; /* make sure regionCounter is initialized to 0 first */ + regionCheckedCounter = 0; + protectStatusCounter = 0; /* make sure protectStatusCounter is initialized to 0 first */ + while (start < endAddress) + { + /* check to see if the address falls within this protection region + * Note that if the entire flash is to be checked, the last protection + * region checked would consist of the last protection start address and + * the start address following the end of flash */ + if ((start >= flashRegionAddress[regionCounter]) && (start < flashRegionAddress[regionCounter + 1])) + { + /* increment regionCheckedCounter to indicate this region was checked */ + regionCheckedCounter++; + + /* check the protection status of this region + * Note: FPROT=1 means NOT protected, FPROT=0 means protected */ + if (!flashRegionProtectStatus[regionCounter]) + { + /* increment protectStatusCounter to indicate this region is protected */ + protectStatusCounter++; + } + start += flashProtectionInfo.regionSize; /* increment to an address within the next region */ + } + regionCounter++; /* increment regionCounter to check for the next flash protection region */ + } + + /* if protectStatusCounter == 0, then no region of the desired flash region is protected */ + if (protectStatusCounter == 0) + { + *protection_state = kFLASH_ProtectionStateUnprotected; + } + /* if protectStatusCounter == regionCheckedCounter, then each region checked was protected */ + else if (protectStatusCounter == regionCheckedCounter) + { + *protection_state = kFLASH_ProtectionStateProtected; + } + /* if protectStatusCounter != regionCheckedCounter, then protection status is mixed + * In other words, some regions are protected while others are unprotected */ + else + { + *protection_state = kFLASH_ProtectionStateMixed; + } + + return (returnCode); +} + +status_t FLASH_IsExecuteOnly(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + flash_execute_only_access_state_t *access_state) +{ +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL + flash_access_config_t flashAccessInfo; /* flash Execute-Only information */ +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + status_t returnCode; + + if (access_state == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Check the supplied address range. */ + returnCode = flash_check_range(config, start, lengthInBytes, FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE); + if (returnCode) + { + return returnCode; + } + +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL + /* Get necessary flash Execute-Only information. */ + returnCode = flash_get_access_info(config, &flashAccessInfo); + if (returnCode) + { + return returnCode; + } + + { + uint32_t executeOnlySegmentCounter = 0; + + /* calculating end address */ + uint32_t endAddress = start + lengthInBytes; + + /* Aligning start address and end address */ + uint32_t alignedStartAddress = ALIGN_DOWN(start, flashAccessInfo.SegmentSize); + uint32_t alignedEndAddress = ALIGN_UP(endAddress, flashAccessInfo.SegmentSize); + + uint32_t segmentIndex = 0; + uint32_t maxSupportedExecuteOnlySegmentCount = + (alignedEndAddress - alignedStartAddress) / flashAccessInfo.SegmentSize; + + while (start < endAddress) + { + uint32_t xacc; + + segmentIndex = (start - flashAccessInfo.SegmentBase) / flashAccessInfo.SegmentSize; + +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER + if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) + { + /* For secondary flash, The two XACCS registers allow up to 16 restricted segments of equal memory size. + */ + if (segmentIndex < 8) + { + xacc = *(const volatile uint8_t *)&FTFx_XACCSL_REG; + } + else if (segmentIndex < flashAccessInfo.SegmentCount) + { + xacc = *(const volatile uint8_t *)&FTFx_XACCSH_REG; + segmentIndex -= 8; + } + else + { + break; + } + } + else +#endif + { + /* For primary flash, The eight XACC registers allow up to 64 restricted segments of equal memory size. + */ + if (segmentIndex < 32) + { + xacc = *(const volatile uint32_t *)&FTFx_XACCL3_REG; + } + else if (segmentIndex < flashAccessInfo.SegmentCount) + { + xacc = *(const volatile uint32_t *)&FTFx_XACCH3_REG; + segmentIndex -= 32; + } + else + { + break; + } + } + + /* Determine if this address range is in a execute-only protection flash segment. */ + if ((~xacc) & (1u << segmentIndex)) + { + executeOnlySegmentCounter++; + } + + start += flashAccessInfo.SegmentSize; + } + + if (executeOnlySegmentCounter < 1u) + { + *access_state = kFLASH_AccessStateUnLimited; + } + else if (executeOnlySegmentCounter < maxSupportedExecuteOnlySegmentCount) + { + *access_state = kFLASH_AccessStateMixed; + } + else + { + *access_state = kFLASH_AccessStateExecuteOnly; + } + } +#else + *access_state = kFLASH_AccessStateUnLimited; +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + + return (returnCode); +} + +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + if ((config == NULL) || (value == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + switch (whichProperty) + { + case kFLASH_PropertyPflashSectorSize: + *value = config->PFlashSectorSize; + break; + + case kFLASH_PropertyPflashTotalSize: + *value = config->PFlashTotalSize; + break; + + case kFLASH_PropertyPflashBlockSize: + *value = config->PFlashTotalSize / FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT; + break; + + case kFLASH_PropertyPflashBlockCount: + *value = (uint32_t)config->PFlashBlockCount; + break; + + case kFLASH_PropertyPflashBlockBaseAddr: + *value = config->PFlashBlockBase; + break; + + case kFLASH_PropertyPflashFacSupport: +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) + *value = FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL; +#else + *value = 0; +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ + break; + + case kFLASH_PropertyPflashAccessSegmentSize: + *value = config->PFlashAccessSegmentSize; + break; + + case kFLASH_PropertyPflashAccessSegmentCount: + *value = config->PFlashAccessSegmentCount; + break; + + case kFLASH_PropertyFlexRamBlockBaseAddr: + *value = config->FlexRAMBlockBase; + break; + + case kFLASH_PropertyFlexRamTotalSize: + *value = config->FlexRAMTotalSize; + break; + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + case kFLASH_PropertyDflashSectorSize: + *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; + break; + case kFLASH_PropertyDflashTotalSize: + *value = config->DFlashTotalSize; + break; + case kFLASH_PropertyDflashBlockSize: + *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE; + break; + case kFLASH_PropertyDflashBlockCount: + *value = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; + break; + case kFLASH_PropertyDflashBlockBaseAddr: + *value = config->DFlashBlockBase; + break; + case kFLASH_PropertyEepromTotalSize: + *value = config->EEpromTotalSize; + break; +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + + default: /* catch inputs that are not recognized */ + return kStatus_FLASH_UnknownProperty; + } + + return kStatus_FLASH_Success; +} + +status_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value) +{ + status_t status = kStatus_FLASH_Success; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + switch (whichProperty) + { +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED + case kFLASH_PropertyFlashMemoryIndex: + if ((value != (uint32_t)kFLASH_MemoryIndexPrimaryFlash) && + (value != (uint32_t)kFLASH_MemoryIndexSecondaryFlash)) + { + return kStatus_FLASH_InvalidPropertyValue; + } + config->FlashMemoryIndex = (uint8_t)value; + break; +#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */ + + case kFLASH_PropertyFlashCacheControllerIndex: + if ((value != (uint32_t)kFLASH_CacheControllerIndexForCore0) && + (value != (uint32_t)kFLASH_CacheControllerIndexForCore1)) + { + return kStatus_FLASH_InvalidPropertyValue; + } + config->FlashCacheControllerIndex = (uint8_t)value; + break; + + case kFLASH_PropertyPflashSectorSize: + case kFLASH_PropertyPflashTotalSize: + case kFLASH_PropertyPflashBlockSize: + case kFLASH_PropertyPflashBlockCount: + case kFLASH_PropertyPflashBlockBaseAddr: + case kFLASH_PropertyPflashFacSupport: + case kFLASH_PropertyPflashAccessSegmentSize: + case kFLASH_PropertyPflashAccessSegmentCount: + case kFLASH_PropertyFlexRamBlockBaseAddr: + case kFLASH_PropertyFlexRamTotalSize: +#if FLASH_SSD_IS_FLEXNVM_ENABLED + case kFLASH_PropertyDflashSectorSize: + case kFLASH_PropertyDflashTotalSize: + case kFLASH_PropertyDflashBlockSize: + case kFLASH_PropertyDflashBlockCount: + case kFLASH_PropertyDflashBlockBaseAddr: + case kFLASH_PropertyEepromTotalSize: +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + status = kStatus_FLASH_ReadOnlyProperty; + break; + default: /* catch inputs that are not recognized */ + status = kStatus_FLASH_UnknownProperty; + break; + } + + return status; +} + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +status_t FLASH_SetFlexramFunction(flash_config_t *config, flash_flexram_function_option_t option) +{ + status_t status; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + status = flasn_check_flexram_function_option_range(option); + if (status != kStatus_FLASH_Success) + { + return status; + } + + /* preparing passing parameter to verify all block command */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_1_2(FTFx_SET_FLEXRAM_FUNCTION, option, 0xFFFFU); + + /* calling flash command sequence function to execute the command */ + return flash_command_sequence(config); +} +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +status_t FLASH_SwapControl(flash_config_t *config, + uint32_t address, + flash_swap_control_option_t option, + flash_swap_state_config_t *returnInfo) +{ + status_t returnCode; + + if ((config == NULL) || (returnInfo == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + if (address & (FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT - 1)) + { + return kStatus_FLASH_AlignmentError; + } + + /* Make sure address provided is in the lower half of Program flash but not in the Flash Configuration Field */ + if ((address >= (config->PFlashTotalSize / 2)) || + ((address >= kFLASH_ConfigAreaStart) && (address <= kFLASH_ConfigAreaEnd))) + { + return kStatus_FLASH_SwapIndicatorAddressError; + } + + /* Check the option. */ + returnCode = flash_check_swap_control_option(option); + if (returnCode) + { + return returnCode; + } + + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_3(FTFx_SWAP_CONTROL, address); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_3(option, 0xFFFFFFU); + + returnCode = flash_command_sequence(config); + + returnInfo->flashSwapState = (flash_swap_state_t)FTFx_FCCOB5_REG; + returnInfo->currentSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB6_REG; + returnInfo->nextSwapBlockStatus = (flash_swap_block_status_t)FTFx_FCCOB7_REG; + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +status_t FLASH_Swap(flash_config_t *config, uint32_t address, flash_swap_function_option_t option) +{ + flash_swap_state_config_t returnInfo; + status_t returnCode; + + memset(&returnInfo, 0xFFU, sizeof(returnInfo)); + + do + { + returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionReportStatus, &returnInfo); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + + if (kFLASH_SwapFunctionOptionDisable == option) + { + if (returnInfo.flashSwapState == kFLASH_SwapStateDisabled) + { + return kStatus_FLASH_Success; + } + else if (returnInfo.flashSwapState == kFLASH_SwapStateUninitialized) + { + /* The swap system changed to the DISABLED state with Program flash block 0 + * located at relative flash address 0x0_0000 */ + returnCode = FLASH_SwapControl(config, address, kFLASH_SwapControlOptionDisableSystem, &returnInfo); + } + else + { + /* Swap disable should be requested only when swap system is in the uninitialized state */ + return kStatus_FLASH_SwapSystemNotInUninitialized; + } + } + else + { + /* When first swap: the initial swap state is Uninitialized, flash swap inidicator address is unset, + * the swap procedure should be Uninitialized -> Update-Erased -> Complete. + * After the first swap has been completed, the flash swap inidicator address cannot be modified + * unless EraseAllBlocks command is issued, the swap procedure is changed to Update -> Update-Erased -> + * Complete. */ + switch (returnInfo.flashSwapState) + { + case kFLASH_SwapStateUninitialized: + /* If current swap mode is Uninitialized, Initialize Swap to Initialized/READY state. */ + returnCode = + FLASH_SwapControl(config, address, kFLASH_SwapControlOptionIntializeSystem, &returnInfo); + break; + case kFLASH_SwapStateReady: + /* Validate whether the address provided to the swap system is matched to + * swap indicator address in the IFR */ + returnCode = flash_validate_swap_indicator_address(config, address); + if (returnCode == kStatus_FLASH_Success) + { + /* If current swap mode is Initialized/Ready, Initialize Swap to UPDATE state. */ + returnCode = + FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInUpdateState, &returnInfo); + } + break; + case kFLASH_SwapStateUpdate: + /* If current swap mode is Update, Erase indicator sector in non active block + * to proceed swap system to update-erased state */ + returnCode = FLASH_Erase(config, address + (config->PFlashTotalSize >> 1), + FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT, kFLASH_ApiEraseKey); + break; + case kFLASH_SwapStateUpdateErased: + /* If current swap mode is Update or Update-Erased, progress Swap to COMPLETE State */ + returnCode = + FLASH_SwapControl(config, address, kFLASH_SwapControlOptionSetInCompleteState, &returnInfo); + break; + case kFLASH_SwapStateComplete: + break; + case kFLASH_SwapStateDisabled: + /* When swap system is in disabled state, We need to clear swap system back to uninitialized + * by issuing EraseAllBlocks command */ + returnCode = kStatus_FLASH_SwapSystemNotInUninitialized; + break; + default: + returnCode = kStatus_FLASH_InvalidArgument; + break; + } + } + if (returnCode != kStatus_FLASH_Success) + { + break; + } + } while (!((kFLASH_SwapStateComplete == returnInfo.flashSwapState) && (kFLASH_SwapFunctionOptionEnable == option))); + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +#if defined(FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD) && FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD +status_t FLASH_ProgramPartition(flash_config_t *config, + flash_partition_flexram_load_option_t option, + uint32_t eepromDataSizeCode, + uint32_t flexnvmPartitionCode) +{ + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* eepromDataSizeCode[7:6], flexnvmPartitionCode[7:4] should be all 1'b0 + * or it will cause access error. */ + /* eepromDataSizeCode &= 0x3FU; */ + /* flexnvmPartitionCode &= 0x0FU; */ + + /* preparing passing parameter to program the flash block */ + kFCCOBx[0] = BYTES_JOIN_TO_WORD_1_2_1(FTFx_PROGRAM_PARTITION, 0xFFFFU, option); + kFCCOBx[1] = BYTES_JOIN_TO_WORD_1_1_2(eepromDataSizeCode, flexnvmPartitionCode, 0xFFFFU); + + flash_cache_clear_process(config, kFLASH_CacheClearProcessPre); + + /* calling flash command sequence function to execute the command */ + returnCode = flash_command_sequence(config); + + flash_cache_clear(config); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + /* Data flash IFR will be updated by program partition command during reset sequence, + * so we just set reserved values for partitioned FlexNVM size here */ + config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif + + return (returnCode); +} +#endif /* FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD */ + +status_t FLASH_PflashSetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER + if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) + { + *kFPROTSL = protectStatus->valueLow32b.prots16b.protsl; + if (protectStatus->valueLow32b.prots16b.protsl != *kFPROTSL) + { + return kStatus_FLASH_CommandFailure; + } + + *kFPROTSH = protectStatus->valueLow32b.prots16b.protsh; + if (protectStatus->valueLow32b.prots16b.protsh != *kFPROTSH) + { + return kStatus_FLASH_CommandFailure; + } + } + else +#endif + { + *kFPROTL = protectStatus->valueLow32b.protl32b; + if (protectStatus->valueLow32b.protl32b != *kFPROTL) + { + return kStatus_FLASH_CommandFailure; + } + +#if defined(FTFx_FPROT_HIGH_REG) + *kFPROTH = protectStatus->valueHigh32b.proth32b; + if (protectStatus->valueHigh32b.proth32b != *kFPROTH) + { + return kStatus_FLASH_CommandFailure; + } +#endif + } + + return kStatus_FLASH_Success; +} + +status_t FLASH_PflashGetProtection(flash_config_t *config, pflash_protection_status_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER + if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) + { + protectStatus->valueLow32b.prots16b.protsl = *kFPROTSL; + protectStatus->valueLow32b.prots16b.protsh = *kFPROTSH; + } + else +#endif + { + protectStatus->valueLow32b.protl32b = *kFPROTL; +#if defined(FTFx_FPROT_HIGH_REG) + protectStatus->valueHigh32b.proth32b = *kFPROTH; +#endif + } + + return kStatus_FLASH_Success; +} + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashSetProtection(flash_config_t *config, uint8_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + FTFx->FDPROT = protectStatus; + + if (FTFx->FDPROT != protectStatus) + { + return kStatus_FLASH_CommandFailure; + } + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_DflashGetProtection(flash_config_t *config, uint8_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->DFlashTotalSize == 0) || (config->DFlashTotalSize == FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + *protectStatus = FTFx->FDPROT; + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromSetProtection(flash_config_t *config, uint8_t protectStatus) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + FTFx->FEPROT = protectStatus; + + if (FTFx->FEPROT != protectStatus) + { + return kStatus_FLASH_CommandFailure; + } + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +status_t FLASH_EepromGetProtection(flash_config_t *config, uint8_t *protectStatus) +{ + if ((config == NULL) || (protectStatus == NULL)) + { + return kStatus_FLASH_InvalidArgument; + } + + if ((config->EEpromTotalSize == 0) || (config->EEpromTotalSize == FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED)) + { + return kStatus_FLASH_CommandNotSupported; + } + + *protectStatus = FTFx->FEPROT; + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +status_t FLASH_PflashSetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus) +{ +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM + { + FTFx_REG32_ACCESS_TYPE regBase; +#if defined(MCM) + regBase = (FTFx_REG32_ACCESS_TYPE)&MCM->PLACR; +#elif defined(MCM0) + regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0->PLACR; +#endif + if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable) + { + if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) + { + return kStatus_FLASH_InvalidSpeculationOption; + } + else + { + *regBase |= MCM_PLACR_DFCS_MASK; + } + } + else + { + *regBase &= ~MCM_PLACR_DFCS_MASK; + if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) + { + *regBase |= MCM_PLACR_EFDS_MASK; + } + else + { + *regBase &= ~MCM_PLACR_EFDS_MASK; + } + } + } +#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC + { + FTFx_REG32_ACCESS_TYPE regBase; + uint32_t b0dpeMask, b0ipeMask; +#if defined(FMC_PFB01CR_B0DPE_MASK) + regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; + b0dpeMask = FMC_PFB01CR_B0DPE_MASK; + b0ipeMask = FMC_PFB01CR_B0IPE_MASK; +#elif defined(FMC_PFB0CR_B0DPE_MASK) + regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; + b0dpeMask = FMC_PFB0CR_B0DPE_MASK; + b0ipeMask = FMC_PFB0CR_B0IPE_MASK; +#endif + if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionEnable) + { + *regBase |= b0ipeMask; + } + else + { + *regBase &= ~b0ipeMask; + } + if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) + { + *regBase |= b0dpeMask; + } + else + { + *regBase &= ~b0dpeMask; + } + +/* Invalidate Prefetch Speculation Buffer */ +#if defined(FMC_PFB01CR_S_INV_MASK) + FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK; +#elif defined(FMC_PFB01CR_S_B_INV_MASK) + FMC->PFB01CR |= FMC_PFB01CR_S_B_INV_MASK; +#elif defined(FMC_PFB0CR_S_INV_MASK) + FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK; +#elif defined(FMC_PFB0CR_S_B_INV_MASK) + FMC->PFB0CR |= FMC_PFB0CR_S_B_INV_MASK; +#endif + } +#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM + { + FTFx_REG32_ACCESS_TYPE regBase; + uint32_t flashSpeculationMask, dataPrefetchMask; + regBase = (FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0]; + flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK; + dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK; + + if (speculationStatus->instructionOption == kFLASH_prefetchSpeculationOptionDisable) + { + if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) + { + return kStatus_FLASH_InvalidSpeculationOption; + } + else + { + *regBase |= flashSpeculationMask; + } + } + else + { + *regBase &= ~flashSpeculationMask; + if (speculationStatus->dataOption == kFLASH_prefetchSpeculationOptionEnable) + { + *regBase &= ~dataPrefetchMask; + } + else + { + *regBase |= dataPrefetchMask; + } + } + } +#endif /* FSL_FEATURE_FTFx_MCM_FLASH_CACHE_CONTROLS */ + + return kStatus_FLASH_Success; +} + +status_t FLASH_PflashGetPrefetchSpeculation(flash_prefetch_speculation_status_t *speculationStatus) +{ + memset(speculationStatus, 0, sizeof(flash_prefetch_speculation_status_t)); + + /* Assuming that all speculation options are enabled. */ + speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionEnable; + speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionEnable; + +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MCM + { + uint32_t value; +#if defined(MCM) + value = MCM->PLACR; +#elif defined(MCM0) + value = MCM0->PLACR; +#endif + if (value & MCM_PLACR_DFCS_MASK) + { + /* Speculation buffer is off. */ + speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; + speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; + } + else + { + /* Speculation buffer is on for instruction. */ + if (!(value & MCM_PLACR_EFDS_MASK)) + { + /* Speculation buffer is off for data. */ + speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; + } + } + } +#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC + { + uint32_t value; + uint32_t b0dpeMask, b0ipeMask; +#if defined(FMC_PFB01CR_B0DPE_MASK) + value = FMC->PFB01CR; + b0dpeMask = FMC_PFB01CR_B0DPE_MASK; + b0ipeMask = FMC_PFB01CR_B0IPE_MASK; +#elif defined(FMC_PFB0CR_B0DPE_MASK) + value = FMC->PFB0CR; + b0dpeMask = FMC_PFB0CR_B0DPE_MASK; + b0ipeMask = FMC_PFB0CR_B0IPE_MASK; +#endif + if (!(value & b0dpeMask)) + { + /* Do not prefetch in response to data references. */ + speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; + } + if (!(value & b0ipeMask)) + { + /* Do not prefetch in response to instruction fetches. */ + speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; + } + } +#elif FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM + { + uint32_t value; + uint32_t flashSpeculationMask, dataPrefetchMask; + value = MSCM->OCMDR[0]; + flashSpeculationMask = MSCM_OCMDR_OCMC1_DFCS_MASK; + dataPrefetchMask = MSCM_OCMDR_OCMC1_DFDS_MASK; + + if (value & flashSpeculationMask) + { + /* Speculation buffer is off. */ + speculationStatus->instructionOption = kFLASH_prefetchSpeculationOptionDisable; + speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; + } + else + { + /* Speculation buffer is on for instruction. */ + if (value & dataPrefetchMask) + { + /* Speculation buffer is off for data. */ + speculationStatus->dataOption = kFLASH_prefetchSpeculationOptionDisable; + } + } + } +#endif + + return kStatus_FLASH_Success; +} + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! + * @brief Copy PIC of flash_run_command() to RAM + */ +static void copy_flash_run_command(uint32_t *flashRunCommand) +{ + assert(sizeof(s_flashRunCommandFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4)); + + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why +1 operation exist. */ + memcpy((void *)flashRunCommand, (void *)s_flashRunCommandFunctionCode, sizeof(s_flashRunCommandFunctionCode)); + callFlashRunCommand = (void (*)(FTFx_REG8_ACCESS_TYPE ftfx_fstat))((uint32_t)flashRunCommand + 1); +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! + * @brief Flash Command Sequence + * + * This function is used to perform the command write sequence to the flash. + * + * @param driver Pointer to storage for the driver runtime state. + * @return An error code or kStatus_FLASH_Success + */ +static status_t flash_command_sequence(flash_config_t *config) +{ + uint8_t registerValue; + +#if FLASH_DRIVER_IS_FLASH_RESIDENT + /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ + FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; + + status_t returnCode = flash_check_execute_in_ram_function_info(config); + if (kStatus_FLASH_Success != returnCode) + { + return returnCode; + } + + /* We pass the ftfx_fstat address as a parameter to flash_run_comamnd() instead of using + * pre-processed MICRO sentences or operating global variable in flash_run_comamnd() + * to make sure that flash_run_command() will be compiled into position-independent code (PIC). */ + callFlashRunCommand((FTFx_REG8_ACCESS_TYPE)(&FTFx->FSTAT)); +#else + /* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register */ + FTFx->FSTAT = FTFx_FSTAT_RDCOLERR_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_FPVIOL_MASK; + + /* clear CCIF bit */ + FTFx->FSTAT = FTFx_FSTAT_CCIF_MASK; + + /* Check CCIF bit of the flash status register, wait till it is set. + * IP team indicates that this loop will always complete. */ + while (!(FTFx->FSTAT & FTFx_FSTAT_CCIF_MASK)) + { + } +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + + /* Check error bits */ + /* Get flash status register value */ + registerValue = FTFx->FSTAT; + + /* checking access error */ + if (registerValue & FTFx_FSTAT_ACCERR_MASK) + { + return kStatus_FLASH_AccessError; + } + /* checking protection error */ + else if (registerValue & FTFx_FSTAT_FPVIOL_MASK) + { + return kStatus_FLASH_ProtectionViolation; + } + /* checking MGSTAT0 non-correctable error */ + else if (registerValue & FTFx_FSTAT_MGSTAT0_MASK) + { + return kStatus_FLASH_CommandFailure; + } + else + { + return kStatus_FLASH_Success; + } +} + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! + * @brief Copy PIC of flash_common_bit_operation() to RAM + * + */ +static void copy_flash_common_bit_operation(uint32_t *flashCommonBitOperation) +{ + assert(sizeof(s_flashCommonBitOperationFunctionCode) <= (kFLASH_ExecuteInRamFunctionMaxSizeInWords * 4)); + + /* Since the value of ARM function pointer is always odd, but the real start address + * of function memory should be even, that's why +1 operation exist. */ + memcpy((void *)flashCommonBitOperation, (void *)s_flashCommonBitOperationFunctionCode, + sizeof(s_flashCommonBitOperationFunctionCode)); + callFlashCommonBitOperation = (void (*)(FTFx_REG32_ACCESS_TYPE base, uint32_t bitMask, uint32_t bitShift, + uint32_t bitValue))((uint32_t)flashCommonBitOperation + 1); + /* Workround for some devices which doesn't need this function */ + callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)0, 0, 0, 0); +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +#if FLASH_CACHE_IS_CONTROLLED_BY_MCM +/*! @brief Performs the cache clear to the flash by MCM.*/ +void mcm_flash_cache_clear(flash_config_t *config) +{ + FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)&MCM0_CACHE_REG; + +#if defined(MCM0) && defined(MCM1) + if (config->FlashCacheControllerIndex == (uint8_t)kFLASH_CacheControllerIndexForCore1) + { + regBase = (FTFx_REG32_ACCESS_TYPE)&MCM1_CACHE_REG; + } +#endif + +#if FLASH_DRIVER_IS_FLASH_RESIDENT + callFlashCommonBitOperation(regBase, MCM_CACHE_CLEAR_MASK, MCM_CACHE_CLEAR_SHIFT, 1U); +#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ + *regBase |= MCM_CACHE_CLEAR_MASK; + + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ +} +#endif /* FLASH_CACHE_IS_CONTROLLED_BY_MCM */ + +#if FLASH_CACHE_IS_CONTROLLED_BY_FMC +/*! @brief Performs the cache clear to the flash by FMC.*/ +void fmc_flash_cache_clear(void) +{ +#if FLASH_DRIVER_IS_FLASH_RESIDENT + FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0; +#if defined(FMC_PFB01CR_CINV_WAY_MASK) + regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; + callFlashCommonBitOperation(regBase, FMC_PFB01CR_CINV_WAY_MASK, FMC_PFB01CR_CINV_WAY_SHIFT, 0xFU); +#else + regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; + callFlashCommonBitOperation(regBase, FMC_PFB0CR_CINV_WAY_MASK, FMC_PFB0CR_CINV_WAY_SHIFT, 0xFU); +#endif +#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ +#if defined(FMC_PFB01CR_CINV_WAY_MASK) + FMC->PFB01CR = (FMC->PFB01CR & ~FMC_PFB01CR_CINV_WAY_MASK) | FMC_PFB01CR_CINV_WAY(~0); +#else + FMC->PFB0CR = (FMC->PFB0CR & ~FMC_PFB0CR_CINV_WAY_MASK) | FMC_PFB0CR_CINV_WAY(~0); +#endif + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ +} +#endif /* FLASH_CACHE_IS_CONTROLLED_BY_FMC */ + +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM +/*! @brief Performs the prefetch speculation buffer clear to the flash by MSCM.*/ +void mscm_flash_prefetch_speculation_enable(bool enable) +{ + uint8_t setValue; + if (enable) + { + setValue = 0x0U; + } + else + { + setValue = 0x3U; + } + +/* The OCMDR[0] is always used to prefetch main Pflash*/ +/* For device with FlexNVM support, the OCMDR[1] is used to prefetch Dflash. + * For device with secondary flash support, the OCMDR[1] is used to prefetch secondary Pflash. */ +#if FLASH_DRIVER_IS_FLASH_RESIDENT + callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[0], MSCM_SPECULATION_DISABLE_MASK, + MSCM_SPECULATION_DISABLE_SHIFT, setValue); +#if FLASH_SSD_IS_FLEXNVM_ENABLED || BL_HAS_SECONDARY_INTERNAL_FLASH + callFlashCommonBitOperation((FTFx_REG32_ACCESS_TYPE)&MSCM->OCMDR[1], MSCM_SPECULATION_DISABLE_MASK, + MSCM_SPECULATION_DISABLE_SHIFT, setValue); +#endif +#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ + MSCM->OCMDR[0] |= MSCM_SPECULATION_DISABLE(setValue); + + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +#if FLASH_SSD_IS_FLEXNVM_ENABLED || BL_HAS_SECONDARY_INTERNAL_FLASH + MSCM->OCMDR[1] |= MSCM_SPECULATION_DISABLE(setValue); + + /* Each cahce clear instaruction should be followed by below code*/ + __ISB(); + __DSB(); +#endif + +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ +} +#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM */ + +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC +/*! @brief Performs the prefetch speculation buffer clear to the flash by FMC.*/ +void fmc_flash_prefetch_speculation_clear(void) +{ +#if FLASH_DRIVER_IS_FLASH_RESIDENT + FTFx_REG32_ACCESS_TYPE regBase = (FTFx_REG32_ACCESS_TYPE)0; +#if defined(FMC_PFB01CR_S_INV_MASK) + regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; + callFlashCommonBitOperation(regBase, FMC_PFB01CR_S_INV_MASK, FMC_PFB01CR_S_INV_SHIFT, 1U); +#elif defined(FMC_PFB01CR_S_B_INV_MASK) + regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB01CR; + callFlashCommonBitOperation(regBase, FMC_PFB01CR_S_B_INV_MASK, FMC_PFB01CR_S_B_INV_SHIFT, 1U); +#elif defined(FMC_PFB0CR_S_INV_MASK) + regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; + callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_INV_MASK, FMC_PFB0CR_S_INV_SHIFT, 1U); +#elif defined(FMC_PFB0CR_S_B_INV_MASK) + regBase = (FTFx_REG32_ACCESS_TYPE)&FMC->PFB0CR; + callFlashCommonBitOperation(regBase, FMC_PFB0CR_S_B_INV_MASK, FMC_PFB0CR_S_B_INV_SHIFT, 1U); +#endif +#else /* !FLASH_DRIVER_IS_FLASH_RESIDENT */ +#if defined(FMC_PFB01CR_S_INV_MASK) + FMC->PFB01CR |= FMC_PFB01CR_S_INV_MASK; +#elif defined(FMC_PFB01CR_S_B_INV_MASK) + FMC->PFB01CR |= FMC_PFB01CR_S_B_INV_MASK; +#elif defined(FMC_PFB0CR_S_INV_MASK) + FMC->PFB0CR |= FMC_PFB0CR_S_INV_MASK; +#elif defined(FMC_PFB0CR_S_B_INV_MASK) + FMC->PFB0CR |= FMC_PFB0CR_S_B_INV_MASK; +#endif + /* Memory barriers for good measure. + * All Cache, Branch predictor and TLB maintenance operations before this instruction complete */ + __ISB(); + __DSB(); +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ +} +#endif /* FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC */ + +/*! + * @brief Flash Cache Clear + * + * This function is used to perform the cache and prefetch speculation clear to the flash. + */ +void flash_cache_clear(flash_config_t *config) +{ + flash_cache_clear_process(config, kFLASH_CacheClearProcessPost); +} + +/*! + * @brief Flash Cache Clear Process + * + * This function is used to perform the cache and prefetch speculation clear process to the flash. + */ +static void flash_cache_clear_process(flash_config_t *config, flash_cache_clear_process_t process) +{ +#if FLASH_DRIVER_IS_FLASH_RESIDENT + status_t returnCode = flash_check_execute_in_ram_function_info(config); + if (kStatus_FLASH_Success != returnCode) + { + return; + } +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + + /* We pass the ftfx register address as a parameter to flash_common_bit_operation() instead of using + * pre-processed MACROs or a global variable in flash_common_bit_operation() + * to make sure that flash_common_bit_operation() will be compiled into position-independent code (PIC). */ + if (process == kFLASH_CacheClearProcessPost) + { +#if FLASH_CACHE_IS_CONTROLLED_BY_MCM + mcm_flash_cache_clear(config); +#endif +#if FLASH_CACHE_IS_CONTROLLED_BY_FMC + fmc_flash_cache_clear(); +#endif +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM + mscm_flash_prefetch_speculation_enable(true); +#endif +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_FMC + fmc_flash_prefetch_speculation_clear(); +#endif + } + if (process == kFLASH_CacheClearProcessPre) + { +#if FLASH_PREFETCH_SPECULATION_IS_CONTROLLED_BY_MSCM + mscm_flash_prefetch_speculation_enable(false); +#endif + } +} + +#if FLASH_DRIVER_IS_FLASH_RESIDENT +/*! @brief Check whether flash execute-in-ram functions are ready */ +static status_t flash_check_execute_in_ram_function_info(flash_config_t *config) +{ + flash_execute_in_ram_function_config_t *flashExecuteInRamFunctionInfo; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + flashExecuteInRamFunctionInfo = (flash_execute_in_ram_function_config_t *)config->flashExecuteInRamFunctionInfo; + + if ((config->flashExecuteInRamFunctionInfo) && + (kFLASH_ExecuteInRamFunctionTotalNum == flashExecuteInRamFunctionInfo->activeFunctionCount)) + { + return kStatus_FLASH_Success; + } + + return kStatus_FLASH_ExecuteInRamFunctionNotReady; +} +#endif /* FLASH_DRIVER_IS_FLASH_RESIDENT */ + +/*! @brief Validates the range and alignment of the given address range.*/ +static status_t flash_check_range(flash_config_t *config, + uint32_t startAddress, + uint32_t lengthInBytes, + uint32_t alignmentBaseline) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Verify the start and length are alignmentBaseline aligned. */ + if ((startAddress & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) + { + return kStatus_FLASH_AlignmentError; + } + + /* check for valid range of the target addresses */ + if ( +#if FLASH_SSD_IS_FLEXNVM_ENABLED + ((startAddress >= config->DFlashBlockBase) && + ((startAddress + lengthInBytes) <= (config->DFlashBlockBase + config->DFlashTotalSize))) || +#endif + ((startAddress >= config->PFlashBlockBase) && + ((startAddress + lengthInBytes) <= (config->PFlashBlockBase + config->PFlashTotalSize)))) + { + return kStatus_FLASH_Success; + } + + return kStatus_FLASH_AddressError; +} + +/*! @brief Gets the right address, sector and block size of current flash type which is indicated by address.*/ +static status_t flash_get_matched_operation_info(flash_config_t *config, + uint32_t address, + flash_operation_config_t *info) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Clean up info Structure*/ + memset(info, 0, sizeof(flash_operation_config_t)); + +#if FLASH_SSD_IS_FLEXNVM_ENABLED + if ((address >= config->DFlashBlockBase) && (address <= (config->DFlashBlockBase + config->DFlashTotalSize))) + { + /* When required by the command, address bit 23 selects between program flash memory + * (=0) and data flash memory (=1).*/ + info->convertedAddress = address - config->DFlashBlockBase + 0x800000U; + info->activeSectorSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE; + info->activeBlockSize = config->DFlashTotalSize / FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT; + + info->blockWriteUnitSize = FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE; + info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT; + info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT; + info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT; + info->checkCmdAddressAligment = FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT; + } + else +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + { + info->convertedAddress = address - config->PFlashBlockBase; + info->activeSectorSize = config->PFlashSectorSize; + info->activeBlockSize = config->PFlashTotalSize / config->PFlashBlockCount; +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED + if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) + { +#if FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER || FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER + /* When required by the command, address bit 23 selects between main flash memory + * (=0) and secondary flash memory (=1).*/ + info->convertedAddress += 0x800000U; +#endif + info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE; + } + else +#endif /* FLASH_SSD_IS_SECONDARY_FLASH_ENABLED */ + { + info->blockWriteUnitSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE; + } + + info->sectorCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT; + info->sectionCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT; + info->resourceCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT; + info->checkCmdAddressAligment = FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT; + } + + return kStatus_FLASH_Success; +} + +/*! @brief Validates the given user key for flash erase APIs.*/ +static status_t flash_check_user_key(uint32_t key) +{ + /* Validate the user key */ + if (key != kFLASH_ApiEraseKey) + { + return kStatus_FLASH_EraseKeyError; + } + + return kStatus_FLASH_Success; +} + +#if FLASH_SSD_IS_FLEXNVM_ENABLED +/*! @brief Updates FlexNVM memory partition status according to data flash 0 IFR.*/ +static status_t flash_update_flexnvm_memory_partition_status(flash_config_t *config) +{ + struct + { + uint32_t reserved0; + uint8_t FlexNVMPartitionCode; + uint8_t EEPROMDataSetSize; + uint16_t reserved1; + } dataIFRReadOut; + status_t returnCode; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD + /* Get FlexNVM memory partition info from data flash IFR */ + returnCode = FLASH_ReadResource(config, DFLASH_IFR_READRESOURCE_START_ADDRESS, (uint32_t *)&dataIFRReadOut, + sizeof(dataIFRReadOut), kFLASH_ResourceOptionFlashIfr); + if (returnCode != kStatus_FLASH_Success) + { + return kStatus_FLASH_PartitionStatusUpdateFailure; + } +#else +#error "Cannot get FlexNVM memory partition info" +#endif + + /* Fill out partitioned EEPROM size */ + dataIFRReadOut.EEPROMDataSetSize &= 0x0FU; + switch (dataIFRReadOut.EEPROMDataSetSize) + { + case 0x00U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000; + break; + case 0x01U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001; + break; + case 0x02U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010; + break; + case 0x03U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011; + break; + case 0x04U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100; + break; + case 0x05U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101; + break; + case 0x06U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110; + break; + case 0x07U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111; + break; + case 0x08U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000; + break; + case 0x09U: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001; + break; + case 0x0AU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010; + break; + case 0x0BU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011; + break; + case 0x0CU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100; + break; + case 0x0DU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101; + break; + case 0x0EU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110; + break; + case 0x0FU: + config->EEpromTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111; + break; + default: + config->EEpromTotalSize = FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_RESERVED; + break; + } + + /* Fill out partitioned DFlash size */ + dataIFRReadOut.FlexNVMPartitionCode &= 0x0FU; + switch (dataIFRReadOut.FlexNVMPartitionCode) + { + case 0x00U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 */ + break; + case 0x01U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 */ + break; + case 0x02U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 */ + break; + case 0x03U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 */ + break; + case 0x04U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 */ + break; + case 0x05U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 */ + break; + case 0x06U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 */ + break; + case 0x07U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 */ + break; + case 0x08U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 */ + break; + case 0x09U: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 */ + break; + case 0x0AU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 */ + break; + case 0x0BU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 */ + break; + case 0x0CU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 */ + break; + case 0x0DU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 */ + break; + case 0x0EU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 */ + break; + case 0x0FU: +#if (FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 != 0xFFFFFFFF) + config->DFlashTotalSize = FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111; +#else + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; +#endif /* FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 */ + break; + default: + config->DFlashTotalSize = FLEX_NVM_DFLASH_SIZE_FOR_DEPART_RESERVED; + break; + } + + return kStatus_FLASH_Success; +} +#endif /* FLASH_SSD_IS_FLEXNVM_ENABLED */ + +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD +/*! @brief Validates the range of the given resource address.*/ +static status_t flash_check_resource_range(uint32_t start, + uint32_t lengthInBytes, + uint32_t alignmentBaseline, + flash_read_resource_option_t option) +{ + status_t status; + uint32_t maxReadbleAddress; + + if ((start & (alignmentBaseline - 1)) || (lengthInBytes & (alignmentBaseline - 1))) + { + return kStatus_FLASH_AlignmentError; + } + + status = kStatus_FLASH_Success; + + maxReadbleAddress = start + lengthInBytes - 1; + if (option == kFLASH_ResourceOptionVersionId) + { + if ((start != kFLASH_ResourceRangeVersionIdStart) || + ((start + lengthInBytes - 1) != kFLASH_ResourceRangeVersionIdEnd)) + { + status = kStatus_FLASH_InvalidArgument; + } + } + else if (option == kFLASH_ResourceOptionFlashIfr) + { + if (maxReadbleAddress < kFLASH_ResourceRangePflashIfrSizeInBytes) + { + } +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP + else if ((start >= kFLASH_ResourceRangePflashSwapIfrStart) && + (maxReadbleAddress <= kFLASH_ResourceRangePflashSwapIfrEnd)) + { + } +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + else if ((start >= kFLASH_ResourceRangeDflashIfrStart) && + (maxReadbleAddress <= kFLASH_ResourceRangeDflashIfrEnd)) + { + } + else + { + status = kStatus_FLASH_InvalidArgument; + } + } + else + { + status = kStatus_FLASH_InvalidArgument; + } + + return status; +} +#endif /* FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD) && FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD +/*! @brief Validates the gived swap control option.*/ +static status_t flash_check_swap_control_option(flash_swap_control_option_t option) +{ + if ((option == kFLASH_SwapControlOptionIntializeSystem) || (option == kFLASH_SwapControlOptionSetInUpdateState) || + (option == kFLASH_SwapControlOptionSetInCompleteState) || (option == kFLASH_SwapControlOptionReportStatus) || + (option == kFLASH_SwapControlOptionDisableSystem)) + { + return kStatus_FLASH_Success; + } + + return kStatus_FLASH_InvalidArgument; +} +#endif /* FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD */ + +#if defined(FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP) && FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP +/*! @brief Validates the gived address to see if it is equal to swap indicator address in pflash swap IFR.*/ +static status_t flash_validate_swap_indicator_address(flash_config_t *config, uint32_t address) +{ + flash_swap_ifr_field_data_t flashSwapIfrFieldData; + uint32_t swapIndicatorAddress; + + status_t returnCode; +#if defined(FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD) && FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD + returnCode = + FLASH_ReadResource(config, kFLASH_ResourceRangePflashSwapIfrStart, flashSwapIfrFieldData.flashSwapIfrData, + sizeof(flashSwapIfrFieldData.flashSwapIfrData), kFLASH_ResourceOptionFlashIfr); + + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } +#else + { + /* From RM, the actual info are stored in FCCOB6,7 */ + uint32_t returnValue[2]; + returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapAddr, returnValue, 4); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress = (uint16_t)returnValue[0]; + returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapEnable, returnValue, 4); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + flashSwapIfrFieldData.flashSwapIfrField.swapEnableWord = (uint16_t)returnValue[0]; + returnCode = FLASH_ReadOnce(config, kFLASH_RecordIndexSwapDisable, returnValue, 4); + if (returnCode != kStatus_FLASH_Success) + { + return returnCode; + } + flashSwapIfrFieldData.flashSwapIfrField.swapDisableWord = (uint16_t)returnValue[0]; + } +#endif + + /* The high bits value of Swap Indicator Address is stored in Program Flash Swap IFR Field, + * the low severval bit value of Swap Indicator Address is always 1'b0 */ + swapIndicatorAddress = (uint32_t)flashSwapIfrFieldData.flashSwapIfrField.swapIndicatorAddress * + FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT; + if (address != swapIndicatorAddress) + { + return kStatus_FLASH_SwapIndicatorAddressError; + } + + return returnCode; +} +#endif /* FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP */ + +#if defined(FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD) && FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD +/*! @brief Validates the gived flexram function option.*/ +static inline status_t flasn_check_flexram_function_option_range(flash_flexram_function_option_t option) +{ + if ((option != kFLASH_FlexramFunctionOptionAvailableAsRam) && + (option != kFLASH_FlexramFunctionOptionAvailableForEeprom)) + { + return kStatus_FLASH_InvalidArgument; + } + + return kStatus_FLASH_Success; +} +#endif /* FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD */ + +/*! @brief Gets the flash protection information (region size, region count).*/ +static status_t flash_get_protection_info(flash_config_t *config, flash_protection_config_t *info) +{ + uint32_t pflashTotalSize; + + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Clean up info Structure*/ + memset(info, 0, sizeof(flash_protection_config_t)); + +/* Note: KW40 has a secondary flash, but it doesn't have independent protection register*/ +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER) + pflashTotalSize = FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE + + FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE; + info->regionBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS; +#else + pflashTotalSize = config->PFlashTotalSize; + info->regionBase = config->PFlashBlockBase; +#endif + +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_PROTECTION_REGISTER + if (config->FlashMemoryIndex == (uint8_t)kFLASH_MemoryIndexSecondaryFlash) + { + info->regionCount = FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT; + } + else +#endif + { + info->regionCount = FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT; + } + + /* Calculate the size of the flash protection region + * If the flash density is > 32KB, then protection region is 1/32 of total flash density + * Else if flash density is < 32KB, then flash protection region is set to 1KB */ + if (pflashTotalSize > info->regionCount * 1024) + { + info->regionSize = (pflashTotalSize) / info->regionCount; + } + else + { + info->regionSize = 1024; + } + + return kStatus_FLASH_Success; +} + +#if defined(FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL) && FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL +/*! @brief Gets the flash Execute-Only access information (Segment size, Segment count).*/ +static status_t flash_get_access_info(flash_config_t *config, flash_access_config_t *info) +{ + if (config == NULL) + { + return kStatus_FLASH_InvalidArgument; + } + + /* Clean up info Structure*/ + memset(info, 0, sizeof(flash_access_config_t)); + +/* Note: KW40 has a secondary flash, but it doesn't have independent access register*/ +#if FLASH_SSD_IS_SECONDARY_FLASH_ENABLED && (!FLASH_SSD_SECONDARY_FLASH_HAS_ITS_OWN_ACCESS_REGISTER) + info->SegmentBase = FSL_FEATURE_FLASH_PFLASH_START_ADDRESS; +#else + info->SegmentBase = config->PFlashBlockBase; +#endif + info->SegmentSize = config->PFlashAccessSegmentSize; + info->SegmentCount = config->PFlashAccessSegmentCount; + + return kStatus_FLASH_Success; +} +#endif /* FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flash.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flash.h new file mode 100644 index 00000000000..e143cb3e1f6 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flash.h @@ -0,0 +1,1386 @@ +/* + * Copyright (c) 2013-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLASH_H_ +#define _FSL_FLASH_H_ + +#if (defined(BL_TARGET_FLASH) || defined(BL_TARGET_ROM) || defined(BL_TARGET_RAM)) +#include +#include +#include "fsl_device_registers.h" +#include "bootloader_common.h" +#else +#include "fsl_common.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! + * @name Flash version + * @{ + */ +/*! @brief Constructs the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief Flash driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1. */ + +/*! @brief Flash driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ + kFLASH_DriverVersionMinor = 3, /*!< Minor flash driver version.*/ + kFLASH_DriverVersionBugfix = 1 /*!< Bugfix for flash driver version.*/ +}; +/*@}*/ + +/*! + * @name Flash configuration + * @{ + */ +/*! @brief Indicates whether to support FlexNVM in the Flash driver */ +#if !defined(FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT) +#define FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT 1 /*!< Enables the FlexNVM support by default. */ +#endif + +/*! @brief Indicates whether the FlexNVM is enabled in the Flash driver */ +#define FLASH_SSD_IS_FLEXNVM_ENABLED (FLASH_SSD_CONFIG_ENABLE_FLEXNVM_SUPPORT && FSL_FEATURE_FLASH_HAS_FLEX_NVM) + +/*! @brief Indicates whether to support Secondary flash in the Flash driver */ +#if !defined(FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT) +#define FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT 1 /*!< Enables the secondary flash support by default. */ +#endif + +/*! @brief Indicates whether the secondary flash is supported in the Flash driver */ +#if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) +#define FLASH_SSD_IS_SECONDARY_FLASH_ENABLED (FLASH_SSD_CONFIG_ENABLE_SECONDARY_FLASH_SUPPORT) +#else +#define FLASH_SSD_IS_SECONDARY_FLASH_ENABLED (0) +#endif + +/*! @brief Flash driver location. */ +#if !defined(FLASH_DRIVER_IS_FLASH_RESIDENT) +#if (!defined(BL_TARGET_ROM) && !defined(BL_TARGET_RAM)) +#define FLASH_DRIVER_IS_FLASH_RESIDENT 1 /*!< Used for the flash resident application. */ +#else +#define FLASH_DRIVER_IS_FLASH_RESIDENT 0 /*!< Used for the non-flash resident application. */ +#endif +#endif + +/*! @brief Flash Driver Export option */ +#if !defined(FLASH_DRIVER_IS_EXPORTED) +#if (defined(BL_TARGET_ROM) || defined(BL_TARGET_FLASH)) +#define FLASH_DRIVER_IS_EXPORTED 1 /*!< Used for the ROM bootloader. */ +#else +#define FLASH_DRIVER_IS_EXPORTED 0 /*!< Used for the MCUXpresso SDK application. */ +#endif +#endif +/*@}*/ + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASH) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Constructs a status code value from a group and a code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum _flash_status +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = + MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ + kStatus_FLASH_PartitionStatusUpdateFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 10), /*!< Failed to update partition status.*/ + kStatus_FLASH_SetFlexramAsEepromError = + MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Failed to set FlexRAM as EEPROM.*/ + kStatus_FLASH_RecoverFlexramAsRamError = + MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< Failed to recover FlexRAM as RAM.*/ + kStatus_FLASH_SetFlexramAsRamError = MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< Failed to set FlexRAM as RAM.*/ + kStatus_FLASH_RecoverFlexramAsEepromError = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< Failed to recover FlexRAM as EEPROM.*/ + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 15), /*!< Flash API is not supported.*/ + kStatus_FLASH_SwapSystemNotInUninitialized = + MAKE_STATUS(kStatusGroupFlashDriver, 16), /*!< Swap system is not in an uninitialzed state.*/ + kStatus_FLASH_SwapIndicatorAddressError = + MAKE_STATUS(kStatusGroupFlashDriver, 17), /*!< The swap indicator address is invalid.*/ + kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 18), /*!< The flash property is read-only.*/ + kStatus_FLASH_InvalidPropertyValue = + MAKE_STATUS(kStatusGroupFlashDriver, 19), /*!< The flash property value is out of range.*/ + kStatus_FLASH_InvalidSpeculationOption = + MAKE_STATUS(kStatusGroupFlashDriver, 20), /*!< The option of flash prefetch speculation is invalid.*/ +}; +/*@}*/ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Constructs the four character code for the Flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for Flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_ApiEraseKey = FOUR_CHAR_CODE('k', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for supported flash margin levels. + */ +typedef enum _flash_margin_value +{ + kFLASH_MarginValueNormal, /*!< Use the 'normal' read level for 1s.*/ + kFLASH_MarginValueUser, /*!< Apply the 'User' margin to the normal read-1 level.*/ + kFLASH_MarginValueFactory, /*!< Apply the 'Factory' margin to the normal read-1 level.*/ + kFLASH_MarginValueInvalid /*!< Not real margin level, Used to determine the range of valid margin level. */ +} flash_margin_value_t; + +/*! + * @brief Enumeration for the three possible flash security states. + */ +typedef enum _flash_security_state +{ + kFLASH_SecurityStateNotSecure, /*!< Flash is not secure.*/ + kFLASH_SecurityStateBackdoorEnabled, /*!< Flash backdoor is enabled.*/ + kFLASH_SecurityStateBackdoorDisabled /*!< Flash backdoor is disabled.*/ +} flash_security_state_t; + +/*! + * @brief Enumeration for the three possible flash protection levels. + */ +typedef enum _flash_protection_state +{ + kFLASH_ProtectionStateUnprotected, /*!< Flash region is not protected.*/ + kFLASH_ProtectionStateProtected, /*!< Flash region is protected.*/ + kFLASH_ProtectionStateMixed /*!< Flash is mixed with protected and unprotected region.*/ +} flash_protection_state_t; + +/*! + * @brief Enumeration for the three possible flash execute access levels. + */ +typedef enum _flash_execute_only_access_state +{ + kFLASH_AccessStateUnLimited, /*!< Flash region is unlimited.*/ + kFLASH_AccessStateExecuteOnly, /*!< Flash region is execute only.*/ + kFLASH_AccessStateMixed /*!< Flash is mixed with unlimited and execute only region.*/ +} flash_execute_only_access_state_t; + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + kFLASH_PropertyPflashFacSupport = 0x05U, /*!< Pflash fac support property.*/ + kFLASH_PropertyPflashAccessSegmentSize = 0x06U, /*!< Pflash access segment size property.*/ + kFLASH_PropertyPflashAccessSegmentCount = 0x07U, /*!< Pflash access segment count property.*/ + kFLASH_PropertyFlexRamBlockBaseAddr = 0x08U, /*!< FlexRam block base address property.*/ + kFLASH_PropertyFlexRamTotalSize = 0x09U, /*!< FlexRam total size property.*/ + kFLASH_PropertyDflashSectorSize = 0x10U, /*!< Dflash sector size property.*/ + kFLASH_PropertyDflashTotalSize = 0x11U, /*!< Dflash total size property.*/ + kFLASH_PropertyDflashBlockSize = 0x12U, /*!< Dflash block size property.*/ + kFLASH_PropertyDflashBlockCount = 0x13U, /*!< Dflash block count property.*/ + kFLASH_PropertyDflashBlockBaseAddr = 0x14U, /*!< Dflash block base address property.*/ + kFLASH_PropertyEepromTotalSize = 0x15U, /*!< EEPROM total size property.*/ + kFLASH_PropertyFlashMemoryIndex = 0x20U, /*!< Flash memory index property.*/ + kFLASH_PropertyFlashCacheControllerIndex = 0x21U /*!< Flash cache controller index property.*/ +} flash_property_tag_t; + +/*! + * @brief Constants for execute-in-RAM flash function. + */ +enum _flash_execute_in_ram_function_constants +{ + kFLASH_ExecuteInRamFunctionMaxSizeInWords = 16U, /*!< The maximum size of execute-in-RAM function.*/ + kFLASH_ExecuteInRamFunctionTotalNum = 2U /*!< Total number of execute-in-RAM functions.*/ +}; + +/*! + * @brief Flash execute-in-RAM function information. + */ +typedef struct _flash_execute_in_ram_function_config +{ + uint32_t activeFunctionCount; /*!< Number of available execute-in-RAM functions.*/ + uint32_t *flashRunCommand; /*!< Execute-in-RAM function: flash_run_command.*/ + uint32_t *flashCommonBitOperation; /*!< Execute-in-RAM function: flash_common_bit_operation.*/ +} flash_execute_in_ram_function_config_t; + +/*! + * @brief Enumeration for the two possible options of flash read resource command. + */ +typedef enum _flash_read_resource_option +{ + kFLASH_ResourceOptionFlashIfr = + 0x00U, /*!< Select code for Program flash 0 IFR, Program flash swap 0 IFR, Data flash 0 IFR */ + kFLASH_ResourceOptionVersionId = 0x01U /*!< Select code for the version ID*/ +} flash_read_resource_option_t; + +/*! + * @brief Enumeration for the range of special-purpose flash resource + */ +enum _flash_read_resource_range +{ +#if (FSL_FEATURE_FLASH_IS_FTFE == 1) + kFLASH_ResourceRangePflashIfrSizeInBytes = 1024U, /*!< Pflash IFR size in byte.*/ + kFLASH_ResourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ + kFLASH_ResourceRangeVersionIdStart = 0x08U, /*!< Version ID IFR start address.*/ + kFLASH_ResourceRangeVersionIdEnd = 0x0FU, /*!< Version ID IFR end address.*/ + kFLASH_ResourceRangePflashSwapIfrStart = 0x40000U, /*!< Pflash swap IFR start address.*/ + kFLASH_ResourceRangePflashSwapIfrEnd = + (kFLASH_ResourceRangePflashSwapIfrStart + 0x3FFU), /*!< Pflash swap IFR end address.*/ +#else /* FSL_FEATURE_FLASH_IS_FTFL == 1 or FSL_FEATURE_FLASH_IS_FTFA = =1 */ + kFLASH_ResourceRangePflashIfrSizeInBytes = 256U, /*!< Pflash IFR size in byte.*/ + kFLASH_ResourceRangeVersionIdSizeInBytes = 8U, /*!< Version ID IFR size in byte.*/ + kFLASH_ResourceRangeVersionIdStart = 0x00U, /*!< Version ID IFR start address.*/ + kFLASH_ResourceRangeVersionIdEnd = 0x07U, /*!< Version ID IFR end address.*/ +#if 0x20000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) + kFLASH_ResourceRangePflashSwapIfrStart = 0x8000U, /*!< Pflash swap IFR start address.*/ +#elif 0x40000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) + kFLASH_ResourceRangePflashSwapIfrStart = 0x10000U, /*!< Pflash swap IFR start address.*/ +#elif 0x80000U == (FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT * FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE) + kFLASH_ResourceRangePflashSwapIfrStart = 0x20000U, /*!< Pflash swap IFR start address.*/ +#else + kFLASH_ResourceRangePflashSwapIfrStart = 0, +#endif + kFLASH_ResourceRangePflashSwapIfrEnd = + (kFLASH_ResourceRangePflashSwapIfrStart + 0xFFU), /*!< Pflash swap IFR end address.*/ +#endif + kFLASH_ResourceRangeDflashIfrStart = 0x800000U, /*!< Dflash IFR start address.*/ + kFLASH_ResourceRangeDflashIfrEnd = 0x8003FFU, /*!< Dflash IFR end address.*/ +}; + +/*! + * @brief Enumeration for the index of read/program once record + */ +enum _k3_flash_read_once_index +{ + kFLASH_RecordIndexSwapAddr = 0xA1U, /*!< Index of Swap indicator address.*/ + kFLASH_RecordIndexSwapEnable = 0xA2U, /*!< Index of Swap system enable.*/ + kFLASH_RecordIndexSwapDisable = 0xA3U, /*!< Index of Swap system disable.*/ +}; + +/*! + * @brief Enumeration for the two possilbe options of set FlexRAM function command. + */ +typedef enum _flash_flexram_function_option +{ + kFLASH_FlexramFunctionOptionAvailableAsRam = 0xFFU, /*!< An option used to make FlexRAM available as RAM */ + kFLASH_FlexramFunctionOptionAvailableForEeprom = 0x00U /*!< An option used to make FlexRAM available for EEPROM */ +} flash_flexram_function_option_t; + +/*! + * @brief Enumeration for acceleration RAM property. + */ +enum _flash_acceleration_ram_property +{ + kFLASH_AccelerationRamSize = 0x400U +}; + +/*! + * @brief Enumeration for the possible options of Swap function + */ +typedef enum _flash_swap_function_option +{ + kFLASH_SwapFunctionOptionEnable = 0x00U, /*!< An option used to enable the Swap function */ + kFLASH_SwapFunctionOptionDisable = 0x01U /*!< An option used to disable the Swap function */ +} flash_swap_function_option_t; + +/*! + * @brief Enumeration for the possible options of Swap control commands + */ +typedef enum _flash_swap_control_option +{ + kFLASH_SwapControlOptionIntializeSystem = 0x01U, /*!< An option used to initialize the Swap system */ + kFLASH_SwapControlOptionSetInUpdateState = 0x02U, /*!< An option used to set the Swap in an update state */ + kFLASH_SwapControlOptionSetInCompleteState = 0x04U, /*!< An option used to set the Swap in a complete state */ + kFLASH_SwapControlOptionReportStatus = 0x08U, /*!< An option used to report the Swap status */ + kFLASH_SwapControlOptionDisableSystem = 0x10U /*!< An option used to disable the Swap status */ +} flash_swap_control_option_t; + +/*! + * @brief Enumeration for the possible flash Swap status. + */ +typedef enum _flash_swap_state +{ + kFLASH_SwapStateUninitialized = 0x00U, /*!< Flash Swap system is in an uninitialized state.*/ + kFLASH_SwapStateReady = 0x01U, /*!< Flash Swap system is in a ready state.*/ + kFLASH_SwapStateUpdate = 0x02U, /*!< Flash Swap system is in an update state.*/ + kFLASH_SwapStateUpdateErased = 0x03U, /*!< Flash Swap system is in an updateErased state.*/ + kFLASH_SwapStateComplete = 0x04U, /*!< Flash Swap system is in a complete state.*/ + kFLASH_SwapStateDisabled = 0x05U /*!< Flash Swap system is in a disabled state.*/ +} flash_swap_state_t; + +/*! + * @breif Enumeration for the possible flash Swap block status + */ +typedef enum _flash_swap_block_status +{ + kFLASH_SwapBlockStatusLowerHalfProgramBlocksAtZero = + 0x00U, /*!< Swap block status is that lower half program block at zero.*/ + kFLASH_SwapBlockStatusUpperHalfProgramBlocksAtZero = + 0x01U, /*!< Swap block status is that upper half program block at zero.*/ +} flash_swap_block_status_t; + +/*! + * @brief Flash Swap information + */ +typedef struct _flash_swap_state_config +{ + flash_swap_state_t flashSwapState; /*!chip < FB_CSAR_COUNT); + assert(config->waitStates <= 0x3FU); + + uint32_t chip = 0; + uint32_t reg_value = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate clock for FLEXBUS */ + CLOCK_EnableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset all the register to default state */ + for (chip = 0; chip < FB_CSAR_COUNT; chip++) + { + /* Reset CSMR register, all chips not valid (disabled) */ + base->CS[chip].CSMR = 0x0000U; + /* Set default base address */ + base->CS[chip].CSAR &= (~FB_CSAR_BA_MASK); + /* Reset FB_CSCRx register */ + base->CS[chip].CSCR = 0x0000U; + } + /* Set FB_CSPMCR register */ + /* FlexBus signal group 1 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup1_FB_ALE << FB_CSPMCR_GROUP1_SHIFT; + /* FlexBus signal group 2 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup2_FB_CS4 << FB_CSPMCR_GROUP2_SHIFT; + /* FlexBus signal group 3 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup3_FB_CS5 << FB_CSPMCR_GROUP3_SHIFT; + /* FlexBus signal group 4 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup4_FB_TBST << FB_CSPMCR_GROUP4_SHIFT; + /* FlexBus signal group 5 multiplex control */ + reg_value |= kFLEXBUS_MultiplexGroup5_FB_TA << FB_CSPMCR_GROUP5_SHIFT; + /* Write to CSPMCR register */ + base->CSPMCR = reg_value; + + /* Update chip value */ + chip = config->chip; + + /* Base address */ + reg_value = config->chipBaseAddress; + /* Write to CSAR register */ + base->CS[chip].CSAR = reg_value; + /* Chip-select validation */ + reg_value = 0x1U << FB_CSMR_V_SHIFT; + /* Write protect */ + reg_value |= (uint32_t)(config->writeProtect) << FB_CSMR_WP_SHIFT; + /* Base address mask */ + reg_value |= config->chipBaseAddressMask << FB_CSMR_BAM_SHIFT; + /* Write to CSMR register */ + base->CS[chip].CSMR = reg_value; + /* Burst write */ + reg_value = (uint32_t)(config->burstWrite) << FB_CSCR_BSTW_SHIFT; + /* Burst read */ + reg_value |= (uint32_t)(config->burstRead) << FB_CSCR_BSTR_SHIFT; + /* Byte-enable mode */ + reg_value |= (uint32_t)(config->byteEnableMode) << FB_CSCR_BEM_SHIFT; + /* Port size */ + reg_value |= (uint32_t)config->portSize << FB_CSCR_PS_SHIFT; + /* The internal transfer acknowledge for accesses */ + reg_value |= (uint32_t)(config->autoAcknowledge) << FB_CSCR_AA_SHIFT; + /* Byte-Lane shift */ + reg_value |= (uint32_t)config->byteLaneShift << FB_CSCR_BLS_SHIFT; + /* The number of wait states */ + reg_value |= (uint32_t)config->waitStates << FB_CSCR_WS_SHIFT; + /* Write address hold or deselect */ + reg_value |= (uint32_t)config->writeAddressHold << FB_CSCR_WRAH_SHIFT; + /* Read address hold or deselect */ + reg_value |= (uint32_t)config->readAddressHold << FB_CSCR_RDAH_SHIFT; + /* Address setup */ + reg_value |= (uint32_t)config->addressSetup << FB_CSCR_ASET_SHIFT; + /* Extended transfer start/extended address latch */ + reg_value |= (uint32_t)(config->extendTransferAddress) << FB_CSCR_EXTS_SHIFT; + /* Secondary wait state */ + reg_value |= (uint32_t)(config->secondaryWaitStates) << FB_CSCR_SWSEN_SHIFT; + /* Write to CSCR register */ + base->CS[chip].CSCR = reg_value; + /* FlexBus signal group 1 multiplex control */ + reg_value = (uint32_t)config->group1MultiplexControl << FB_CSPMCR_GROUP1_SHIFT; + /* FlexBus signal group 2 multiplex control */ + reg_value |= (uint32_t)config->group2MultiplexControl << FB_CSPMCR_GROUP2_SHIFT; + /* FlexBus signal group 3 multiplex control */ + reg_value |= (uint32_t)config->group3MultiplexControl << FB_CSPMCR_GROUP3_SHIFT; + /* FlexBus signal group 4 multiplex control */ + reg_value |= (uint32_t)config->group4MultiplexControl << FB_CSPMCR_GROUP4_SHIFT; + /* FlexBus signal group 5 multiplex control */ + reg_value |= (uint32_t)config->group5MultiplexControl << FB_CSPMCR_GROUP5_SHIFT; + /* Write to CSPMCR register */ + base->CSPMCR = reg_value; +} + +void FLEXBUS_Deinit(FB_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock for FLEXBUS */ + CLOCK_DisableClock(s_flexbusClocks[FLEXBUS_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void FLEXBUS_GetDefaultConfig(flexbus_config_t *config) +{ + config->chip = 0; /* Chip 0 FlexBus for validation */ + config->writeProtect = 0; /* Write accesses are allowed */ + config->burstWrite = 0; /* Burst-Write disable */ + config->burstRead = 0; /* Burst-Read disable */ + config->byteEnableMode = 0; /* Byte-Enable mode is asserted for data write only */ + config->autoAcknowledge = true; /* Auto-Acknowledge enable */ + config->extendTransferAddress = 0; /* Extend transfer start/extend address latch disable */ + config->secondaryWaitStates = 0; /* Secondary wait state disable */ + config->byteLaneShift = kFLEXBUS_NotShifted; /* Byte-Lane shift disable */ + config->writeAddressHold = kFLEXBUS_Hold1Cycle; /* Write address hold 1 cycles */ + config->readAddressHold = kFLEXBUS_Hold1Or0Cycles; /* Read address hold 0 cycles */ + config->addressSetup = + kFLEXBUS_FirstRisingEdge; /* Assert ~FB_CSn on the first rising clock edge after the address is asserted */ + config->portSize = kFLEXBUS_1Byte; /* 1 byte port size of transfer */ + config->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; /* FB_ALE */ + config->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4; /* FB_CS4 */ + config->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; /* FB_CS5 */ + config->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; /* FB_TBST */ + config->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; /* FB_TA */ +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexbus.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexbus.h new file mode 100644 index 00000000000..f20ed44f055 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexbus.h @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_FLEXBUS_H_ +#define _FSL_FLEXBUS_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexbus + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_FLEXBUS_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ +/*@}*/ + +/*! + * @brief Defines port size for FlexBus peripheral. + */ +typedef enum _flexbus_port_size +{ + kFLEXBUS_4Bytes = 0x00U, /*!< 32-bit port size */ + kFLEXBUS_1Byte = 0x01U, /*!< 8-bit port size */ + kFLEXBUS_2Bytes = 0x02U /*!< 16-bit port size */ +} flexbus_port_size_t; + +/*! + * @brief Defines number of cycles to hold address and attributes for FlexBus peripheral. + */ +typedef enum _flexbus_write_address_hold +{ + kFLEXBUS_Hold1Cycle = 0x00U, /*!< Hold address and attributes one cycles after FB_CSn negates on writes */ + kFLEXBUS_Hold2Cycles = 0x01U, /*!< Hold address and attributes two cycles after FB_CSn negates on writes */ + kFLEXBUS_Hold3Cycles = 0x02U, /*!< Hold address and attributes three cycles after FB_CSn negates on writes */ + kFLEXBUS_Hold4Cycles = 0x03U /*!< Hold address and attributes four cycles after FB_CSn negates on writes */ +} flexbus_write_address_hold_t; + +/*! + * @brief Defines number of cycles to hold address and attributes for FlexBus peripheral. + */ +typedef enum _flexbus_read_address_hold +{ + kFLEXBUS_Hold1Or0Cycles = 0x00U, /*!< Hold address and attributes 1 or 0 cycles on reads */ + kFLEXBUS_Hold2Or1Cycles = 0x01U, /*!< Hold address and attributes 2 or 1 cycles on reads */ + kFLEXBUS_Hold3Or2Cycle = 0x02U, /*!< Hold address and attributes 3 or 2 cycles on reads */ + kFLEXBUS_Hold4Or3Cycle = 0x03U /*!< Hold address and attributes 4 or 3 cycles on reads */ +} flexbus_read_address_hold_t; + +/*! + * @brief Address setup for FlexBus peripheral. + */ +typedef enum _flexbus_address_setup +{ + kFLEXBUS_FirstRisingEdge = 0x00U, /*!< Assert FB_CSn on first rising clock edge after address is asserted */ + kFLEXBUS_SecondRisingEdge = 0x01U, /*!< Assert FB_CSn on second rising clock edge after address is asserted */ + kFLEXBUS_ThirdRisingEdge = 0x02U, /*!< Assert FB_CSn on third rising clock edge after address is asserted */ + kFLEXBUS_FourthRisingEdge = 0x03U, /*!< Assert FB_CSn on fourth rising clock edge after address is asserted */ +} flexbus_address_setup_t; + +/*! + * @brief Defines byte-lane shift for FlexBus peripheral. + */ +typedef enum _flexbus_bytelane_shift +{ + kFLEXBUS_NotShifted = 0x00U, /*!< Not shifted. Data is left-justified on FB_AD */ + kFLEXBUS_Shifted = 0x01U, /*!< Shifted. Data is right justified on FB_AD */ +} flexbus_bytelane_shift_t; + +/*! + * @brief Defines multiplex group1 valid signals. + */ +typedef enum _flexbus_multiplex_group1_signal +{ + kFLEXBUS_MultiplexGroup1_FB_ALE = 0x00U, /*!< FB_ALE */ + kFLEXBUS_MultiplexGroup1_FB_CS1 = 0x01U, /*!< FB_CS1 */ + kFLEXBUS_MultiplexGroup1_FB_TS = 0x02U, /*!< FB_TS */ +} flexbus_multiplex_group1_t; + +/*! + * @brief Defines multiplex group2 valid signals. + */ +typedef enum _flexbus_multiplex_group2_signal +{ + kFLEXBUS_MultiplexGroup2_FB_CS4 = 0x00U, /*!< FB_CS4 */ + kFLEXBUS_MultiplexGroup2_FB_TSIZ0 = 0x01U, /*!< FB_TSIZ0 */ + kFLEXBUS_MultiplexGroup2_FB_BE_31_24 = 0x02U, /*!< FB_BE_31_24 */ +} flexbus_multiplex_group2_t; + +/*! + * @brief Defines multiplex group3 valid signals. + */ +typedef enum _flexbus_multiplex_group3_signal +{ + kFLEXBUS_MultiplexGroup3_FB_CS5 = 0x00U, /*!< FB_CS5 */ + kFLEXBUS_MultiplexGroup3_FB_TSIZ1 = 0x01U, /*!< FB_TSIZ1 */ + kFLEXBUS_MultiplexGroup3_FB_BE_23_16 = 0x02U, /*!< FB_BE_23_16 */ +} flexbus_multiplex_group3_t; + +/*! + * @brief Defines multiplex group4 valid signals. + */ +typedef enum _flexbus_multiplex_group4_signal +{ + kFLEXBUS_MultiplexGroup4_FB_TBST = 0x00U, /*!< FB_TBST */ + kFLEXBUS_MultiplexGroup4_FB_CS2 = 0x01U, /*!< FB_CS2 */ + kFLEXBUS_MultiplexGroup4_FB_BE_15_8 = 0x02U, /*!< FB_BE_15_8 */ +} flexbus_multiplex_group4_t; + +/*! + * @brief Defines multiplex group5 valid signals. + */ +typedef enum _flexbus_multiplex_group5_signal +{ + kFLEXBUS_MultiplexGroup5_FB_TA = 0x00U, /*!< FB_TA */ + kFLEXBUS_MultiplexGroup5_FB_CS3 = 0x01U, /*!< FB_CS3 */ + kFLEXBUS_MultiplexGroup5_FB_BE_7_0 = 0x02U, /*!< FB_BE_7_0 */ +} flexbus_multiplex_group5_t; + +/*! + * @brief Configuration structure that the user needs to set. + */ +typedef struct _flexbus_config +{ + uint8_t chip; /*!< Chip FlexBus for validation */ + uint8_t waitStates; /*!< Value of wait states */ + uint32_t chipBaseAddress; /*!< Chip base address for using FlexBus */ + uint32_t chipBaseAddressMask; /*!< Chip base address mask */ + bool writeProtect; /*!< Write protected */ + bool burstWrite; /*!< Burst-Write enable */ + bool burstRead; /*!< Burst-Read enable */ + bool byteEnableMode; /*!< Byte-enable mode support */ + bool autoAcknowledge; /*!< Auto acknowledge setting */ + bool extendTransferAddress; /*!< Extend transfer start/extend address latch enable */ + bool secondaryWaitStates; /*!< Secondary wait states number */ + flexbus_port_size_t portSize; /*!< Port size of transfer */ + flexbus_bytelane_shift_t byteLaneShift; /*!< Byte-lane shift enable */ + flexbus_write_address_hold_t writeAddressHold; /*!< Write address hold or deselect option */ + flexbus_read_address_hold_t readAddressHold; /*!< Read address hold or deselect option */ + flexbus_address_setup_t addressSetup; /*!< Address setup setting */ + flexbus_multiplex_group1_t group1MultiplexControl; /*!< FlexBus Signal Group 1 Multiplex control */ + flexbus_multiplex_group2_t group2MultiplexControl; /*!< FlexBus Signal Group 2 Multiplex control */ + flexbus_multiplex_group3_t group3MultiplexControl; /*!< FlexBus Signal Group 3 Multiplex control */ + flexbus_multiplex_group4_t group4MultiplexControl; /*!< FlexBus Signal Group 4 Multiplex control */ + flexbus_multiplex_group5_t group5MultiplexControl; /*!< FlexBus Signal Group 5 Multiplex control */ +} flexbus_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name FlexBus functional operation + * @{ + */ + +/*! + * @brief Initializes and configures the FlexBus module. + * + * This function enables the clock gate for FlexBus module. + * Only chip 0 is validated and set to known values. Other chips are disabled. + * Note that in this function, certain parameters, depending on external memories, must + * be set before using the FLEXBUS_Init() function. + * This example shows how to set up the uart_state_t and the + * flexbus_config_t parameters and how to call the FLEXBUS_Init function by passing + * in these parameters. + @code + flexbus_config_t flexbusConfig; + FLEXBUS_GetDefaultConfig(&flexbusConfig); + flexbusConfig.waitStates = 2U; + flexbusConfig.chipBaseAddress = 0x60000000U; + flexbusConfig.chipBaseAddressMask = 7U; + FLEXBUS_Init(FB, &flexbusConfig); + @endcode + * + * @param base FlexBus peripheral address. + * @param config Pointer to the configuration structure +*/ +void FLEXBUS_Init(FB_Type *base, const flexbus_config_t *config); + +/*! + * @brief De-initializes a FlexBus instance. + * + * This function disables the clock gate of the FlexBus module clock. + * + * @param base FlexBus peripheral address. + */ +void FLEXBUS_Deinit(FB_Type *base); + +/*! + * @brief Initializes the FlexBus configuration structure. + * + * This function initializes the FlexBus configuration structure to default value. The default + * values are. + @code + fbConfig->chip = 0; + fbConfig->writeProtect = 0; + fbConfig->burstWrite = 0; + fbConfig->burstRead = 0; + fbConfig->byteEnableMode = 0; + fbConfig->autoAcknowledge = true; + fbConfig->extendTransferAddress = 0; + fbConfig->secondaryWaitStates = 0; + fbConfig->byteLaneShift = kFLEXBUS_NotShifted; + fbConfig->writeAddressHold = kFLEXBUS_Hold1Cycle; + fbConfig->readAddressHold = kFLEXBUS_Hold1Or0Cycles; + fbConfig->addressSetup = kFLEXBUS_FirstRisingEdge; + fbConfig->portSize = kFLEXBUS_1Byte; + fbConfig->group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; + fbConfig->group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4 ; + fbConfig->group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; + fbConfig->group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; + fbConfig->group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; + @endcode + * @param config Pointer to the initialization structure. + * @see FLEXBUS_Init + */ +void FLEXBUS_GetDefaultConfig(flexbus_config_t *config); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_FLEXBUS_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.c new file mode 100644 index 00000000000..f58f3f55f05 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.c @@ -0,0 +1,1407 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_flexcan.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ + +#define FLEXCAN_TIME_QUANTA_NUM (10) + +/*! @brief FlexCAN Internal State. */ +enum _flexcan_state +{ + kFLEXCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ + kFLEXCAN_StateRxData = 0x1, /*!< MB receiving.*/ + kFLEXCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ + kFLEXCAN_StateTxData = 0x3, /*!< MB transmitting.*/ + kFLEXCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ + kFLEXCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ +}; + +/*! @brief FlexCAN message buffer CODE for Rx buffers. */ +enum _flexcan_mb_code_rx +{ + kFLEXCAN_RxMbInactive = 0x0, /*!< MB is not active.*/ + kFLEXCAN_RxMbFull = 0x2, /*!< MB is full.*/ + kFLEXCAN_RxMbEmpty = 0x4, /*!< MB is active and empty.*/ + kFLEXCAN_RxMbOverrun = 0x6, /*!< MB is overwritten into a full buffer.*/ + kFLEXCAN_RxMbBusy = 0x8, /*!< FlexCAN is updating the contents of the MB.*/ + /*! The CPU must not access the MB.*/ + kFLEXCAN_RxMbRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame */ + /*! and transmit a Response Frame in return.*/ + kFLEXCAN_RxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/*! @brief FlexCAN message buffer CODE FOR Tx buffers. */ +enum _flexcan_mb_code_tx +{ + kFLEXCAN_TxMbInactive = 0x8, /*!< MB is not active.*/ + kFLEXCAN_TxMbAbort = 0x9, /*!< MB is aborted.*/ + kFLEXCAN_TxMbDataOrRemote = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */ + /*!< MB is a TX Remote Request Frame (when MB RTR = 1).*/ + kFLEXCAN_TxMbTanswer = 0xE, /*!< MB is a TX Response Request Frame from */ + /*! an incoming Remote Request Frame.*/ + kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/* Typedef for interrupt handler. */ +typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the FlexCAN instance from peripheral base address. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base); + +/*! + * @brief Enter FlexCAN Freeze Mode. + * + * This function makes the FlexCAN work under Freeze Mode. + * + * @param base FlexCAN peripheral base address. + */ +static void FLEXCAN_EnterFreezeMode(CAN_Type *base); + +/*! + * @brief Exit FlexCAN Freeze Mode. + * + * This function makes the FlexCAN leave Freeze Mode. + * + * @param base FlexCAN peripheral base address. + */ +static void FLEXCAN_ExitFreezeMode(CAN_Type *base); + +#if !defined(NDEBUG) +/*! + * @brief Check if Message Buffer is occupied by Rx FIFO. + * + * This function check if Message Buffer is occupied by Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + */ +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +/*! + * @brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * @param base FlexCAN peripheral base address. + * @return The first valid Message Buffer Number. + */ +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base); +#endif + +/*! + * @brief Check if Message Buffer interrupt is enabled. + * + * This function check if Message Buffer interrupt is enabled. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + */ +static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx); + +/*! + * @brief Reset the FlexCAN Instance. + * + * Restores the FlexCAN module to reset state, notice that this function + * will set all the registers to reset state so the FlexCAN module can not work + * after calling this API. + * + * @param base FlexCAN peripheral base address. +*/ +static void FLEXCAN_Reset(CAN_Type *base); + +/*! + * @brief Set Baud Rate of FlexCAN. + * + * This function set the baud rate of FlexCAN. + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param baudRate_Bps Baud Rate in Bps. + */ +static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of FlexCAN peripheral base address. */ +static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS; + +/* Array of FlexCAN IRQ number. */ +static const IRQn_Type s_flexcanRxWarningIRQ[] = CAN_Rx_Warning_IRQS; +static const IRQn_Type s_flexcanTxWarningIRQ[] = CAN_Tx_Warning_IRQS; +static const IRQn_Type s_flexcanWakeUpIRQ[] = CAN_Wake_Up_IRQS; +static const IRQn_Type s_flexcanErrorIRQ[] = CAN_Error_IRQS; +static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS; +static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; + +/* Array of FlexCAN handle. */ +static flexcan_handle_t *s_flexcanHandle[ARRAY_SIZE(s_flexcanBases)]; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of FlexCAN clock name. */ +static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; +#if defined(FLEXCAN_PERIPH_CLOCKS) +/* Array of FlexCAN serial clock name. */ +static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS; +#endif /* FLEXCAN_PERIPH_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* FlexCAN ISR for transactional APIs. */ +static flexcan_isr_t s_flexcanIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t FLEXCAN_GetInstance(CAN_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexcanBases); instance++) + { + if (s_flexcanBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexcanBases)); + + return instance; +} + +static void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + /* Set Freeze, Halt bits. */ + base->MCR |= CAN_MCR_HALT_MASK; + + /* Wait until the FlexCAN Module enter freeze mode. */ + while (!(base->MCR & CAN_MCR_FRZACK_MASK)) + { + } +} + +static void FLEXCAN_ExitFreezeMode(CAN_Type *base) +{ + /* Clear Freeze, Halt bits. */ + base->MCR &= ~CAN_MCR_HALT_MASK; + + /* Wait until the FlexCAN Module exit freeze mode. */ + while (base->MCR & CAN_MCR_FRZACK_MASK) + { + } +} + +#if !defined(NDEBUG) +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) +{ + uint8_t lastOccupiedMb; + + /* Is Rx FIFO enabled? */ + if (base->MCR & CAN_MCR_RFEN_MASK) + { + /* Get RFFN value. */ + lastOccupiedMb = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ + lastOccupiedMb = ((lastOccupiedMb + 1) * 2) + 5; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + if (mbIdx <= (lastOccupiedMb + 1)) +#else + if (mbIdx <= lastOccupiedMb) +#endif + { + return true; + } + else + { + return false; + } + } + else + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + if (0 == mbIdx) + { + return true; + } + else + { + return false; + } +#else + return false; +#endif + } +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base) +{ + uint32_t firstValidMbNum; + + if (base->MCR & CAN_MCR_RFEN_MASK) + { + firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + firstValidMbNum = ((firstValidMbNum + 1) * 2) + 6; + } + else + { + firstValidMbNum = 0; + } + + return firstValidMbNum; +} +#endif + +static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx) +{ + /* Assertion. */ + assert(mbIdx < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)); + +#if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + if (mbIdx < 32) + { +#endif + if (base->IMASK1 & ((uint32_t)(1 << mbIdx))) + { + return true; + } + else + { + return false; + } +#if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + } + else + { + if (base->IMASK2 & ((uint32_t)(1 << (mbIdx - 32)))) + { + return true; + } + else + { + return false; + } + } +#endif +} + +static void FLEXCAN_Reset(CAN_Type *base) +{ + /* The module must should be first exit from low power + * mode, and then soft reset can be applied. + */ + assert(!(base->MCR & CAN_MCR_MDIS_MASK)); + + uint8_t i; + +#if (FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT != 0) + /* De-assert DOZE Enable Bit. */ + base->MCR &= ~CAN_MCR_DOZE_MASK; +#endif + + /* Wait until FlexCAN exit from any Low Power Mode. */ + while (base->MCR & CAN_MCR_LPMACK_MASK) + { + } + + /* Assert Soft Reset Signal. */ + base->MCR |= CAN_MCR_SOFTRST_MASK; + /* Wait until FlexCAN reset completes. */ + while (base->MCR & CAN_MCR_SOFTRST_MASK) + { + } + +/* Reset MCR rigister. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | + CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); +#else + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); +#endif + + /* Reset CTRL1 and CTRL2 rigister. */ + base->CTRL1 = CAN_CTRL1_SMP_MASK; + base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK; + + /* Clean all individual Rx Mask of Message Buffers. */ + for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) + { + base->RXIMR[i] = 0x3FFFFFFF; + } + + /* Clean Global Mask of Message Buffers. */ + base->RXMGMASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 14. */ + base->RX14MASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 15. */ + base->RX15MASK = 0x3FFFFFFF; + /* Clean Global Mask of Rx FIFO. */ + base->RXFGMASK = 0x3FFFFFFF; + + /* Clean all Message Buffer CS fields. */ + for (i = 0; i < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) + { + base->MB[i].CS = 0x0; + } +} + +static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps) +{ + flexcan_timing_config_t timingConfig; + uint32_t priDiv = baudRate_Bps * FLEXCAN_TIME_QUANTA_NUM; + + /* Assertion: Desired baud rate is too high. */ + assert(baudRate_Bps <= 1000000U); + /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */ + assert(priDiv <= sourceClock_Hz); + + if (0 == priDiv) + { + priDiv = 1; + } + + priDiv = (sourceClock_Hz / priDiv) - 1; + + /* Desired baud rate is too low. */ + if (priDiv > 0xFF) + { + priDiv = 0xFF; + } + + /* FlexCAN timing setting formula: + * FLEXCAN_TIME_QUANTA_NUM = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); + */ + timingConfig.preDivider = priDiv; + timingConfig.phaseSeg1 = 3; + timingConfig.phaseSeg2 = 2; + timingConfig.propSeg = 1; + timingConfig.rJumpwidth = 1; + + /* Update actual timing characteristic. */ + FLEXCAN_SetTimingConfig(base, &timingConfig); +} + +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz) +{ + uint32_t mcrTemp; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance; +#endif + + /* Assertion. */ + assert(config); + assert((config->maxMbNum > 0) && (config->maxMbNum <= FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + instance = FLEXCAN_GetInstance(base); + /* Enable FlexCAN clock. */ + CLOCK_EnableClock(s_flexcanClock[instance]); +#if defined(FLEXCAN_PERIPH_CLOCKS) + /* Enable FlexCAN serial clock. */ + CLOCK_EnableClock(s_flexcanPeriphClock[instance]); +#endif /* FLEXCAN_PERIPH_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE + /* Disable FlexCAN Module. */ + FLEXCAN_Enable(base, false); + + /* Protocol-Engine clock source selection, This bit must be set + * when FlexCAN Module in Disable Mode. + */ + base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK : + base->CTRL1 | CAN_CTRL1_CLKSRC_MASK; +#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + + /* Enable FlexCAN Module for configuartion. */ + FLEXCAN_Enable(base, true); + + /* Reset to known status. */ + FLEXCAN_Reset(base); + + /* Save current MCR value and enable to enter Freeze mode(enabled by default). */ + mcrTemp = base->MCR; + + /* Set the maximum number of Message Buffers */ + mcrTemp = (mcrTemp & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB(config->maxMbNum - 1); + + /* Enable Loop Back Mode? */ + base->CTRL1 = (config->enableLoopBack) ? base->CTRL1 | CAN_CTRL1_LPB_MASK : base->CTRL1 & ~CAN_CTRL1_LPB_MASK; + + /* Enable Self Wake Up Mode? */ + mcrTemp = (config->enableSelfWakeup) ? mcrTemp | CAN_MCR_SLFWAK_MASK : mcrTemp & ~CAN_MCR_SLFWAK_MASK; + + /* Enable Individual Rx Masking? */ + mcrTemp = (config->enableIndividMask) ? mcrTemp | CAN_MCR_IRMQ_MASK : mcrTemp & ~CAN_MCR_IRMQ_MASK; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + /* Enable Doze Mode? */ + mcrTemp = (config->enableDoze) ? mcrTemp | CAN_MCR_DOZE_MASK : mcrTemp & ~CAN_MCR_DOZE_MASK; +#endif + + /* Save MCR Configuation. */ + base->MCR = mcrTemp; + + /* Baud Rate Configuration.*/ + FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate); +} + +void FLEXCAN_Deinit(CAN_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance; +#endif + /* Reset all Register Contents. */ + FLEXCAN_Reset(base); + + /* Disable FlexCAN module. */ + FLEXCAN_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + instance = FLEXCAN_GetInstance(base); +#if defined(FLEXCAN_PERIPH_CLOCKS) + /* Disable FlexCAN serial clock. */ + CLOCK_DisableClock(s_flexcanPeriphClock[instance]); +#endif /* FLEXCAN_PERIPH_CLOCKS */ + /* Disable FlexCAN clock. */ + CLOCK_DisableClock(s_flexcanClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void FLEXCAN_GetDefaultConfig(flexcan_config_t *config) +{ + /* Assertion. */ + assert(config); + + /* Initialize FlexCAN Module config struct with default value. */ +#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE + config->clkSrc = kFLEXCAN_ClkSrcOsc; +#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + config->baudRate = 125000U; + config->maxMbNum = 16; + config->enableLoopBack = false; + config->enableSelfWakeup = false; + config->enableIndividMask = false; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + config->enableDoze = false; +#endif +} + +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) +{ + /* Assertion. */ + assert(config); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Cleaning previous Timing Setting. */ + base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_PROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CTRL1 |= + (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | + CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg)); + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx Message Buffer Global Mask value. */ + base->RXMGMASK = mask; + base->RX14MASK = mask; + base->RX15MASK = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx FIFO Global Mask value. */ + base->RXFGMASK = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) +{ + assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx Individual Mask value. */ + base->RXIMR[maskIdx] = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + /* Inactivate Message Buffer. */ + if (enable) + { + base->MB[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + } + else + { + base->MB[mbIdx].CS = 0; + } + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; +} + +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(((config) || (false == enable))); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp = 0; + + /* Inactivate Message Buffer. */ + base->MB[mbIdx].CS = 0; + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; + + if (enable) + { + /* Setup Message Buffer ID. */ + base->MB[mbIdx].ID = config->id; + + /* Setup Message Buffer format. */ + if (kFLEXCAN_FrameFormatExtend == config->format) + { + cs_temp |= CAN_CS_IDE_MASK; + } + + /* Setup Message Buffer type. */ + if (kFLEXCAN_FrameTypeRemote == config->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + /* Activate Rx Message Buffer. */ + cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); + base->MB[mbIdx].CS = cs_temp; + } +} + +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) +{ + /* Assertion. */ + assert((config) || (false == enable)); + + volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS); + uint8_t setup_mb, i, rffn = 0; + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + { + assert(config->idFilterNum <= 128); + + /* Get the setup_mb value. */ + setup_mb = (base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT; + setup_mb = (setup_mb < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ? + setup_mb : + FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); + + /* Determine RFFN value. */ + for (i = 0; i <= 0xF; i++) + { + if ((8 * (i + 1)) >= config->idFilterNum) + { + rffn = i; + assert(((setup_mb - 8) - (2 * rffn)) > 0); + + base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(rffn); + break; + } + } + } + else + { + rffn = (base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT; + } + + /* Clean ID filter table occuyied Message Buffer Region. */ + rffn = (rffn + 1) * 8; + for (i = 0; i < rffn; i++) + { + idFilterRegion[i] = 0x0; + } + + if (enable) + { + /* Disable unused Rx FIFO Filter. */ + for (i = config->idFilterNum; i < rffn; i++) + { + idFilterRegion[i] = 0xFFFFFFFFU; + } + + /* Copy ID filter table to Message Buffer Region. */ + for (i = 0; i < config->idFilterNum; i++) + { + idFilterRegion[i] = config->idFilterTable[i]; + } + + /* Setup ID Fitlter Type. */ + switch (config->idFilterType) + { + case kFLEXCAN_RxFifoFilterTypeA: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x0); + break; + case kFLEXCAN_RxFifoFilterTypeB: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x1); + break; + case kFLEXCAN_RxFifoFilterTypeC: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x2); + break; + case kFLEXCAN_RxFifoFilterTypeD: + /* All frames rejected. */ + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3); + break; + default: + break; + } + + /* Setting Message Reception Priority. */ + base->CTRL2 = (config->priority == kFLEXCAN_RxFifoPrioHigh) ? base->CTRL2 & ~CAN_CTRL2_MRP_MASK : + base->CTRL2 | CAN_CTRL2_MRP_MASK; + + /* Enable Rx Message FIFO. */ + base->MCR |= CAN_MCR_RFEN_MASK; + } + else + { + /* Disable Rx Message FIFO. */ + base->MCR &= ~CAN_MCR_RFEN_MASK; + + /* Clean MB0 ~ MB5. */ + FLEXCAN_SetRxMbConfig(base, 0, NULL, false); + FLEXCAN_SetRxMbConfig(base, 1, NULL, false); + FLEXCAN_SetRxMbConfig(base, 2, NULL, false); + FLEXCAN_SetRxMbConfig(base, 3, NULL, false); + FLEXCAN_SetRxMbConfig(base, 4, NULL, false); + FLEXCAN_SetRxMbConfig(base, 5, NULL, false); + } + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) +{ + if (enable) + { + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Enable FlexCAN DMA. */ + base->MCR |= CAN_MCR_DMA_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + } + else + { + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Disable FlexCAN DMA. */ + base->MCR &= ~CAN_MCR_DMA_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + } +} +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(txFrame); + assert(txFrame->length <= 8); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp = 0; + + /* Check if Message Buffer is available. */ + if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) + { + /* Inactive Tx Message Buffer. */ + base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + + /* Fill Message ID field. */ + base->MB[mbIdx].ID = txFrame->id; + + /* Fill Message Format field. */ + if (kFLEXCAN_FrameFormatExtend == txFrame->format) + { + cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; + } + + /* Fill Message Type field. */ + if (kFLEXCAN_FrameTypeRemote == txFrame->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length); + + /* Load Message Payload. */ + base->MB[mbIdx].WORD0 = txFrame->dataWord0; + base->MB[mbIdx].WORD1 = txFrame->dataWord1; + + /* Activate Tx Message Buffer. */ + base->MB[mbIdx].CS = cs_temp; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + + return kStatus_Success; + } + else + { + /* Tx Message Buffer is activated, return immediately. */ + return kStatus_Fail; + } +} + +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(rxFrame); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp; + uint8_t rx_code; + + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[mbIdx].CS; + /* Get Rx Message Buffer Code field. */ + rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; + + /* Check to see if Rx Message Buffer is full. */ + if ((kFLEXCAN_RxMbFull == rx_code) || (kFLEXCAN_RxMbOverrun == rx_code)) + { + /* Store Message ID. */ + rxFrame->id = base->MB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; + + /* Store Message Payload. */ + rxFrame->dataWord0 = base->MB[mbIdx].WORD0; + rxFrame->dataWord1 = base->MB[mbIdx].WORD1; + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + if (kFLEXCAN_RxMbFull == rx_code) + { + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxOverflow; + } + } + else + { + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + return kStatus_Fail; + } +} + +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) +{ + /* Assertion. */ + assert(rxFrame); + + uint32_t cs_temp; + + /* Check if Rx FIFO is Enabled. */ + if (base->MCR & CAN_MCR_RFEN_MASK) + { + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[0].CS; + + /* Read data from Rx FIFO output port. */ + /* Store Message ID. */ + rxFrame->id = base->MB[0].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) ? kFLEXCAN_FrameFormatExtend : kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + rxFrame->type = (cs_temp & CAN_CS_RTR_MASK) ? kFLEXCAN_FrameTypeRemote : kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT; + + /* Store Message Payload. */ + rxFrame->dataWord0 = base->MB[0].WORD0; + rxFrame->dataWord1 = base->MB[0].WORD1; + + /* Store ID Filter Hit Index. */ + rxFrame->idhit = (uint8_t)(base->RXFIR & CAN_RXFIR_IDHIT_MASK); + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) +{ + /* Write Tx Message Buffer to initiate a data sending. */ + if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, txFrame)) + { + /* Wait until CAN Message send out. */ + while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) + { + } + + /* Clean Tx Message Buffer Flag. */ + FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); + + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) +{ + /* Wait until Rx Message Buffer non-empty. */ + while (!FLEXCAN_GetMbStatusFlags(base, 1 << mbIdx)) + { + } + + /* Clean Rx Message Buffer Flag. */ + FLEXCAN_ClearMbStatusFlags(base, 1 << mbIdx); + + /* Read Received CAN Message. */ + return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame); +} + +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) +{ + status_t rxFifoStatus; + + /* Wait until Rx FIFO non-empty. */ + while (!FLEXCAN_GetMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag)) + { + } + + /* */ + rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame); + + /* Clean Rx Fifo available flag. */ + FLEXCAN_ClearMbStatusFlags(base, kFLEXCAN_RxFifoFrameAvlFlag); + + return rxFifoStatus; +} + +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint8_t instance; + + /* Clean FlexCAN transfer handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Get instance from peripheral base address. */ + instance = FLEXCAN_GetInstance(base); + + /* Save the context in global variables to support the double weak mechanism. */ + s_flexcanHandle[instance] = handle; + + /* Register Callback function. */ + handle->callback = callback; + handle->userData = userData; + + s_flexcanIsr = FLEXCAN_TransferHandleIRQ; + + /* We Enable Error & Status interrupt here, because this interrupt just + * report current status of FlexCAN module through Callback function. + * It is insignificance without a available callback function. + */ + if (handle->callback != NULL) + { + FLEXCAN_EnableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable | + kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable | + kFLEXCAN_WakeUpInterruptEnable); + } + else + { + FLEXCAN_DisableInterrupts(base, kFLEXCAN_BusOffInterruptEnable | kFLEXCAN_ErrorInterruptEnable | + kFLEXCAN_RxWarningInterruptEnable | kFLEXCAN_TxWarningInterruptEnable | + kFLEXCAN_WakeUpInterruptEnable); + } + + /* Enable interrupts in NVIC. */ + EnableIRQ((IRQn_Type)(s_flexcanRxWarningIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanTxWarningIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanWakeUpIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanErrorIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanBusOffIRQ[instance])); + EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance])); +} + +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) +{ + /* Assertion. */ + assert(handle); + assert(xfer); + assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); + + /* Check if Message Buffer is idle. */ + if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) + { + /* Distinguish transmit type. */ + if (kFLEXCAN_FrameTypeRemote == xfer->frame->type) + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxRemote; + + /* Register user Frame buffer to receive remote Frame. */ + handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; + } + else + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateTxData; + } + + if (kStatus_Success == FLEXCAN_WriteTxMb(base, xfer->mbIdx, xfer->frame)) + { + /* Enable Message Buffer Interrupt. */ + FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); + + return kStatus_Success; + } + else + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateIdle; + return kStatus_Fail; + } + } + else + { + return kStatus_FLEXCAN_TxBusy; + } +} + +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) +{ + /* Assertion. */ + assert(handle); + assert(xfer); + assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); + + /* Check if Message Buffer is idle. */ + if (kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) + { + handle->mbState[xfer->mbIdx] = kFLEXCAN_StateRxData; + + /* Register Message Buffer. */ + handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; + + /* Enable Message Buffer Interrupt. */ + FLEXCAN_EnableMbInterrupts(base, 1 << xfer->mbIdx); + + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxBusy; + } +} + +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *xfer) +{ + /* Assertion. */ + assert(handle); + assert(xfer); + + /* Check if Message Buffer is idle. */ + if (kFLEXCAN_StateIdle == handle->rxFifoState) + { + handle->rxFifoState = kFLEXCAN_StateRxFifo; + + /* Register Message Buffer. */ + handle->rxFifoFrameBuf = xfer->frame; + + /* Enable Message Buffer Interrupt. */ + FLEXCAN_EnableMbInterrupts( + base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag); + + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxFifoBusy; + } +} + +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + /* Disable Message Buffer Interrupt. */ + FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); + + /* Un-register handle. */ + handle->mbFrameBuf[mbIdx] = 0x0; + + /* Clean Message Buffer. */ + FLEXCAN_SetTxMbConfig(base, mbIdx, true); + + handle->mbState[mbIdx] = kFLEXCAN_StateIdle; +} + +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + /* Disable Message Buffer Interrupt. */ + FLEXCAN_DisableMbInterrupts(base, 1 << mbIdx); + + /* Un-register handle. */ + handle->mbFrameBuf[mbIdx] = 0x0; + handle->mbState[mbIdx] = kFLEXCAN_StateIdle; +} + +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(handle); + + /* Check if Rx FIFO is enabled. */ + if (base->MCR & CAN_MCR_RFEN_MASK) + { + /* Disable Rx Message FIFO Interrupts. */ + FLEXCAN_DisableMbInterrupts( + base, kFLEXCAN_RxFifoOverflowFlag | kFLEXCAN_RxFifoWarningFlag | kFLEXCAN_RxFifoFrameAvlFlag); + + /* Un-register handle. */ + handle->rxFifoFrameBuf = 0x0; + } + + handle->rxFifoState = kFLEXCAN_StateIdle; +} + +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(handle); + + status_t status = kStatus_FLEXCAN_UnHandled; + uint32_t result; + + /* Store Current FlexCAN Module Error and Status. */ + result = base->ESR1; + + do + { + /* Solve FlexCAN Error and Status Interrupt. */ + if (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | + kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)) + { + status = kStatus_FLEXCAN_ErrorStatus; + + /* Clear FlexCAN Error and Status Interrupt. */ + FLEXCAN_ClearStatusFlags(base, kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | + kFLEXCAN_BusOffIntFlag | kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag); + } + /* Solve FlexCAN Rx FIFO & Message Buffer Interrupt. */ + else + { + /* For this implementation, we solve the Message with lowest MB index first. */ + for (result = 0; result < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++) + { + /* Get the lowest unhandled Message Buffer */ + if ((FLEXCAN_GetMbStatusFlags(base, 1 << result)) && (FLEXCAN_IsMbIntEnabled(base, result))) + { + break; + } + } + + /* Does not find Message to deal with. */ + if (result == FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) + { + break; + } + + /* Solve Rx FIFO interrupt. */ + if ((kFLEXCAN_StateIdle != handle->rxFifoState) && ((1 << result) <= kFLEXCAN_RxFifoOverflowFlag)) + { + switch (1 << result) + { + case kFLEXCAN_RxFifoOverflowFlag: + status = kStatus_FLEXCAN_RxFifoOverflow; + break; + + case kFLEXCAN_RxFifoWarningFlag: + status = kStatus_FLEXCAN_RxFifoWarning; + break; + + case kFLEXCAN_RxFifoFrameAvlFlag: + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxFifoIdle; + } + FLEXCAN_TransferAbortReceiveFifo(base, handle); + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + } + else + { + /* Get current State of Message Buffer. */ + switch (handle->mbState[result]) + { + /* Solve Rx Data Frame. */ + case kFLEXCAN_StateRxData: + status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } + FLEXCAN_TransferAbortReceive(base, handle, result); + break; + + /* Solve Rx Remote Frame. */ + case kFLEXCAN_StateRxRemote: + status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } + FLEXCAN_TransferAbortReceive(base, handle, result); + break; + + /* Solve Tx Data Frame. */ + case kFLEXCAN_StateTxData: + status = kStatus_FLEXCAN_TxIdle; + FLEXCAN_TransferAbortSend(base, handle, result); + break; + + /* Solve Tx Remote Frame. */ + case kFLEXCAN_StateTxRemote: + handle->mbState[result] = kFLEXCAN_StateRxRemote; + status = kStatus_FLEXCAN_TxSwitchToRx; + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + } + + /* Clear resolved Message Buffer IRQ. */ + FLEXCAN_ClearMbStatusFlags(base, 1 << result); + } + + /* Calling Callback Function if has one. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, status, result, handle->userData); + } + + /* Reset return status */ + status = kStatus_FLEXCAN_UnHandled; + + /* Store Current FlexCAN Module Error and Status. */ + result = base->ESR1; + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFFFFFFFFFU)) || + (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | + kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)))); +#else + while ((0 != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) || + (0 != (result & (kFLEXCAN_TxWarningIntFlag | kFLEXCAN_RxWarningIntFlag | kFLEXCAN_BusOffIntFlag | + kFLEXCAN_ErrorIntFlag | kFLEXCAN_WakeUpIntFlag)))); +#endif +} + +#if defined(CAN0) +void CAN0_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[0]); + + s_flexcanIsr(CAN0, s_flexcanHandle[0]); +} +#endif + +#if defined(CAN1) +void CAN1_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[1]); + + s_flexcanIsr(CAN1, s_flexcanHandle[1]); +} +#endif + +#if defined(CAN2) +void CAN2_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[2]); + + s_flexcanIsr(CAN2, s_flexcanHandle[2]); +} +#endif + +#if defined(CAN3) +void CAN3_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[3]); + + s_flexcanIsr(CAN3, s_flexcanHandle[3]); +} +#endif + +#if defined(CAN4) +void CAN4_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[4]); + + s_flexcanIsr(CAN4, s_flexcanHandle[4]); +} +#endif + +#if defined(DMA_CAN0) +void DMA_FLEXCAN0_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN0)]); + + s_flexcanIsr(DMA_CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN0)]); +} +#endif + +#if defined(DMA_CAN1) +void DMA_FLEXCAN1_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN1)]); + + s_flexcanIsr(DMA_CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN1)]); +} +#endif + +#if defined(DMA_CAN2) +void DMA_FLEXCAN2_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN2)]); + + s_flexcanIsr(DMA_CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA_CAN2)]); +} +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h new file mode 100644 index 00000000000..118badf58fb --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h @@ -0,0 +1,1052 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FLEXCAN_H_ +#define _FSL_FLEXCAN_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcan_driver + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCAN driver version 2.2.0. */ +#define FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +/*! @brief FlexCAN Frame ID helper macro. */ +#define FLEXCAN_ID_STD(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */ +#define FLEXCAN_ID_EXT(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_EXT_SHIFT)) & \ + (CAN_ID_EXT_MASK | CAN_ID_STD_MASK)) /*!< Extend Frame ID helper macro. */ + +/*! @brief FlexCAN Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_STD_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */ + +/*! @brief FlexCAN Rx FIFO Mask helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (((uint32_t)(id) & 0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + (((uint32_t)(id) & 0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \ + (((uint32_t)(id) & 0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \ + (((uint32_t)(id) & 0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \ + (((uint32_t)(id) & 0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \ + (((uint32_t)(id) & 0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ + 15)) /*!< Extend Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) << 3) /*!< Extend Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 5) /*!< Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 13) /*!< Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> 21) /*!< Extend Rx FIFO Mask helper macro Type C lower part helper macro. */ + +/*! @brief FlexCAN Rx FIFO Filter helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ + */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ + */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) /*!< Extend Rx FIFO Filter helper macro Type C lower part helper macro. */ + +/*! @brief FlexCAN transfer status. */ +enum _flexcan_status +{ + kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */ + kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */ + kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS( + kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */ + kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */ + kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */ + kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */ + kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */ + kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */ + kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */ + kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */ + kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< FlexCAN Module Error and Status. */ + kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< UnHadled Interrupt asserted. */ +}; + +/*! @brief FlexCAN frame format. */ +typedef enum _flexcan_frame_format +{ + kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */ + kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */ +} flexcan_frame_format_t; + +/*! @brief FlexCAN frame type. */ +typedef enum _flexcan_frame_type +{ + kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ + kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ +} flexcan_frame_type_t; + +#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE +/*! @brief FlexCAN clock source. */ +typedef enum _flexcan_clock_source +{ + kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */ + kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */ +} flexcan_clock_source_t; +#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + +/*! @brief FlexCAN Rx Fifo Filter type. */ +typedef enum _flexcan_rx_fifo_filter_type +{ + kFLEXCAN_RxFifoFilterTypeA = 0x0U, /*!< One full ID (standard and extended) per ID Filter element. */ + kFLEXCAN_RxFifoFilterTypeB = + 0x1U, /*!< Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeC = + 0x2U, /*!< Four partial 8-bit Standard or extended ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeD = 0x3U, /*!< All frames rejected. */ +} flexcan_rx_fifo_filter_type_t; + +/*! + * @brief FlexCAN Rx FIFO priority. + * + * The matching process starts from the Rx MB(or Rx FIFO) with higher priority. + * If no MB(or Rx FIFO filter) is satisfied, the matching process goes on with + * the Rx FIFO(or Rx MB) with lower priority. + */ +typedef enum _flexcan_rx_fifo_priority +{ + kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first*/ + kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Rx FIFO first*/ +} flexcan_rx_fifo_priority_t; + +/*! + * @brief FlexCAN interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the FlexCAN Module interrupt configurations. + * Note: FlexCAN Message Buffers and Rx FIFO have their own interrupts. + */ +enum _flexcan_interrupt_enable +{ + kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt. */ + kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< Error interrupt. */ + kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt. */ + kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt. */ + kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Wake Up interrupt. */ +}; + +/*! + * @brief FlexCAN status flags. + * + * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. + * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to + * read FlEXCAN_ErrorFlag and distinguish which error is occur using + * @ref _flexcan_error_flags enumerations. + */ +enum _flexcan_flags +{ + kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */ + kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */ + kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */ + kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */ + kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */ + kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< CAN IDLE Status Flag. */ + kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< Fault Confinement State Flag. */ + kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */ + kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */ + kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */ + kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< Error Interrupt Flag. */ + kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Wake-Up Interrupt Flag. */ + kFLEXCAN_ErrorFlag = CAN_ESR1_BIT1ERR_MASK | /*!< All FlexCAN Error Status. */ + CAN_ESR1_BIT0ERR_MASK | + CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK, +}; + +/*! + * @brief FlexCAN error status flags. + * + * The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. + * This enumerations should be used with KFLEXCAN_ErrorFlag in @ref _flexcan_flags enumerations + * to ditermine which error is generated. + */ +enum _flexcan_error_flags +{ + kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */ + kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */ + kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */ +}; + +/*! + * @brief FlexCAN Rx FIFO status flags. + * + * The FlexCAN Rx FIFO Status enumerations are used to determine the status of the + * Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies + * more Message Buffer space), Rx FIFO status flags are mapped to the corresponding + * Message Buffer status flags. + */ +enum _flexcan_rx_fifo_flags +{ + kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */ + kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */ + kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */ +}; + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/*! @brief FlexCAN message frame structure. */ +typedef struct _flexcan_frame +{ + struct + { + uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */ + uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t : 1; /*!< Reserved. */ + uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */ + }; + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + uint32_t : 3; /*!< Reserved. */ + }; + union + { + struct + { + uint32_t dataWord0; /*!< CAN Frame payload word0. */ + uint32_t dataWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t dataByte3; /*!< CAN Frame payload byte3. */ + uint8_t dataByte2; /*!< CAN Frame payload byte2. */ + uint8_t dataByte1; /*!< CAN Frame payload byte1. */ + uint8_t dataByte0; /*!< CAN Frame payload byte0. */ + uint8_t dataByte7; /*!< CAN Frame payload byte7. */ + uint8_t dataByte6; /*!< CAN Frame payload byte6. */ + uint8_t dataByte5; /*!< CAN Frame payload byte5. */ + uint8_t dataByte4; /*!< CAN Frame payload byte4. */ + }; + }; +} flexcan_frame_t; + +/*! @brief FlexCAN module configuration structure. */ +typedef struct _flexcan_config +{ + uint32_t baudRate; /*!< FlexCAN baud rate in bps. */ +#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE + flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ +#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ + bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */ + bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */ + bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + bool enableDoze; /*!< Enable or Disable Doze Mode. */ +#endif +} flexcan_config_t; + +/*! @brief FlexCAN protocol timing characteristic configuration structure. */ +typedef struct _flexcan_timing_config +{ + uint8_t preDivider; /*!< Clock Pre-scaler Division Factor. */ + uint8_t rJumpwidth; /*!< Re-sync Jump Width. */ + uint8_t phaseSeg1; /*!< Phase Segment 1. */ + uint8_t phaseSeg2; /*!< Phase Segment 2. */ + uint8_t propSeg; /*!< Propagation Segment. */ +} flexcan_timing_config_t; + +/*! + * @brief FlexCAN Receive Message Buffer configuration structure + * + * This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. + * The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive + * Message Buffer. The function abort previous receiving process, clean the + * Message Buffer and activate the Rx Message Buffer using given Message Buffer + * setting. + */ +typedef struct _flexcan_rx_mb_config +{ + uint32_t id; /*!< CAN Message Buffer Frame Identifier, should be set using + FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + flexcan_frame_format_t format; /*!< CAN Frame Identifier format(Standard of Extend). */ + flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */ +} flexcan_rx_mb_config_t; + +/*! @brief FlexCAN Rx FIFO configuration structure. */ +typedef struct _flexcan_rx_fifo_config +{ + uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Rx FIFO identifier filter table. */ + uint8_t idFilterNum; /*!< The quantity of filter elements. */ + flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Rx FIFO Filter type. */ + flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Rx FIFO receive priority. */ +} flexcan_rx_fifo_config_t; + +/*! @brief FlexCAN Message Buffer transfer. */ +typedef struct _flexcan_mb_transfer +{ + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ + uint8_t mbIdx; /*!< The index of Message buffer used to transfer Message. */ +} flexcan_mb_transfer_t; + +/*! @brief FlexCAN Rx FIFO transfer. */ +typedef struct _flexcan_fifo_transfer +{ + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */ +} flexcan_fifo_transfer_t; + +/*! @brief FlexCAN handle structure definition. */ +typedef struct _flexcan_handle flexcan_handle_t; + +/*! @brief FlexCAN transfer callback function. + * + * The FlexCAN transfer callback returns a value from the underlying layer. + * If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of + * FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of + * Message Buffer that generate transfer event. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be + * Ignored. + */ +typedef void (*flexcan_transfer_callback_t)( + CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData); + +/*! @brief FlexCAN handle structure. */ +struct _flexcan_handle +{ + flexcan_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< FlexCAN callback function parameter.*/ + flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT]; + /*!< The buffer for received data from Message Buffers. */ + flexcan_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */ + volatile uint8_t mbState[CAN_WORD1_COUNT]; /*!< Message Buffer transfer state. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ +}; + +/****************************************************************************** + * API + *****************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters. + * @code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig.baudRate = 125000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL); + * @endcode + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the user-defined configuration structure. + * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz); + +/*! + * @brief De-initializes a FlexCAN instance. + * + * This function disables the FlexCAN module clock and sets all register values + * to the reset value. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_Deinit(CAN_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the FlexCAN configuration structure to default values. The default + * values are as follows. + * flexcanConfig->clkSrc = KFLEXCAN_ClkSrcOsc; + * flexcanConfig->baudRate = 125000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->enableDoze = false; + * + * @param config Pointer to the FlexCAN configuration structure. + */ +void FLEXCAN_GetDefaultConfig(flexcan_config_t *config); + +/* @} */ + +/*! + * @name Configuration. + * @{ + */ + +/*! + * @brief Sets the FlexCAN protocol timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the FLEXCAN_Init() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + * + * Note that calling FLEXCAN_SetTimingConfig() overrides the baud rate set + * in FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the timing configuration structure. + */ +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config); + +/*! + * @brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for the FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Message Buffer Global Mask value. + */ +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Fifo Global Mask value. + */ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for the FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). + * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with the same index. Note that only the first 32 + * individual masks can be used as the Rx FIFO filter mask. + * + * @param base FlexCAN peripheral base address. + * @param maskIdx The Index of individual Mask. + * @param mask Rx Individual Mask value. + */ +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); + +/*! + * @brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); + +/*! + * @brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param config Pointer to the FlexCAN Message Buffer configuration structure. + * @param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable); + +/*! + * @brief Configures the FlexCAN Rx FIFO. + * + * This function configures the Rx FIFO with given Rx FIFO configuration. + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the FlexCAN Rx FIFO configuration structure. + * @param enable Enable/disable Rx FIFO. + * - true: Enable Rx FIFO. + * - false: Disable Rx FIFO. + */ +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexCAN module interrupt flags. + * + * This function gets all FlexCAN status flags. The flags are returned as the logical + * OR value of the enumerators @ref _flexcan_flags. To check the specific status, + * compare the return value with enumerators in @ref _flexcan_flags. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags. + */ +static inline uint32_t FLEXCAN_GetStatusFlags(CAN_Type *base) +{ + return base->ESR1; +} + +/*! + * @brief Clears status flags with the provided mask. + * + * This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag + * can't be cleared by this function. + * + * @param base FlexCAN peripheral base address. + * @param mask The status flags to be cleared, it is logical OR value of @ref _flexcan_flags. + */ +static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) +{ + /* Write 1 to clear status flag. */ + base->ESR1 = mask; +} + +/*! + * @brief Gets the FlexCAN Bus Error Counter value. + * + * This function gets the FlexCAN Bus Error Counter value for both Tx and + * Rx direction. These values may be needed in the upper layer error handling. + * + * @param base FlexCAN peripheral base address. + * @param txErrBuf Buffer to store Tx Error Counter value. + * @param rxErrBuf Buffer to store Rx Error Counter value. + */ +static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) +{ + if (txErrBuf) + { + *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT); + } + + if (rxErrBuf) + { + *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT); + } +} + +/*! + * @brief Gets the FlexCAN Message Buffer interrupt flags. + * + * This function gets the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + * @return The status of given Message Buffers. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + return ((((uint64_t)base->IFLAG1) & mask) | ((((uint64_t)base->IFLAG2) << 32) & mask)); +#else + return (base->IFLAG1 & mask); +#endif +} + +/*! + * @brief Clears the FlexCAN Message Buffer interrupt flags. + * + * This function clears the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU); + base->IFLAG2 = (uint32_t)(mask >> 32); +#else + base->IFLAG1 = mask; +#endif +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables FlexCAN interrupts according to the provided mask. + * + * This function enables the FlexCAN interrupts according to the provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _flexcan_interrupt_enable. + */ +static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask) +{ + /* Solve Wake Up Interrupt. */ + if (mask & kFLEXCAN_WakeUpInterruptEnable) + { + base->MCR |= CAN_MCR_WAKMSK_MASK; + } + + /* Solve others. */ + base->CTRL1 |= (mask & (~((uint32_t)kFLEXCAN_WakeUpInterruptEnable))); +} + +/*! + * @brief Disables FlexCAN interrupts according to the provided mask. + * + * This function disables the FlexCAN interrupts according to the provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _flexcan_interrupt_enable. + */ +static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) +{ + /* Solve Wake Up Interrupt. */ + if (mask & kFLEXCAN_WakeUpInterruptEnable) + { + base->MCR &= ~CAN_MCR_WAKMSK_MASK; + } + + /* Solve others. */ + base->CTRL1 &= ~(mask & (~((uint32_t)kFLEXCAN_WakeUpInterruptEnable))); +} + +/*! + * @brief Enables FlexCAN Message Buffer interrupts. + * + * This function enables the interrupts of given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU); + base->IMASK2 |= (uint32_t)(mask >> 32); +#else + base->IMASK1 |= mask; +#endif +} + +/*! + * @brief Disables FlexCAN Message Buffer interrupts. + * + * This function disables the interrupts of given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); + base->IMASK2 &= ~((uint32_t)(mask >> 32)); +#else + base->IMASK1 &= ~mask; +#endif +} + +/* @} */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param enable true to enable, false to disable. + */ +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable); + +/*! + * @brief Gets the Rx FIFO Head address. + * + * This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN Rx FIFO Head address. + */ +static inline uint32_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base) +{ + return (uint32_t) & (base->MB[0].CS); +} + +/* @} */ +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN module operation. + * + * This function enables or disables the FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param enable true to enable, false to disable. + */ +static inline void FLEXCAN_Enable(CAN_Type *base, bool enable) +{ + if (enable) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN exit from low-power mode. */ + while (base->MCR & CAN_MCR_LPMACK_MASK) + { + } + } + else + { + base->MCR |= CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN enter low-power mode. */ + while (!(base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + } +} + +/*! + * @brief Writes a FlexCAN Message to the Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param txFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame); + +/*! + * @brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); + +/*! + * @brief Reads a FlexCAN Message from Rx FIFO. + * + * This function reads a CAN message from the FlexCAN build-in Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param txFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); + +/*! + * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); + +/*! + * @brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle, which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success Start Tx Message Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Message Buffer failed. + * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); + +/*! + * @brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); + +/*! + * @brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN Rx FIFO transfer structure. See the @ref flexcan_fifo_transfer_t. + * @retval kStatus_Success - Start Rx FIFO receiving process successfully. + * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle); + +/*! + * @brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FLEXCAN_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_ftm.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_ftm.c new file mode 100644 index 00000000000..9cca44b0e41 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_ftm.c @@ -0,0 +1,908 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_ftm.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base FTM peripheral base address + * + * @return The FTM instance + */ +static uint32_t FTM_GetInstance(FTM_Type *base); + +/*! + * @brief Sets the FTM register PWM synchronization method + * + * This function will set the necessary bits for the PWM synchronization mode that + * user wishes to use. + * + * @param base FTM peripheral base address + * @param syncMethod Syncronization methods to use to update buffered registers. This is a logical + * OR of members of the enumeration ::ftm_pwm_sync_method_t + */ +static void FTM_SetPwmSync(FTM_Type *base, uint32_t syncMethod); + +/*! + * @brief Sets the reload points used as loading points for register update + * + * This function will set the necessary bits based on what the user wishes to use as loading + * points for FTM register update. When using this it is not required to use PWM synchnronization. + * + * @param base FTM peripheral base address + * @param reloadPoints FTM reload points. This is a logical OR of members of the + * enumeration ::ftm_reload_point_t + */ +static void FTM_SetReloadPoints(FTM_Type *base, uint32_t reloadPoints); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to FTM bases for each instance. */ +static FTM_Type *const s_ftmBases[] = FTM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to FTM clocks for each instance. */ +static const clock_ip_name_t s_ftmClocks[] = FTM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t FTM_GetInstance(FTM_Type *base) +{ + uint32_t instance; + uint32_t ftmArrayCount = (sizeof(s_ftmBases) / sizeof(s_ftmBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ftmArrayCount; instance++) + { + if (s_ftmBases[instance] == base) + { + break; + } + } + + assert(instance < ftmArrayCount); + + return instance; +} + +static void FTM_SetPwmSync(FTM_Type *base, uint32_t syncMethod) +{ + uint8_t chnlNumber = 0; + uint32_t reg = 0, syncReg = 0; + + syncReg = base->SYNC; + /* Enable PWM synchronization of output mask register */ + syncReg |= FTM_SYNC_SYNCHOM_MASK; + + reg = base->COMBINE; + for (chnlNumber = 0; chnlNumber < (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2); chnlNumber++) + { + /* Enable PWM synchronization of registers C(n)V and C(n+1)V */ + reg |= (1U << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber))); + } + base->COMBINE = reg; + + reg = base->SYNCONF; + + /* Use enhanced PWM synchronization method. Use PWM sync to update register values */ + reg |= (FTM_SYNCONF_SYNCMODE_MASK | FTM_SYNCONF_CNTINC_MASK | FTM_SYNCONF_INVC_MASK | FTM_SYNCONF_SWOC_MASK); + + if (syncMethod & FTM_SYNC_SWSYNC_MASK) + { + /* Enable needed bits for software trigger to update registers with its buffer value */ + reg |= (FTM_SYNCONF_SWRSTCNT_MASK | FTM_SYNCONF_SWWRBUF_MASK | FTM_SYNCONF_SWINVC_MASK | + FTM_SYNCONF_SWSOC_MASK | FTM_SYNCONF_SWOM_MASK); + } + + if (syncMethod & (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK)) + { + /* Enable needed bits for hardware trigger to update registers with its buffer value */ + reg |= (FTM_SYNCONF_HWRSTCNT_MASK | FTM_SYNCONF_HWWRBUF_MASK | FTM_SYNCONF_HWINVC_MASK | + FTM_SYNCONF_HWSOC_MASK | FTM_SYNCONF_HWOM_MASK); + + /* Enable the appropriate hardware trigger that is used for PWM sync */ + if (syncMethod & FTM_SYNC_TRIG0_MASK) + { + syncReg |= FTM_SYNC_TRIG0_MASK; + } + if (syncMethod & FTM_SYNC_TRIG1_MASK) + { + syncReg |= FTM_SYNC_TRIG1_MASK; + } + if (syncMethod & FTM_SYNC_TRIG2_MASK) + { + syncReg |= FTM_SYNC_TRIG2_MASK; + } + } + + /* Write back values to the SYNC register */ + base->SYNC = syncReg; + + /* Write the PWM synch values to the SYNCONF register */ + base->SYNCONF = reg; +} + +static void FTM_SetReloadPoints(FTM_Type *base, uint32_t reloadPoints) +{ + uint32_t chnlNumber = 0; + uint32_t reg = 0; + + /* Need CNTINC bit to be 1 for CNTIN register to update with its buffer value on reload */ + base->SYNCONF |= FTM_SYNCONF_CNTINC_MASK; + + reg = base->COMBINE; + for (chnlNumber = 0; chnlNumber < (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2); chnlNumber++) + { + /* Need SYNCEN bit to be 1 for CnV reg to update with its buffer value on reload */ + reg |= (1U << (FTM_COMBINE_SYNCEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlNumber))); + } + base->COMBINE = reg; + + /* Set the reload points */ + reg = base->PWMLOAD; + + /* Enable the selected channel match reload points */ + reg &= ~((1U << FSL_FEATURE_FTM_CHANNEL_COUNTn(base)) - 1); + reg |= (reloadPoints & ((1U << FSL_FEATURE_FTM_CHANNEL_COUNTn(base)) - 1)); + +#if defined(FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD) && (FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD) + /* Enable half cycle match as a reload point */ + if (reloadPoints & kFTM_HalfCycMatch) + { + reg |= FTM_PWMLOAD_HCSEL_MASK; + } + else + { + reg &= ~FTM_PWMLOAD_HCSEL_MASK; + } +#endif /* FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD */ + + base->PWMLOAD = reg; + + /* These reload points are used when counter is in up-down counting mode */ + reg = base->SYNC; + if (reloadPoints & kFTM_CntMax) + { + /* Reload when counter turns from up to down */ + reg |= FTM_SYNC_CNTMAX_MASK; + } + else + { + reg &= ~FTM_SYNC_CNTMAX_MASK; + } + + if (reloadPoints & kFTM_CntMin) + { + /* Reload when counter turns from down to up */ + reg |= FTM_SYNC_CNTMIN_MASK; + } + else + { + reg &= ~FTM_SYNC_CNTMIN_MASK; + } + base->SYNC = reg; +} + +status_t FTM_Init(FTM_Type *base, const ftm_config_t *config) +{ + assert(config); + + uint32_t reg; + + if (!(config->pwmSyncMode & + (FTM_SYNC_TRIG0_MASK | FTM_SYNC_TRIG1_MASK | FTM_SYNC_TRIG2_MASK | FTM_SYNC_SWSYNC_MASK))) + { + /* Invalid PWM sync mode */ + return kStatus_Fail; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the FTM clock*/ + CLOCK_EnableClock(s_ftmClocks[FTM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure the fault mode, enable FTM mode and disable write protection */ + base->MODE = FTM_MODE_FAULTM(config->faultMode) | FTM_MODE_FTMEN_MASK | FTM_MODE_WPDIS_MASK; + + /* Configure the update mechanism for buffered registers */ + FTM_SetPwmSync(base, config->pwmSyncMode); + + /* Setup intermediate register reload points */ + FTM_SetReloadPoints(base, config->reloadPoints); + + /* Set the clock prescale factor */ + base->SC = FTM_SC_PS(config->prescale); + + /* Setup the counter operation */ + base->CONF = (FTM_CONF_BDMMODE(config->bdmMode) | FTM_CONF_GTBEEN(config->useGlobalTimeBase)); + + /* Initial state of channel output */ + base->OUTINIT = config->chnlInitState; + + /* Channel polarity */ + base->POL = config->chnlPolarity; + + /* Set the external trigger sources */ + base->EXTTRIG = config->extTriggers; +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER) && (FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER) + if (config->extTriggers & kFTM_ReloadInitTrigger) + { + base->CONF |= FTM_CONF_ITRIGR_MASK; + } + else + { + base->CONF &= ~FTM_CONF_ITRIGR_MASK; + } +#endif /* FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER */ + + /* FTM deadtime insertion control */ + base->DEADTIME = (0u | +#if defined(FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE) && (FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE) + /* Has extended deadtime value register) */ + FTM_DEADTIME_DTVALEX(config->deadTimeValue >> 6) | +#endif /* FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE */ + FTM_DEADTIME_DTPS(config->deadTimePrescale) | + FTM_DEADTIME_DTVAL(config->deadTimeValue)); + + /* FTM fault filter value */ + reg = base->FLTCTRL; + reg &= ~FTM_FLTCTRL_FFVAL_MASK; + reg |= FTM_FLTCTRL_FFVAL(config->faultFilterValue); + base->FLTCTRL = reg; + + return kStatus_Success; +} + +void FTM_Deinit(FTM_Type *base) +{ + /* Set clock source to none to disable counter */ + base->SC &= ~(FTM_SC_CLKS_MASK); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the FTM clock */ + CLOCK_DisableClock(s_ftmClocks[FTM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void FTM_GetDefaultConfig(ftm_config_t *config) +{ + assert(config); + + /* Divide FTM clock by 1 */ + config->prescale = kFTM_Prescale_Divide_1; + /* FTM behavior in BDM mode */ + config->bdmMode = kFTM_BdmMode_0; + /* Software trigger will be used to update registers */ + config->pwmSyncMode = kFTM_SoftwareTrigger; + /* No intermediate register load */ + config->reloadPoints = 0; + /* Fault control disabled for all channels */ + config->faultMode = kFTM_Fault_Disable; + /* Disable the fault filter */ + config->faultFilterValue = 0; + /* Divide the system clock by 1 */ + config->deadTimePrescale = kFTM_Deadtime_Prescale_1; + /* No counts are inserted */ + config->deadTimeValue = 0; + /* No external trigger */ + config->extTriggers = 0; + /* Initialization value is 0 for all channels */ + config->chnlInitState = 0; + /* Active high polarity for all channels */ + config->chnlPolarity = 0; + /* Use internal FTM counter as timebase */ + config->useGlobalTimeBase = false; +} + +status_t FTM_SetupPwm(FTM_Type *base, + const ftm_chnl_pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + ftm_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz) +{ + assert(chnlParams); + assert(srcClock_Hz); + assert(pwmFreq_Hz); + assert(numOfChnls); + + uint32_t mod, reg; + uint32_t ftmClock = (srcClock_Hz / (1U << (base->SC & FTM_SC_PS_MASK))); + uint16_t cnv, cnvFirstEdge; + uint8_t i; + + switch (mode) + { + case kFTM_EdgeAlignedPwm: + case kFTM_CombinedPwm: + base->SC &= ~FTM_SC_CPWMS_MASK; + mod = (ftmClock / pwmFreq_Hz) - 1; + break; + case kFTM_CenterAlignedPwm: + base->SC |= FTM_SC_CPWMS_MASK; + mod = ftmClock / (pwmFreq_Hz * 2); + break; + default: + return kStatus_Fail; + } + + /* Return an error in case we overflow the registers, probably would require changing + * clock source to get the desired frequency */ + if (mod > 65535U) + { + return kStatus_Fail; + } + /* Set the PWM period */ + base->MOD = mod; + + /* Setup each FTM channel */ + for (i = 0; i < numOfChnls; i++) + { + /* Return error if requested dutycycle is greater than the max allowed */ + if (chnlParams->dutyCyclePercent > 100) + { + return kStatus_Fail; + } + + if ((mode == kFTM_EdgeAlignedPwm) || (mode == kFTM_CenterAlignedPwm)) + { + /* Clear the current mode and edge level bits */ + reg = base->CONTROLS[chnlParams->chnlNumber].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + /* Setup the active level */ + reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT); + + /* Edge-aligned mode needs MSB to be 1, don't care for Center-aligned mode */ + reg |= FTM_CnSC_MSB(1U); + + /* Update the mode and edge level */ + base->CONTROLS[chnlParams->chnlNumber].CnSC = reg; + + if (chnlParams->dutyCyclePercent == 0) + { + /* Signal stays low */ + cnv = 0; + } + else + { + cnv = (mod * chnlParams->dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + } + + base->CONTROLS[chnlParams->chnlNumber].CnV = cnv; +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to output mode */ + FTM_SetPwmOutputEnable(base, chnlParams->chnlNumber, true); +#endif + } + else + { + /* This check is added for combined mode as the channel number should be the pair number */ + if (chnlParams->chnlNumber >= (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2)) + { + return kStatus_Fail; + } + + /* Return error if requested value is greater than the max allowed */ + if (chnlParams->firstEdgeDelayPercent > 100) + { + return kStatus_Fail; + } + + /* Configure delay of the first edge */ + if (chnlParams->firstEdgeDelayPercent == 0) + { + /* No delay for the first edge */ + cnvFirstEdge = 0; + } + else + { + cnvFirstEdge = (mod * chnlParams->firstEdgeDelayPercent) / 100; + } + + /* Configure dutycycle */ + if (chnlParams->dutyCyclePercent == 0) + { + /* Signal stays low */ + cnv = 0; + cnvFirstEdge = 0; + } + else + { + cnv = (mod * chnlParams->dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + } + + /* Clear the current mode and edge level bits for channel n */ + reg = base->CONTROLS[chnlParams->chnlNumber * 2].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + /* Setup the active level for channel n */ + reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT); + + /* Update the mode and edge level for channel n */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnSC = reg; + + /* Clear the current mode and edge level bits for channel n + 1 */ + reg = base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + /* Setup the active level for channel n + 1 */ + reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT); + + /* Update the mode and edge level for channel n + 1*/ + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC = reg; + + /* Set the combine bit for the channel pair */ + base->COMBINE |= + (1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlParams->chnlNumber))); + + /* Set the channel pair values */ + base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge; + base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to output mode */ + FTM_SetPwmOutputEnable(base, (ftm_chnl_t)((uint8_t)chnlParams->chnlNumber * 2), true); + FTM_SetPwmOutputEnable(base, (ftm_chnl_t)((uint8_t)chnlParams->chnlNumber * 2 + 1), true); +#endif + } + chnlParams++; + } + + return kStatus_Success; +} + +void FTM_UpdatePwmDutycycle(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_pwm_mode_t currentPwmMode, + uint8_t dutyCyclePercent) +{ + uint16_t cnv, cnvFirstEdge = 0, mod; + + mod = base->MOD; + if ((currentPwmMode == kFTM_EdgeAlignedPwm) || (currentPwmMode == kFTM_CenterAlignedPwm)) + { + cnv = (mod * dutyCyclePercent) / 100; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + base->CONTROLS[chnlNumber].CnV = cnv; + } + else + { + /* This check is added for combined mode as the channel number should be the pair number */ + if (chnlNumber >= (FSL_FEATURE_FTM_CHANNEL_COUNTn(base) / 2)) + { + return; + } + + cnv = (mod * dutyCyclePercent) / 100; + cnvFirstEdge = base->CONTROLS[chnlNumber * 2].CnV; + /* For 100% duty cycle */ + if (cnv >= mod) + { + cnv = mod + 1; + } + base->CONTROLS[(chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv; + } +} + +void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level) +{ + uint32_t reg = base->CONTROLS[chnlNumber].CnSC; + + /* Clear the field and write the new level value */ + reg &= ~(FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= ((uint32_t)level << FTM_CnSC_ELSA_SHIFT) & (FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + + base->CONTROLS[chnlNumber].CnSC = reg; +} + +void FTM_SetupInputCapture(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_input_capture_edge_t captureMode, + uint32_t filterValue) +{ + uint32_t reg; + + /* Clear the combine bit for the channel pair */ + base->COMBINE &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1)))); + /* Clear the dual edge capture mode because it's it's higher priority */ + base->COMBINE &= ~(1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1)))); + /* Clear the quadrature decoder mode beacause it's higher priority */ + base->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK; + + reg = base->CONTROLS[chnlNumber].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= captureMode; + + /* Set the requested input capture mode */ + base->CONTROLS[chnlNumber].CnSC = reg; + /* Input filter available only for channels 0, 1, 2, 3 */ + if (chnlNumber < kFTM_Chnl_4) + { + reg = base->FILTER; + reg &= ~(FTM_FILTER_CH0FVAL_MASK << (FTM_FILTER_CH1FVAL_SHIFT * chnlNumber)); + reg |= (filterValue << (FTM_FILTER_CH1FVAL_SHIFT * chnlNumber)); + base->FILTER = reg; + } +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to input mode */ + FTM_SetPwmOutputEnable(base, chnlNumber, false); +#endif +} + +void FTM_SetupOutputCompare(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_output_compare_mode_t compareMode, + uint32_t compareValue) +{ + uint32_t reg; + + /* Clear the combine bit for the channel pair */ + base->COMBINE &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1)))); + /* Clear the dual edge capture mode because it's it's higher priority */ + base->COMBINE &= ~(1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1)))); + /* Clear the quadrature decoder mode beacause it's higher priority */ + base->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK; + + reg = base->CONTROLS[chnlNumber].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= compareMode; + /* Setup the channel output behaviour when a match occurs with the compare value */ + base->CONTROLS[chnlNumber].CnSC = reg; + + /* Set output on match to the requested level */ + base->CONTROLS[chnlNumber].CnV = compareValue; + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to output mode */ + FTM_SetPwmOutputEnable(base, chnlNumber, true); +#endif +} + +void FTM_SetupDualEdgeCapture(FTM_Type *base, + ftm_chnl_t chnlPairNumber, + const ftm_dual_edge_capture_param_t *edgeParam, + uint32_t filterValue) +{ + assert(edgeParam); + + uint32_t reg; + + reg = base->COMBINE; + /* Clear the combine bit for the channel pair */ + reg &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + /* Enable the DECAPEN bit */ + reg |= (1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + reg |= (1U << (FTM_COMBINE_DECAP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + base->COMBINE = reg; + + /* Setup the edge detection from channel n and n + 1 */ + reg = base->CONTROLS[chnlPairNumber * 2].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= ((uint32_t)edgeParam->mode | (uint32_t)edgeParam->currChanEdgeMode); + base->CONTROLS[chnlPairNumber * 2].CnSC = reg; + + reg = base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC; + reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK); + reg |= ((uint32_t)edgeParam->mode | (uint32_t)edgeParam->nextChanEdgeMode); + base->CONTROLS[(chnlPairNumber * 2) + 1].CnSC = reg; + + /* Input filter available only for channels 0, 1, 2, 3 */ + if (chnlPairNumber < kFTM_Chnl_4) + { + reg = base->FILTER; + reg &= ~(FTM_FILTER_CH0FVAL_MASK << (FTM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); + reg |= (filterValue << (FTM_FILTER_CH1FVAL_SHIFT * chnlPairNumber)); + base->FILTER = reg; + } + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) + /* Set to input mode */ + FTM_SetPwmOutputEnable(base, chnlPairNumber, false); +#endif +} + +void FTM_SetupQuadDecode(FTM_Type *base, + const ftm_phase_params_t *phaseAParams, + const ftm_phase_params_t *phaseBParams, + ftm_quad_decode_mode_t quadMode) +{ + assert(phaseAParams); + assert(phaseBParams); + + uint32_t reg; + + /* Set Phase A filter value if phase filter is enabled */ + if (phaseAParams->enablePhaseFilter) + { + reg = base->FILTER; + reg &= ~(FTM_FILTER_CH0FVAL_MASK); + reg |= FTM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal); + base->FILTER = reg; + } + + /* Set Phase B filter value if phase filter is enabled */ + if (phaseBParams->enablePhaseFilter) + { + reg = base->FILTER; + reg &= ~(FTM_FILTER_CH1FVAL_MASK); + reg |= FTM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal); + base->FILTER = reg; + } + + /* Set Quadrature decode properties */ + reg = base->QDCTRL; + reg &= ~(FTM_QDCTRL_QUADMODE_MASK | FTM_QDCTRL_PHAFLTREN_MASK | FTM_QDCTRL_PHBFLTREN_MASK | FTM_QDCTRL_PHAPOL_MASK | + FTM_QDCTRL_PHBPOL_MASK); + reg |= (FTM_QDCTRL_QUADMODE(quadMode) | FTM_QDCTRL_PHAFLTREN(phaseAParams->enablePhaseFilter) | + FTM_QDCTRL_PHBFLTREN(phaseBParams->enablePhaseFilter) | FTM_QDCTRL_PHAPOL(phaseAParams->phasePolarity) | + FTM_QDCTRL_PHBPOL(phaseBParams->phasePolarity)); + base->QDCTRL = reg; + /* Enable Quad decode */ + base->QDCTRL |= FTM_QDCTRL_QUADEN_MASK; +} + +void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams) +{ + assert(faultParams); + + uint32_t reg; + + reg = base->FLTCTRL; + if (faultParams->enableFaultInput) + { + /* Enable the fault input */ + reg |= (FTM_FLTCTRL_FAULT0EN_MASK << faultNumber); + } + else + { + /* Disable the fault input */ + reg &= ~(FTM_FLTCTRL_FAULT0EN_MASK << faultNumber); + } + + if (faultParams->useFaultFilter) + { + /* Enable the fault filter */ + reg |= (FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber)); + } + else + { + /* Disable the fault filter */ + reg &= ~(FTM_FLTCTRL_FFLTR0EN_MASK << (FTM_FLTCTRL_FFLTR0EN_SHIFT + faultNumber)); + } + base->FLTCTRL = reg; + + if (faultParams->faultLevel) + { + /* Active low polarity for the fault input pin */ + base->FLTPOL |= (1U << faultNumber); + } + else + { + /* Active high polarity for the fault input pin */ + base->FLTPOL &= ~(1U << faultNumber); + } +} + +void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask) +{ + uint32_t chnlInts = (mask & 0xFFU); + uint8_t chnlNumber = 0; + + /* Enable the timer overflow interrupt */ + if (mask & kFTM_TimeOverflowInterruptEnable) + { + base->SC |= FTM_SC_TOIE_MASK; + } + + /* Enable the fault interrupt */ + if (mask & kFTM_FaultInterruptEnable) + { + base->MODE |= FTM_MODE_FAULTIE_MASK; + } + +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Enable the reload interrupt available only on certain SoC's */ + if (mask & kFTM_ReloadInterruptEnable) + { + base->SC |= FTM_SC_RIE_MASK; + } +#endif + + /* Enable the channel interrupts */ + while (chnlInts) + { + if (chnlInts & 0x1) + { + base->CONTROLS[chnlNumber].CnSC |= FTM_CnSC_CHIE_MASK; + } + chnlNumber++; + chnlInts = chnlInts >> 1U; + } +} + +void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask) +{ + uint32_t chnlInts = (mask & 0xFF); + uint8_t chnlNumber = 0; + + /* Disable the timer overflow interrupt */ + if (mask & kFTM_TimeOverflowInterruptEnable) + { + base->SC &= ~FTM_SC_TOIE_MASK; + } + /* Disable the fault interrupt */ + if (mask & kFTM_FaultInterruptEnable) + { + base->MODE &= ~FTM_MODE_FAULTIE_MASK; + } + +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Disable the reload interrupt available only on certain SoC's */ + if (mask & kFTM_ReloadInterruptEnable) + { + base->SC &= ~FTM_SC_RIE_MASK; + } +#endif + + /* Disable the channel interrupts */ + while (chnlInts) + { + if (chnlInts & 0x1) + { + base->CONTROLS[chnlNumber].CnSC &= ~FTM_CnSC_CHIE_MASK; + } + chnlNumber++; + chnlInts = chnlInts >> 1U; + } +} + +uint32_t FTM_GetEnabledInterrupts(FTM_Type *base) +{ + uint32_t enabledInterrupts = 0; + int8_t chnlCount = FSL_FEATURE_FTM_CHANNEL_COUNTn(base); + + /* The CHANNEL_COUNT macro returns -1 if it cannot match the FTM instance */ + assert(chnlCount != -1); + + /* Check if timer overflow interrupt is enabled */ + if (base->SC & FTM_SC_TOIE_MASK) + { + enabledInterrupts |= kFTM_TimeOverflowInterruptEnable; + } + /* Check if fault interrupt is enabled */ + if (base->MODE & FTM_MODE_FAULTIE_MASK) + { + enabledInterrupts |= kFTM_FaultInterruptEnable; + } + +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Check if the reload interrupt is enabled */ + if (base->SC & FTM_SC_RIE_MASK) + { + enabledInterrupts |= kFTM_ReloadInterruptEnable; + } +#endif + + /* Check if the channel interrupts are enabled */ + while (chnlCount > 0) + { + chnlCount--; + if (base->CONTROLS[chnlCount].CnSC & FTM_CnSC_CHIE_MASK) + { + enabledInterrupts |= (1U << chnlCount); + } + } + + return enabledInterrupts; +} + +uint32_t FTM_GetStatusFlags(FTM_Type *base) +{ + uint32_t statusFlags = 0; + + /* Check the timer flag */ + if (base->SC & FTM_SC_TOF_MASK) + { + statusFlags |= kFTM_TimeOverflowFlag; + } + /* Check fault flag */ + if (base->FMS & FTM_FMS_FAULTF_MASK) + { + statusFlags |= kFTM_FaultFlag; + } + /* Check channel trigger flag */ + if (base->EXTTRIG & FTM_EXTTRIG_TRIGF_MASK) + { + statusFlags |= kFTM_ChnlTriggerFlag; + } +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Check reload flag */ + if (base->SC & FTM_SC_RF_MASK) + { + statusFlags |= kFTM_ReloadFlag; + } +#endif + + /* Lower 8 bits contain the channel status flags */ + statusFlags |= (base->STATUS & 0xFFU); + + return statusFlags; +} + +void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask) +{ + /* Clear the timer overflow flag by writing a 0 to the bit while it is set */ + if (mask & kFTM_TimeOverflowFlag) + { + base->SC &= ~FTM_SC_TOF_MASK; + } + /* Clear fault flag by writing a 0 to the bit while it is set */ + if (mask & kFTM_FaultFlag) + { + base->FMS &= ~FTM_FMS_FAULTF_MASK; + } + /* Clear channel trigger flag */ + if (mask & kFTM_ChnlTriggerFlag) + { + base->EXTTRIG &= ~FTM_EXTTRIG_TRIGF_MASK; + } + +#if defined(FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) && (FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT) + /* Check reload flag by writing a 0 to the bit while it is set */ + if (mask & kFTM_ReloadFlag) + { + base->SC &= ~FTM_SC_RF_MASK; + } +#endif + /* Clear the channel status flags by writing a 0 to the bit */ + base->STATUS &= ~(mask & 0xFFU); +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_ftm.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_ftm.h new file mode 100644 index 00000000000..8db81a633ac --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_ftm.h @@ -0,0 +1,973 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_FTM_H_ +#define _FSL_FTM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ftm + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_FTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ + /*@}*/ + +/*! + * @brief List of FTM channels + * @note Actual number of available channels is SoC dependent + */ +typedef enum _ftm_chnl +{ + kFTM_Chnl_0 = 0U, /*!< FTM channel number 0*/ + kFTM_Chnl_1, /*!< FTM channel number 1 */ + kFTM_Chnl_2, /*!< FTM channel number 2 */ + kFTM_Chnl_3, /*!< FTM channel number 3 */ + kFTM_Chnl_4, /*!< FTM channel number 4 */ + kFTM_Chnl_5, /*!< FTM channel number 5 */ + kFTM_Chnl_6, /*!< FTM channel number 6 */ + kFTM_Chnl_7 /*!< FTM channel number 7 */ +} ftm_chnl_t; + +/*! @brief List of FTM faults */ +typedef enum _ftm_fault_input +{ + kFTM_Fault_0 = 0U, /*!< FTM fault 0 input pin */ + kFTM_Fault_1, /*!< FTM fault 1 input pin */ + kFTM_Fault_2, /*!< FTM fault 2 input pin */ + kFTM_Fault_3 /*!< FTM fault 3 input pin */ +} ftm_fault_input_t; + +/*! @brief FTM PWM operation modes */ +typedef enum _ftm_pwm_mode +{ + kFTM_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */ + kFTM_CenterAlignedPwm, /*!< Center-aligned PWM */ + kFTM_CombinedPwm /*!< Combined PWM */ +} ftm_pwm_mode_t; + +/*! @brief FTM PWM output pulse mode: high-true, low-true or no output */ +typedef enum _ftm_pwm_level_select +{ + kFTM_NoPwmSignal = 0U, /*!< No PWM output on pin */ + kFTM_LowTrue, /*!< Low true pulses */ + kFTM_HighTrue /*!< High true pulses */ +} ftm_pwm_level_select_t; + +/*! @brief Options to configure a FTM channel's PWM signal */ +typedef struct _ftm_chnl_pwm_signal_param +{ + ftm_chnl_t chnlNumber; /*!< The channel/channel pair number. + In combined mode, this represents the channel pair number. */ + ftm_pwm_level_select_t level; /*!< PWM output active level select. */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0 = inactive signal(0% duty cycle)... + 100 = always active signal (100% duty cycle).*/ + uint8_t firstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate an asymmetrical PWM. + Specifies the delay to the first edge in a PWM period. + If unsure leave as 0; Should be specified as a + percentage of the PWM period */ +} ftm_chnl_pwm_signal_param_t; + +/*! @brief FlexTimer output compare mode */ +typedef enum _ftm_output_compare_mode +{ + kFTM_NoOutputSignal = (1U << FTM_CnSC_MSA_SHIFT), /*!< No channel output when counter reaches CnV */ + kFTM_ToggleOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (1U << FTM_CnSC_ELSA_SHIFT)), /*!< Toggle output */ + kFTM_ClearOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (2U << FTM_CnSC_ELSA_SHIFT)), /*!< Clear output */ + kFTM_SetOnMatch = ((1U << FTM_CnSC_MSA_SHIFT) | (3U << FTM_CnSC_ELSA_SHIFT)) /*!< Set output */ +} ftm_output_compare_mode_t; + +/*! @brief FlexTimer input capture edge */ +typedef enum _ftm_input_capture_edge +{ + kFTM_RisingEdge = (1U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on rising edge only*/ + kFTM_FallingEdge = (2U << FTM_CnSC_ELSA_SHIFT), /*!< Capture on falling edge only*/ + kFTM_RiseAndFallEdge = (3U << FTM_CnSC_ELSA_SHIFT) /*!< Capture on rising or falling edge */ +} ftm_input_capture_edge_t; + +/*! @brief FlexTimer dual edge capture modes */ +typedef enum _ftm_dual_edge_capture_mode +{ + kFTM_OneShot = 0U, /*!< One-shot capture mode */ + kFTM_Continuous = (1U << FTM_CnSC_MSA_SHIFT) /*!< Continuous capture mode */ +} ftm_dual_edge_capture_mode_t; + +/*! @brief FlexTimer dual edge capture parameters */ +typedef struct _ftm_dual_edge_capture_param +{ + ftm_dual_edge_capture_mode_t mode; /*!< Dual Edge Capture mode */ + ftm_input_capture_edge_t currChanEdgeMode; /*!< Input capture edge select for channel n */ + ftm_input_capture_edge_t nextChanEdgeMode; /*!< Input capture edge select for channel n+1 */ +} ftm_dual_edge_capture_param_t; + +/*! @brief FlexTimer quadrature decode modes */ +typedef enum _ftm_quad_decode_mode +{ + kFTM_QuadPhaseEncode = 0U, /*!< Phase A and Phase B encoding mode */ + kFTM_QuadCountAndDir /*!< Count and direction encoding mode */ +} ftm_quad_decode_mode_t; + +/*! @brief FlexTimer quadrature phase polarities */ +typedef enum _ftm_phase_polarity +{ + kFTM_QuadPhaseNormal = 0U, /*!< Phase input signal is not inverted */ + kFTM_QuadPhaseInvert /*!< Phase input signal is inverted */ +} ftm_phase_polarity_t; + +/*! @brief FlexTimer quadrature decode phase parameters */ +typedef struct _ftm_phase_param +{ + bool enablePhaseFilter; /*!< True: enable phase filter; false: disable filter */ + uint32_t phaseFilterVal; /*!< Filter value, used only if phase filter is enabled */ + ftm_phase_polarity_t phasePolarity; /*!< Phase polarity */ +} ftm_phase_params_t; + +/*! @brief Structure is used to hold the parameters to configure a FTM fault */ +typedef struct _ftm_fault_param +{ + bool enableFaultInput; /*!< True: Fault input is enabled; false: Fault input is disabled */ + bool faultLevel; /*!< True: Fault polarity is active low; in other words, '0' indicates a fault; + False: Fault polarity is active high */ + bool useFaultFilter; /*!< True: Use the filtered fault signal; + False: Use the direct path from fault input */ +} ftm_fault_param_t; + +/*! @brief FlexTimer pre-scaler factor for the dead time insertion*/ +typedef enum _ftm_deadtime_prescale +{ + kFTM_Deadtime_Prescale_1 = 1U, /*!< Divide by 1 */ + kFTM_Deadtime_Prescale_4, /*!< Divide by 4 */ + kFTM_Deadtime_Prescale_16 /*!< Divide by 16 */ +} ftm_deadtime_prescale_t; + +/*! @brief FlexTimer clock source selection*/ +typedef enum _ftm_clock_source +{ + kFTM_SystemClock = 1U, /*!< System clock selected */ + kFTM_FixedClock, /*!< Fixed frequency clock */ + kFTM_ExternalClock /*!< External clock */ +} ftm_clock_source_t; + +/*! @brief FlexTimer pre-scaler factor selection for the clock source*/ +typedef enum _ftm_clock_prescale +{ + kFTM_Prescale_Divide_1 = 0U, /*!< Divide by 1 */ + kFTM_Prescale_Divide_2, /*!< Divide by 2 */ + kFTM_Prescale_Divide_4, /*!< Divide by 4 */ + kFTM_Prescale_Divide_8, /*!< Divide by 8 */ + kFTM_Prescale_Divide_16, /*!< Divide by 16 */ + kFTM_Prescale_Divide_32, /*!< Divide by 32 */ + kFTM_Prescale_Divide_64, /*!< Divide by 64 */ + kFTM_Prescale_Divide_128 /*!< Divide by 128 */ +} ftm_clock_prescale_t; + +/*! @brief Options for the FlexTimer behaviour in BDM Mode */ +typedef enum _ftm_bdm_mode +{ + kFTM_BdmMode_0 = 0U, + /*!< FTM counter stopped, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V + registers bypass the register buffers */ + kFTM_BdmMode_1, + /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are forced to their safe value , writes to + MOD,CNTIN and C(n)V registers bypass the register buffers */ + kFTM_BdmMode_2, + /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are frozen when chip enters in BDM mode, + writes to MOD,CNTIN and C(n)V registers bypass the register buffers */ + kFTM_BdmMode_3 + /*!< FTM counter in functional mode, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and + C(n)V registers is in fully functional mode */ +} ftm_bdm_mode_t; + +/*! @brief Options for the FTM fault control mode */ +typedef enum _ftm_fault_mode +{ + kFTM_Fault_Disable = 0U, /*!< Fault control is disabled for all channels */ + kFTM_Fault_EvenChnls, /*!< Enabled for even channels only(0,2,4,6) with manual fault clearing */ + kFTM_Fault_AllChnlsMan, /*!< Enabled for all channels with manual fault clearing */ + kFTM_Fault_AllChnlsAuto /*!< Enabled for all channels with automatic fault clearing */ +} ftm_fault_mode_t; + +/*! + * @brief FTM external trigger options + * @note Actual available external trigger sources are SoC-specific + */ +typedef enum _ftm_external_trigger +{ + kFTM_Chnl0Trigger = (1U << 4), /*!< Generate trigger when counter equals chnl 0 CnV reg */ + kFTM_Chnl1Trigger = (1U << 5), /*!< Generate trigger when counter equals chnl 1 CnV reg */ + kFTM_Chnl2Trigger = (1U << 0), /*!< Generate trigger when counter equals chnl 2 CnV reg */ + kFTM_Chnl3Trigger = (1U << 1), /*!< Generate trigger when counter equals chnl 3 CnV reg */ + kFTM_Chnl4Trigger = (1U << 2), /*!< Generate trigger when counter equals chnl 4 CnV reg */ + kFTM_Chnl5Trigger = (1U << 3), /*!< Generate trigger when counter equals chnl 5 CnV reg */ + kFTM_Chnl6Trigger = + (1U << 8), /*!< Available on certain SoC's, generate trigger when counter equals chnl 6 CnV reg */ + kFTM_Chnl7Trigger = + (1U << 9), /*!< Available on certain SoC's, generate trigger when counter equals chnl 7 CnV reg */ + kFTM_InitTrigger = (1U << 6), /*!< Generate Trigger when counter is updated with CNTIN */ + kFTM_ReloadInitTrigger = (1U << 7) /*!< Available on certain SoC's, trigger on reload point */ +} ftm_external_trigger_t; + +/*! @brief FlexTimer PWM sync options to update registers with buffer */ +typedef enum _ftm_pwm_sync_method +{ + kFTM_SoftwareTrigger = FTM_SYNC_SWSYNC_MASK, /*!< Software triggers PWM sync */ + kFTM_HardwareTrigger_0 = FTM_SYNC_TRIG0_MASK, /*!< Hardware trigger 0 causes PWM sync */ + kFTM_HardwareTrigger_1 = FTM_SYNC_TRIG1_MASK, /*!< Hardware trigger 1 causes PWM sync */ + kFTM_HardwareTrigger_2 = FTM_SYNC_TRIG2_MASK /*!< Hardware trigger 2 causes PWM sync */ +} ftm_pwm_sync_method_t; + +/*! + * @brief FTM options available as loading point for register reload + * @note Actual available reload points are SoC-specific + */ +typedef enum _ftm_reload_point +{ + kFTM_Chnl0Match = (1U << 0), /*!< Channel 0 match included as a reload point */ + kFTM_Chnl1Match = (1U << 1), /*!< Channel 1 match included as a reload point */ + kFTM_Chnl2Match = (1U << 2), /*!< Channel 2 match included as a reload point */ + kFTM_Chnl3Match = (1U << 3), /*!< Channel 3 match included as a reload point */ + kFTM_Chnl4Match = (1U << 4), /*!< Channel 4 match included as a reload point */ + kFTM_Chnl5Match = (1U << 5), /*!< Channel 5 match included as a reload point */ + kFTM_Chnl6Match = (1U << 6), /*!< Channel 6 match included as a reload point */ + kFTM_Chnl7Match = (1U << 7), /*!< Channel 7 match included as a reload point */ + kFTM_CntMax = (1U << 8), /*!< Use in up-down count mode only, reload when counter reaches the maximum value */ + kFTM_CntMin = (1U << 9), /*!< Use in up-down count mode only, reload when counter reaches the minimum value */ + kFTM_HalfCycMatch = (1U << 10) /*!< Available on certain SoC's, half cycle match reload point */ +} ftm_reload_point_t; + +/*! + * @brief List of FTM interrupts + * @note Actual available interrupts are SoC-specific + */ +typedef enum _ftm_interrupt_enable +{ + kFTM_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt */ + kFTM_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt */ + kFTM_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt */ + kFTM_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt */ + kFTM_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt */ + kFTM_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt */ + kFTM_Chnl6InterruptEnable = (1U << 6), /*!< Channel 6 interrupt */ + kFTM_Chnl7InterruptEnable = (1U << 7), /*!< Channel 7 interrupt */ + kFTM_FaultInterruptEnable = (1U << 8), /*!< Fault interrupt */ + kFTM_TimeOverflowInterruptEnable = (1U << 9), /*!< Time overflow interrupt */ + kFTM_ReloadInterruptEnable = (1U << 10) /*!< Reload interrupt; Available only on certain SoC's */ +} ftm_interrupt_enable_t; + +/*! + * @brief List of FTM flags + * @note Actual available flags are SoC-specific + */ +typedef enum _ftm_status_flags +{ + kFTM_Chnl0Flag = (1U << 0), /*!< Channel 0 Flag */ + kFTM_Chnl1Flag = (1U << 1), /*!< Channel 1 Flag */ + kFTM_Chnl2Flag = (1U << 2), /*!< Channel 2 Flag */ + kFTM_Chnl3Flag = (1U << 3), /*!< Channel 3 Flag */ + kFTM_Chnl4Flag = (1U << 4), /*!< Channel 4 Flag */ + kFTM_Chnl5Flag = (1U << 5), /*!< Channel 5 Flag */ + kFTM_Chnl6Flag = (1U << 6), /*!< Channel 6 Flag */ + kFTM_Chnl7Flag = (1U << 7), /*!< Channel 7 Flag */ + kFTM_FaultFlag = (1U << 8), /*!< Fault Flag */ + kFTM_TimeOverflowFlag = (1U << 9), /*!< Time overflow Flag */ + kFTM_ChnlTriggerFlag = (1U << 10), /*!< Channel trigger Flag */ + kFTM_ReloadFlag = (1U << 11) /*!< Reload Flag; Available only on certain SoC's */ +} ftm_status_flags_t; + +/*! + * @brief List of FTM Quad Decoder flags. + */ +enum _ftm_quad_decoder_flags +{ + kFTM_QuadDecoderCountingIncreaseFlag = FTM_QDCTRL_QUADIR_MASK, /*!< Counting direction is increasing (FTM counter + increment), or the direction is decreasing. */ + kFTM_QuadDecoderCountingOverflowOnTopFlag = FTM_QDCTRL_TOFDIR_MASK, /*!< Indicates if the TOF bit was set on the top + or the bottom of counting. */ +}; + +/*! + * @brief FTM configuration structure + * + * This structure holds the configuration settings for the FTM peripheral. To initialize this + * structure to reasonable defaults, call the FTM_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ftm_config +{ + ftm_clock_prescale_t prescale; /*!< FTM clock prescale value */ + ftm_bdm_mode_t bdmMode; /*!< FTM behavior in BDM mode */ + uint32_t pwmSyncMode; /*!< Synchronization methods to use to update buffered registers; Multiple + update modes can be used by providing an OR'ed list of options + available in enumeration ::ftm_pwm_sync_method_t. */ + uint32_t reloadPoints; /*!< FTM reload points; When using this, the PWM + synchronization is not required. Multiple reload points can be used by providing + an OR'ed list of options available in + enumeration ::ftm_reload_point_t. */ + ftm_fault_mode_t faultMode; /*!< FTM fault control mode */ + uint8_t faultFilterValue; /*!< Fault input filter value */ + ftm_deadtime_prescale_t deadTimePrescale; /*!< The dead time prescalar value */ + uint32_t deadTimeValue; /*!< The dead time value + deadTimeValue's available range is 0-1023 when register has DTVALEX, + otherwise its available range is 0-63. */ + uint32_t extTriggers; /*!< External triggers to enable. Multiple trigger sources can be + enabled by providing an OR'ed list of options available in + enumeration ::ftm_external_trigger_t. */ + uint8_t chnlInitState; /*!< Defines the initialization value of the channels in OUTINT register */ + uint8_t chnlPolarity; /*!< Defines the output polarity of the channels in POL register */ + bool useGlobalTimeBase; /*!< True: Use of an external global time base is enabled; + False: disabled */ +} ftm_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the FTM clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application which is using the FTM driver. + * + * @param base FTM peripheral base address + * @param config Pointer to the user configuration structure. + * + * @return kStatus_Success indicates success; Else indicates failure. + */ +status_t FTM_Init(FTM_Type *base, const ftm_config_t *config); + +/*! + * @brief Gates the FTM clock. + * + * @param base FTM peripheral base address + */ +void FTM_Deinit(FTM_Type *base); + +/*! + * @brief Fills in the FTM configuration structure with the default settings. + * + * The default values are: + * @code + * config->prescale = kFTM_Prescale_Divide_1; + * config->bdmMode = kFTM_BdmMode_0; + * config->pwmSyncMode = kFTM_SoftwareTrigger; + * config->reloadPoints = 0; + * config->faultMode = kFTM_Fault_Disable; + * config->faultFilterValue = 0; + * config->deadTimePrescale = kFTM_Deadtime_Prescale_1; + * config->deadTimeValue = 0; + * config->extTriggers = 0; + * config->chnlInitState = 0; + * config->chnlPolarity = 0; + * config->useGlobalTimeBase = false; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void FTM_GetDefaultConfig(ftm_config_t *config); + +/*! @}*/ + +/*! + * @name Channel mode operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Call this function to configure the PWM signal period, mode, duty cycle, and edge. Use this + * function to configure all FTM channels that are used to output a PWM signal. + * + * @param base FTM peripheral base address + * @param chnlParams Array of PWM channel parameters to configure the channel(s) + * @param numOfChnls Number of channels to configure; This should be the size of the array passed in + * @param mode PWM operation mode, options available in enumeration ::ftm_pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz FTM counter clock in Hz + * + * @return kStatus_Success if the PWM setup was successful + * kStatus_Error on failure + */ +status_t FTM_SetupPwm(FTM_Type *base, + const ftm_chnl_pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + ftm_pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz); + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @param base FTM peripheral base address + * @param chnlNumber The channel/channel pair number. In combined mode, this represents + * the channel pair number + * @param currentPwmMode The current PWM mode set during PWM setup + * @param dutyCyclePercent New PWM pulse width; The value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void FTM_UpdatePwmDutycycle(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_pwm_mode_t currentPwmMode, + uint8_t dutyCyclePercent); + +/*! + * @brief Updates the edge level selection for a channel. + * + * @param base FTM peripheral base address + * @param chnlNumber The channel number + * @param level The level to be set to the ELSnB:ELSnA field; Valid values are 00, 01, 10, 11. + * See the Kinetis SoC reference manual for details about this field. + */ +void FTM_UpdateChnlEdgeLevelSelect(FTM_Type *base, ftm_chnl_t chnlNumber, uint8_t level); + +/*! + * @brief Enables capturing an input signal on the channel using the function parameters. + * + * When the edge specified in the captureMode argument occurs on the channel, the FTM counter is + * captured into the CnV register. The user has to read the CnV register separately to get this + * value. The filter function is disabled if the filterVal argument passed in is 0. The filter + * function is available only for channels 0, 1, 2, 3. + * + * @param base FTM peripheral base address + * @param chnlNumber The channel number + * @param captureMode Specifies which edge to capture + * @param filterValue Filter value, specify 0 to disable filter. Available only for channels 0-3. + */ +void FTM_SetupInputCapture(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_input_capture_edge_t captureMode, + uint32_t filterValue); + +/*! + * @brief Configures the FTM to generate timed pulses. + * + * When the FTM counter matches the value of compareVal argument (this is written into CnV reg), + * the channel output is changed based on what is specified in the compareMode argument. + * + * @param base FTM peripheral base address + * @param chnlNumber The channel number + * @param compareMode Action to take on the channel output when the compare condition is met + * @param compareValue Value to be programmed in the CnV register. + */ +void FTM_SetupOutputCompare(FTM_Type *base, + ftm_chnl_t chnlNumber, + ftm_output_compare_mode_t compareMode, + uint32_t compareValue); + +/*! + * @brief Configures the dual edge capture mode of the FTM. + * + * This function sets up the dual edge capture mode on a channel pair. The capture edge for the + * channel pair and the capture mode (one-shot or continuous) is specified in the parameter + * argument. The filter function is disabled if the filterVal argument passed is zero. The filter + * function is available only on channels 0 and 2. The user has to read the channel CnV registers + * separately to get the capture values. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param edgeParam Sets up the dual edge capture function + * @param filterValue Filter value, specify 0 to disable filter. Available only for channel pair 0 and 1. + */ +void FTM_SetupDualEdgeCapture(FTM_Type *base, + ftm_chnl_t chnlPairNumber, + const ftm_dual_edge_capture_param_t *edgeParam, + uint32_t filterValue); + +/*! @}*/ + +/*! + * @brief Sets up the working of the FTM fault protection. + * + * FTM can have up to 4 fault inputs. This function sets up fault parameters, fault level, and a filter. + * + * @param base FTM peripheral base address + * @param faultNumber FTM fault to configure. + * @param faultParams Parameters passed in to set up the fault + */ +void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected FTM interrupts. + * + * @param base FTM peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ftm_interrupt_enable_t + */ +void FTM_EnableInterrupts(FTM_Type *base, uint32_t mask); + +/*! + * @brief Disables the selected FTM interrupts. + * + * @param base FTM peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ftm_interrupt_enable_t + */ +void FTM_DisableInterrupts(FTM_Type *base, uint32_t mask); + +/*! + * @brief Gets the enabled FTM interrupts. + * + * @param base FTM peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ftm_interrupt_enable_t + */ +uint32_t FTM_GetEnabledInterrupts(FTM_Type *base); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the FTM status flags. + * + * @param base FTM peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ftm_status_flags_t + */ +uint32_t FTM_GetStatusFlags(FTM_Type *base); + +/*! + * @brief Clears the FTM status flags. + * + * @param base FTM peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ftm_status_flags_t + */ +void FTM_ClearStatusFlags(FTM_Type *base, uint32_t mask); + +/*! @}*/ + +/*! + * @name Read and write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of ticks. + * + * Timers counts from 0 until it equals the count value set here. The count value is written to + * the MOD register. + * + * @note + * 1. This API allows the user to use the FTM module as a timer. Do not mix usage + * of this API with FTM's PWM setup API's. + * 2. Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks. + * + * @param base FTM peripheral base address + * @param ticks A timer period in units of ticks, which should be equal or greater than 1. + */ +static inline void FTM_SetTimerPeriod(FTM_Type *base, uint32_t ticks) +{ + base->MOD = ticks; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value in a range from 0 to a + * timer period. + * + * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec. + * + * @param base FTM peripheral base address + * + * @return The current counter value in ticks + */ +static inline uint32_t FTM_GetCurrentTimerCount(FTM_Type *base) +{ + return (uint32_t)((base->CNT & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT); +} + +/*! @}*/ +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the FTM counter. + * + * @param base FTM peripheral base address + * @param clockSource FTM clock source; After the clock source is set, the counter starts running. + */ +static inline void FTM_StartTimer(FTM_Type *base, ftm_clock_source_t clockSource) +{ + uint32_t reg = base->SC; + + reg &= ~(FTM_SC_CLKS_MASK); + reg |= FTM_SC_CLKS(clockSource); + base->SC = reg; +} + +/*! + * @brief Stops the FTM counter. + * + * @param base FTM peripheral base address + */ +static inline void FTM_StopTimer(FTM_Type *base) +{ + /* Set clock source to none to disable counter */ + base->SC &= ~(FTM_SC_CLKS_MASK); +} + +/*! @}*/ + +/*! + * @name Software output control + * @{ + */ + +/*! + * @brief Enables or disables the channel software output control. + * + * @param base FTM peripheral base address + * @param chnlNumber Channel to be enabled or disabled + * @param value true: channel output is affected by software output control + false: channel output is unaffected by software output control + */ +static inline void FTM_SetSoftwareCtrlEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) +{ + if (value) + { + base->SWOCTRL |= (1U << chnlNumber); + } + else + { + base->SWOCTRL &= ~(1U << chnlNumber); + } +} + +/*! + * @brief Sets the channel software output control value. + * + * @param base FTM peripheral base address. + * @param chnlNumber Channel to be configured + * @param value true to set 1, false to set 0 + */ +static inline void FTM_SetSoftwareCtrlVal(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) +{ + if (value) + { + base->SWOCTRL |= (1U << (chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT)); + } + else + { + base->SWOCTRL &= ~(1U << (chnlNumber + FTM_SWOCTRL_CH0OCV_SHIFT)); + } +} + +/*! @}*/ + +/*! + * @brief Enables or disables the FTM global time base signal generation to other FTMs. + * + * @param base FTM peripheral base address + * @param enable true to enable, false to disable + */ +static inline void FTM_SetGlobalTimeBaseOutputEnable(FTM_Type *base, bool enable) +{ + if (enable) + { + base->CONF |= FTM_CONF_GTBEOUT_MASK; + } + else + { + base->CONF &= ~FTM_CONF_GTBEOUT_MASK; + } +} + +/*! + * @brief Sets the FTM peripheral timer channel output mask. + * + * @param base FTM peripheral base address + * @param chnlNumber Channel to be configured + * @param mask true: masked, channel is forced to its inactive state; false: unmasked + */ +static inline void FTM_SetOutputMask(FTM_Type *base, ftm_chnl_t chnlNumber, bool mask) +{ + if (mask) + { + base->OUTMASK |= (1U << chnlNumber); + } + else + { + base->OUTMASK &= ~(1U << chnlNumber); + } +} + +#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) +/*! + * @brief Allows users to enable an output on an FTM channel. + * + * To enable the PWM channel output call this function with val=true. For input mode, + * call this function with val=false. + * + * @param base FTM peripheral base address + * @param chnlNumber Channel to be configured + * @param value true: enable output; false: output is disabled, used in input mode + */ +static inline void FTM_SetPwmOutputEnable(FTM_Type *base, ftm_chnl_t chnlNumber, bool value) +{ + if (value) + { + base->SC |= (1U << (chnlNumber + FTM_SC_PWMEN0_SHIFT)); + } + else + { + base->SC &= ~(1U << (chnlNumber + FTM_SC_PWMEN0_SHIFT)); + } +} +#endif + +/*! + * @name Channel pair operations + * @{ + */ + +/*! + * @brief This function enables/disables the fault control in a channel pair. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param value true: Enable fault control for this channel pair; false: No fault control + */ +static inline void FTM_SetFaultControlEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) +{ + if (value) + { + base->COMBINE |= (1U << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } + else + { + base->COMBINE &= ~(1U << (FTM_COMBINE_FAULTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } +} + +/*! + * @brief This function enables/disables the dead time insertion in a channel pair. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param value true: Insert dead time in this channel pair; false: No dead time inserted + */ +static inline void FTM_SetDeadTimeEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) +{ + if (value) + { + base->COMBINE |= (1U << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } + else + { + base->COMBINE &= ~(1U << (FTM_COMBINE_DTEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } +} + +/*! + * @brief This function enables/disables complementary mode in a channel pair. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param value true: enable complementary mode; false: disable complementary mode + */ +static inline void FTM_SetComplementaryEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) +{ + if (value) + { + base->COMBINE |= (1U << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } + else + { + base->COMBINE &= ~(1U << (FTM_COMBINE_COMP0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlPairNumber))); + } +} + +/*! + * @brief This function enables/disables inverting control in a channel pair. + * + * @param base FTM peripheral base address + * @param chnlPairNumber The FTM channel pair number; options are 0, 1, 2, 3 + * @param value true: enable inverting; false: disable inverting + */ +static inline void FTM_SetInvertEnable(FTM_Type *base, ftm_chnl_t chnlPairNumber, bool value) +{ + if (value) + { + base->INVCTRL |= (1U << chnlPairNumber); + } + else + { + base->INVCTRL &= ~(1U << chnlPairNumber); + } +} + +/*! @}*/ + +/*! + * @name Quad Decoder + * @{ + */ + +/*! + * @brief Configures the parameters and activates the quadrature decoder mode. + * + * @param base FTM peripheral base address + * @param phaseAParams Phase A configuration parameters + * @param phaseBParams Phase B configuration parameters + * @param quadMode Selects encoding mode used in quadrature decoder mode + */ +void FTM_SetupQuadDecode(FTM_Type *base, + const ftm_phase_params_t *phaseAParams, + const ftm_phase_params_t *phaseBParams, + ftm_quad_decode_mode_t quadMode); + +/*! + * @brief Gets the FTM Quad Decoder flags. + * + * @param base FTM peripheral base address. + * @return Flag mask of FTM Quad Decoder, see #_ftm_quad_decoder_flags. + */ +static inline uint32_t FTM_GetQuadDecoderFlags(FTM_Type *base) +{ + return base->QDCTRL & (FTM_QDCTRL_QUADIR_MASK | FTM_QDCTRL_TOFDIR_MASK); +} + +/*! + * @brief Sets the modulo values for Quad Decoder. + * + * The modulo values configure the minimum and maximum values that the Quad decoder counter can reach. After the counter goes + * over, the counter value goes to the other side and decrease/increase again. + * + * @param base FTM peripheral base address. + * @param startValue The low limit value for Quad Decoder counter. + * @param overValue The high limit value for Quad Decoder counter. + */ +static inline void FTM_SetQuadDecoderModuloValue(FTM_Type *base, uint32_t startValue, uint32_t overValue) +{ + base->CNTIN = startValue; + base->MOD = overValue; +} + +/*! + * @brief Gets the current Quad Decoder counter value. + * + * @param base FTM peripheral base address. + * @return Current quad Decoder counter value. + */ +static inline uint32_t FTM_GetQuadDecoderCounterValue(FTM_Type *base) +{ + return base->CNT; +} + +/*! + * @brief Clears the current Quad Decoder counter value. + * + * The counter is set as the initial value. + * + * @param base FTM peripheral base address. + */ +static inline void FTM_ClearQuadDecoderCounterValue(FTM_Type *base) +{ + base->CNT = base->CNTIN; +} + +/*! @}*/ + +/*! + * @brief Enables or disables the FTM software trigger for PWM synchronization. + * + * @param base FTM peripheral base address + * @param enable true: software trigger is selected, false: software trigger is not selected + */ +static inline void FTM_SetSoftwareTrigger(FTM_Type *base, bool enable) +{ + if (enable) + { + base->SYNC |= FTM_SYNC_SWSYNC_MASK; + } + else + { + base->SYNC &= ~FTM_SYNC_SWSYNC_MASK; + } +} + +/*! + * @brief Enables or disables the FTM write protection. + * + * @param base FTM peripheral base address + * @param enable true: Write-protection is enabled, false: Write-protection is disabled + */ +static inline void FTM_SetWriteProtection(FTM_Type *base, bool enable) +{ + /* Configure write protection */ + if (enable) + { + base->FMS |= FTM_FMS_WPEN_MASK; + } + else + { + base->MODE |= FTM_MODE_WPDIS_MASK; + } +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FTM_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_gpio.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_gpio.c new file mode 100644 index 00000000000..b40ee3ac11c --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_gpio.c @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_gpio.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; + +/******************************************************************************* +* Prototypes +******************************************************************************/ + +/*! +* @brief Gets the GPIO instance according to the GPIO base +* +* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) +* @retval GPIO instance +*/ +static uint32_t GPIO_GetInstance(GPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gpioBases)); + + return instance; +} + +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(config); + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= ~(1U << pin); + } + else + { + GPIO_WritePinOutput(base, pin, config->outputLogic); + base->PDDR |= (1U << pin); + } +} + +uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) +{ + uint8_t instance; + PORT_Type *portBase; + instance = GPIO_GetInstance(base); + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + PORT_Type *portBase; + instance = GPIO_GetInstance(base); + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute) +{ + base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) | + ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT); +} +#endif + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/******************************************************************************* + * Variables + ******************************************************************************/ +static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; + +/******************************************************************************* +* Prototypes +******************************************************************************/ +/*! +* @brief Gets the FGPIO instance according to the GPIO base +* +* @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) +* @retval FGPIO instance +*/ +static uint32_t FGPIO_GetInstance(FGPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t FGPIO_GetInstance(FGPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++) + { + if (s_fgpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_fgpioBases)); + + return instance; +} + +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(config); + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= ~(1U << pin); + } + else + { + FGPIO_WritePinOutput(base, pin, config->outputLogic); + base->PDDR |= (1U << pin); + } +} + +uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base) +{ + uint8_t instance; + instance = FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + instance = FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} + +#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute) +{ + base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) | + (attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT); +} +#endif + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_gpio.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_gpio.h new file mode 100644 index 00000000000..410e2b8ee46 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_gpio.h @@ -0,0 +1,440 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version 2.1.1. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +/*! @brief GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! @brief GPIO checker attribute */ +typedef enum _gpio_checker_attribute +{ + kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW = + 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW = + 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW = + 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW = + 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW = + 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW = + 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR = + 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */ + kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN = + 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */ + kGPIO_IgnoreAttributeCheck = 0x10U, /*!< Ignores the attribute check */ +} gpio_checker_attribute_t; +#endif + +/*! + * @brief The GPIO pin configuration structure. + * + * Each pin can only be configured as either an output pin or an input pin at a time. + * If configured as an input pin, leave the outputConfig unused. + * Note that in some use cases, the corresponding port property should be configured in advance + * with the PORT_SetPinConfig(). + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations; ignore if configured as an input pin */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ +} gpio_pin_config_t; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * @code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO port pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1U << pin; + } + else + { + base->PSOR = 1U << pin; + } +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} +/*@}*/ + +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the GPIO port. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} +/*@}*/ + +/*! @name GPIO Interrupt */ +/*@{*/ + +/*! + * @brief Reads the GPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base); + +/*! + * @brief Clears multiple GPIO pin interrupt status flags. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask); + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! + * @brief The GPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute); +#endif + +/*@}*/ +/*! @} */ + +/*! + * @addtogroup fgpio_driver + * @{ + */ + +/* + * Introduces the FGPIO feature. + * + * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT + * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and + * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. + */ + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/*! @name FGPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * @code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO port pin number + * @param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name FGPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @param output FGPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1 << pin; + } + else + { + base->PSOR = 1 << pin; + } +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple FGPIO pins. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} +/*@}*/ + +/*! @name FGPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the FGPIO port. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @retval FGPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} +/*@}*/ + +/*! @name FGPIO Interrupt */ +/*@{*/ + +/*! + * @brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base); + +/*! + * @brief Clears the multiple FGPIO pin interrupt status flag. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask); + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! + * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute); +#endif + +/*@}*/ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_i2c.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_i2c.c new file mode 100644 index 00000000000..6c9770af256 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_i2c.c @@ -0,0 +1,1757 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_i2c.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief i2c transfer state. */ +enum _i2c_transfer_states +{ + kIdleState = 0x0U, /*!< I2C bus idle. */ + kCheckAddressState = 0x1U, /*!< 7-bit address check state. */ + kSendCommandState = 0x2U, /*!< Send command byte phase. */ + kSendDataState = 0x3U, /*!< Send data transfer phase. */ + kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */ + kReceiveDataState = 0x5U, /*!< Receive data transfer phase. */ +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _i2c_flag_constants +{ +/*! All flags which are cleared by the driver upon starting a transfer. */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StartDetectFlag | kI2C_StopDetectFlag, + kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StartStopDetectInterruptEnable, +#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag | kI2C_StopDetectFlag, + kIrqFlags = kI2C_GlobalInterruptEnable | kI2C_StopDetectInterruptEnable, +#else + kClearFlags = kI2C_ArbitrationLostFlag | kI2C_IntPendingFlag, + kIrqFlags = kI2C_GlobalInterruptEnable, +#endif + +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for I2C module. + * + * @param base I2C peripheral base address. + */ +uint32_t I2C_GetInstance(I2C_Type *base); + +/*! +* @brief Set SCL/SDA hold time, this API receives SCL stop hold time, calculate the +* closest SCL divider and MULT value for the SDA hold time, SCL start and SCL stop +* hold time. To reduce the ROM size, SDA/SCL hold value mapping table is not provided, +* assume SCL divider = SCL stop hold value *2 to get the closest SCL divider value and MULT +* value, then the related SDA hold time, SCL start and SCL stop hold time is used. +* +* @param base I2C peripheral base address. +* @param sourceClock_Hz I2C functional clock frequency in Hertz. +* @param sclStopHoldTime_ns SCL stop hold time in ns. +*/ +static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz); + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + */ +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Check and clear status operation. + * + * @param base I2C peripheral base address. + * @param status current i2c hardware status. + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + */ +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + * @param isDone input param to get whether the thing is done, true is done + * @retval kStatus_Success No error found. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStatus_I2C_Nak Received Nak error. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); + +/*! + * @brief I2C common interrupt handler. + * + * @param base I2C peripheral base address. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to i2c handles for each instance. */ +static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT] = {NULL}; + +/*! @brief SCL clock divider used to calculate baudrate. */ +static const uint16_t s_i2cDividerTable[] = { + 20, 22, 24, 26, 28, 30, 34, 40, 28, 32, 36, 40, 44, 48, 56, 68, + 48, 56, 64, 72, 80, 88, 104, 128, 80, 96, 112, 128, 144, 160, 192, 240, + 160, 192, 224, 256, 288, 320, 384, 480, 320, 384, 448, 512, 576, 640, 768, 960, + 640, 768, 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840}; + +/*! @brief Pointers to i2c bases for each instance. */ +static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS; + +/*! @brief Pointers to i2c IRQ number for each instance. */ +static const IRQn_Type s_i2cIrqs[] = I2C_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to i2c clocks for each instance. */ +static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointer to master IRQ handler for each instance. */ +static i2c_isr_t s_i2cMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static i2c_isr_t s_i2cSlaveIsr; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +uint32_t I2C_GetInstance(I2C_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_i2cBases); instance++) + { + if (s_i2cBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_i2cBases)); + + return instance; +} + +static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz) +{ + uint32_t multiplier; + uint32_t computedSclHoldTime; + uint32_t absError; + uint32_t bestError = UINT32_MAX; + uint32_t bestMult = 0u; + uint32_t bestIcr = 0u; + uint8_t mult; + uint8_t i; + + /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register, + * and ranges from 0-2. It selects the multiplier factor for the divider. */ + /* SDA hold time = bus period (s) * mul * SDA hold value. */ + /* SCL start hold time = bus period (s) * mul * SCL start hold value. */ + /* SCL stop hold time = bus period (s) * mul * SCL stop hold value. */ + + for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult) + { + multiplier = 1u << mult; + + /* Scan table to find best match. */ + for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i) + { + /* Assume SCL hold(stop) value = s_i2cDividerTable[i]/2. */ + computedSclHoldTime = ((multiplier * s_i2cDividerTable[i]) * 500000000U) / sourceClock_Hz; + absError = sclStopHoldTime_ns > computedSclHoldTime ? (sclStopHoldTime_ns - computedSclHoldTime) : + (computedSclHoldTime - sclStopHoldTime_ns); + + if (absError < bestError) + { + bestMult = mult; + bestIcr = i; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0) + { + break; + } + } + } + } + + /* Set frequency register based on best settings. */ + base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr); +} + +static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + status_t result = kStatus_Success; + i2c_direction_t direction = xfer->direction; + + /* Initialize the handle transfer information. */ + handle->transfer = *xfer; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Initial transfer state. */ + if (handle->transfer.subaddressSize > 0) + { + if (xfer->direction == kI2C_Read) + { + direction = kI2C_Write; + } + } + + handle->state = kCheckAddressState; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* If repeated start is requested, send repeated start. */ + if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); + } + + return result; +} + +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check arbitration lost. */ + if (status & kI2C_ArbitrationLostFlag) + { + /* Clear arbitration lost flag. */ + base->S = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + /* Check NAK */ + else if (status & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Nak; + } + else + { + } + + return result; +} + +static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = base->S; + *isDone = false; + volatile uint8_t dummy = 0; + bool ignoreNak = ((handle->state == kSendDataState) && (handle->transfer.dataSize == 0U)) || + ((handle->state == kReceiveDataState) && (handle->transfer.dataSize == 1U)); + + /* Add this to avoid build warning. */ + dummy++; + + /* Check & clear error flags. */ + result = I2C_CheckAndClearError(base, statusFlags); + + /* Ignore Nak when it's appeared for last byte. */ + if ((result == kStatus_I2C_Nak) && ignoreNak) + { + result = kStatus_Success; + } + + /* Handle Check address state to check the slave address is Acked in slave + probe application. */ + if (handle->state == kCheckAddressState) + { + if (statusFlags & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Addr_Nak; + } + else + { + if (handle->transfer.subaddressSize > 0) + { + handle->state = kSendCommandState; + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + } + else + { + /* Next state, receive data begin. */ + handle->state = kReceiveDataBeginState; + } + } + } + } + + if (result) + { + return result; + } + + /* Run state machine. */ + switch (handle->state) + { + /* Send I2C command. */ + case kSendCommandState: + if (handle->transfer.subaddressSize) + { + handle->transfer.subaddressSize--; + base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); + } + else + { + if (handle->transfer.direction == kI2C_Write) + { + /* Next state, send data. */ + handle->state = kSendDataState; + + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0) + { + base->D = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + } + else + { + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); + + /* Next state, receive data begin. */ + handle->state = kReceiveDataBeginState; + } + } + break; + + /* Send I2C data. */ + case kSendDataState: + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0) + { + base->D = *handle->transfer.data; + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + *isDone = true; + } + break; + + /* Start I2C data receive. */ + case kReceiveDataBeginState: + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Read dummy to release the bus. */ + dummy = base->D; + + /* Next state, receive data. */ + handle->state = kReceiveDataState; + break; + + /* Receive I2C data. */ + case kReceiveDataState: + /* Receive one byte of data. */ + if (handle->transfer.dataSize--) + { + if (handle->transfer.dataSize == 0) + { + *isDone = true; + + /* Send stop if kI2C_TransferNoStop is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + result = I2C_MasterStop(base); + } + else + { + base->C1 |= I2C_C1_TX_MASK; + } + } + + /* Send NAK at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Read the data byte into the transfer buffer. */ + *handle->transfer.data = base->D; + handle->transfer.data++; + } + break; + + default: + break; + } + + return result; +} + +static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle) +{ + /* Check if master interrupt. */ + if ((base->S & kI2C_ArbitrationLostFlag) || (base->C1 & I2C_C1_MST_MASK)) + { + s_i2cMasterIsr(base, handle); + } + else + { + s_i2cSlaveIsr(base, handle); + } + __DSB(); +} + +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(masterConfig && srcClock_Hz); + + /* Temporary register for filter read. */ + uint8_t fltReg; +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + uint8_t s2Reg; +#endif +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable I2C clock. */ + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module. */ + base->A1 = 0; + base->F = 0; + base->C1 = 0; + base->S = 0xFFU; + base->C2 = 0; +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + base->FLT = 0x50U; +#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + base->FLT = 0x40U; +#endif + base->RA = 0; + + /* Disable I2C prior to configuring it. */ + base->C1 &= ~(I2C_C1_IICEN_MASK); + + /* Clear all flags. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Configure baud rate. */ + I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); + + /* Read out the FLT register. */ + fltReg = base->FLT; + +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + /* Configure the stop / hold enable. */ + fltReg &= ~(I2C_FLT_SHEN_MASK); + fltReg |= I2C_FLT_SHEN(masterConfig->enableStopHold); +#endif + + /* Configure the glitch filter value. */ + fltReg &= ~(I2C_FLT_FLT_MASK); + fltReg |= I2C_FLT_FLT(masterConfig->glitchFilterWidth); + + /* Write the register value back to the filter register. */ + base->FLT = fltReg; + +/* Enable/Disable double buffering. */ +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + s2Reg = base->S2 & (~I2C_S2_DFEN_MASK); + base->S2 = s2Reg | I2C_S2_DFEN(masterConfig->enableDoubleBuffering); +#endif + + /* Enable the I2C peripheral based on the configuration. */ + base->C1 = I2C_C1_IICEN(masterConfig->enableMaster); +} + +void I2C_MasterDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) +{ + assert(masterConfig); + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; + +/* Default stop hold enable is disabled. */ +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + masterConfig->enableStopHold = false; +#endif + + /* Default glitch filter value is no filter. */ + masterConfig->glitchFilterWidth = 0U; + +/* Default enable double buffering. */ +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + masterConfig->enableDoubleBuffering = true; +#endif + + /* Enable the I2C peripheral. */ + masterConfig->enableMaster = true; +} + +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask) +{ +#ifdef I2C_HAS_STOP_DETECT + uint8_t fltReg; +#endif + + if (mask & kI2C_GlobalInterruptEnable) + { + base->C1 |= I2C_C1_IICIE_MASK; + } + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + if (mask & kI2C_StopDetectInterruptEnable) + { + fltReg = base->FLT; + + /* Keep STOPF flag. */ + fltReg &= ~I2C_FLT_STOPF_MASK; + + /* Stop detect enable. */ + fltReg |= I2C_FLT_STOPIE_MASK; + base->FLT = fltReg; + } +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (mask & kI2C_StartStopDetectInterruptEnable) + { + fltReg = base->FLT; + + /* Keep STARTF and STOPF flags. */ + fltReg &= ~(I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK); + + /* Start and stop detect enable. */ + fltReg |= I2C_FLT_SSIE_MASK; + base->FLT = fltReg; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +} + +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask) +{ + if (mask & kI2C_GlobalInterruptEnable) + { + base->C1 &= ~I2C_C1_IICIE_MASK; + } + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + if (mask & kI2C_StopDetectInterruptEnable) + { + base->FLT &= ~(I2C_FLT_STOPIE_MASK | I2C_FLT_STOPF_MASK); + } +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (mask & kI2C_StartStopDetectInterruptEnable) + { + base->FLT &= ~(I2C_FLT_SSIE_MASK | I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK); + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +} + +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t multiplier; + uint32_t computedRate; + uint32_t absError; + uint32_t bestError = UINT32_MAX; + uint32_t bestMult = 0u; + uint32_t bestIcr = 0u; + uint8_t mult; + uint8_t i; + + /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register, + * and ranges from 0-2. It selects the multiplier factor for the divider. */ + for (mult = 0u; (mult <= 2u) && (bestError != 0); ++mult) + { + multiplier = 1u << mult; + + /* Scan table to find best match. */ + for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(uint16_t); ++i) + { + computedRate = srcClock_Hz / (multiplier * s_i2cDividerTable[i]); + absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps); + + if (absError < bestError) + { + bestMult = mult; + bestIcr = i; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0) + { + break; + } + } + } + } + + /* Set frequency register based on best settings. */ + base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr); +} + +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + + /* Return an error if the bus is already in use. */ + if (statusFlags & kI2C_BusBusyFlag) + { + result = kStatus_I2C_Busy; + } + else + { + /* Send the START signal. */ + base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK; + +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING + while (!(base->S2 & I2C_S2_EMPTY_MASK)) + { + } +#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ + + base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction) +{ + status_t result = kStatus_Success; + uint8_t savedMult; + uint32_t statusFlags = I2C_MasterGetStatusFlags(base); + uint8_t timeDelay = 6; + + /* Return an error if the bus is already in use, but not by us. */ + if ((statusFlags & kI2C_BusBusyFlag) && ((base->C1 & I2C_C1_MST_MASK) == 0)) + { + result = kStatus_I2C_Busy; + } + else + { + savedMult = base->F; + base->F = savedMult & (~I2C_F_MULT_MASK); + + /* We are already in a transfer, so send a repeated start. */ + base->C1 |= I2C_C1_RSTA_MASK | I2C_C1_TX_MASK; + + /* Restore the multiplier factor. */ + base->F = savedMult; + + /* Add some delay to wait the Re-Start signal. */ + while (timeDelay--) + { + __NOP(); + } + +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING + while (!(base->S2 & I2C_S2_EMPTY_MASK)) + { + } +#endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */ + + base->D = (((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U)); + } + + return result; +} + +status_t I2C_MasterStop(I2C_Type *base) +{ + status_t result = kStatus_Success; + uint16_t timeout = UINT16_MAX; + + /* Issue the STOP command on the bus. */ + base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Wait until data transfer complete. */ + while ((base->S & kI2C_BusBusyFlag) && (--timeout)) + { + } + + if (timeout == 0) + { + result = kStatus_I2C_Timeout; + } + + return result; +} + +uint32_t I2C_MasterGetStatusFlags(I2C_Type *base) +{ + uint32_t statusFlags = base->S; + +#ifdef I2C_HAS_STOP_DETECT + /* Look up the STOPF bit from the filter register. */ + if (base->FLT & I2C_FLT_STOPF_MASK) + { + statusFlags |= kI2C_StopDetectFlag; + } +#endif + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Look up the STARTF bit from the filter register. */ + if (base->FLT & I2C_FLT_STARTF_MASK) + { + statusFlags |= kI2C_StartDetectFlag; + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + + return statusFlags; +} + +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags) +{ + status_t result = kStatus_Success; + uint8_t statusFlags = 0; + + /* Wait until the data register is ready for transmit. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to transmit data. */ + base->C1 |= I2C_C1_TX_MASK; + + while (txSize--) + { + /* Send a byte of data. */ + base->D = *txBuff++; + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + statusFlags = base->S; + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */ + if (statusFlags & kI2C_ArbitrationLostFlag) + { + base->S = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + + if ((statusFlags & kI2C_ReceiveNakFlag) && txSize) + { + base->S = kI2C_ReceiveNakFlag; + result = kStatus_I2C_Nak; + } + + if (result != kStatus_Success) + { + /* Breaking out of the send loop. */ + break; + } + } + + if (((result == kStatus_Success) && (!(flags & kI2C_TransferNoStopFlag))) || (result == kStatus_I2C_Nak)) + { + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send stop. */ + result = I2C_MasterStop(base); + } + + return result; +} + +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Wait until the data register is ready for transmit. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to receive data. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* If rxSize equals 1, configure to send NAK. */ + if (rxSize == 1) + { + /* Issue NACK on read. */ + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Do dummy read. */ + dummy = base->D; + + while ((rxSize--)) + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Single byte use case. */ + if (rxSize == 0) + { + if (!(flags & kI2C_TransferNoStopFlag)) + { + /* Issue STOP command before reading last byte. */ + result = I2C_MasterStop(base); + } + else + { + /* Change direction to Tx to avoid extra clocks. */ + base->C1 |= I2C_C1_TX_MASK; + } + } + + if (rxSize == 1) + { + /* Issue NACK on read. */ + base->C1 |= I2C_C1_TXAK_MASK; + } + + /* Read from the data register. */ + *rxBuff++ = base->D; + } + + return result; +} + +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) +{ + assert(xfer); + + i2c_direction_t direction = xfer->direction; + status_t result = kStatus_Success; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Wait until ready to complete. */ + while (!(base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Change to send write address when it's a read operation with command. */ + if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + /* If repeated start is requested, send repeated start. */ + if (xfer->flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, xfer->slaveAddress, direction); + } + + /* Return if error. */ + if (result) + { + return result; + } + + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + /* Return if error. */ + if (result) + { + if (result == kStatus_I2C_Nak) + { + result = kStatus_I2C_Addr_Nak; + + I2C_MasterStop(base); + } + + return result; + } + + /* Send subaddress. */ + if (xfer->subaddressSize) + { + do + { + /* Clear interrupt pending flag. */ + base->S = kI2C_IntPendingFlag; + + xfer->subaddressSize--; + base->D = ((xfer->subaddress) >> (8 * xfer->subaddressSize)); + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + if (result == kStatus_I2C_Nak) + { + I2C_MasterStop(base); + } + + return result; + } + + } while ((xfer->subaddressSize > 0) && (result == kStatus_Success)); + + if (xfer->direction == kI2C_Read) + { + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read); + + /* Return if error. */ + if (result) + { + return result; + } + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + if (result == kStatus_I2C_Nak) + { + result = kStatus_I2C_Addr_Nak; + + I2C_MasterStop(base); + } + + return result; + } + } + } + + /* Transmit data. */ + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) + { + /* Send Data. */ + result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + + /* Receive Data. */ + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) + { + result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); + } + + return result; +} + +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save master interrupt handler. */ + s_i2cMasterIsr = I2C_MasterTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + EnableIRQ(s_i2cIrqs[instance]); +} + +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result = kStatus_Success; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != kIdleState) + { + result = kStatus_I2C_Busy; + } + else + { + /* Start up the master transfer state machine. */ + result = I2C_InitTransferStateMachine(base, handle, xfer); + + if (result == kStatus_Success) + { + /* Enable the I2C interrupts. */ + I2C_EnableInterrupts(base, kI2C_GlobalInterruptEnable); + } + } + + return result; +} + +void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) +{ + assert(handle); + + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); + + /* Reset the state to idle. */ + handle->state = kIdleState; + + /* Send STOP signal. */ + if (handle->transfer.direction == kI2C_Read) + { + base->C1 |= I2C_C1_TXAK_MASK; + while (!(base->S & kI2C_IntPendingFlag)) + { + } + base->S = kI2C_IntPendingFlag; + + base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + dummy = base->D; + } + else + { + while (!(base->S & kI2C_IntPendingFlag)) + { + } + base->S = kI2C_IntPendingFlag; + base->C1 &= ~(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + } +} + +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle); + + i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle; + status_t result = kStatus_Success; + bool isDone; + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check transfer complete flag. */ + result = I2C_MasterTransferRunStateMachine(base, handle, &isDone); + + if (isDone || result) + { + /* Send stop command if transfer done or received Nak. */ + if ((!(handle->transfer.flags & kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak) || + (result == kStatus_I2C_Addr_Nak)) + { + /* Ensure stop command is a need. */ + if ((base->C1 & I2C_C1_MST_MASK)) + { + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + } + } + + /* Restore handle to idle state. */ + handle->state = kIdleState; + + /* Disable interrupt. */ + I2C_DisableInterrupts(base, kI2C_GlobalInterruptEnable); + + /* Call the callback function after the function has completed. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz) +{ + assert(slaveConfig); + + uint8_t tmpReg; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the module. */ + base->A1 = 0; + base->F = 0; + base->C1 = 0; + base->S = 0xFFU; + base->C2 = 0; +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + base->FLT = 0x50U; +#elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + base->FLT = 0x40U; +#endif + base->RA = 0; + + /* Configure addressing mode. */ + switch (slaveConfig->addressingMode) + { + case kI2C_Address7bit: + base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; + break; + + case kI2C_RangeMatch: + assert(slaveConfig->slaveAddress < slaveConfig->upperAddress); + base->A1 = ((uint32_t)(slaveConfig->slaveAddress)) << 1U; + base->RA = ((uint32_t)(slaveConfig->upperAddress)) << 1U; + base->C2 |= I2C_C2_RMEN_MASK; + break; + + default: + break; + } + + /* Configure low power wake up feature. */ + tmpReg = base->C1; + tmpReg &= ~I2C_C1_WUEN_MASK; + base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave); + + /* Configure general call & baud rate control. */ + tmpReg = base->C2; + tmpReg &= ~(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK); + tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall); + base->C2 = tmpReg; + +/* Enable/Disable double buffering. */ +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + tmpReg = base->S2 & (~I2C_S2_DFEN_MASK); + base->S2 = tmpReg | I2C_S2_DFEN(slaveConfig->enableDoubleBuffering); +#endif + + /* Set hold time. */ + I2C_SetHoldTime(base, slaveConfig->sclStopHoldTime_ns, srcClock_Hz); +} + +void I2C_SlaveDeinit(I2C_Type *base) +{ + /* Disable I2C module. */ + I2C_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable I2C clock. */ + CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + /* By default slave is addressed with 7-bit address. */ + slaveConfig->addressingMode = kI2C_Address7bit; + + /* General call mode is disabled by default. */ + slaveConfig->enableGeneralCall = false; + + /* Slave address match waking up MCU from low power mode is disabled. */ + slaveConfig->enableWakeUp = false; + + /* Independent slave mode baud rate at maximum frequency is disabled. */ + slaveConfig->enableBaudRateCtl = false; + +/* Default enable double buffering. */ +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + slaveConfig->enableDoubleBuffering = true; +#endif + + /* Set default SCL stop hold time to 4us which is minimum requirement in I2C spec. */ + slaveConfig->sclStopHoldTime_ns = 4000; + + /* Enable the I2C peripheral. */ + slaveConfig->enableSlave = true; +} + +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize) +{ + status_t result = kStatus_Success; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Check start flag. */ + while (!(base->FLT & I2C_FLT_STARTF_MASK)) + { + } + /* Clear STARTF flag. */ + base->FLT |= I2C_FLT_STARTF_MASK; + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + + /* Wait for address match flag. */ + while (!(base->S & kI2C_AddressMatchFlag)) + { + } + + /* Read dummy to release bus. */ + dummy = base->D; + + result = I2C_MasterWriteBlocking(base, txBuff, txSize, kI2C_TransferDefaultFlag); + + /* Switch to receive mode. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = base->D; + + return result; +} + +void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) +{ + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + +/* Wait until address match. */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Check start flag. */ + while (!(base->FLT & I2C_FLT_STARTF_MASK)) + { + } + /* Clear STARTF flag. */ + base->FLT |= I2C_FLT_STARTF_MASK; + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + + /* Wait for address match and int pending flag. */ + while (!(base->S & kI2C_AddressMatchFlag)) + { + } + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Read dummy to release bus. */ + dummy = base->D; + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Setup the I2C peripheral to receive data. */ + base->C1 &= ~(I2C_C1_TX_MASK); + + while (rxSize--) + { + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Read from the data register. */ + *rxBuff++ = base->D; + } +} + +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + s_i2cHandle[instance] = handle; + + /* Save slave interrupt handler. */ + s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ; + + /* Enable NVIC interrupt. */ + EnableIRQ(s_i2cIrqs[instance]); +} + +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask) +{ + assert(handle); + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->isBusy) + { + return kStatus_I2C_Busy; + } + else + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + I2C_DisableInterrupts(base, kIrqFlags); + + /* Clear transfer in handle. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->isBusy = true; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | kI2C_SlaveGenaralcallEvent; + + /* Clear all flags. */ + I2C_SlaveClearStatusFlags(base, kClearFlags); + + /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I2C_EnableInterrupts(base, kIrqFlags); + } + + return kStatus_Success; +} + +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) +{ + assert(handle); + + if (handle->isBusy) + { + /* Disable interrupts. */ + I2C_DisableInterrupts(base, kIrqFlags); + + /* Reset transfer info. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Reset the state to idle. */ + handle->isBusy = false; + } +} + +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transfer.transferredCount; + + return kStatus_Success; +} + +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle) +{ + assert(i2cHandle); + + uint16_t status; + bool doTransmit = false; + i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle; + i2c_slave_transfer_t *xfer; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + status = I2C_SlaveGetStatusFlags(base); + xfer = &(handle->transfer); + +#ifdef I2C_HAS_STOP_DETECT + /* Check stop flag. */ + if (status & kI2C_StopDetectFlag) + { + I2C_MasterClearStatusFlags(base, kI2C_StopDetectFlag); + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + /* Call slave callback if this is the STOP of the transfer. */ + if (handle->isBusy) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + if (!(status & kI2C_AddressMatchFlag)) + { + return; + } + } +#endif /* I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + /* Check start flag. */ + if (status & kI2C_StartDetectFlag) + { + I2C_MasterClearStatusFlags(base, kI2C_StartDetectFlag); + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + xfer->event = kI2C_SlaveStartEvent; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + if (!(status & kI2C_AddressMatchFlag)) + { + return; + } + } +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + + /* Clear the interrupt flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check NAK */ + if (status & kI2C_ReceiveNakFlag) + { + /* Set receive mode. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy. */ + dummy = base->D; + + if (handle->transfer.dataSize != 0) + { + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_I2C_Nak; + handle->isBusy = false; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + else + { +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } + /* Check address match. */ + else if (status & kI2C_AddressMatchFlag) + { + handle->isBusy = true; + xfer->event = kI2C_SlaveAddressMatchEvent; + + /* Slave transmit, master reading from slave. */ + if (status & kI2C_TransferDirectionFlag) + { + /* Change direction to send data. */ + base->C1 |= I2C_C1_TX_MASK; + + doTransmit = true; + } + else + { + /* Slave receive, master writing to slave. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy to release the bus. */ + dummy = base->D; + + if (dummy == 0) + { + xfer->event = kI2C_SlaveGenaralcallEvent; + } + } + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + /* Check transfer complete flag. */ + else if (status & kI2C_TransferCompleteFlag) + { + /* Slave transmit, master reading from slave. */ + if (status & kI2C_TransferDirectionFlag) + { + doTransmit = true; + } + else + { + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kI2C_SlaveReceiveEvent; + + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + /* Slave receive, master writing to slave. */ + uint8_t data = base->D; + + if (handle->transfer.dataSize) + { + /* Receive data. */ + *handle->transfer.data++ = data; + handle->transfer.dataSize--; + xfer->transferredCount++; + if (!handle->transfer.dataSize) + { +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + /* Proceed receive complete event. */ + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } + } + } + else + { + /* Read dummy to release bus. */ + dummy = base->D; + } + + /* Send data if there is the need. */ + if (doTransmit) + { + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kI2C_SlaveTransmitEvent; + + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + xfer->transferredCount = 0; + } + + if (handle->transfer.dataSize) + { + /* Send data. */ + base->D = *handle->transfer.data++; + handle->transfer.dataSize--; + xfer->transferredCount++; + } + else + { + /* Switch to receive mode. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy to release bus. */ + dummy = base->D; + +#ifndef I2C_HAS_STOP_DETECT + xfer->event = kI2C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + /* Proceed txdone event. */ + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +#endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */ + } + } +} + +#if defined(I2C0) +void I2C0_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]); +} +#endif + +#if defined(I2C1) +void I2C1_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]); +} +#endif + +#if defined(I2C2) +void I2C2_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]); +} +#endif + +#if defined(I2C3) +void I2C3_DriverIRQHandler(void) +{ + I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]); +} +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_i2c.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_i2c.h new file mode 100644 index 00000000000..d55fd1d8ea3 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_i2c.h @@ -0,0 +1,794 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2C_H_ +#define _FSL_I2C_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup i2c_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C driver version 2.0.3. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +#if (defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT || \ + defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT) +#define I2C_HAS_STOP_DETECT +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +/*! @brief I2C status return codes. */ +enum _i2c_status +{ + kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C is busy with current transfer. */ + kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< Bus is Idle. */ + kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< NAK received during transfer. */ + kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< Arbitration lost during transfer. */ + kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Wait event timeout. */ + kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_I2C, 5), /*!< NAK received during the address probe. */ +}; + +/*! + * @brief I2C peripheral flags + * + * The following status register flags can be cleared: + * - #kI2C_ArbitrationLostFlag + * - #kI2C_IntPendingFlag + * - #kI2C_StartDetectFlag + * - #kI2C_StopDetectFlag + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + * + */ +enum _i2c_flags +{ + kI2C_ReceiveNakFlag = I2C_S_RXAK_MASK, /*!< I2C receive NAK flag. */ + kI2C_IntPendingFlag = I2C_S_IICIF_MASK, /*!< I2C interrupt pending flag. */ + kI2C_TransferDirectionFlag = I2C_S_SRW_MASK, /*!< I2C transfer direction flag. */ + kI2C_RangeAddressMatchFlag = I2C_S_RAM_MASK, /*!< I2C range address match flag. */ + kI2C_ArbitrationLostFlag = I2C_S_ARBL_MASK, /*!< I2C arbitration lost flag. */ + kI2C_BusBusyFlag = I2C_S_BUSY_MASK, /*!< I2C bus busy flag. */ + kI2C_AddressMatchFlag = I2C_S_IAAS_MASK, /*!< I2C address match flag. */ + kI2C_TransferCompleteFlag = I2C_S_TCF_MASK, /*!< I2C transfer complete flag. */ +#ifdef I2C_HAS_STOP_DETECT + kI2C_StopDetectFlag = I2C_FLT_STOPF_MASK << 8, /*!< I2C stop detect flag. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT / FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_StartDetectFlag = I2C_FLT_STARTF_MASK << 8, /*!< I2C start detect flag. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +}; + +/*! @brief I2C feature interrupt source. */ +enum _i2c_interrupt_enable +{ + kI2C_GlobalInterruptEnable = I2C_C1_IICIE_MASK, /*!< I2C global interrupt. */ + +#if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT + kI2C_StopDetectInterruptEnable = I2C_FLT_STOPIE_MASK, /*!< I2C stop detect interrupt. */ +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_StartStopDetectInterruptEnable = I2C_FLT_SSIE_MASK, /*!< I2C start&stop detect interrupt. */ +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ +}; + +/*! @brief The direction of master and slave transfers. */ +typedef enum _i2c_direction +{ + kI2C_Write = 0x0U, /*!< Master transmits to the slave. */ + kI2C_Read = 0x1U, /*!< Master receives from the slave. */ +} i2c_direction_t; + +/*! @brief Addressing mode. */ +typedef enum _i2c_slave_address_mode +{ + kI2C_Address7bit = 0x0U, /*!< 7-bit addressing mode. */ + kI2C_RangeMatch = 0X2U, /*!< Range address match addressing mode. */ +} i2c_slave_address_mode_t; + +/*! @brief I2C transfer control flag. */ +enum _i2c_master_transfer_flags +{ + kI2C_TransferDefaultFlag = 0x0U, /*!< A transfer starts with a start signal, stops with a stop signal. */ + kI2C_TransferNoStartFlag = 0x1U, /*!< A transfer starts without a start signal. */ + kI2C_TransferRepeatedStartFlag = 0x2U, /*!< A transfer starts with a repeated start signal. */ + kI2C_TransferNoStopFlag = 0x4U, /*!< A transfer ends without a stop signal. */ +}; + +/*! + * @brief Set of events sent to the callback for nonblocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to I2C_SlaveTransferNonBlocking() to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _i2c_slave_transfer_event +{ + kI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kI2C_SlaveTransmitEvent = 0x02U, /*!< A callback is requested to provide data to transmit + (slave-transmitter role). */ + kI2C_SlaveReceiveEvent = 0x04U, /*!< A callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kI2C_SlaveTransmitAckEvent = 0x08U, /*!< A callback needs to either transmit an ACK or NACK. */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_SlaveStartEvent = 0x10U, /*!< A start/repeated start was detected. */ +#endif + kI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected or finished transfer, completing the transfer. */ + kI2C_SlaveGenaralcallEvent = 0x40U, /*!< Received the general call address after a start or repeated start. */ + + /*! A bit mask of all available events. */ + kI2C_SlaveAllEvents = kI2C_SlaveAddressMatchEvent | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent | +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + kI2C_SlaveStartEvent | +#endif + kI2C_SlaveCompletionEvent | kI2C_SlaveGenaralcallEvent, +} i2c_slave_transfer_event_t; + +/*! @brief I2C master user configuration. */ +typedef struct _i2c_master_config +{ + bool enableMaster; /*!< Enables the I2C peripheral at initialization time. */ +#if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF + bool enableStopHold; /*!< Controls the stop hold enable. */ +#endif +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + bool enableDoubleBuffering; /*!< Controls double buffer enable; notice that + enabling the double buffer disables the clock stretch. */ +#endif + uint32_t baudRate_Bps; /*!< Baud rate configuration of I2C peripheral. */ + uint8_t glitchFilterWidth; /*!< Controls the width of the glitch. */ +} i2c_master_config_t; + +/*! @brief I2C slave user configuration. */ +typedef struct _i2c_slave_config +{ + bool enableSlave; /*!< Enables the I2C peripheral at initialization time. */ + bool enableGeneralCall; /*!< Enables the general call addressing mode. */ + bool enableWakeUp; /*!< Enables/disables waking up MCU from low-power mode. */ +#if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE + bool enableDoubleBuffering; /*!< Controls a double buffer enable; notice that + enabling the double buffer disables the clock stretch. */ +#endif + bool enableBaudRateCtl; /*!< Enables/disables independent slave baud rate on SCL in very fast I2C modes. */ + uint16_t slaveAddress; /*!< A slave address configuration. */ + uint16_t upperAddress; /*!< A maximum boundary slave address used in a range matching mode. */ + i2c_slave_address_mode_t + addressingMode; /*!< An addressing mode configuration of i2c_slave_address_mode_config_t. */ + uint32_t sclStopHoldTime_ns; /*!< the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C + data) while SCL is high (stop condition), SDA hold time and SCL start hold time + are also configured according to the SCL stop hold time. */ +} i2c_slave_config_t; + +/*! @brief I2C master handle typedef. */ +typedef struct _i2c_master_handle i2c_master_handle_t; + +/*! @brief I2C master transfer callback typedef. */ +typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base, + i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C slave handle typedef. */ +typedef struct _i2c_slave_handle i2c_slave_handle_t; + +/*! @brief I2C master transfer structure. */ +typedef struct _i2c_master_transfer +{ + uint32_t flags; /*!< A transfer flag which controls the transfer. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + i2c_direction_t direction; /*!< A transfer direction, read or write. */ + uint32_t subaddress; /*!< A sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< A size of the command buffer. */ + uint8_t *volatile data; /*!< A transfer buffer. */ + volatile size_t dataSize; /*!< A transfer size. */ +} i2c_master_transfer_t; + +/*! @brief I2C master handle structure. */ +struct _i2c_master_handle +{ + i2c_master_transfer_t transfer; /*!< I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< A transfer state maintained during transfer. */ + i2c_master_transfer_callback_t completionCallback; /*!< A callback function called when the transfer is finished. */ + void *userData; /*!< A callback parameter passed to the callback function. */ +}; + +/*! @brief I2C slave transfer structure. */ +typedef struct _i2c_slave_transfer +{ + i2c_slave_transfer_event_t event; /*!< A reason that the callback is invoked. */ + uint8_t *volatile data; /*!< A transfer buffer. */ + volatile size_t dataSize; /*!< A transfer size. */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< A number of bytes actually transferred since the start or since the last repeated + start. */ +} i2c_slave_transfer_t; + +/*! @brief I2C slave transfer callback typedef. */ +typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *xfer, void *userData); + +/*! @brief I2C slave handle structure. */ +struct _i2c_slave_handle +{ + volatile bool isBusy; /*!< Indicates whether a transfer is busy. */ + i2c_slave_transfer_t transfer; /*!< I2C slave transfer copy. */ + uint32_t eventMask; /*!< A mask of enabled events. */ + i2c_slave_transfer_callback_t callback; /*!< A callback function called at the transfer event. */ + void *userData; /*!< A callback parameter passed to the callback. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and configure the I2C with master configuration. + * + * @note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can be custom filled + * or it can be set with default values by using the I2C_MasterGetDefaultConfig(). + * After calling this API, the master is ready to transfer. + * This is an example. + * @code + * i2c_master_config_t config = { + * .enableMaster = true, + * .enableStopHold = false, + * .highDrive = false, + * .baudRate_Bps = 100000, + * .glitchFilterWidth = 0 + * }; + * I2C_MasterInit(I2C0, &config, 12000000U); + * @endcode + * + * @param base I2C base pointer + * @param masterConfig A pointer to the master configuration structure + * @param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Initializes the I2C peripheral. Call this API to ungate the I2C clock + * and initialize the I2C with the slave configuration. + * + * @note This API should be called at the beginning of the application. + * Otherwise, any operation to the I2C module can cause a hard fault + * because the clock is not enabled. The configuration structure can partly be set + * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user. + * This is an example. + * @code + * i2c_slave_config_t config = { + * .enableSlave = true, + * .enableGeneralCall = false, + * .addressingMode = kI2C_Address7bit, + * .slaveAddress = 0x1DU, + * .enableWakeUp = false, + * .enablehighDrive = false, + * .enableBaudRateCtl = false, + * .sclStopHoldTime_ns = 4000 + * }; + * I2C_SlaveInit(I2C0, &config, 12000000U); + * @endcode + * + * @param base I2C base pointer + * @param slaveConfig A pointer to the slave configuration structure + * @param srcClock_Hz I2C peripheral clock frequency in Hz + */ +void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz); + +/*! + * @brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock. + * The I2C master module can't work unless the I2C_MasterInit is called. + * @param base I2C base pointer + */ +void I2C_MasterDeinit(I2C_Type *base); + +/*! + * @brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock. + * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock. + * @param base I2C base pointer + */ +void I2C_SlaveDeinit(I2C_Type *base); + +/*! + * @brief Sets the I2C master configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure(). + * Use the initialized structure unchanged in the I2C_MasterConfigure() or modify + * the structure before calling the I2C_MasterConfigure(). + * This is an example. + * @code + * i2c_master_config_t config; + * I2C_MasterGetDefaultConfig(&config); + * @endcode + * @param masterConfig A pointer to the master configuration structure. +*/ +void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig); + +/*! + * @brief Sets the I2C slave configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveConfigure(). + * Modify fields of the structure before calling the I2C_SlaveConfigure(). + * This is an example. + * @code + * i2c_slave_config_t config; + * I2C_SlaveGetDefaultConfig(&config); + * @endcode + * @param slaveConfig A pointer to the slave configuration structure. + */ +void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig); + +/*! + * @brief Enables or disabless the I2C peripheral operation. + * + * @param base I2C base pointer + * @param enable Pass true to enable and false to disable the module. + */ +static inline void I2C_Enable(I2C_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= I2C_C1_IICEN_MASK; + } + else + { + base->C1 &= ~I2C_C1_IICEN_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags to get the related status. + */ +uint32_t I2C_MasterGetStatusFlags(I2C_Type *base); + +/*! + * @brief Gets the I2C status flags. + * + * @param base I2C base pointer + * @return status flag, use status flag to AND #_i2c_flags to get the related status. + */ +static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base) +{ + return I2C_MasterGetStatusFlags(base); +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag. + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter can be any combination of the following values: + * @arg kI2C_StartDetectFlag (if available) + * @arg kI2C_StopDetectFlag (if available) + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ +/* Must clear the STARTF / STOPF bits prior to clearing IICIF */ +#if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT + if (statusMask & kI2C_StartDetectFlag) + { + /* Shift the odd-ball flags back into place. */ + base->FLT |= (uint8_t)(statusMask >> 8U); + } +#endif + +#ifdef I2C_HAS_STOP_DETECT + if (statusMask & kI2C_StopDetectFlag) + { + /* Shift the odd-ball flags back into place. */ + base->FLT |= (uint8_t)(statusMask >> 8U); + } +#endif + + base->S = (uint8_t)statusMask; +} + +/*! + * @brief Clears the I2C status flag state. + * + * The following status register flags can be cleared kI2C_ArbitrationLostFlag and kI2C_IntPendingFlag + * + * @param base I2C base pointer + * @param statusMask The status flag mask, defined in type i2c_status_flag_t. + * The parameter can be any combination of the following values: + * @arg kI2C_StartDetectFlag (if available) + * @arg kI2C_StopDetectFlag (if available) + * @arg kI2C_ArbitrationLostFlag + * @arg kI2C_IntPendingFlagFlag + */ +static inline void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusMask) +{ + I2C_MasterClearStatusFlags(base, statusMask); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables I2C interrupt requests. + * + * @param base I2C base pointer + * @param mask interrupt source + * The parameter can be combination of the following source if defined: + * @arg kI2C_GlobalInterruptEnable + * @arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable + * @arg kI2C_SdaTimeoutInterruptEnable + */ +void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask); + +/*! + * @name DMA Control + * @{ + */ +#if defined(FSL_FEATURE_I2C_HAS_DMA_SUPPORT) && FSL_FEATURE_I2C_HAS_DMA_SUPPORT +/*! + * @brief Enables/disables the I2C DMA interrupt. + * + * @param base I2C base pointer + * @param enable true to enable, false to disable +*/ +static inline void I2C_EnableDMA(I2C_Type *base, bool enable) +{ + if (enable) + { + base->C1 |= I2C_C1_DMAEN_MASK; + } + else + { + base->C1 &= ~I2C_C1_DMAEN_MASK; + } +} + +#endif /* FSL_FEATURE_I2C_HAS_DMA_SUPPORT */ + +/*! + * @brief Gets the I2C tx/rx data register address. This API is used to provide a transfer address + * for I2C DMA transfer configuration. + * + * @param base I2C base pointer + * @return data register address + */ +static inline uint32_t I2C_GetDataRegAddr(I2C_Type *base) +{ + return (uint32_t)(&(base->D)); +} + +/* @} */ +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the I2C master transfer baud rate. + * + * @param base I2C base pointer + * @param baudRate_Bps the baud rate value in bps + * @param srcClock_Hz Source clock + */ +void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends a START on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. + * The slave address is sent following the I2C START signal. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy. + */ +status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * @retval kStatus_Success Successfully send the stop signal. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterStop(I2C_Type *base); + +/*! + * @brief Sends a REPEATED START on the I2C bus. + * + * @param base I2C peripheral base pointer + * @param address 7-bit slave device address. + * @param direction Master transfer directions(transmit/receive). + * @retval kStatus_Success Successfully send the start signal. + * @retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master. + */ +status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag +* to issue a stop and kI2C_TransferNoStop to not send a stop. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @note The I2C_MasterReadBlocking function stops the bus before reading the final byte. + * Without stopping the bus prior for the final read, the bus issues another read, resulting + * in garbage data being read into the data register. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + * @param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag +* to issue a stop and kI2C_TransferNoStop to not send a stop. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Timeout Send stop signal failed, timeout. + */ +status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @param base I2C peripheral base pointer. + * @param rxBuff The pointer to the data to store the received data. + * @param rxSize The length in bytes of the data to be received. + */ +void I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to arbitration lost or receiving a NAK. + * + * @param base I2C peripheral base address. + * @param xfer Pointer to the transfer structure. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_MasterTransferCreateHandle(I2C_Type *base, + i2c_master_handle_t *handle, + i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note Calling the API returns immediately after transfer initiates. The user needs + * to call I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer + * is finished. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param xfer pointer to i2c_master_transfer_t structure. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_I2C_Busy Previous transmission still not finished. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + */ +status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_master_handle_t structure which stores the transfer state + */ +void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_master_handle_t structure. + */ +void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void I2C_SlaveTransferCreateHandle(I2C_Type *base, + i2c_slave_handle_t *handle, + i2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ +status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Aborts the slave transfer. + * + * @note This API can be called at any time to stop slave for handling the bus events. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state. + */ +void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer. + * + * @param base I2C base pointer. + * @param handle pointer to i2c_slave_handle_t structure. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Slave interrupt handler. + * + * @param base I2C base pointer. + * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state + */ +void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ + +#endif /* _FSL_I2C_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_i2c_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_i2c_edma.c new file mode 100644 index 00000000000..28a415e075a --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_i2c_edma.c @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_i2c_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*base, false); + + /* Send stop if kI2C_TransferNoStop flag is not asserted. */ + if (!(i2cPrivateHandle->handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read) + { + /* Change to send NAK at the last byte. */ + i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK; + + /* Wait the last data to be received. */ + while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Send stop signal. */ + result = I2C_MasterStop(i2cPrivateHandle->base); + + /* Read the last data byte. */ + *(i2cPrivateHandle->handle->transfer.data + i2cPrivateHandle->handle->transfer.dataSize - 1) = + i2cPrivateHandle->base->D; + } + else + { + /* Wait the last data to be sent. */ + while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Send stop signal. */ + result = I2C_MasterStop(i2cPrivateHandle->base); + } + } + else + { + if (i2cPrivateHandle->handle->transfer.direction == kI2C_Read) + { + /* Change to send NAK at the last byte. */ + i2cPrivateHandle->base->C1 |= I2C_C1_TXAK_MASK; + + /* Wait the last data to be received. */ + while (!(i2cPrivateHandle->base->S & kI2C_TransferCompleteFlag)) + { + } + + /* Change direction to send. */ + i2cPrivateHandle->base->C1 |= I2C_C1_TX_MASK; + + /* Read the last data byte. */ + *(i2cPrivateHandle->handle->transfer.data + i2cPrivateHandle->handle->transfer.dataSize - 1) = + i2cPrivateHandle->base->D; + } + } + + i2cPrivateHandle->handle->state = kIdleState; + + if (i2cPrivateHandle->handle->completionCallback) + { + i2cPrivateHandle->handle->completionCallback(i2cPrivateHandle->base, i2cPrivateHandle->handle, result, + i2cPrivateHandle->handle->userData); + } +} + +static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check arbitration lost. */ + if (status & kI2C_ArbitrationLostFlag) + { + /* Clear arbitration lost flag. */ + base->S = kI2C_ArbitrationLostFlag; + result = kStatus_I2C_ArbitrationLost; + } + /* Check NAK */ + else if (status & kI2C_ReceiveNakFlag) + { + result = kStatus_I2C_Nak; + } + else + { + } + + return result; +} + +static status_t I2C_InitTransferStateMachineEDMA(I2C_Type *base, + i2c_master_edma_handle_t *handle, + i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result = kStatus_Success; + + if (handle->state != kIdleState) + { + return kStatus_I2C_Busy; + } + else + { + i2c_direction_t direction = xfer->direction; + + /* Init the handle member. */ + handle->transfer = *xfer; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + handle->state = kTransferDataState; + + /* Clear all status before transfer. */ + I2C_MasterClearStatusFlags(base, kClearFlags); + + /* Change to send write address when it's a read operation with command. */ + if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + /* If repeated start is requested, send repeated start. */ + if (handle->transfer.flags & kI2C_TransferRepeatedStartFlag) + { + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction); + } + + if (result) + { + return result; + } + + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + /* Return if error. */ + if (result) + { + if (result == kStatus_I2C_Nak) + { + result = kStatus_I2C_Addr_Nak; + + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + + if (handle->completionCallback) + { + (handle->completionCallback)(base, handle, result, handle->userData); + } + } + + return result; + } + + /* Send subaddress. */ + if (handle->transfer.subaddressSize) + { + do + { + /* Clear interrupt pending flag. */ + base->S = kI2C_IntPendingFlag; + + handle->transfer.subaddressSize--; + base->D = ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)); + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + return result; + } + + } while ((handle->transfer.subaddressSize > 0) && (result == kStatus_Success)); + + if (handle->transfer.direction == kI2C_Read) + { + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send repeated start and slave address. */ + result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read); + + if (result) + { + return result; + } + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Check if there's transfer error. */ + result = I2C_CheckAndClearError(base, base->S); + + if (result) + { + return result; + } + } + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + } + + return result; +} + +static void I2C_MasterTransferEDMAConfig(I2C_Type *base, i2c_master_edma_handle_t *handle) +{ + edma_transfer_config_t transfer_config; + + if (handle->transfer.direction == kI2C_Read) + { + transfer_config.srcAddr = (uint32_t)I2C_GetDataRegAddr(base); + transfer_config.destAddr = (uint32_t)(handle->transfer.data); + transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1); + transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes; + transfer_config.srcOffset = 0; + transfer_config.destTransferSize = kEDMA_TransferSize1Bytes; + transfer_config.destOffset = 1; + transfer_config.minorLoopBytes = 1; + } + else + { + transfer_config.srcAddr = (uint32_t)(handle->transfer.data + 1); + transfer_config.destAddr = (uint32_t)I2C_GetDataRegAddr(base); + transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1); + transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes; + transfer_config.srcOffset = 1; + transfer_config.destTransferSize = kEDMA_TransferSize1Bytes; + transfer_config.destOffset = 0; + transfer_config.minorLoopBytes = 1; + } + + /* Store the initially configured eDMA minor byte transfer count into the I2C handle */ + handle->nbytes = transfer_config.minorLoopBytes; + + EDMA_SubmitTransfer(handle->dmaHandle, &transfer_config); + EDMA_StartTransfer(handle->dmaHandle); +} + +void I2C_MasterCreateEDMAHandle(I2C_Type *base, + i2c_master_edma_handle_t *handle, + i2c_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaHandle) +{ + assert(handle); + assert(edmaHandle); + + uint32_t instance = I2C_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the user callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Set the base for the handle. */ + base = base; + + /* Set the handle for EDMA. */ + handle->dmaHandle = edmaHandle; + + s_edmaPrivateHandle[instance].base = base; + s_edmaPrivateHandle[instance].handle = handle; + + EDMA_SetCallback(edmaHandle, (edma_callback)I2C_MasterTransferCallbackEDMA, &s_edmaPrivateHandle[instance]); +} + +status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + status_t result; + uint8_t tmpReg; + volatile uint8_t dummy = 0; + + /* Add this to avoid build warning. */ + dummy++; + + /* Disable dma xfer. */ + I2C_EnableDMA(base, false); + + /* Send address and command buffer(if there is), until senddata phase or receive data phase. */ + result = I2C_InitTransferStateMachineEDMA(base, handle, xfer); + + if (result) + { + /* Send stop if received Nak. */ + if (result == kStatus_I2C_Nak) + { + if (I2C_MasterStop(base) != kStatus_Success) + { + result = kStatus_I2C_Timeout; + } + } + + /* Reset the state to idle state. */ + handle->state = kIdleState; + + return result; + } + + /* Configure dma transfer. */ + /* For i2c send, need to send 1 byte first to trigger the dma, for i2c read, + need to send stop before reading the last byte, so the dma transfer size should + be (xSize - 1). */ + if (handle->transfer.dataSize > 1) + { + I2C_MasterTransferEDMAConfig(base, handle); + if (handle->transfer.direction == kI2C_Read) + { + /* Change direction for receive. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); + + /* Read dummy to release the bus. */ + dummy = base->D; + + /* Enabe dma transfer. */ + I2C_EnableDMA(base, true); + } + else + { + /* Enabe dma transfer. */ + I2C_EnableDMA(base, true); + + /* Send the first data. */ + base->D = *handle->transfer.data; + } + } + else /* If transfer size is 1, use polling method. */ + { + if (handle->transfer.direction == kI2C_Read) + { + tmpReg = base->C1; + + /* Change direction to Rx. */ + tmpReg &= ~I2C_C1_TX_MASK; + + /* Configure send NAK */ + tmpReg |= I2C_C1_TXAK_MASK; + + base->C1 = tmpReg; + + /* Read dummy to release the bus. */ + dummy = base->D; + } + else + { + base->D = *handle->transfer.data; + } + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear pending flag. */ + base->S = kI2C_IntPendingFlag; + + /* Send stop if kI2C_TransferNoStop flag is not asserted. */ + if (!(handle->transfer.flags & kI2C_TransferNoStopFlag)) + { + result = I2C_MasterStop(base); + } + else + { + /* Change direction to send. */ + base->C1 |= I2C_C1_TX_MASK; + } + + /* Read the last byte of data. */ + if (handle->transfer.direction == kI2C_Read) + { + *handle->transfer.data = base->D; + } + + /* Reset the state to idle. */ + handle->state = kIdleState; + } + + return result; +} + +status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count) +{ + assert(handle->dmaHandle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + if (kIdleState != handle->state) + { + *count = (handle->transferSize - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + else + { + *count = handle->transferSize; + } + + return kStatus_Success; +} + +void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle) +{ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable dma transfer. */ + I2C_EnableDMA(base, false); + + /* Reset the state to idle. */ + handle->state = kIdleState; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_i2c_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_i2c_edma.h new file mode 100644 index 00000000000..40cb648ea99 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_i2c_edma.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_I2C_DMA_H_ +#define _FSL_I2C_DMA_H_ + +#include "fsl_i2c.h" +#include "fsl_dmamux.h" +#include "fsl_edma.h" + +/*! + * @addtogroup i2c_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief I2C master eDMA handle typedef. */ +typedef struct _i2c_master_edma_handle i2c_master_edma_handle_t; + +/*! @brief I2C master eDMA transfer callback typedef. */ +typedef void (*i2c_master_edma_transfer_callback_t)(I2C_Type *base, + i2c_master_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief I2C master eDMA transfer structure. */ +struct _i2c_master_edma_handle +{ + i2c_master_transfer_t transfer; /*!< I2C master transfer structure. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint8_t state; /*!< I2C master transfer status. */ + edma_handle_t *dmaHandle; /*!< The eDMA handler used. */ + i2c_master_edma_transfer_callback_t + completionCallback; /*!< A callback function called after the eDMA transfer is finished. */ + void *userData; /*!< A callback parameter passed to the callback function. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name I2C Block eDMA Transfer Operation + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transcational functions. + * + * @param base I2C peripheral base address. + * @param handle A pointer to the i2c_master_edma_handle_t structure. + * @param callback A pointer to the user callback function. + * @param userData A user parameter passed to the callback function. + * @param edmaHandle eDMA handle pointer. + */ +void I2C_MasterCreateEDMAHandle(I2C_Type *base, + i2c_master_edma_handle_t *handle, + i2c_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaHandle); + +/*! + * @brief Performs a master eDMA non-blocking transfer on the I2C bus. + * + * @param base I2C peripheral base address. + * @param handle A pointer to the i2c_master_edma_handle_t structure. + * @param xfer A pointer to the transfer structure of i2c_master_transfer_t. + * @retval kStatus_Success Sucessfully completed the data transmission. + * @retval kStatus_I2C_Busy A previous transmission is still not finished. + * @retval kStatus_I2C_Timeout Transfer error, waits for a signal timeout. + * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + */ +status_t I2C_MasterTransferEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Gets a master transfer status during the eDMA non-blocking transfer. + * + * @param base I2C peripheral base address. + * @param handle A pointer to the i2c_master_edma_handle_t structure. + * @param count A number of bytes transferred by the non-blocking transaction. + */ +status_t I2C_MasterTransferGetCountEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle, size_t *count); + +/*! + * @brief Aborts a master eDMA non-blocking transfer early. + * + * @param base I2C peripheral base address. + * @param handle A pointer to the i2c_master_edma_handle_t structure. + */ +void I2C_MasterTransferAbortEDMA(I2C_Type *base, i2c_master_edma_handle_t *handle); + +/* @} */ +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ +#endif /*_FSL_I2C_DMA_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_llwu.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_llwu.c new file mode 100644 index 00000000000..74b1001a88a --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_llwu.c @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_llwu.h" + +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) +void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + volatile uint32_t *regBase; + uint32_t regOffset; + uint32_t reg; + + switch (pinIndex >> 4U) + { + case 0U: + regBase = &base->PE1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 1U: + regBase = &base->PE2; + break; +#endif + default: + regBase = NULL; + break; + } +#else + volatile uint8_t *regBase; + uint8_t regOffset; + uint8_t reg; + switch (pinIndex >> 2U) + { + case 0U: + regBase = &base->PE1; + break; + case 1U: + regBase = &base->PE2; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 2U: + regBase = &base->PE3; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 12)) + case 3U: + regBase = &base->PE4; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 4U: + regBase = &base->PE5; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 20)) + case 5U: + regBase = &base->PE6; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 6U: + regBase = &base->PE7; + break; +#endif +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 28)) + case 7U: + regBase = &base->PE8; + break; +#endif + default: + regBase = NULL; + break; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH == 32 */ + + if (regBase) + { + reg = *regBase; +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + regOffset = ((pinIndex & 0x0FU) << 1U); +#else + regOffset = ((pinIndex & 0x03U) << 1U); +#endif + reg &= ~(0x3U << regOffset); + reg |= ((uint32_t)pinMode << regOffset); + *regBase = reg; + } +} + +bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->PF & (1U << pinIndex)); +#else + volatile uint8_t *regBase; + + switch (pinIndex >> 3U) + { +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + case 0U: + regBase = &base->PF1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->PF2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->PF3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->PF4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#else + case 0U: + regBase = &base->F1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->F2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->F3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->F4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_HAS_PF */ + default: + regBase = NULL; + break; + } + + if (regBase) + { + return (bool)(*regBase & (1U << pinIndex % 8)); + } + else + { + return false; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + base->PF = (1U << pinIndex); +#else + volatile uint8_t *regBase; + switch (pinIndex >> 3U) + { +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + case 0U: + regBase = &base->PF1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->PF2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->PF3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->PF4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#else + case 0U: + regBase = &base->F1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 8)) + case 1U: + regBase = &base->F2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + case 2U: + regBase = &base->F3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 24)) + case 3U: + regBase = &base->F4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_HAS_PF */ + default: + regBase = NULL; + break; + } + if (regBase) + { + *regBase = (1U << pinIndex % 8U); + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + uint32_t reg; + + reg = base->FILT; + reg &= ~((LLWU_FILT_FILTSEL1_MASK | LLWU_FILT_FILTE1_MASK) << (filterIndex * 8U - 1U)); + reg |= (((filterMode.pinIndex << LLWU_FILT_FILTSEL1_SHIFT) | (filterMode.filterMode << LLWU_FILT_FILTE1_SHIFT) + /* Clear the Filter Detect Flag */ + | LLWU_FILT_FILTF1_MASK) + << (filterIndex * 8U - 1U)); + base->FILT = reg; +#else + volatile uint8_t *regBase; + uint8_t reg; + + switch (filterIndex) + { + case 1: + regBase = &base->FILT1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + regBase = &base->FILT2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + regBase = &base->FILT3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + regBase = &base->FILT4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + regBase = NULL; + break; + } + + if (regBase) + { + reg = *regBase; + reg &= ~(LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTE_MASK); + reg |= ((uint32_t)filterMode.pinIndex << LLWU_FILT1_FILTSEL_SHIFT); + reg |= ((uint32_t)filterMode.filterMode << LLWU_FILT1_FILTE_SHIFT); + /* Clear the Filter Detect Flag */ + reg |= LLWU_FILT1_FILTF_MASK; + *regBase = reg; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->FILT & (1U << (filterIndex * 8U - 1))); +#else + bool status = false; + + switch (filterIndex) + { + case 1: + status = (base->FILT1 & LLWU_FILT1_FILTF_MASK); + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + status = (base->FILT2 & LLWU_FILT2_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + status = (base->FILT3 & LLWU_FILT3_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + status = (base->FILT4 & LLWU_FILT4_FILTF_MASK); + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + break; + } + + return status; +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} + +void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex) +{ +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + uint32_t reg; + + reg = base->FILT; + switch (filterIndex) + { + case 1: + reg |= LLWU_FILT_FILTF1_MASK; + break; + case 2: + reg |= LLWU_FILT_FILTF2_MASK; + break; + case 3: + reg |= LLWU_FILT_FILTF3_MASK; + break; + case 4: + reg |= LLWU_FILT_FILTF4_MASK; + break; + default: + break; + } + base->FILT = reg; +#else + volatile uint8_t *regBase; + uint8_t reg; + + switch (filterIndex) + { + case 1: + regBase = &base->FILT1; + break; +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 1)) + case 2: + regBase = &base->FILT2; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 2)) + case 3: + regBase = &base->FILT3; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && (FSL_FEATURE_LLWU_HAS_PIN_FILTER > 3)) + case 4: + regBase = &base->FILT4; + break; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + default: + regBase = NULL; + break; + } + + if (regBase) + { + reg = *regBase; + reg |= LLWU_FILT1_FILTF_MASK; + *regBase = reg; + } +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +} +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) +void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode) +{ + uint8_t reg; + + reg = base->RST; + reg &= ~(LLWU_RST_LLRSTE_MASK | LLWU_RST_RSTFILT_MASK); + reg |= + (((uint32_t)pinEnable << LLWU_RST_LLRSTE_SHIFT) | ((uint32_t)enableInLowLeakageMode << LLWU_RST_RSTFILT_SHIFT)); + base->RST = reg; +} +#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_llwu.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_llwu.h new file mode 100644 index 00000000000..d5a0037bb58 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_llwu.h @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LLWU_H_ +#define _FSL_LLWU_H_ + +#include "fsl_common.h" + +/*! @addtogroup llwu */ +/*! @{ */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LLWU driver version 2.0.1. */ +#define FSL_LLWU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief External input pin control modes + */ +typedef enum _llwu_external_pin_mode +{ + kLLWU_ExternalPinDisable = 0U, /*!< Pin disabled as a wakeup input. */ + kLLWU_ExternalPinRisingEdge = 1U, /*!< Pin enabled with the rising edge detection. */ + kLLWU_ExternalPinFallingEdge = 2U, /*!< Pin enabled with the falling edge detection.*/ + kLLWU_ExternalPinAnyEdge = 3U /*!< Pin enabled with any change detection. */ +} llwu_external_pin_mode_t; + +/*! + * @brief Digital filter control modes + */ +typedef enum _llwu_pin_filter_mode +{ + kLLWU_PinFilterDisable = 0U, /*!< Filter disabled. */ + kLLWU_PinFilterRisingEdge = 1U, /*!< Filter positive edge detection.*/ + kLLWU_PinFilterFallingEdge = 2U, /*!< Filter negative edge detection.*/ + kLLWU_PinFilterAnyEdge = 3U /*!< Filter any edge detection. */ +} llwu_pin_filter_mode_t; + +#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _llwu_version_id +{ + uint16_t feature; /*!< A feature specification number. */ + uint8_t minor; /*!< The minor version number. */ + uint8_t major; /*!< The major version number. */ +} llwu_version_id_t; +#endif /* FSL_FEATURE_LLWU_HAS_VERID */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) +/*! + * @brief IP parameter definition. + */ +typedef struct _llwu_param +{ + uint8_t filters; /*!< A number of the pin filter. */ + uint8_t dmas; /*!< A number of the wakeup DMA. */ + uint8_t modules; /*!< A number of the wakeup module. */ + uint8_t pins; /*!< A number of the wake up pin. */ +} llwu_param_t; +#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +/*! + * @brief An external input pin filter control structure + */ +typedef struct _llwu_external_pin_filter_mode +{ + uint32_t pinIndex; /*!< A pin number */ + llwu_pin_filter_mode_t filterMode; /*!< Filter mode */ +} llwu_external_pin_filter_mode_t; +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Low-Leakage Wakeup Unit Control APIs + * @{ + */ + +#if (defined(FSL_FEATURE_LLWU_HAS_VERID) && FSL_FEATURE_LLWU_HAS_VERID) +/*! + * @brief Gets the LLWU version ID. + * + * This function gets the LLWU version ID, including the major version number, + * the minor version number, and the feature specification number. + * + * @param base LLWU peripheral base address. + * @param versionId A pointer to the version ID structure. + */ +static inline void LLWU_GetVersionId(LLWU_Type *base, llwu_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_LLWU_HAS_VERID */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PARAM) && FSL_FEATURE_LLWU_HAS_PARAM) +/*! + * @brief Gets the LLWU parameter. + * + * This function gets the LLWU parameter, including a wakeup pin number, a module + * number, a DMA number, and a pin filter number. + * + * @param base LLWU peripheral base address. + * @param param A pointer to the LLWU parameter structure. + */ +static inline void LLWU_GetParam(LLWU_Type *base, llwu_param_t *param) +{ + *((uint32_t *)param) = base->PARAM; +} +#endif /* FSL_FEATURE_LLWU_HAS_PARAM */ + +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) +/*! + * @brief Sets the external input pin source mode. + * + * This function sets the external input pin source mode that is used + * as a wake up source. + * + * @param base LLWU peripheral base address. + * @param pinIndex A pin index to be enabled as an external wakeup source starting from 1. + * @param pinMode A pin configuration mode defined in the llwu_external_pin_modes_t. + */ +void LLWU_SetExternalWakeupPinMode(LLWU_Type *base, uint32_t pinIndex, llwu_external_pin_mode_t pinMode); + +/*! + * @brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woken up by the specific pin. + * + * @param base LLWU peripheral base address. + * @param pinIndex A pin index, which starts from 1. + * @return True if the specific pin is a wakeup source. + */ +bool LLWU_GetExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); + +/*! + * @brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * @param base LLWU peripheral base address. + * @param pinIndex A pin index, which starts from 1. + */ +void LLWU_ClearExternalWakeupPinFlag(LLWU_Type *base, uint32_t pinIndex); +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ + +#if (defined(FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) && FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE) +/*! + * @brief Enables/disables the internal module source. + * + * This function enables/disables the internal module source mode that is used + * as a wake up source. + * + * @param base LLWU peripheral base address. + * @param moduleIndex A module index to be enabled as an internal wakeup source starting from 1. + * @param enable An enable or a disable setting + */ +static inline void LLWU_EnableInternalModuleInterruptWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) +{ + if (enable) + { + base->ME |= 1U << moduleIndex; + } + else + { + base->ME &= ~(1U << moduleIndex); + } +} + +/*! + * @brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the system is + * woken up by the specific pin. + * + * @param base LLWU peripheral base address. + * @param moduleIndex A module index, which starts from 1. + * @return True if the specific pin is a wake up source. + */ +static inline bool LLWU_GetInternalWakeupModuleFlag(LLWU_Type *base, uint32_t moduleIndex) +{ +#if (defined(FSL_FEATURE_LLWU_HAS_MF) && FSL_FEATURE_LLWU_HAS_MF) +#if (defined(FSL_FEATURE_LLWU_REG_BITWIDTH) && (FSL_FEATURE_LLWU_REG_BITWIDTH == 32)) + return (bool)(base->MF & (1U << moduleIndex)); +#else + return (bool)(base->MF5 & (1U << moduleIndex)); +#endif /* FSL_FEATURE_LLWU_REG_BITWIDTH */ +#else +#if (defined(FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN) && (FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN > 16)) + return (bool)(base->F5 & (1U << moduleIndex)); +#else +#if (defined(FSL_FEATURE_LLWU_HAS_PF) && FSL_FEATURE_LLWU_HAS_PF) + return (bool)(base->PF3 & (1U << moduleIndex)); +#else + return (bool)(base->F3 & (1U << moduleIndex)); +#endif /* FSL_FEATURE_LLWU_HAS_PF */ +#endif /* FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN */ +#endif /* FSL_FEATURE_LLWU_HAS_MF */ +} +#endif /* FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE */ + +#if (defined(FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) && FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG) +/*! + * @brief Enables/disables the internal module DMA wakeup source. + * + * This function enables/disables the internal DMA that is used as a wake up source. + * + * @param base LLWU peripheral base address. + * @param moduleIndex An internal module index which is used as a DMA request source, starting from 1. + * @param enable Enable or disable the DMA request source + */ +static inline void LLWU_EnableInternalModuleDmaRequestWakup(LLWU_Type *base, uint32_t moduleIndex, bool enable) +{ + if (enable) + { + base->DE |= 1U << moduleIndex; + } + else + { + base->DE &= ~(1U << moduleIndex); + } +} +#endif /* FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG */ + +#if (defined(FSL_FEATURE_LLWU_HAS_PIN_FILTER) && FSL_FEATURE_LLWU_HAS_PIN_FILTER) +/*! + * @brief Sets the pin filter configuration. + * + * This function sets the pin filter configuration. + * + * @param base LLWU peripheral base address. + * @param filterIndex A pin filter index used to enable/disable the digital filter, starting from 1. + * @param filterMode A filter mode configuration + */ +void LLWU_SetPinFilterMode(LLWU_Type *base, uint32_t filterIndex, llwu_external_pin_filter_mode_t filterMode); + +/*! + * @brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * @param base LLWU peripheral base address. + * @param filterIndex A pin filter index, which starts from 1. + * @return True if the flag is a source of the existing low-leakage power mode. + */ +bool LLWU_GetPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); + +/*! + * @brief Clears the pin filter configuration. + * + * This function clears the pin filter flag. + * + * @param base LLWU peripheral base address. + * @param filterIndex A pin filter index to clear the flag, starting from 1. + */ +void LLWU_ClearPinFilterFlag(LLWU_Type *base, uint32_t filterIndex); + +#endif /* FSL_FEATURE_LLWU_HAS_PIN_FILTER */ + +#if (defined(FSL_FEATURE_LLWU_HAS_RESET_ENABLE) && FSL_FEATURE_LLWU_HAS_RESET_ENABLE) +/*! + * @brief Sets the reset pin mode. + * + * This function determines how the reset pin is used as a low leakage mode exit source. + * + * @param pinEnable Enable reset the pin filter + * @param pinFilterEnable Specify whether the pin filter is enabled in Low-Leakage power mode. + */ +void LLWU_SetResetPinMode(LLWU_Type *base, bool pinEnable, bool enableInLowLeakageMode); +#endif /* FSL_FEATURE_LLWU_HAS_RESET_ENABLE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ +#endif /* _FSL_LLWU_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_lptmr.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_lptmr.c new file mode 100644 index 00000000000..67b3b9785cf --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_lptmr.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_lptmr.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base LPTMR peripheral base address + * + * @return The LPTMR instance + */ +static uint32_t LPTMR_GetInstance(LPTMR_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to LPTMR bases for each instance. */ +static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to LPTMR clocks for each instance. */ +static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS; + +#if defined(LPTMR_PERIPH_CLOCKS) +/* Array of LPTMR functional clock name. */ +static const clock_ip_name_t s_lptmrPeriphClocks[] = LPTMR_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t LPTMR_GetInstance(LPTMR_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_lptmrBases); instance++) + { + if (s_lptmrBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lptmrBases)); + + return instance; +} + +void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPTMR_GetInstance(base); + + /* Ungate the LPTMR clock*/ + CLOCK_EnableClock(s_lptmrClocks[instance]); +#if defined(LPTMR_PERIPH_CLOCKS) + CLOCK_EnableClock(s_lptmrPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure the timers operation mode and input pin setup */ + base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) | + LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect)); + + /* Configure the prescale value and clock source */ + base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) | + LPTMR_PSR_PCS(config->prescalerClockSource)); +} + +void LPTMR_Deinit(LPTMR_Type *base) +{ + /* Disable the LPTMR and reset the internal logic */ + base->CSR &= ~LPTMR_CSR_TEN_MASK; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPTMR_GetInstance(base); + + /* Gate the LPTMR clock*/ + CLOCK_DisableClock(s_lptmrClocks[instance]); +#if defined(LPTMR_PERIPH_CLOCKS) + CLOCK_DisableClock(s_lptmrPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void LPTMR_GetDefaultConfig(lptmr_config_t *config) +{ + assert(config); + + /* Use time counter mode */ + config->timerMode = kLPTMR_TimerModeTimeCounter; + /* Use input 0 as source in pulse counter mode */ + config->pinSelect = kLPTMR_PinSelectInput_0; + /* Pulse input pin polarity is active-high */ + config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + /* Counter resets whenever TCF flag is set */ + config->enableFreeRunning = false; + /* Bypass the prescaler */ + config->bypassPrescaler = true; + /* LPTMR clock source */ + config->prescalerClockSource = kLPTMR_PrescalerClock_1; + /* Divide the prescaler clock by 2 */ + config->value = kLPTMR_Prescale_Glitch_0; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_lptmr.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_lptmr.h new file mode 100644 index 00000000000..6cc909b3148 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_lptmr.h @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_LPTMR_H_ +#define _FSL_LPTMR_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lptmr + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ +/*@}*/ + +/*! @brief LPTMR pin selection used in pulse counter mode.*/ +typedef enum _lptmr_pin_select +{ + kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */ + kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */ + kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */ + kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */ +} lptmr_pin_select_t; + +/*! @brief LPTMR pin polarity used in pulse counter mode.*/ +typedef enum _lptmr_pin_polarity +{ + kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */ + kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */ +} lptmr_pin_polarity_t; + +/*! @brief LPTMR timer mode selection.*/ +typedef enum _lptmr_timer_mode +{ + kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */ + kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */ +} lptmr_timer_mode_t; + +/*! @brief LPTMR prescaler/glitch filter values*/ +typedef enum _lptmr_prescaler_glitch_value +{ + kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */ + kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */ + kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */ + kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */ + kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */ + kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */ + kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */ + kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */ + kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */ + kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/ + kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */ + kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */ + kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */ + kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */ + kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */ + kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */ +} lptmr_prescaler_glitch_value_t; + +/*! + * @brief LPTMR prescaler/glitch filter clock select. + * @note Clock connections are SoC-specific + */ +typedef enum _lptmr_prescaler_clock_select +{ + kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */ + kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */ + kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */ + kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */ +} lptmr_prescaler_clock_select_t; + +/*! @brief List of the LPTMR interrupts */ +typedef enum _lptmr_interrupt_enable +{ + kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */ +} lptmr_interrupt_enable_t; + +/*! @brief List of the LPTMR status flags */ +typedef enum _lptmr_status_flags +{ + kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */ +} lptmr_status_flags_t; + +/*! + * @brief LPTMR config structure + * + * This structure holds the configuration settings for the LPTMR peripheral. To initialize this + * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a + * pointer to your configuration structure instance. + * + * The configuration struct can be made constant so it resides in flash. + */ +typedef struct _lptmr_config +{ + lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */ + lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */ + lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */ + bool enableFreeRunning; /*!< True: enable free running, counter is reset on overflow + False: counter is reset when the compare flag is set */ + bool bypassPrescaler; /*!< True: bypass prescaler; false: use clock from prescaler */ + lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */ + lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */ +} lptmr_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the LPTMR clock and configures the peripheral for a basic operation. + * + * @note This API should be called at the beginning of the application using the LPTMR driver. + * + * @param base LPTMR peripheral base address + * @param config A pointer to the LPTMR configuration structure. + */ +void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config); + +/*! + * @brief Gates the LPTMR clock. + * + * @param base LPTMR peripheral base address + */ +void LPTMR_Deinit(LPTMR_Type *base); + +/*! + * @brief Fills in the LPTMR configuration structure with default settings. + * + * The default values are as follows. + * @code + * config->timerMode = kLPTMR_TimerModeTimeCounter; + * config->pinSelect = kLPTMR_PinSelectInput_0; + * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + * config->enableFreeRunning = false; + * config->bypassPrescaler = true; + * config->prescalerClockSource = kLPTMR_PrescalerClock_1; + * config->value = kLPTMR_Prescale_Glitch_0; + * @endcode + * @param config A pointer to the LPTMR configuration structure. + */ +void LPTMR_GetDefaultConfig(lptmr_config_t *config); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask) +{ + uint32_t reg = base->CSR; + + /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ + reg &= ~(LPTMR_CSR_TCF_MASK); + reg |= mask; + base->CSR = reg; +} + +/*! + * @brief Disables the selected LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t. + */ +static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask) +{ + uint32_t reg = base->CSR; + + /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ + reg &= ~(LPTMR_CSR_TCF_MASK); + reg &= ~mask; + base->CSR = reg; +} + +/*! + * @brief Gets the enabled LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base) +{ + return (base->CSR & LPTMR_CSR_TIE_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the LPTMR status flags. + * + * @param base LPTMR peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::lptmr_status_flags_t + */ +static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base) +{ + return (base->CSR & LPTMR_CSR_TCF_MASK); +} + +/*! + * @brief Clears the LPTMR status flags. + * + * @param base LPTMR peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::lptmr_status_flags_t. + */ +static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask) +{ + base->CSR |= mask; +} + +/*! @}*/ + +/*! + * @name Read and write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers counts from 0 until it equals the count value set here. The count value is written to + * the CMR register. + * + * @note + * 1. The TCF flag is set with the CNR equals the count provided here and then increments. + * 2. Call the utility macros provided in the fsl_common.h to convert to ticks. + * + * @param base LPTMR peripheral base address + * @param ticks A timer period in units of ticks, which should be equal or greater than 1. + */ +static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks) +{ + assert(ticks > 0); + base->CMR = ticks - 1; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value in a range from 0 to a + * timer period. + * + * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec. + * + * @param base LPTMR peripheral base address + * + * @return The current counter value in ticks + */ +static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base) +{ + /* Must first write any value to the CNR. This synchronizes and registers the current value + * of the CNR into a temporary register which can then be read + */ + base->CNR = 0U; + return (uint32_t)((base->CNR & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT); +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer. + * + * After calling this function, the timer counts up to the CMR register value. + * Each time the timer reaches the CMR value and then increments, it generates a + * trigger pulse and sets the timeout interrupt flag. An interrupt is also + * triggered if the timer interrupt is enabled. + * + * @param base LPTMR peripheral base address + */ +static inline void LPTMR_StartTimer(LPTMR_Type *base) +{ + uint32_t reg = base->CSR; + + /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */ + reg &= ~(LPTMR_CSR_TCF_MASK); + reg |= LPTMR_CSR_TEN_MASK; + base->CSR = reg; +} + +/*! + * @brief Stops the timer. + * + * This function stops the timer and resets the timer's counter register. + * + * @param base LPTMR peripheral base address + */ +static inline void LPTMR_StopTimer(LPTMR_Type *base) +{ + uint32_t reg = base->CSR; + + /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */ + reg &= ~(LPTMR_CSR_TCF_MASK); + reg &= ~LPTMR_CSR_TEN_MASK; + base->CSR = reg; +} + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPTMR_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pdb.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pdb.c new file mode 100644 index 00000000000..1fc4a9a486a --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pdb.c @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pdb.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for PDB module. + * + * @param base PDB peripheral base address + */ +static uint32_t PDB_GetInstance(PDB_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PDB bases for each instance. */ +static PDB_Type *const s_pdbBases[] = PDB_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to PDB clocks for each instance. */ +static const clock_ip_name_t s_pdbClocks[] = PDB_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t PDB_GetInstance(PDB_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_pdbBases); instance++) + { + if (s_pdbBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_pdbBases)); + + return instance; +} + +void PDB_Init(PDB_Type *base, const pdb_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_pdbClocks[PDB_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure. */ + /* PDBx_SC. */ + tmp32 = base->SC & + ~(PDB_SC_LDMOD_MASK | PDB_SC_PRESCALER_MASK | PDB_SC_TRGSEL_MASK | PDB_SC_MULT_MASK | PDB_SC_CONT_MASK); + + tmp32 |= PDB_SC_LDMOD(config->loadValueMode) | PDB_SC_PRESCALER(config->prescalerDivider) | + PDB_SC_TRGSEL(config->triggerInputSource) | PDB_SC_MULT(config->dividerMultiplicationFactor); + if (config->enableContinuousMode) + { + tmp32 |= PDB_SC_CONT_MASK; + } + base->SC = tmp32; + + PDB_Enable(base, true); /* Enable the PDB module. */ +} + +void PDB_Deinit(PDB_Type *base) +{ + PDB_Enable(base, false); /* Disable the PDB module. */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_pdbClocks[PDB_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void PDB_GetDefaultConfig(pdb_config_t *config) +{ + assert(NULL != config); + + config->loadValueMode = kPDB_LoadValueImmediately; + config->prescalerDivider = kPDB_PrescalerDivider1; + config->dividerMultiplicationFactor = kPDB_DividerMultiplicationFactor1; + config->triggerInputSource = kPDB_TriggerSoftware; + config->enableContinuousMode = false; +} + +#if defined(FSL_FEATURE_PDB_HAS_DAC) && FSL_FEATURE_PDB_HAS_DAC +void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config) +{ + assert(channel < PDB_INTC_COUNT); + assert(NULL != config); + + uint32_t tmp32 = 0U; + + /* PDBx_DACINTC. */ + if (config->enableExternalTriggerInput) + { + tmp32 |= PDB_INTC_EXT_MASK; + } + if (config->enableIntervalTrigger) + { + tmp32 |= PDB_INTC_TOE_MASK; + } + base->DAC[channel].INTC = tmp32; +} +#endif /* FSL_FEATURE_PDB_HAS_DAC */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pdb.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pdb.h new file mode 100644 index 00000000000..3dec9463462 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pdb.h @@ -0,0 +1,576 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_PDB_H_ +#define _FSL_PDB_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pdb + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PDB driver version 2.0.1. */ +#define FSL_PDB_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief PDB flags. + */ +enum _pdb_status_flags +{ + kPDB_LoadOKFlag = PDB_SC_LDOK_MASK, /*!< This flag is automatically cleared when the values in buffers are + loaded into the internal registers after the LDOK bit is set or the + PDBEN is cleared. */ + kPDB_DelayEventFlag = PDB_SC_PDBIF_MASK, /*!< PDB timer delay event flag. */ +}; + +/*! + * @brief PDB ADC PreTrigger channel flags. + */ +enum _pdb_adc_pretrigger_flags +{ + /* PDB PreTrigger channel match flags. */ + kPDB_ADCPreTriggerChannel0Flag = PDB_S_CF(1U << 0), /*!< Pre-trigger 0 flag. */ + kPDB_ADCPreTriggerChannel1Flag = PDB_S_CF(1U << 1), /*!< Pre-trigger 1 flag. */ +#if (PDB_DLY_COUNT2 > 2) + kPDB_ADCPreTriggerChannel2Flag = PDB_S_CF(1U << 2), /*!< Pre-trigger 2 flag. */ + kPDB_ADCPreTriggerChannel3Flag = PDB_S_CF(1U << 3), /*!< Pre-trigger 3 flag. */ +#endif /* PDB_DLY_COUNT2 > 2 */ +#if (PDB_DLY_COUNT2 > 4) + kPDB_ADCPreTriggerChannel4Flag = PDB_S_CF(1U << 4), /*!< Pre-trigger 4 flag. */ + kPDB_ADCPreTriggerChannel5Flag = PDB_S_CF(1U << 5), /*!< Pre-trigger 5 flag. */ + kPDB_ADCPreTriggerChannel6Flag = PDB_S_CF(1U << 6), /*!< Pre-trigger 6 flag. */ + kPDB_ADCPreTriggerChannel7Flag = PDB_S_CF(1U << 7), /*!< Pre-trigger 7 flag. */ +#endif /* PDB_DLY_COUNT2 > 4 */ + + /* PDB PreTrigger channel error flags. */ + kPDB_ADCPreTriggerChannel0ErrorFlag = PDB_S_ERR(1U << 0), /*!< Pre-trigger 0 Error. */ + kPDB_ADCPreTriggerChannel1ErrorFlag = PDB_S_ERR(1U << 1), /*!< Pre-trigger 1 Error. */ +#if (PDB_DLY_COUNT2 > 2) + kPDB_ADCPreTriggerChannel2ErrorFlag = PDB_S_ERR(1U << 2), /*!< Pre-trigger 2 Error. */ + kPDB_ADCPreTriggerChannel3ErrorFlag = PDB_S_ERR(1U << 3), /*!< Pre-trigger 3 Error. */ +#endif /* PDB_DLY_COUNT2 > 2 */ +#if (PDB_DLY_COUNT2 > 4) + kPDB_ADCPreTriggerChannel4ErrorFlag = PDB_S_ERR(1U << 4), /*!< Pre-trigger 4 Error. */ + kPDB_ADCPreTriggerChannel5ErrorFlag = PDB_S_ERR(1U << 5), /*!< Pre-trigger 5 Error. */ + kPDB_ADCPreTriggerChannel6ErrorFlag = PDB_S_ERR(1U << 6), /*!< Pre-trigger 6 Error. */ + kPDB_ADCPreTriggerChannel7ErrorFlag = PDB_S_ERR(1U << 7), /*!< Pre-trigger 7 Error. */ +#endif /* PDB_DLY_COUNT2 > 4 */ +}; + +/*! + * @brief PDB buffer interrupts. + */ +enum _pdb_interrupt_enable +{ + kPDB_SequenceErrorInterruptEnable = PDB_SC_PDBEIE_MASK, /*!< PDB sequence error interrupt enable. */ + kPDB_DelayInterruptEnable = PDB_SC_PDBIE_MASK, /*!< PDB delay interrupt enable. */ +}; + +/*! + * @brief PDB load value mode. + * + * Selects the mode to load the internal values after doing the load operation (write 1 to PDBx_SC[LDOK]). + * These values are for the following operations. + * - PDB counter (PDBx_MOD, PDBx_IDLY) + * - ADC trigger (PDBx_CHnDLYm) + * - DAC trigger (PDBx_DACINTx) + * - CMP trigger (PDBx_POyDLY) + */ +typedef enum _pdb_load_value_mode +{ + kPDB_LoadValueImmediately = 0U, /*!< Load immediately after 1 is written to LDOK. */ + kPDB_LoadValueOnCounterOverflow = 1U, /*!< Load when the PDB counter overflows (reaches the MOD + register value). */ + kPDB_LoadValueOnTriggerInput = 2U, /*!< Load a trigger input event is detected. */ + kPDB_LoadValueOnCounterOverflowOrTriggerInput = 3U, /*!< Load either when the PDB counter overflows or a trigger + input is detected. */ +} pdb_load_value_mode_t; + +/*! + * @brief Prescaler divider. + * + * Counting uses the peripheral clock divided by multiplication factor selected by times of MULT. + */ +typedef enum _pdb_prescaler_divider +{ + kPDB_PrescalerDivider1 = 0U, /*!< Divider x1. */ + kPDB_PrescalerDivider2 = 1U, /*!< Divider x2. */ + kPDB_PrescalerDivider4 = 2U, /*!< Divider x4. */ + kPDB_PrescalerDivider8 = 3U, /*!< Divider x8. */ + kPDB_PrescalerDivider16 = 4U, /*!< Divider x16. */ + kPDB_PrescalerDivider32 = 5U, /*!< Divider x32. */ + kPDB_PrescalerDivider64 = 6U, /*!< Divider x64. */ + kPDB_PrescalerDivider128 = 7U, /*!< Divider x128. */ +} pdb_prescaler_divider_t; + +/*! + * @brief Multiplication factor select for prescaler. + * + * Selects the multiplication factor of the prescaler divider for the counter clock. + */ +typedef enum _pdb_divider_multiplication_factor +{ + kPDB_DividerMultiplicationFactor1 = 0U, /*!< Multiplication factor is 1. */ + kPDB_DividerMultiplicationFactor10 = 1U, /*!< Multiplication factor is 10. */ + kPDB_DividerMultiplicationFactor20 = 2U, /*!< Multiplication factor is 20. */ + kPDB_DividerMultiplicationFactor40 = 3U, /*!< Multiplication factor is 40. */ +} pdb_divider_multiplication_factor_t; + +/*! + * @brief Trigger input source + * + * Selects the trigger input source for the PDB. The trigger input source can be internal or external (EXTRG pin), or + * the software trigger. See chip configuration details for the actual PDB input trigger connections. + */ +typedef enum _pdb_trigger_input_source +{ + kPDB_TriggerInput0 = 0U, /*!< Trigger-In 0. */ + kPDB_TriggerInput1 = 1U, /*!< Trigger-In 1. */ + kPDB_TriggerInput2 = 2U, /*!< Trigger-In 2. */ + kPDB_TriggerInput3 = 3U, /*!< Trigger-In 3. */ + kPDB_TriggerInput4 = 4U, /*!< Trigger-In 4. */ + kPDB_TriggerInput5 = 5U, /*!< Trigger-In 5. */ + kPDB_TriggerInput6 = 6U, /*!< Trigger-In 6. */ + kPDB_TriggerInput7 = 7U, /*!< Trigger-In 7. */ + kPDB_TriggerInput8 = 8U, /*!< Trigger-In 8. */ + kPDB_TriggerInput9 = 9U, /*!< Trigger-In 9. */ + kPDB_TriggerInput10 = 10U, /*!< Trigger-In 10. */ + kPDB_TriggerInput11 = 11U, /*!< Trigger-In 11. */ + kPDB_TriggerInput12 = 12U, /*!< Trigger-In 12. */ + kPDB_TriggerInput13 = 13U, /*!< Trigger-In 13. */ + kPDB_TriggerInput14 = 14U, /*!< Trigger-In 14. */ + kPDB_TriggerSoftware = 15U, /*!< Trigger-In 15, software trigger. */ +} pdb_trigger_input_source_t; + +/*! + * @brief PDB module configuration. + */ +typedef struct _pdb_config +{ + pdb_load_value_mode_t loadValueMode; /*!< Select the load value mode. */ + pdb_prescaler_divider_t prescalerDivider; /*!< Select the prescaler divider. */ + pdb_divider_multiplication_factor_t dividerMultiplicationFactor; /*!< Multiplication factor select for prescaler. */ + pdb_trigger_input_source_t triggerInputSource; /*!< Select the trigger input source. */ + bool enableContinuousMode; /*!< Enable the PDB operation in Continuous mode.*/ +} pdb_config_t; + +/*! + * @brief PDB ADC Pre-trigger configuration. + */ +typedef struct _pdb_adc_pretrigger_config +{ + uint32_t enablePreTriggerMask; /*!< PDB Channel Pre-trigger Enable. */ + uint32_t enableOutputMask; /*!< PDB Channel Pre-trigger Output Select. + PDB channel's corresponding pre-trigger asserts when the counter + reaches the channel delay register. */ + uint32_t enableBackToBackOperationMask; /*!< PDB Channel pre-trigger Back-to-Back Operation Enable. + Back-to-back operation enables the ADC conversions complete to trigger + the next PDB channel pre-trigger and trigger output, so that the ADC + conversions can be triggered on next set of configuration and results + registers.*/ +} pdb_adc_pretrigger_config_t; + +/*! + * @brief PDB DAC trigger configuration. + */ +typedef struct _pdb_dac_trigger_config +{ + bool enableExternalTriggerInput; /*!< Enables the external trigger for DAC interval counter. */ + bool enableIntervalTrigger; /*!< Enables the DAC interval trigger. */ +} pdb_dac_trigger_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the PDB module. + * + * This function initializes the PDB module. The operations included are as follows. + * - Enable the clock for PDB instance. + * - Configure the PDB module. + * - Enable the PDB module. + * + * @param base PDB peripheral base address. + * @param config Pointer to the configuration structure. See "pdb_config_t". + */ +void PDB_Init(PDB_Type *base, const pdb_config_t *config); + +/*! + * @brief De-initializes the PDB module. + * + * @param base PDB peripheral base address. + */ +void PDB_Deinit(PDB_Type *base); + +/*! + * @brief Initializes the PDB user configuration structure. + * + * This function initializes the user configuration structure to a default value. The default values are as follows. + * @code + * config->loadValueMode = kPDB_LoadValueImmediately; + * config->prescalerDivider = kPDB_PrescalerDivider1; + * config->dividerMultiplicationFactor = kPDB_DividerMultiplicationFactor1; + * config->triggerInputSource = kPDB_TriggerSoftware; + * config->enableContinuousMode = false; + * @endcode + * @param config Pointer to configuration structure. See "pdb_config_t". + */ +void PDB_GetDefaultConfig(pdb_config_t *config); + +/*! + * @brief Enables the PDB module. + * + * @param base PDB peripheral base address. + * @param enable Enable the module or not. + */ +static inline void PDB_Enable(PDB_Type *base, bool enable) +{ + if (enable) + { + base->SC |= PDB_SC_PDBEN_MASK; + } + else + { + base->SC &= ~PDB_SC_PDBEN_MASK; + } +} + +/* @} */ + +/*! + * @name Basic Counter + * @{ + */ + +/*! + * @brief Triggers the PDB counter by software. + * + * @param base PDB peripheral base address. + */ +static inline void PDB_DoSoftwareTrigger(PDB_Type *base) +{ + base->SC |= PDB_SC_SWTRIG_MASK; +} + +/*! + * @brief Loads the counter values. + * + * This function loads the counter values from the internal buffer. + * See "pdb_load_value_mode_t" about PDB's load mode. + * + * @param base PDB peripheral base address. + */ +static inline void PDB_DoLoadValues(PDB_Type *base) +{ + base->SC |= PDB_SC_LDOK_MASK; +} + +/*! + * @brief Enables the DMA for the PDB module. + * + * @param base PDB peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PDB_EnableDMA(PDB_Type *base, bool enable) +{ + if (enable) + { + base->SC |= PDB_SC_DMAEN_MASK; + } + else + { + base->SC &= ~PDB_SC_DMAEN_MASK; + } +} + +/*! + * @brief Enables the interrupts for the PDB module. + * + * @param base PDB peripheral base address. + * @param mask Mask value for interrupts. See "_pdb_interrupt_enable". + */ +static inline void PDB_EnableInterrupts(PDB_Type *base, uint32_t mask) +{ + assert(0U == (mask & ~(PDB_SC_PDBEIE_MASK | PDB_SC_PDBIE_MASK))); + + base->SC |= mask; +} + +/*! + * @brief Disables the interrupts for the PDB module. + * + * @param base PDB peripheral base address. + * @param mask Mask value for interrupts. See "_pdb_interrupt_enable". + */ +static inline void PDB_DisableInterrupts(PDB_Type *base, uint32_t mask) +{ + assert(0U == (mask & ~(PDB_SC_PDBEIE_MASK | PDB_SC_PDBIE_MASK))); + + base->SC &= ~mask; +} + +/*! + * @brief Gets the status flags of the PDB module. + * + * @param base PDB peripheral base address. + * + * @return Mask value for asserted flags. See "_pdb_status_flags". + */ +static inline uint32_t PDB_GetStatusFlags(PDB_Type *base) +{ + return base->SC & (PDB_SC_PDBIF_MASK | PDB_SC_LDOK_MASK); +} + +/*! + * @brief Clears the status flags of the PDB module. + * + * @param base PDB peripheral base address. + * @param mask Mask value of flags. See "_pdb_status_flags". + */ +static inline void PDB_ClearStatusFlags(PDB_Type *base, uint32_t mask) +{ + assert(0U == (mask & ~PDB_SC_PDBIF_MASK)); + + base->SC &= ~mask; +} + +/*! + * @brief Specifies the counter period. + * + * @param base PDB peripheral base address. + * @param value Setting value for the modulus. 16-bit is available. + */ +static inline void PDB_SetModulusValue(PDB_Type *base, uint32_t value) +{ + base->MOD = PDB_MOD_MOD(value); +} + +/*! + * @brief Gets the PDB counter's current value. + * + * @param base PDB peripheral base address. + * + * @return PDB counter's current value. + */ +static inline uint32_t PDB_GetCounterValue(PDB_Type *base) +{ + return base->CNT; +} + +/*! + * @brief Sets the value for the PDB counter delay event. + * + * @param base PDB peripheral base address. + * @param value Setting value for PDB counter delay event. 16-bit is available. + */ +static inline void PDB_SetCounterDelayValue(PDB_Type *base, uint32_t value) +{ + base->IDLY = PDB_IDLY_IDLY(value); +} +/* @} */ + +/*! + * @name ADC Pre-trigger + * @{ + */ + +/*! + * @brief Configures the ADC pre-trigger in the PDB module. + * + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * @param config Pointer to the configuration structure. See "pdb_adc_pretrigger_config_t". + */ +static inline void PDB_SetADCPreTriggerConfig(PDB_Type *base, uint32_t channel, pdb_adc_pretrigger_config_t *config) +{ + assert(channel < PDB_C1_COUNT); + assert(NULL != config); + + base->CH[channel].C1 = PDB_C1_BB(config->enableBackToBackOperationMask) | PDB_C1_TOS(config->enableOutputMask) | + PDB_C1_EN(config->enablePreTriggerMask); +} + +/*! + * @brief Sets the value for the ADC pre-trigger delay event. + * + * This function sets the value for ADC pre-trigger delay event. It specifies the delay value for the channel's + * corresponding pre-trigger. The pre-trigger asserts when the PDB counter is equal to the set value. + * + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * @param preChannel Channel group index for ADC instance. + * @param value Setting value for ADC pre-trigger delay event. 16-bit is available. + */ +static inline void PDB_SetADCPreTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t preChannel, uint32_t value) +{ + assert(channel < PDB_C1_COUNT); + assert(preChannel < PDB_DLY_COUNT2); + /* xx_COUNT2 is actually the count for pre-triggers in header file. xx_COUNT is used for the count of channels. */ + + base->CH[channel].DLY[preChannel] = PDB_DLY_DLY(value); +} + +/*! + * @brief Gets the ADC pre-trigger's status flags. + * + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * + * @return Mask value for asserted flags. See "_pdb_adc_pretrigger_flags". + */ +static inline uint32_t PDB_GetADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel) +{ + assert(channel < PDB_C1_COUNT); + + return base->CH[channel].S; +} + +/*! + * @brief Clears the ADC pre-trigger status flags. + * + * @param base PDB peripheral base address. + * @param channel Channel index for ADC instance. + * @param mask Mask value for flags. See "_pdb_adc_pretrigger_flags". + */ +static inline void PDB_ClearADCPreTriggerStatusFlags(PDB_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < PDB_C1_COUNT); + + base->CH[channel].S &= ~mask; +} + +/* @} */ + +#if defined(FSL_FEATURE_PDB_HAS_DAC) && FSL_FEATURE_PDB_HAS_DAC +/*! + * @name DAC Interval Trigger + * @{ + */ + +/*! + * @brief Configures the DAC trigger in the PDB module. + * + * @param base PDB peripheral base address. + * @param channel Channel index for DAC instance. + * @param config Pointer to the configuration structure. See "pdb_dac_trigger_config_t". + */ +void PDB_SetDACTriggerConfig(PDB_Type *base, uint32_t channel, pdb_dac_trigger_config_t *config); + +/*! + * @brief Sets the value for the DAC interval event. + * + * This fucntion sets the value for DAC interval event. DAC interval trigger triggers the DAC module to update + * the buffer when the DAC interval counter is equal to the set value. + * + * @param base PDB peripheral base address. + * @param channel Channel index for DAC instance. + * @param value Setting value for the DAC interval event. + */ +static inline void PDB_SetDACTriggerIntervalValue(PDB_Type *base, uint32_t channel, uint32_t value) +{ + assert(channel < PDB_INT_COUNT); + + base->DAC[channel].INT = PDB_INT_INT(value); +} + +/* @} */ +#endif /* FSL_FEATURE_PDB_HAS_DAC */ + +/*! + * @name Pulse-Out Trigger + * @{ + */ + +/*! + * @brief Enables the pulse out trigger channels. + * + * @param base PDB peripheral base address. + * @param channelMask Channel mask value for multiple pulse out trigger channel. + * @param enable Whether the feature is enabled or not. + */ +static inline void PDB_EnablePulseOutTrigger(PDB_Type *base, uint32_t channelMask, bool enable) +{ + if (enable) + { + base->POEN |= PDB_POEN_POEN(channelMask); + } + else + { + base->POEN &= ~(PDB_POEN_POEN(channelMask)); + } +} + +/*! + * @brief Sets event values for the pulse out trigger. + * + * This function is used to set event values for the pulse output trigger. + * These pulse output trigger delay values specify the delay for the PDB Pulse-out. Pulse-out goes high when the PDB + * counter is equal to the pulse output high value (value1). Pulse-out goes low when the PDB counter is equal to the + * pulse output low value (value2). + * + * @param base PDB peripheral base address. + * @param channel Channel index for pulse out trigger channel. + * @param value1 Setting value for pulse out high. + * @param value2 Setting value for pulse out low. + */ +static inline void PDB_SetPulseOutTriggerDelayValue(PDB_Type *base, uint32_t channel, uint32_t value1, uint32_t value2) +{ + assert(channel < PDB_PODLY_COUNT); + + base->PODLY[channel] = PDB_PODLY_DLY1(value1) | PDB_PODLY_DLY2(value2); +} + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_PDB_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pit.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pit.c new file mode 100644 index 00000000000..e5c3c4e013d --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pit.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_pit.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base PIT peripheral base address + * + * @return The PIT instance + */ +static uint32_t PIT_GetInstance(PIT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PIT bases for each instance. */ +static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to PIT clocks for each instance. */ +static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t PIT_GetInstance(PIT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++) + { + if (s_pitBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_pitBases)); + + return instance; +} + +void PIT_Init(PIT_Type *base, const pit_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the PIT clock*/ + CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Enable PIT timers */ + base->MCR &= ~PIT_MCR_MDIS_MASK; + + /* Config timer operation when in debug mode */ + if (config->enableRunInDebug) + { + base->MCR &= ~PIT_MCR_FRZ_MASK; + } + else + { + base->MCR |= PIT_MCR_FRZ_MASK; + } +} + +void PIT_Deinit(PIT_Type *base) +{ + /* Disable PIT timers */ + base->MCR |= PIT_MCR_MDIS_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the PIT clock*/ + CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER + +uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base) +{ + uint32_t valueH = 0U; + uint32_t valueL = 0U; + + /* LTMR64H should be read before LTMR64L */ + valueH = base->LTMR64H; + valueL = base->LTMR64L; + + return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); +} + +#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pit.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pit.h new file mode 100644 index 00000000000..99c30e1e4bc --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pit.h @@ -0,0 +1,354 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PIT_H_ +#define _FSL_PIT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pit + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! + * @brief List of PIT channels + * @note Actual number of available channels is SoC dependent + */ +typedef enum _pit_chnl +{ + kPIT_Chnl_0 = 0U, /*!< PIT channel number 0*/ + kPIT_Chnl_1, /*!< PIT channel number 1 */ + kPIT_Chnl_2, /*!< PIT channel number 2 */ + kPIT_Chnl_3, /*!< PIT channel number 3 */ +} pit_chnl_t; + +/*! @brief List of PIT interrupts */ +typedef enum _pit_interrupt_enable +{ + kPIT_TimerInterruptEnable = PIT_TCTRL_TIE_MASK, /*!< Timer interrupt enable*/ +} pit_interrupt_enable_t; + +/*! @brief List of PIT status flags */ +typedef enum _pit_status_flags +{ + kPIT_TimerFlag = PIT_TFLG_TIF_MASK, /*!< Timer flag */ +} pit_status_flags_t; + +/*! + * @brief PIT configuration structure + * + * This structure holds the configuration settings for the PIT peripheral. To initialize this + * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _pit_config +{ + bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */ +} pit_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations. + * + * @note This API should be called at the beginning of the application using the PIT driver. + * + * @param base PIT peripheral base address + * @param config Pointer to the user's PIT config structure + */ +void PIT_Init(PIT_Type *base, const pit_config_t *config); + +/*! + * @brief Gates the PIT clock and disables the PIT module. + * + * @param base PIT peripheral base address + */ +void PIT_Deinit(PIT_Type *base); + +/*! + * @brief Fills in the PIT configuration structure with the default settings. + * + * The default values are as follows. + * @code + * config->enableRunInDebug = false; + * @endcode + * @param config Pointer to the onfiguration structure. + */ +static inline void PIT_GetDefaultConfig(pit_config_t *config) +{ + assert(config); + + /* Timers are stopped in Debug mode */ + config->enableRunInDebug = false; +} + +#if defined(FSL_FEATURE_PIT_HAS_CHAIN_MODE) && FSL_FEATURE_PIT_HAS_CHAIN_MODE + +/*! + * @brief Enables or disables chaining a timer with the previous timer. + * + * When a timer has a chain mode enabled, it only counts after the previous + * timer has expired. If the timer n-1 has counted down to 0, counter n + * decrements the value by one. Each timer is 32-bits, which allows the developers + * to chain timers together and form a longer timer (64-bits and larger). The first timer + * (timer 0) can't be chained to any other timer. + * + * @param base PIT peripheral base address + * @param channel Timer channel number which is chained with the previous timer + * @param enable Enable or disable chain. + * true: Current timer is chained with the previous timer. + * false: Timer doesn't chain with other timers. + */ +static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable) +{ + if (enable) + { + base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; + } + else + { + base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; + } +} + +#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */ + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TCTRL |= mask; +} + +/*! + * @brief Disables the selected PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TCTRL &= ~mask; +} + +/*! + * @brief Gets the enabled PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel) +{ + return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PIT status flags. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pit_status_flags_t + */ +static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel) +{ + return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK); +} + +/*! + * @brief Clears the PIT status flags. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pit_status_flags_t + */ +static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TFLG = mask; +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers begin counting from the value set by this function until it reaches 0, + * then it generates an interrupt and load this register value again. + * Writing a new value to this register does not restart the timer. Instead, the value + * is loaded after the timer expires. + * + * @note Users can call the utility macros provided in fsl_common.h to convert to ticks. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param count Timer period in units of ticks + */ +static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count) +{ + base->CHANNEL[channel].LDVAL = count; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return Current timer counting value in ticks + */ +static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel) +{ + return base->CHANNEL[channel].CVAL; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load period value, count down to 0 and + * then load the respective start value again. Each time a timer reaches 0, + * it generates a trigger pulse and sets the timeout interrupt flag. + * + * @param base PIT peripheral base address + * @param channel Timer channel number. + */ +static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel) +{ + base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops every timer counting. Timers reload their periods + * respectively after the next time they call the PIT_DRV_StartTimer. + * + * @param base PIT peripheral base address + * @param channel Timer channel number. + */ +static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel) +{ + base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; +} + +/*! @}*/ + +#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER + +/*! + * @brief Reads the current lifetime counter value. + * + * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. + * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. + * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1". + * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit + * has the value of timer 0. + * + * @param base PIT peripheral base address + * + * @return Current lifetime timer value + */ +uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base); + +#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PIT_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pmc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pmc.c new file mode 100644 index 00000000000..bcdd5cb8231 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pmc.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_pmc.h" + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +void PMC_GetParam(PMC_Type *base, pmc_param_t *param) +{ + uint32_t reg = base->PARAM; + ; + param->vlpoEnable = (bool)(reg & PMC_PARAM_VLPOE_MASK); + param->hvdEnable = (bool)(reg & PMC_PARAM_HVDE_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_PARAM */ + +void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config) +{ + base->LVDSC1 = (0U | +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) + ((uint32_t)config->voltSelect << PMC_LVDSC1_LVDV_SHIFT) | +#endif + ((uint32_t)config->enableInt << PMC_LVDSC1_LVDIE_SHIFT) | + ((uint32_t)config->enableReset << PMC_LVDSC1_LVDRE_SHIFT) + /* Clear the Low Voltage Detect Flag with previouse power detect setting */ + | PMC_LVDSC1_LVDACK_MASK); +} + +void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config) +{ + base->LVDSC2 = (0U | +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) + ((uint32_t)config->voltSelect << PMC_LVDSC2_LVWV_SHIFT) | +#endif + ((uint32_t)config->enableInt << PMC_LVDSC2_LVWIE_SHIFT) + /* Clear the Low Voltage Warning Flag with previouse power detect setting */ + | PMC_LVDSC2_LVWACK_MASK); +} + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config) +{ + base->HVDSC1 = (((uint32_t)config->voltSelect << PMC_HVDSC1_HVDV_SHIFT) | + ((uint32_t)config->enableInt << PMC_HVDSC1_HVDIE_SHIFT) | + ((uint32_t)config->enableReset << PMC_HVDSC1_HVDRE_SHIFT) + /* Clear the High Voltage Detect Flag with previouse power detect setting */ + | PMC_HVDSC1_HVDACK_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config) +{ + base->REGSC = (0U +#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) + | ((uint32_t)config->enable << PMC_REGSC_BGBE_SHIFT) +#endif /* FSL_FEATURE_PMC_HAS_BGBE */ +#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) + | (((uint32_t)config->enableInLowPowerMode << PMC_REGSC_BGEN_SHIFT)) +#endif /* FSL_FEATURE_PMC_HAS_BGEN */ +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) + | ((uint32_t)config->drive << PMC_REGSC_BGBDS_SHIFT) +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ + ); +} +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pmc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pmc.h new file mode 100644 index 00000000000..99fc149fc22 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_pmc.h @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PMC_H_ +#define _FSL_PMC_H_ + +#include "fsl_common.h" + +/*! @addtogroup pmc */ +/*! @{ */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PMC driver version */ +#define FSL_PMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) +/*! + * @brief Low-voltage Detect Voltage Select + */ +typedef enum _pmc_low_volt_detect_volt_select +{ + kPMC_LowVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VLVD = VLVDL )*/ + kPMC_LowVoltDetectHighTrip = 1U /*!< High-trip point selected (VLVD = VLVDH )*/ +} pmc_low_volt_detect_volt_select_t; +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) +/*! + * @brief Low-voltage Warning Voltage Select + */ +typedef enum _pmc_low_volt_warning_volt_select +{ + kPMC_LowVoltWarningLowTrip = 0U, /*!< Low-trip point selected (VLVW = VLVW1)*/ + kPMC_LowVoltWarningMid1Trip = 1U, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/ + kPMC_LowVoltWarningMid2Trip = 2U, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/ + kPMC_LowVoltWarningHighTrip = 3U /*!< High-trip point selected (VLVW = VLVW4)*/ +} pmc_low_volt_warning_volt_select_t; +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief High-voltage Detect Voltage Select + */ +typedef enum _pmc_high_volt_detect_volt_select +{ + kPMC_HighVoltDetectLowTrip = 0U, /*!< Low-trip point selected (VHVD = VHVDL )*/ + kPMC_HighVoltDetectHighTrip = 1U /*!< High-trip point selected (VHVD = VHVDH )*/ +} pmc_high_volt_detect_volt_select_t; +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) +/*! + * @brief Bandgap Buffer Drive Select. + */ +typedef enum _pmc_bandgap_buffer_drive_select +{ + kPMC_BandgapBufferDriveLow = 0U, /*!< Low-drive. */ + kPMC_BandgapBufferDriveHigh = 1U /*!< High-drive. */ +} pmc_bandgap_buffer_drive_select_t; +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ + +#if (defined(FSL_FEATURE_PMC_HAS_VLPO) && FSL_FEATURE_PMC_HAS_VLPO) +/*! + * @brief VLPx Option + */ +typedef enum _pmc_vlp_freq_option +{ + kPMC_FreqRestrict = 0U, /*!< Frequency is restricted in VLPx mode. */ + kPMC_FreqUnrestrict = 1U /*!< Frequency is unrestricted in VLPx mode. */ +} pmc_vlp_freq_mode_t; +#endif /* FSL_FEATURE_PMC_HAS_VLPO */ + +#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) +/*! + @brief IP version ID definition. + */ +typedef struct _pmc_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} pmc_version_id_t; +#endif /* FSL_FEATURE_PMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +/*! @brief IP parameter definition. */ +typedef struct _pmc_param +{ + bool vlpoEnable; /*!< VLPO enable. */ + bool hvdEnable; /*!< HVD enable. */ +} pmc_param_t; +#endif /* FSL_FEATURE_PMC_HAS_PARAM */ + +/*! + * @brief Low-voltage Detect Configuration Structure + */ +typedef struct _pmc_low_volt_detect_config +{ + bool enableInt; /*!< Enable interrupt when Low-voltage detect*/ + bool enableReset; /*!< Enable system reset when Low-voltage detect*/ +#if (defined(FSL_FEATURE_PMC_HAS_LVDV) && FSL_FEATURE_PMC_HAS_LVDV) + pmc_low_volt_detect_volt_select_t voltSelect; /*!< Low-voltage detect trip point voltage selection*/ +#endif +} pmc_low_volt_detect_config_t; + +/*! + * @brief Low-voltage Warning Configuration Structure + */ +typedef struct _pmc_low_volt_warning_config +{ + bool enableInt; /*!< Enable interrupt when low-voltage warning*/ +#if (defined(FSL_FEATURE_PMC_HAS_LVWV) && FSL_FEATURE_PMC_HAS_LVWV) + pmc_low_volt_warning_volt_select_t voltSelect; /*!< Low-voltage warning trip point voltage selection*/ +#endif +} pmc_low_volt_warning_config_t; + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief High-voltage Detect Configuration Structure + */ +typedef struct _pmc_high_volt_detect_config +{ + bool enableInt; /*!< Enable interrupt when high-voltage detect*/ + bool enableReset; /*!< Enable system reset when high-voltage detect*/ + pmc_high_volt_detect_volt_select_t voltSelect; /*!< High-voltage detect trip point voltage selection*/ +} pmc_high_volt_detect_config_t; +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +/*! + * @brief Bandgap Buffer configuration. + */ +typedef struct _pmc_bandgap_buffer_config +{ +#if (defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) + bool enable; /*!< Enable bandgap buffer. */ +#endif +#if (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) + bool enableInLowPowerMode; /*!< Enable bandgap buffer in low-power mode. */ +#endif /* FSL_FEATURE_PMC_HAS_BGEN */ +#if (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS) + pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select. */ +#endif /* FSL_FEATURE_PMC_HAS_BGBDS */ +} pmc_bandgap_buffer_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name Power Management Controller Control APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_PMC_HAS_VERID) && FSL_FEATURE_PMC_HAS_VERID) +/*! + * @brief Gets the PMC version ID. + * + * This function gets the PMC version ID, including major version number, + * minor version number, and a feature specification number. + * + * @param base PMC peripheral base address. + * @param versionId Pointer to version ID structure. + */ +static inline void PMC_GetVersionId(PMC_Type *base, pmc_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_PMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_PMC_HAS_PARAM) && FSL_FEATURE_PMC_HAS_PARAM) +/*! + * @brief Gets the PMC parameter. + * + * This function gets the PMC parameter including the VLPO enable and the HVD enable. + * + * @param base PMC peripheral base address. + * @param param Pointer to PMC param structure. + */ +void PMC_GetParam(PMC_Type *base, pmc_param_t *param); +#endif + +/*! + * @brief Configures the low-voltage detect setting. + * + * This function configures the low-voltage detect setting, including the trip + * point voltage setting, enables or disables the interrupt, enables or disables the system reset. + * + * @param base PMC peripheral base address. + * @param config Low-voltage detect configuration structure. + */ +void PMC_ConfigureLowVoltDetect(PMC_Type *base, const pmc_low_volt_detect_config_t *config); + +/*! + * @brief Gets the Low-voltage Detect Flag status. + * + * This function reads the current LVDF status. If it returns 1, a low-voltage event is detected. + * + * @param base PMC peripheral base address. + * @return Current low-voltage detect flag + * - true: Low-voltage detected + * - false: Low-voltage not detected + */ +static inline bool PMC_GetLowVoltDetectFlag(PMC_Type *base) +{ + return (bool)(base->LVDSC1 & PMC_LVDSC1_LVDF_MASK); +} + +/*! + * @brief Acknowledges clearing the Low-voltage Detect flag. + * + * This function acknowledges the low-voltage detection errors (write 1 to + * clear LVDF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearLowVoltDetectFlag(PMC_Type *base) +{ + base->LVDSC1 |= PMC_LVDSC1_LVDACK_MASK; +} + +/*! + * @brief Configures the low-voltage warning setting. + * + * This function configures the low-voltage warning setting, including the trip + * point voltage setting and enabling or disabling the interrupt. + * + * @param base PMC peripheral base address. + * @param config Low-voltage warning configuration structure. + */ +void PMC_ConfigureLowVoltWarning(PMC_Type *base, const pmc_low_volt_warning_config_t *config); + +/*! + * @brief Gets the Low-voltage Warning Flag status. + * + * This function polls the current LVWF status. When 1 is returned, it + * indicates a low-voltage warning event. LVWF is set when V Supply transitions + * below the trip point or after reset and V Supply is already below the V LVW. + * + * @param base PMC peripheral base address. + * @return Current LVWF status + * - true: Low-voltage Warning Flag is set. + * - false: the Low-voltage Warning does not happen. + */ +static inline bool PMC_GetLowVoltWarningFlag(PMC_Type *base) +{ + return (bool)(base->LVDSC2 & PMC_LVDSC2_LVWF_MASK); +} + +/*! + * @brief Acknowledges the Low-voltage Warning flag. + * + * This function acknowledges the low voltage warning errors (write 1 to + * clear LVWF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearLowVoltWarningFlag(PMC_Type *base) +{ + base->LVDSC2 |= PMC_LVDSC2_LVWACK_MASK; +} + +#if (defined(FSL_FEATURE_PMC_HAS_HVDSC1) && FSL_FEATURE_PMC_HAS_HVDSC1) +/*! + * @brief Configures the high-voltage detect setting. + * + * This function configures the high-voltage detect setting, including the trip + * point voltage setting, enabling or disabling the interrupt, enabling or disabling the system reset. + * + * @param base PMC peripheral base address. + * @param config High-voltage detect configuration structure. + */ +void PMC_ConfigureHighVoltDetect(PMC_Type *base, const pmc_high_volt_detect_config_t *config); + +/*! + * @brief Gets the High-voltage Detect Flag status. + * + * This function reads the current HVDF status. If it returns 1, a low + * voltage event is detected. + * + * @param base PMC peripheral base address. + * @return Current high-voltage detect flag + * - true: High-voltage detected + * - false: High-voltage not detected + */ +static inline bool PMC_GetHighVoltDetectFlag(PMC_Type *base) +{ + return (bool)(base->HVDSC1 & PMC_HVDSC1_HVDF_MASK); +} + +/*! + * @brief Acknowledges clearing the High-voltage Detect flag. + * + * This function acknowledges the high-voltage detection errors (write 1 to + * clear HVDF). + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearHighVoltDetectFlag(PMC_Type *base) +{ + base->HVDSC1 |= PMC_HVDSC1_HVDACK_MASK; +} +#endif /* FSL_FEATURE_PMC_HAS_HVDSC1 */ + +#if ((defined(FSL_FEATURE_PMC_HAS_BGBE) && FSL_FEATURE_PMC_HAS_BGBE) || \ + (defined(FSL_FEATURE_PMC_HAS_BGEN) && FSL_FEATURE_PMC_HAS_BGEN) || \ + (defined(FSL_FEATURE_PMC_HAS_BGBDS) && FSL_FEATURE_PMC_HAS_BGBDS)) +/*! + * @brief Configures the PMC bandgap. + * + * This function configures the PMC bandgap, including the drive select and + * behavior in low-power mode. + * + * @param base PMC peripheral base address. + * @param config Pointer to the configuration structure + */ +void PMC_ConfigureBandgapBuffer(PMC_Type *base, const pmc_bandgap_buffer_config_t *config); +#endif + +#if (defined(FSL_FEATURE_PMC_HAS_ACKISO) && FSL_FEATURE_PMC_HAS_ACKISO) +/*! + * @brief Gets the acknowledge Peripherals and I/O pads isolation flag. + * + * This function reads the Acknowledge Isolation setting that indicates + * whether certain peripherals and the I/O pads are in a latched state as + * a result of having been in the VLLS mode. + * + * @param base PMC peripheral base address. + * @param base Base address for current PMC instance. + * @return ACK isolation + * 0 - Peripherals and I/O pads are in a normal run state. + * 1 - Certain peripherals and I/O pads are in an isolated and + * latched state. + */ +static inline bool PMC_GetPeriphIOIsolationFlag(PMC_Type *base) +{ + return (bool)(base->REGSC & PMC_REGSC_ACKISO_MASK); +} + +/*! + * @brief Acknowledges the isolation flag to Peripherals and I/O pads. + * + * This function clears the ACK Isolation flag. Writing one to this setting + * when it is set releases the I/O pads and certain peripherals to their normal + * run mode state. + * + * @param base PMC peripheral base address. + */ +static inline void PMC_ClearPeriphIOIsolationFlag(PMC_Type *base) +{ + base->REGSC |= PMC_REGSC_ACKISO_MASK; +} +#endif /* FSL_FEATURE_PMC_HAS_ACKISO */ + +#if (defined(FSL_FEATURE_PMC_HAS_REGONS) && FSL_FEATURE_PMC_HAS_REGONS) +/*! + * @brief Gets the regulator regulation status. + * + * This function returns the regulator to run a regulation status. It provides + * the current status of the internal voltage regulator. + * + * @param base PMC peripheral base address. + * @param base Base address for current PMC instance. + * @return Regulation status + * 0 - Regulator is in a stop regulation or in transition to/from the regulation. + * 1 - Regulator is in a run regulation. + * + */ +static inline bool PMC_IsRegulatorInRunRegulation(PMC_Type *base) +{ + return (bool)(base->REGSC & PMC_REGSC_REGONS_MASK); +} +#endif /* FSL_FEATURE_PMC_HAS_REGONS */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_PMC_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_port.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_port.h new file mode 100644 index 00000000000..eb8e77e6ddd --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_port.h @@ -0,0 +1,431 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_PORT_H_ +#define _FSL_PORT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup port + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! Version 2.0.2. */ +#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE +/*! @brief Internal resistor pull feature selection */ +enum _port_pull +{ + kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */ + kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */ + kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */ + +#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE +/*! @brief Slew rate selection */ +enum _port_slew_rate +{ + kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */ + kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */ + +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN +/*! @brief Open Drain feature enable/disable */ +enum _port_open_drain_enable +{ + kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */ + kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + +#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER +/*! @brief Passive filter feature enable/disable */ +enum _port_passive_filter_enable +{ + kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */ + kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */ +}; +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH +/*! @brief Configures the drive strength. */ +enum _port_drive_strength +{ + kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */ + kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */ + +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK +/*! @brief Unlock/lock the pin control register field[15:0] */ +enum _port_lock_register +{ + kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */ + kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH +/*! @brief Pin mux selection */ +typedef enum _port_mux +{ + kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */ + kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */ + kPORT_MuxAlt2 = 2U, /*!< Chip-specific */ + kPORT_MuxAlt3 = 3U, /*!< Chip-specific */ + kPORT_MuxAlt4 = 4U, /*!< Chip-specific */ + kPORT_MuxAlt5 = 5U, /*!< Chip-specific */ + kPORT_MuxAlt6 = 6U, /*!< Chip-specific */ + kPORT_MuxAlt7 = 7U, /*!< Chip-specific */ + kPORT_MuxAlt8 = 8U, /*!< Chip-specific */ + kPORT_MuxAlt9 = 9U, /*!< Chip-specific */ + kPORT_MuxAlt10 = 10U, /*!< Chip-specific */ + kPORT_MuxAlt11 = 11U, /*!< Chip-specific */ + kPORT_MuxAlt12 = 12U, /*!< Chip-specific */ + kPORT_MuxAlt13 = 13U, /*!< Chip-specific */ + kPORT_MuxAlt14 = 14U, /*!< Chip-specific */ + kPORT_MuxAlt15 = 15U, /*!< Chip-specific */ +} port_mux_t; +#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ + +/*! @brief Configures the interrupt generation condition. */ +typedef enum _port_interrupt +{ + kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ +#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST + kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ + kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ + kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ +#endif +#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG + kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ +#endif + kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ +#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER + kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ + kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ +#endif +} port_interrupt_t; + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER +/*! @brief Digital filter clock source selection */ +typedef enum _port_digital_filter_clock_source +{ + kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */ + kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */ +} port_digital_filter_clock_source_t; + +/*! @brief PORT digital filter feature configuration definition */ +typedef struct _port_digital_filter_config +{ + uint32_t digitalFilterWidth; /*!< Set digital filter width */ + port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */ +} port_digital_filter_config_t; +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH +/*! @brief PORT pin configuration structure */ +typedef struct _port_pin_config +{ +#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE + uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */ +#else + uint16_t : 2; +#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */ + +#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE + uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */ + + uint16_t : 1; + +#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER + uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */ + +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN + uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH + uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */ +#else + uint16_t : 1; +#endif + + uint16_t : 1; + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH + uint16_t mux : 3; /*!< Pin mux Configure */ +#else + uint16_t : 3; +#endif + + uint16_t : 4; + +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK + uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ +} port_pin_config_t; +#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ + +/******************************************************************************* +* API +******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the port PCR register. + * + * This is an example to define an input pin or output pin PCR configuration. + * @code + * // Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnLockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT PCR register configuration structure. + */ +static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) +{ + assert(config); + uint32_t addr = (uint32_t)&base->PCR[pin]; + *(volatile uint16_t *)(addr) = *((const uint16_t *)config); +} + +/*! + * @brief Sets the port PCR register for multiple pins. + * + * This is an example to define input pins or output pins PCR configuration. + * @code + * // Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp , + * kPORT_PullEnable, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnlockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + * @param config PORT PCR register configuration structure. + */ +static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config) +{ + assert(config); + + uint16_t pcrl = *((const uint16_t *)config); + + if (mask & 0xffffU) + { + base->GPCLR = ((mask & 0xffffU) << 16) | pcrl; + } + if (mask >> 16) + { + base->GPCHR = (mask & 0xffff0000U) | pcrl; + } +} + +/*! + * @brief Configures the pin muxing. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param mux pin muxing slot selection. + * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function. + * - #kPORT_MuxAsGpio : Set as GPIO. + * - #kPORT_MuxAlt2 : chip-specific. + * - #kPORT_MuxAlt3 : chip-specific. + * - #kPORT_MuxAlt4 : chip-specific. + * - #kPORT_MuxAlt5 : chip-specific. + * - #kPORT_MuxAlt6 : chip-specific. + * - #kPORT_MuxAlt7 : chip-specific. + * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because + * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is + * reset to zero : kPORT_PinDisabledOrAnalog). + * This function is recommended to use to reset the pin mux + * + */ +static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); +} +#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER + +/*! + * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + */ +static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable) +{ + if (enable == true) + { + base->DFER |= mask; + } + else + { + base->DFER &= ~mask; + } +} + +/*! + * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param config PORT digital filter configuration structure. + */ +static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config) +{ + assert(config); + + base->DFCR = PORT_DFCR_CS(config->clockSource); + base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth); +} + +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ + +/*@}*/ + +/*! @name Interrupt */ +/*@{*/ + +/*! + * @brief Configures the port pin interrupt/DMA request. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT pin interrupt configuration. + * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. + * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kPORT_InterruptLogicZero : Interrupt when logic zero. + * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. + * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. + * - #kPORT_InterruptEitherEdge : Interrupt on either edge. + * - #kPORT_InterruptLogicOne : Interrupt when logic one. + * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit). + */ +static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); +} + +/*! + * @brief Reads the whole port status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base PORT peripheral base pointer. + * @return Current port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 16 have the interrupt. + */ +static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base) +{ + return base->ISFR; +} + +/*! + * @brief Clears the multiple pin interrupt status flag. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + */ +static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask) +{ + base->ISFR = mask; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PORT_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rcm.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rcm.c new file mode 100644 index 00000000000..0d738643b53 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rcm.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rcm.h" + +void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config) +{ + assert(config); + +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + uint32_t reg; + + reg = (((uint32_t)config->enableFilterInStop << RCM_RPC_RSTFLTSS_SHIFT) | (uint32_t)config->filterInRunWait); + if (config->filterInRunWait == kRCM_FilterBusClock) + { + reg |= ((uint32_t)config->busClockFilterCount << RCM_RPC_RSTFLTSEL_SHIFT); + } + base->RPC = reg; +#else + base->RPFC = ((uint8_t)(config->enableFilterInStop << RCM_RPFC_RSTFLTSS_SHIFT) | (uint8_t)config->filterInRunWait); + if (config->filterInRunWait == kRCM_FilterBusClock) + { + base->RPFW = config->busClockFilterCount; + } +#endif /* FSL_FEATURE_RCM_REG_WIDTH */ +} + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config) +{ + uint32_t reg; + + reg = base->FM; + reg &= ~RCM_FM_FORCEROM_MASK; + reg |= ((uint32_t)config << RCM_FM_FORCEROM_SHIFT); + base->FM = reg; +} +#endif /* #if FSL_FEATURE_RCM_HAS_BOOTROM */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rcm.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rcm.h new file mode 100644 index 00000000000..99b843aaf3a --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rcm.h @@ -0,0 +1,431 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RCM_H_ +#define _FSL_RCM_H_ + +#include "fsl_common.h" + +/*! @addtogroup rcm */ +/*! @{*/ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief RCM driver version 2.0.1. */ +#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief System Reset Source Name definitions + */ +typedef enum _rcm_reset_source +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) +/* RCM register bit width is 32. */ +#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) + kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ +#endif + kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< Low-voltage detect reset */ +#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) + kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOC */ +#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) + kRCM_SourceLol = RCM_SRS_LOL_MASK, /*!< Loss of lock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOL */ + kRCM_SourceWdog = RCM_SRS_WDOG_MASK, /*!< Watchdog reset */ + kRCM_SourcePin = RCM_SRS_PIN_MASK, /*!< External pin reset */ + kRCM_SourcePor = RCM_SRS_POR_MASK, /*!< Power on reset */ +#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) + kRCM_SourceJtag = RCM_SRS_JTAG_MASK, /*!< JTAG generated reset */ +#endif /* FSL_FEATURE_RCM_HAS_JTAG */ + kRCM_SourceLockup = RCM_SRS_LOCKUP_MASK, /*!< Core lock up reset */ + kRCM_SourceSw = RCM_SRS_SW_MASK, /*!< Software reset */ +#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) + kRCM_SourceMdmap = RCM_SRS_MDM_AP_MASK, /*!< MDM-AP system reset */ +#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ +#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) + kRCM_SourceEzpt = RCM_SRS_EZPT_MASK, /*!< EzPort reset */ +#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ + kRCM_SourceSackerr = RCM_SRS_SACKERR_MASK, /*!< Parameter could get all reset flags */ + +#else /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +/* RCM register bit width is 8. */ +#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP) + kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */ +#endif + kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< Low-voltage detect reset */ +#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC) + kRCM_SourceLoc = RCM_SRS0_LOC_MASK, /*!< Loss of clock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOC */ +#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL) + kRCM_SourceLol = RCM_SRS0_LOL_MASK, /*!< Loss of lock reset */ +#endif /* FSL_FEATURE_RCM_HAS_LOL */ + kRCM_SourceWdog = RCM_SRS0_WDOG_MASK, /*!< Watchdog reset */ + kRCM_SourcePin = RCM_SRS0_PIN_MASK, /*!< External pin reset */ + kRCM_SourcePor = RCM_SRS0_POR_MASK, /*!< Power on reset */ +#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG) + kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U, /*!< JTAG generated reset */ +#endif /* FSL_FEATURE_RCM_HAS_JTAG */ + kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */ + kRCM_SourceSw = RCM_SRS1_SW_MASK << 8U, /*!< Software reset */ +#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP) + kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U, /*!< MDM-AP system reset */ +#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */ +#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT) + kRCM_SourceEzpt = RCM_SRS1_EZPT_MASK << 8U, /*!< EzPort reset */ +#endif /* FSL_FEATURE_RCM_HAS_EZPORT */ + kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */ +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ + kRCM_SourceAll = 0xffffffffU, +} rcm_reset_source_t; + +/*! + * @brief Reset pin filter select in Run and Wait modes. + */ +typedef enum _rcm_run_wait_filter_mode +{ + kRCM_FilterDisable = 0U, /*!< All filtering disabled */ + kRCM_FilterBusClock = 1U, /*!< Bus clock filter enabled */ + kRCM_FilterLpoClock = 2U /*!< LPO clock filter enabled */ +} rcm_run_wait_filter_mode_t; + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +/*! + * @brief Boot from ROM configuration. + */ +typedef enum _rcm_boot_rom_config +{ + kRCM_BootFlash = 0U, /*!< Boot from flash */ + kRCM_BootRomCfg0 = 1U, /*!< Boot from boot ROM due to BOOTCFG0 */ + kRCM_BootRomFopt = 2U, /*!< Boot from boot ROM due to FOPT[7] */ + kRCM_BootRomBoth = 3U /*!< Boot from boot ROM due to both BOOTCFG0 and FOPT[7] */ +} rcm_boot_rom_config_t; +#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ + +#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) +/*! + * @brief Maximum delay time from interrupt asserts to system reset. + */ +typedef enum _rcm_reset_delay +{ + kRCM_ResetDelay8Lpo = 0U, /*!< Delay 8 LPO cycles. */ + kRCM_ResetDelay32Lpo = 1U, /*!< Delay 32 LPO cycles. */ + kRCM_ResetDelay128Lpo = 2U, /*!< Delay 128 LPO cycles. */ + kRCM_ResetDelay512Lpo = 3U /*!< Delay 512 LPO cycles. */ +} rcm_reset_delay_t; + +/*! + * @brief System reset interrupt enable bit definitions. + */ +typedef enum _rcm_interrupt_enable +{ + kRCM_IntNone = 0U, /*!< No interrupt enabled. */ + kRCM_IntLossOfClk = RCM_SRIE_LOC_MASK, /*!< Loss of clock interrupt. */ + kRCM_IntLossOfLock = RCM_SRIE_LOL_MASK, /*!< Loss of lock interrupt. */ + kRCM_IntWatchDog = RCM_SRIE_WDOG_MASK, /*!< Watch dog interrupt. */ + kRCM_IntExternalPin = RCM_SRIE_PIN_MASK, /*!< External pin interrupt. */ + kRCM_IntGlobal = RCM_SRIE_GIE_MASK, /*!< Global interrupts. */ + kRCM_IntCoreLockup = RCM_SRIE_LOCKUP_MASK, /*!< Core lock up interrupt */ + kRCM_IntSoftware = RCM_SRIE_SW_MASK, /*!< software interrupt */ + kRCM_IntStopModeAckErr = RCM_SRIE_SACKERR_MASK, /*!< Stop mode ACK error interrupt. */ +#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) + kRCM_IntCore1 = RCM_SRIE_CORE1_MASK, /*!< Core 1 interrupt. */ +#endif + kRCM_IntAll = RCM_SRIE_LOC_MASK /*!< Enable all interrupts. */ + | + RCM_SRIE_LOL_MASK | RCM_SRIE_WDOG_MASK | RCM_SRIE_PIN_MASK | RCM_SRIE_GIE_MASK | + RCM_SRIE_LOCKUP_MASK | RCM_SRIE_SW_MASK | RCM_SRIE_SACKERR_MASK +#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1) + | + RCM_SRIE_CORE1_MASK +#endif +} rcm_interrupt_enable_t; +#endif /* FSL_FEATURE_RCM_HAS_SRIE */ + +#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _rcm_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} rcm_version_id_t; +#endif + +/*! + * @brief Reset pin filter configuration. + */ +typedef struct _rcm_reset_pin_filter_config +{ + bool enableFilterInStop; /*!< Reset pin filter select in stop mode. */ + rcm_run_wait_filter_mode_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */ + uint8_t busClockFilterCount; /*!< Reset pin bus clock filter width. */ +} rcm_reset_pin_filter_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name Reset Control Module APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID) +/*! + * @brief Gets the RCM version ID. + * + * This function gets the RCM version ID including the major version number, + * the minor version number, and the feature specification number. + * + * @param base RCM peripheral base address. + * @param versionId Pointer to the version ID structure. + */ +static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif + +#if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM) +/*! + * @brief Gets the reset source implemented status. + * + * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented. + * Use source masks defined in the rcm_reset_source_t to get the desired source status. + * + * This is an example. + @code + uint32_t status; + + // To test whether the MCU is reset using Watchdog. + status = RCM_GetResetSourceImplementedStatus(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @return All reset source implemented status bit map. + */ +static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base) +{ + return base->PARAM; +} +#endif /* FSL_FEATURE_RCM_HAS_PARAM */ + +/*! + * @brief Gets the reset source status which caused a previous reset. + * + * This function gets the current reset source status. Use source masks + * defined in the rcm_reset_source_t to get the desired source status. + * + * This is an example. + @code + uint32_t resetStatus; + + // To get all reset source statuses. + resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll; + + // To test whether the MCU is reset using Watchdog. + resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceWdog; + + // To test multiple reset sources. + resetStatus = RCM_GetPreviousResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @return All reset source status bit map. + */ +static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + return base->SRS; +#else + return (uint32_t)((uint32_t)base->SRS0 | ((uint32_t)base->SRS1 << 8U)); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} + +#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS) +/*! + * @brief Gets the sticky reset source status. + * + * This function gets the current reset source status that has not been cleared + * by software for a specific source. + * + * This is an example. + @code + uint32_t resetStatus; + + // To get all reset source statuses. + resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll; + + // To test whether the MCU is reset using Watchdog. + resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceWdog; + + // To test multiple reset sources. + resetStatus = RCM_GetStickyResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @return All reset source status bit map. + */ +static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + return base->SSRS; +#else + return (base->SSRS0 | ((uint32_t)base->SSRS1 << 8U)); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} + +/*! + * @brief Clears the sticky reset source status. + * + * This function clears the sticky system reset flags indicated by source masks. + * + * This is an example. + @code + // Clears multiple reset sources. + RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin); + @endcode + * + * @param base RCM peripheral base address. + * @param sourceMasks reset source status bit map + */ +static inline void RCM_ClearStickyResetSources(RCM_Type *base, uint32_t sourceMasks) +{ +#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32)) + base->SSRS = sourceMasks; +#else + base->SSRS0 = (sourceMasks & 0xffU); + base->SSRS1 = ((sourceMasks >> 8U) & 0xffU); +#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */ +} +#endif /* FSL_FEATURE_RCM_HAS_SSRS */ + +/*! + * @brief Configures the reset pin filter. + * + * This function sets the reset pin filter including the filter source, filter + * width, and so on. + * + * @param base RCM peripheral base address. + * @param config Pointer to the configuration structure. + */ +void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config); + +#if (defined(FSL_FEATURE_RCM_HAS_EZPMS) && FSL_FEATURE_RCM_HAS_EZPMS) +/*! + * @brief Gets the EZP_MS_B pin assert status. + * + * This function gets the easy port mode status (EZP_MS_B) pin assert status. + * + * @param base RCM peripheral base address. + * @return status true - asserted, false - reasserted + */ +static inline bool RCM_GetEasyPortModePinStatus(RCM_Type *base) +{ + return (bool)(base->MR & RCM_MR_EZP_MS_MASK); +} +#endif /* FSL_FEATURE_RCM_HAS_EZPMS */ + +#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM) +/*! + * @brief Gets the ROM boot source. + * + * This function gets the ROM boot source during the last chip reset. + * + * @param base RCM peripheral base address. + * @return The ROM boot source. + */ +static inline rcm_boot_rom_config_t RCM_GetBootRomSource(RCM_Type *base) +{ + return (rcm_boot_rom_config_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT); +} + +/*! + * @brief Clears the ROM boot source flag. + * + * This function clears the ROM boot source flag. + * + * @param base Register base address of RCM + */ +static inline void RCM_ClearBootRomSource(RCM_Type *base) +{ + base->MR |= RCM_MR_BOOTROM_MASK; +} + +/*! + * @brief Forces the boot from ROM. + * + * This function forces booting from ROM during all subsequent system resets. + * + * @param base RCM peripheral base address. + * @param config Boot configuration. + */ +void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config); +#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */ + +#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE) +/*! + * @brief Sets the system reset interrupt configuration. + * + * For a graceful shut down, the RCM supports delaying the assertion of the system + * reset for a period of time when the reset interrupt is generated. This function + * can be used to enable the interrupt and the delay period. The interrupts + * are passed in as bit mask. See rcm_int_t for details. For example, to + * delay a reset for 512 LPO cycles after the WDOG timeout or loss-of-clock occurs, + * configure as follows: + * RCM_SetSystemResetInterruptConfig(kRCM_IntWatchDog | kRCM_IntLossOfClk, kRCM_ResetDelay512Lpo); + * + * @param base RCM peripheral base address. + * @param intMask Bit mask of the system reset interrupts to enable. See + * rcm_interrupt_enable_t for details. + * @param Delay Bit mask of the system reset interrupts to enable. + */ +static inline void RCM_SetSystemResetInterruptConfig(RCM_Type *base, uint32_t intMask, rcm_reset_delay_t delay) +{ + base->SRIE = (intMask | delay); +} +#endif /* FSL_FEATURE_RCM_HAS_SRIE */ +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_RCM_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rnga.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rnga.c new file mode 100644 index 00000000000..6f0adc66f59 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rnga.c @@ -0,0 +1,287 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rnga.h" + +#if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/******************************************************************************* + * RNG_CR - RNGA Control Register + ******************************************************************************/ +/*! + * @brief RNG_CR - RNGA Control Register (RW) + * + * Reset value: 0x00000000U + * + * Controls the operation of RNGA. + */ +/*! + * @name Constants and macros for entire RNG_CR register + */ +/*@{*/ +#define RNG_CR_REG(base) ((base)->CR) +#define RNG_RD_CR(base) (RNG_CR_REG(base)) +#define RNG_WR_CR(base, value) (RNG_CR_REG(base) = (value)) +#define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value))) +/*@}*/ + +/*! + * @name Register RNG_CR, field GO[0] (RW) + * + * Specifies whether random-data generation and loading (into OR[RANDOUT]) is + * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading + * OR[RANDOUT] with data. + * + * Values: + * - 0b0 - Disabled + * - 0b1 - Enabled + */ +/*@{*/ +/*! @brief Read current value of the RNG_CR_GO field. */ +#define RNG_RD_CR_GO(base) ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT) + +/*! @brief Set the GO field to a new value. */ +#define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value))) +/*@}*/ + +/*! + * @name Register RNG_CR, field SLP[4] (RW) + * + * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep + * mode by asserting the DOZE signal. + * + * Values: + * - 0b0 - Normal mode + * - 0b1 - Sleep (low-power) mode + */ +/*@{*/ +/*! @brief Read current value of the RNG_CR_SLP field. */ +#define RNG_RD_CR_SLP(base) ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT) + +/*! @brief Set the SLP field to a new value. */ +#define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value))) +/*@}*/ + +/******************************************************************************* + * RNG_SR - RNGA Status Register + ******************************************************************************/ +#define RNG_SR_REG(base) ((base)->SR) + +/*! + * @name Register RNG_SR, field OREG_LVL[15:8] (RO) + * + * Indicates the number of random-data words that are in OR[RANDOUT], which + * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL] + * is not 0, then the contents of a random number contained in OR[RANDOUT] are + * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL]. + * + * Values: + * - 0b00000000 - No words (empty) + * - 0b00000001 - One word (valid) + */ +/*@{*/ +/*! @brief Read current value of the RNG_SR_OREG_LVL field. */ +#define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT) +/*@}*/ + +/*! + * @name Register RNG_SR, field SLP[4] (RO) + * + * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep + * mode by asserting the DOZE signal. + * + * Values: + * - 0b0 - Normal mode + * - 0b1 - Sleep (low-power) mode + */ +/*@{*/ +/*! @brief Read current value of the RNG_SR_SLP field. */ +#define RNG_RD_SR_SLP(base) ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT) +/*@}*/ + +/******************************************************************************* + * RNG_OR - RNGA Output Register + ******************************************************************************/ +/*! + * @brief RNG_OR - RNGA Output Register (RO) + * + * Reset value: 0x00000000U + * + * Stores a random-data word generated by RNGA. + */ +/*! + * @name Constants and macros for entire RNG_OR register + */ +/*@{*/ +#define RNG_OR_REG(base) ((base)->OR) +#define RNG_RD_OR(base) (RNG_OR_REG(base)) +/*@}*/ + +/******************************************************************************* + * RNG_ER - RNGA Entropy Register + ******************************************************************************/ +/*! + * @brief RNG_ER - RNGA Entropy Register (WORZ) + * + * Reset value: 0x00000000U + * + * Specifies an entropy value that RNGA uses in addition to its ring oscillators + * to seed its pseudorandom algorithm. This is a write-only register; reads + * return all zeros. + */ +/*! + * @name Constants and macros for entire RNG_ER register + */ +/*@{*/ +#define RNG_ER_REG(base) ((base)->ER) +#define RNG_RD_ER(base) (RNG_ER_REG(base)) +#define RNG_WR_ER(base, value) (RNG_ER_REG(base) = (value)) +/*@}*/ + +/******************************************************************************* + * Prototypes + *******************************************************************************/ + +static uint32_t rnga_ReadEntropy(RNG_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +void RNGA_Init(RNG_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock gate. */ + CLOCK_EnableClock(kCLOCK_Rnga0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + CLOCK_DisableClock(kCLOCK_Rnga0); /* To solve the release version on twrkm43z75m */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Rnga0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the registers for RNGA module to reset state. */ + RNG_WR_CR(base, 0); + /* Enables the RNGA random data generation and loading.*/ + RNG_WR_CR_GO(base, 1); +} + +void RNGA_Deinit(RNG_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock for RNGA module.*/ + CLOCK_DisableClock(kCLOCK_Rnga0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Get a random data from RNGA. + * + * @param base RNGA base address + */ +static uint32_t rnga_ReadEntropy(RNG_Type *base) +{ + uint32_t data = 0; + if (RNGA_GetMode(base) == kRNGA_ModeNormal) /* Is in normal mode.*/ + { + /* Wait for valid random-data.*/ + while (RNG_RD_SR_OREG_LVL(base) == 0) + { + } + data = RNG_RD_OR(base); + } + /* Get random-data word generated by RNGA.*/ + return data; +} + +status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size) +{ + status_t result = kStatus_Success; + uint32_t random_32; + uint8_t *random_p; + uint32_t random_size; + uint8_t *data_p = (uint8_t *)data; + uint32_t i; + + /* Check input parameters.*/ + if (base && data && data_size) + { + do + { + /* Read Entropy.*/ + random_32 = rnga_ReadEntropy(base); + + random_p = (uint8_t *)&random_32; + + if (data_size < sizeof(random_32)) + { + random_size = data_size; + } + else + { + random_size = sizeof(random_32); + } + + for (i = 0; i < random_size; i++) + { + *data_p++ = *random_p++; + } + + data_size -= random_size; + } while (data_size > 0); + } + else + { + result = kStatus_InvalidArgument; + } + + return result; +} + +void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode) +{ + RNG_WR_CR_SLP(base, (uint32_t)mode); +} + +rnga_mode_t RNGA_GetMode(RNG_Type *base) +{ + return (rnga_mode_t)RNG_RD_SR_SLP(base); +} + +void RNGA_Seed(RNG_Type *base, uint32_t seed) +{ + /* Write to RNGA Entropy Register.*/ + RNG_WR_ER(base, seed); +} + +#endif /* FSL_FEATURE_SOC_RNG_COUNT */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rnga.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rnga.h new file mode 100644 index 00000000000..92f5bff8bec --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rnga.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RNGA_DRIVER_H_ +#define _FSL_RNGA_DRIVER_H_ + +#include "fsl_common.h" + +#if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT +/*! + * @addtogroup rnga + * @{ + */ + + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief RNGA driver version 2.0.1. */ +#define FSL_RNGA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief RNGA working mode */ +typedef enum _rnga_mode +{ + kRNGA_ModeNormal = 0U, /*!< Normal Mode. The ring-oscillator clocks are active; RNGA generates entropy + (randomness) from the clocks and stores it in shift registers.*/ + kRNGA_ModeSleep = 1U, /*!< Sleep Mode. The ring-oscillator clocks are inactive; RNGA does not generate entropy.*/ +} rnga_mode_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the RNGA. + * + * This function initializes the RNGA. + * When called, the RNGA entropy generation starts immediately. + * + * @param base RNGA base address + */ +void RNGA_Init(RNG_Type *base); + +/*! + * @brief Shuts down the RNGA. + * + * This function shuts down the RNGA. + * + * @param base RNGA base address + */ +void RNGA_Deinit(RNG_Type *base); + +/*! + * @brief Gets random data. + * + * This function gets random data from the RNGA. + * + * @param base RNGA base address + * @param data pointer to user buffer to be filled by random data + * @param data_size size of data in bytes + * @return RNGA status + */ +status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size); + +/*! + * @brief Feeds the RNGA module. + * + * This function inputs an entropy value that the RNGA uses to seed its + * pseudo-random algorithm. + * + * @param base RNGA base address + * @param seed input seed value + */ +void RNGA_Seed(RNG_Type *base, uint32_t seed); + +/*! + * @brief Sets the RNGA in normal mode or sleep mode. + * + * This function sets the RNGA in sleep mode or normal mode. + * + * @param base RNGA base address + * @param mode normal mode or sleep mode + */ +void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode); + +/*! + * @brief Gets the RNGA working mode. + * + * This function gets the RNGA working mode. + * + * @param base RNGA base address + * @return normal mode or sleep mode + */ +rnga_mode_t RNGA_GetMode(RNG_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FEATURE_SOC_RNG_COUNT */ +#endif /* _FSL_RNGA_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rtc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rtc.c new file mode 100644 index 00000000000..d68055a2690 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rtc.c @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_rtc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime); + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) + { + return false; + } + + return true; +} + +static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Number of days from begin of the non Leap-year*/ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += ((datetime->year / 4) - (1970U / 4)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += (datetime->day - 1); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t x; + uint32_t secondsRemaining, days; + uint16_t daysInYear; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60U; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if (datetime->year & 3U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1; + } + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + for (x = 1U; x <= 12U; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; +} + +void RTC_Init(RTC_Type *base, const rtc_config_t *config) +{ + assert(config); + + uint32_t reg; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Rtc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Issue a software reset if timer is invalid */ + if (RTC_GetStatusFlags(RTC) & kRTC_TimeInvalidFlag) + { + RTC_Reset(RTC); + } + + reg = base->CR; + /* Setup the update mode and supervisor access mode */ + reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK); + reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess); +#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION + /* Setup the wakeup pin select */ + reg &= ~(RTC_CR_WPS_MASK); + reg |= RTC_CR_WPS(config->wakeupSelect); +#endif /* FSL_FEATURE_RTC_HAS_WAKEUP_PIN */ + base->CR = reg; + + /* Configure the RTC time compensation register */ + base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime)); +} + +void RTC_GetDefaultConfig(rtc_config_t *config) +{ + assert(config); + + /* Wakeup pin will assert if the RTC interrupt asserts or if the wakeup pin is turned on */ + config->wakeupSelect = false; + /* Registers cannot be written when locked */ + config->updateMode = false; + /* Non-supervisor mode write accesses are not supported and will generate a bus error */ + config->supervisorAccess = false; + /* Compensation interval used by the crystal compensation logic */ + config->compensationInterval = 0; + /* Compensation time used by the crystal compensation logic */ + config->compensationTime = 0; +} + +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Return error if the time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + base->TSR = RTC_ConvertDatetimeToSeconds(datetime); + + return kStatus_Success; +} + +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0; + + seconds = base->TSR; + RTC_ConvertSecondsToDatetime(seconds, datetime); +} + +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) +{ + assert(alarmTime); + + uint32_t alarmSeconds = 0; + uint32_t currSeconds = 0; + + /* Return error if the alarm time provided is not valid */ + if (!(RTC_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); + + /* Get the current time */ + currSeconds = base->TSR; + + /* Return error if the alarm time has passed */ + if (alarmSeconds < currSeconds) + { + return kStatus_Fail; + } + + /* Set alarm in seconds*/ + base->TAR = alarmSeconds; + + return kStatus_Success; +} + +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0; + + /* Get alarm in seconds */ + alarmSeconds = base->TAR; + + RTC_ConvertSecondsToDatetime(alarmSeconds, datetime); +} + +void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) +{ + /* The alarm flag is cleared by writing to the TAR register */ + if (mask & kRTC_AlarmFlag) + { + base->TAR = 0U; + } + + /* The timer overflow flag is cleared by initializing the TSR register. + * The time counter should be disabled for this write to be successful + */ + if (mask & kRTC_TimeOverflowFlag) + { + base->TSR = 1U; + } + + /* The timer overflow flag is cleared by initializing the TSR register. + * The time counter should be disabled for this write to be successful + */ + if (mask & kRTC_TimeInvalidFlag) + { + base->TSR = 1U; + } +} + +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + +void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter) +{ + assert(counter); + + *counter = (((uint64_t)base->MCHR << 32) | ((uint64_t)base->MCLR)); +} + +void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter) +{ + /* Prepare to initialize the register with the new value written */ + base->MER &= ~RTC_MER_MCE_MASK; + + base->MCHR = (uint32_t)((counter) >> 32); + base->MCLR = (uint32_t)(counter); +} + +status_t RTC_IncrementMonotonicCounter(RTC_Type *base) +{ + if (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK)) + { + return kStatus_Fail; + } + + /* Prepare to switch to increment mode */ + base->MER |= RTC_MER_MCE_MASK; + /* Write anything so the counter increments*/ + base->MCLR = 1U; + + return kStatus_Success; +} + +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rtc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rtc.h new file mode 100644 index 00000000000..99effc6dcb9 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_rtc.h @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_RTC_H_ +#define _FSL_RTC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rtc + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of RTC interrupts */ +typedef enum _rtc_interrupt_enable +{ + kRTC_TimeInvalidInterruptEnable = RTC_IER_TIIE_MASK, /*!< Time invalid interrupt.*/ + kRTC_TimeOverflowInterruptEnable = RTC_IER_TOIE_MASK, /*!< Time overflow interrupt.*/ + kRTC_AlarmInterruptEnable = RTC_IER_TAIE_MASK, /*!< Alarm interrupt.*/ + kRTC_SecondsInterruptEnable = RTC_IER_TSIE_MASK /*!< Seconds interrupt.*/ +} rtc_interrupt_enable_t; + +/*! @brief List of RTC flags */ +typedef enum _rtc_status_flags +{ + kRTC_TimeInvalidFlag = RTC_SR_TIF_MASK, /*!< Time invalid flag */ + kRTC_TimeOverflowFlag = RTC_SR_TOF_MASK, /*!< Time overflow flag */ + kRTC_AlarmFlag = RTC_SR_TAF_MASK /*!< Alarm flag*/ +} rtc_status_flags_t; + +#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP) + +/*! @brief List of RTC Oscillator capacitor load settings */ +typedef enum _rtc_osc_cap_load +{ + kRTC_Capacitor_2p = RTC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ + kRTC_Capacitor_4p = RTC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ + kRTC_Capacitor_8p = RTC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ + kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16 pF capacitor load */ +} rtc_osc_cap_load_t; + +#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */ + +/*! @brief Structure is used to hold the date and time */ +typedef struct _rtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} rtc_datetime_t; + +/*! + * @brief RTC config structure + * + * This structure holds the configuration settings for the RTC peripheral. To initialize this + * structure to reasonable defaults, call the RTC_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _rtc_config +{ + bool wakeupSelect; /*!< true: Wakeup pin outputs the 32 KHz clock; + false:Wakeup pin used to wakeup the chip */ + bool updateMode; /*!< true: Registers can be written even when locked under certain + conditions, false: No writes allowed when registers are locked */ + bool supervisorAccess; /*!< true: Non-supervisor accesses are allowed; + false: Non-supervisor accesses are not supported */ + uint32_t compensationInterval; /*!< Compensation interval that is written to the CIR field in RTC TCR Register */ + uint32_t compensationTime; /*!< Compensation time that is written to the TCR field in RTC TCR Register */ +} rtc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the RTC clock and configures the peripheral for basic operation. + * + * This function issues a software reset if the timer invalid flag is set. + * + * @note This API should be called at the beginning of the application using the RTC driver. + * + * @param base RTC peripheral base address + * @param config Pointer to the user's RTC configuration structure. + */ +void RTC_Init(RTC_Type *base, const rtc_config_t *config); + +/*! + * @brief Stops the timer and gate the RTC clock. + * + * @param base RTC peripheral base address + */ +static inline void RTC_Deinit(RTC_Type *base) +{ + /* Stop the RTC timer */ + base->SR &= ~RTC_SR_TCE_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the module clock */ + CLOCK_DisableClock(kCLOCK_Rtc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Fills in the RTC config struct with the default settings. + * + * The default values are as follows. + * @code + * config->wakeupSelect = false; + * config->updateMode = false; + * config->supervisorAccess = false; + * config->compensationInterval = 0; + * config->compensationTime = 0; + * @endcode + * @param config Pointer to the user's RTC configuration structure. + */ +void RTC_GetDefaultConfig(rtc_config_t *config); + +/*! @}*/ + +/*! + * @name Current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the RTC date and time according to the given time structure. + * + * The RTC counter must be stopped prior to calling this function because writes to the RTC + * seconds register fail if the RTC counter is running. + * + * @param base RTC peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + * + * @return kStatus_Success: Success in setting the time and starting the RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); + +/*! + * @brief Gets the RTC time and stores it in the given time structure. + * + * @param base RTC peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + */ +void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); + +/*! + * @brief Sets the RTC alarm time. + * + * The function checks whether the specified alarm time is greater than the present + * time. If not, the function does not set the alarm and returns an error. + * + * @param base RTC peripheral base address + * @param alarmTime Pointer to the structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); + +/*! + * @brief Returns the RTC alarm time. + * + * @param base RTC peripheral base address + * @param datetime Pointer to the structure where the alarm date and time details are stored. + */ +void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected RTC interrupts. + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disables the selected RTC interrupts. + * + * @param base RTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! + * @brief Gets the enabled RTC interrupts. + * + * @param base RTC peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::rtc_interrupt_enable_t + */ +static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) +{ + return (base->IER & (RTC_IER_TIIE_MASK | RTC_IER_TOIE_MASK | RTC_IER_TAIE_MASK | RTC_IER_TSIE_MASK)); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the RTC status flags. + * + * @param base RTC peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) +{ + return (base->SR & (RTC_SR_TIF_MASK | RTC_SR_TOF_MASK | RTC_SR_TAF_MASK)); +} + +/*! + * @brief Clears the RTC status flags. + * + * @param base RTC peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::rtc_status_flags_t + */ +void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the RTC time counter. + * + * After calling this function, the timer counter increments once a second provided SR[TOF] or + * SR[TIF] are not set. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StartTimer(RTC_Type *base) +{ + base->SR |= RTC_SR_TCE_MASK; +} + +/*! + * @brief Stops the RTC time counter. + * + * RTC's seconds register can be written to only when the timer is stopped. + * + * @param base RTC peripheral base address + */ +static inline void RTC_StopTimer(RTC_Type *base) +{ + base->SR &= ~RTC_SR_TCE_MASK; +} + +/*! @}*/ + +#if (defined(FSL_FEATURE_RTC_HAS_OSC_SCXP) && FSL_FEATURE_RTC_HAS_OSC_SCXP) + +/*! + * @brief This function sets the specified capacitor configuration for the RTC oscillator. + * + * @param base RTC peripheral base address + * @param capLoad Oscillator loads to enable. This is a logical OR of members of the + * enumeration ::rtc_osc_cap_load_t + */ +static inline void RTC_SetOscCapLoad(RTC_Type *base, uint32_t capLoad) +{ + uint32_t reg = base->CR; + + reg &= ~(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK); + reg |= capLoad; + + base->CR = reg; +} + +#endif /* FSL_FEATURE_SCG_HAS_OSC_SCXP */ + +/*! + * @brief Performs a software reset on the RTC module. + * + * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR + * registers. The SWR bit is cleared by software explicitly clearing it. + * + * @param base RTC peripheral base address + */ +static inline void RTC_Reset(RTC_Type *base) +{ + base->CR |= RTC_CR_SWR_MASK; + base->CR &= ~RTC_CR_SWR_MASK; + + /* Set TSR register to 0x1 to avoid the timer invalid (TIF) bit being set in the SR register */ + base->TSR = 1U; +} + +#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC) + +/*! + * @name Monotonic counter functions + * @{ + */ + +/*! + * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns + * them as a single value. + * + * @param base RTC peripheral base address + * @param counter Pointer to variable where the value is stored. + */ +void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter); + +/*! + * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing + * the given single value. + * + * @param base RTC peripheral base address + * @param counter Counter value + */ +void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter); + +/*! + * @brief Increments the Monotonic Counter by one. + * + * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting + * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the + * monotonic counter low that causes it to overflow also increments the monotonic counter high. + * + * @param base RTC peripheral base address + * + * @return kStatus_Success: success + * kStatus_Fail: error occurred, either time invalid or monotonic overflow flag was found + */ +status_t RTC_IncrementMonotonicCounter(RTC_Type *base); + +/*! @}*/ + +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_RTC_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.c new file mode 100644 index 00000000000..73ea64fa4ee --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.c @@ -0,0 +1,1192 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sai.h" + +/******************************************************************************* + * Definitations + ******************************************************************************/ +enum _sai_transfer_state +{ + kSAI_Busy = 0x0U, /*!< SAI is busy */ + kSAI_Idle, /*!< Transfer is done. */ + kSAI_Error /*!< Transfer error occured. */ +}; + +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + +/*! + * @brief Set the master clock divider. + * + * This API will compute the master clock divider according to master clock frequency and master + * clock source clock source frequency. + * + * @param base SAI base pointer. + * @param mclk_Hz Mater clock frequency in Hz. + * @param mclkSrcClock_Hz Master clock source frequency in Hz. + */ +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz); +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +/*! + * @brief Get the instance number for SAI. + * + * @param base SAI base pointer. + */ +uint32_t SAI_GetInstance(I2S_Type *base); + +/*! + * @brief sends a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel Data channel used. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Receive a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel Data channel used. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Base pointer array */ +static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; +/*!@brief SAI handle pointer */ +sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2]; +/* IRQ number array */ +static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; +static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Clock name array */ +static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz) +{ + uint32_t freq = mclkSrcClock_Hz; + uint16_t fract, divide; + uint32_t remaind = 0; + uint32_t current_remainder = 0xFFFFFFFFU; + uint16_t current_fract = 0; + uint16_t current_divide = 0; + uint32_t mul_freq = 0; + uint32_t max_fract = 256; + + /*In order to prevent overflow */ + freq /= 100; + mclk_Hz /= 100; + + /* Compute the max fract number */ + max_fract = mclk_Hz * 4096 / freq + 1; + if (max_fract > 256) + { + max_fract = 256; + } + + /* Looking for the closet frequency */ + for (fract = 1; fract < max_fract; fract++) + { + mul_freq = freq * fract; + remaind = mul_freq % mclk_Hz; + divide = mul_freq / mclk_Hz; + + /* Find the exactly frequency */ + if (remaind == 0) + { + current_fract = fract; + current_divide = mul_freq / mclk_Hz; + break; + } + + /* Closer to next one, set the closest to next data */ + if (remaind > mclk_Hz / 2) + { + remaind = mclk_Hz - remaind; + divide += 1; + } + + /* Update the closest div and fract */ + if (remaind < current_remainder) + { + current_fract = fract; + current_divide = divide; + current_remainder = remaind; + } + } + + /* Fill the computed fract and divider to registers */ + base->MDR = I2S_MDR_DIVIDE(current_divide - 1) | I2S_MDR_FRACT(current_fract - 1); + + /* Waiting for the divider updated */ + while (base->MCR & I2S_MCR_DUF_MASK) + { + } +} +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +uint32_t SAI_GetInstance(I2S_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_saiBases); instance++) + { + if (s_saiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_saiBases)); + + return instance; +} + +static void SAI_WriteNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + uint32_t temp = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = 0; j < bytesPerWord; j++) + { + temp = (uint32_t)(*buffer); + data |= (temp << (8U * j)); + buffer++; + } + base->TDR[channel] = data; + data = 0; + } +} + +static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + data = base->RDR[channel]; + for (j = 0; j < bytesPerWord; j++) + { + *buffer = (data >> (8U * j)) & 0xFF; + buffer++; + } + } +} + +void SAI_TxInit(I2S_Type *base, const sai_config_t *config) +{ + uint32_t val = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SAI clock */ + CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + + /* Configure audio protocol */ + switch (config->protocol) + { + case kSAI_BusLeftJustified: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusRightJustified: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusI2S: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(1U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusPCMA: + base->TCR2 &= ~I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusPCMB: + base->TCR2 &= ~I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + default: + break; + } + + /* Set master or slave */ + if (config->masterSlave == kSAI_Master) + { + base->TCR2 |= I2S_TCR2_BCD_MASK; + base->TCR4 |= I2S_TCR4_FSD_MASK; + + /* Bit clock source setting */ + val = base->TCR2 & (~I2S_TCR2_MSEL_MASK); + base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource)); + } + else + { + base->TCR2 &= ~I2S_TCR2_BCD_MASK; + base->TCR4 &= ~I2S_TCR4_FSD_MASK; + } + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(1U)); + /* If sync with Rx, should set Rx to async mode */ + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; + case kSAI_ModeSyncWithOtherTx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(3U)); + break; + default: + break; + } +} + +void SAI_RxInit(I2S_Type *base, const sai_config_t *config) +{ + uint32_t val = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable SAI clock first. */ + CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + + /* Configure audio protocol */ + switch (config->protocol) + { + case kSAI_BusLeftJustified: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusRightJustified: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusI2S: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(1U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusPCMA: + base->RCR2 &= ~I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusPCMB: + base->RCR2 &= ~I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + default: + break; + } + + /* Set master or slave */ + if (config->masterSlave == kSAI_Master) + { + base->RCR2 |= I2S_RCR2_BCD_MASK; + base->RCR4 |= I2S_RCR4_FSD_MASK; + + /* Bit clock source setting */ + val = base->RCR2 & (~I2S_RCR2_MSEL_MASK); + base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource)); + } + else + { + base->RCR2 &= ~I2S_RCR2_BCD_MASK; + base->RCR4 &= ~I2S_RCR4_FSD_MASK; + } + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(1U)); + /* If sync with Tx, should set Tx to async mode */ + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; + case kSAI_ModeSyncWithOtherTx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(3U)); + break; + default: + break; + } +} + +void SAI_Deinit(I2S_Type *base) +{ + SAI_TxEnable(base, false); + SAI_RxEnable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void SAI_TxGetDefaultConfig(sai_config_t *config) +{ + config->bclkSource = kSAI_BclkSourceMclkDiv; + config->masterSlave = kSAI_Master; + config->mclkSource = kSAI_MclkSourceSysclk; + config->protocol = kSAI_BusLeftJustified; + config->syncMode = kSAI_ModeAsync; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +} + +void SAI_RxGetDefaultConfig(sai_config_t *config) +{ + config->bclkSource = kSAI_BclkSourceMclkDiv; + config->masterSlave = kSAI_Master; + config->mclkSource = kSAI_MclkSourceSysclk; + config->protocol = kSAI_BusLeftJustified; + config->syncMode = kSAI_ModeSync; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +} + +void SAI_TxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->TCSR = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->TCSR &= ~I2S_TCSR_SR_MASK; + + /* Reset all Tx register values */ + base->TCR2 = 0; + base->TCR3 = 0; + base->TCR4 = 0; + base->TCR5 = 0; + base->TMR = 0; +} + +void SAI_RxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->RCSR = I2S_RCSR_SR_MASK | I2S_RCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->RCSR &= ~I2S_RCSR_SR_MASK; + + /* Reset all Rx register values */ + base->RCR2 = 0; + base->RCR3 = 0; + base->RCR4 = 0; + base->RCR5 = 0; + base->RMR = 0; +} + +void SAI_TxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Rx, should enable RE bit. */ + if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) == 0x1U) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + } + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + } + else + { + /* Should not close RE even sync with Rx */ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK)); + } +} + +void SAI_RxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Tx, should enable TE bit. */ + if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) == 0x1U) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + } + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + } + else + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK)); + } +} + +void SAI_TxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + uint32_t bclk = format->sampleRate_Hz * 32U * 2U; + +/* Compute the mclk */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled, then set master clock divider */ + if (base->MCR & I2S_MCR_MOE_MASK) + { + SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + + /* Set bclk if needed */ + if (base->TCR2 & I2S_TCR2_BCD_MASK) + { + base->TCR2 &= ~I2S_TCR2_DIV_MASK; + base->TCR2 |= I2S_TCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); + } + + /* Set bitWidth */ + if (format->protocol == kSAI_BusRightJustified) + { + base->TCR5 = I2S_TCR5_WNW(31U) | I2S_TCR5_W0W(31U) | I2S_TCR5_FBT(31U); + } + else + { + base->TCR5 = I2S_TCR5_WNW(31U) | I2S_TCR5_W0W(31U) | I2S_TCR5_FBT(format->bitWidth - 1); + } + + /* Set mono or stereo */ + base->TMR = (uint32_t)format->stereo; + + /* Set data channel */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(1U << format->channel); + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Set watermark */ + base->TCR1 = format->watermark; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +void SAI_RxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + uint32_t bclk = format->sampleRate_Hz * 32U * 2U; + +/* Compute the mclk */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled */ + if (base->MCR & I2S_MCR_MOE_MASK) + { + SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + + /* Set bclk if needed */ + if (base->RCR2 & I2S_RCR2_BCD_MASK) + { + base->RCR2 &= ~I2S_RCR2_DIV_MASK; + base->RCR2 |= I2S_RCR2_DIV((bclkSourceClockHz / bclk) / 2U - 1U); + } + + /* Set bitWidth */ + if (format->protocol == kSAI_BusRightJustified) + { + base->RCR5 = I2S_RCR5_WNW(31U) | I2S_RCR5_W0W(31U) | I2S_RCR5_FBT(31U); + } + else + { + base->RCR5 = I2S_RCR5_WNW(31U) | I2S_RCR5_W0W(31U) | I2S_RCR5_FBT(format->bitWidth - 1); + } + + /* Set mono or stereo */ + base->RMR = (uint32_t)format->stereo; + + /* Set data channel */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + base->RCR3 |= I2S_RCR3_RCE(1U << format->channel); + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Set watermark */ + base->RCR1 = format->watermark; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + while (i < size) + { + /* Wait until it can write data */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } + + SAI_WriteNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + i += bytesPerWord; + } + + /* Wait until the last data is sent */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } +} + +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + while (i < size) + { + /* Wait until data is received */ + while (!(base->RCSR & I2S_RCSR_FWF_MASK)) + { + } + + SAI_ReadNonBlocking(base, channel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + i += bytesPerWord; + } +} + +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + s_saiHandle[SAI_GetInstance(base)][0] = handle; + + handle->callback = callback; + handle->userData = userData; + + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + + /* Enable Tx irq */ + EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); +} + +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + s_saiHandle[SAI_GetInstance(base)][1] = handle; + + handle->callback = callback; + handle->userData = userData; + + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + + /* Enable Rx irq */ + EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); +} + +status_t SAI_TransferTxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle); + + if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) + { + return kStatus_InvalidArgument; + } + + /* Copy format to handle */ + handle->bitWidth = format->bitWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = format->watermark; +#endif + handle->channel = format->channel; + + SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + return kStatus_Success; +} + +status_t SAI_TransferRxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle); + + if ((mclkSourceClockHz < format->sampleRate_Hz) || (bclkSourceClockHz < format->sampleRate_Hz)) + { + return kStatus_InvalidArgument; + } + + /* Copy format to handle */ + handle->bitWidth = format->bitWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = format->watermark; +#endif + handle->channel = format->channel; + + SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + return kStatus_Success; +} + +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set the state to busy */ + handle->state = kSAI_Busy; + +/* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error*/ + SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* Enable Tx transfer */ + SAI_TxEnable(base, true); + + return kStatus_Success; +} + +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = kSAI_Busy; + +/* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error*/ + SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* Enable Rx transfer */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); + } + + return status; +} + +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); + } + + return status; +} + +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + SAI_TxEnable(base, false); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error */ + SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + handle->state = kSAI_Idle; + + /* Clear the queue */ + memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + SAI_RxEnable(base, false); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error */ + SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + handle->state = kSAI_Idle; + + /* Clear the queue */ + memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle Error */ + if (base->TCSR & I2S_TCSR_FEF_MASK) + { + /* Clear FIFO error flag to continue transfer */ + SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag); + + /* Call the callback */ + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_TxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if (base->TCSR & I2S_TCSR_FRF_MASK) + { + /* Judge if the data need to transmit is less than space */ + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), + (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - handle->watermark) * dataSize)); + + /* Copy the data from sai buffer to FIFO */ + SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#else + if (base->TCSR & I2S_TCSR_FWF_MASK) + { + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_WriteNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* If finished a blcok, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_TxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortSend(base, handle); + } +} + +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle Error */ + if (base->RCSR & I2S_RCSR_FEF_MASK) + { + /* Clear FIFO error flag to continue transfer */ + SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag); + + /* Call the callback */ + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_RxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if (base->RCSR & I2S_RCSR_FRF_MASK) + { + /* Judge if the data need to transmit is less than space */ + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), (handle->watermark * dataSize)); + + /* Copy the data from sai buffer to FIFO */ + SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#else + if (base->RCSR & I2S_RCSR_FWF_MASK) + { + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_ReadNonBlocking(base, handle->channel, handle->bitWidth, buffer, size); + + /* Update internal state */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* If finished a blcok, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_RxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortReceive(base, handle); + } +} + +#if defined(I2S0) +void I2S0_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFORequestFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S0->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S0->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S0, s_saiHandle[0][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFORequestFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S0->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S0->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S0, s_saiHandle[0][0]); + } +} + +void I2S0_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); +} + +void I2S0_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); +} +#endif /* I2S0*/ + +#if defined(I2S1) +void I2S1_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFORequestFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S1->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFOWarningFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S1->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFORequestFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S1->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFOWarningFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S1->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S1, s_saiHandle[1][0]); + } +} + +void I2S1_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][0]); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); +} + +void I2S1_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][1]); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); +} +#endif /* I2S1*/ + +#if defined(I2S2) +void I2S2_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFORequestFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S2->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFOWarningFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S2->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S2, s_saiHandle[2][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFORequestFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S2->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFOWarningFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S2->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S2, s_saiHandle[2][0]); + } +} + +void I2S2_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[2][0]); + s_saiTxIsr(I2S2, s_saiHandle[2][0]); +} + +void I2S2_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[2][1]); + s_saiRxIsr(I2S2, s_saiHandle[2][1]); +} +#endif /* I2S2*/ + +#if defined(I2S3) +void I2S3_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFORequestFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S3->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFOWarningFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S3->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFORequestFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S3->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFOWarningFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S3->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S3, s_saiHandle[3][0]); + } +} + +void I2S3_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][0]); + s_saiTxIsr(I2S3, s_saiHandle[3][0]); +} + +void I2S3_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][1]); + s_saiRxIsr(I2S3, s_saiHandle[3][1]); +} +#endif /* I2S3*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.h new file mode 100644 index 00000000000..64a2f667fce --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.h @@ -0,0 +1,848 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SAI_H_ +#define _FSL_SAI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sai + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2 */ +/*@}*/ + +/*! @brief SAI return status*/ +enum _sai_status_t +{ + kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */ + kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */ + kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */ + kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */ + kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */ + kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */ + kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ +}; + +/*! @brief Define the SAI bus type */ +typedef enum _sai_protocol +{ + kSAI_BusLeftJustified = 0x0U, /*!< Uses left justified format.*/ + kSAI_BusRightJustified, /*!< Uses right justified format. */ + kSAI_BusI2S, /*!< Uses I2S format. */ + kSAI_BusPCMA, /*!< Uses I2S PCM A format.*/ + kSAI_BusPCMB /*!< Uses I2S PCM B format. */ +} sai_protocol_t; + +/*! @brief Master or slave mode */ +typedef enum _sai_master_slave +{ + kSAI_Master = 0x0U, /*!< Master mode */ + kSAI_Slave = 0x1U /*!< Slave mode */ +} sai_master_slave_t; + +/*! @brief Mono or stereo audio format */ +typedef enum _sai_mono_stereo +{ + kSAI_Stereo = 0x0U, /*!< Stereo sound. */ + kSAI_MonoLeft, /*!< Only left channel have sound. */ + kSAI_MonoRight /*!< Only Right channel have sound. */ +} sai_mono_stereo_t; + +/*! @brief Synchronous or asynchronous mode */ +typedef enum _sai_sync_mode +{ + kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */ + kSAI_ModeSync, /*!< Synchronous mode (with receiver or transmit) */ + kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */ + kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */ +} sai_sync_mode_t; + +/*! @brief Mater clock source */ +typedef enum _sai_mclk_source +{ + kSAI_MclkSourceSysclk = 0x0U, /*!< Master clock from the system clock */ + kSAI_MclkSourceSelect1, /*!< Master clock from source 1 */ + kSAI_MclkSourceSelect2, /*!< Master clock from source 2 */ + kSAI_MclkSourceSelect3 /*!< Master clock from source 3 */ +} sai_mclk_source_t; + +/*! @brief Bit clock source */ +typedef enum _sai_bclk_source +{ + kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */ + kSAI_BclkSourceMclkDiv, /*!< Bit clock using master clock divider */ + kSAI_BclkSourceOtherSai0, /*!< Bit clock from other SAI device */ + kSAI_BclkSourceOtherSai1 /*!< Bit clock from other SAI device */ +} sai_bclk_source_t; + +/*! @brief The SAI interrupt enable flag */ +enum _sai_interrupt_enable_t +{ + kSAI_WordStartInterruptEnable = + I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */ + kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +}; + +/*! @brief The DMA request sources */ +enum _sai_dma_enable_t +{ + kSAI_FIFOWarningDMAEnable = I2S_TCSR_FWDE_MASK, /*!< FIFO warning caused by the DMA request */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestDMAEnable = I2S_TCSR_FRDE_MASK, /*!< FIFO request caused by the DMA request */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +}; + +/*! @brief The SAI status flag */ +enum _sai_flags +{ + kSAI_WordStartFlag = I2S_TCSR_WSF_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorFlag = I2S_TCSR_SEF_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestFlag = I2S_TCSR_FRF_MASK, /*!< FIFO request flag. */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + kSAI_FIFOWarningFlag = I2S_TCSR_FWF_MASK, /*!< FIFO warning flag */ +}; + +/*! @brief The reset type */ +typedef enum _sai_reset_type +{ + kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */ + kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */ + kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */ +} sai_reset_type_t; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief The SAI packing mode + * The mode includes 8 bit and 16 bit packing. + */ +typedef enum _sai_fifo_packing +{ + kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */ + kSAI_FifoPacking8bit = 0x2U, /*!< 8 bit packing enabled */ + kSAI_FifoPacking16bit = 0x3U /*!< 16bit packing enabled */ +} sai_fifo_packing_t; +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +/*! @brief SAI user configuration structure */ +typedef struct _sai_config +{ + sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ + sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */ +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + sai_mclk_source_t mclkSource; /*!< Master Clock source */ + sai_bclk_source_t bclkSource; /*!< Bit Clock source */ + sai_master_slave_t masterSlave; /*!< Master or slave */ +} sai_config_t; + +/*!@brief SAI transfer queue size, user can refine it according to use case. */ +#define SAI_XFER_QUEUE_SIZE (4) + +/*! @brief Audio sample rate */ +typedef enum _sai_sample_rate +{ + kSAI_SampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ + kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ + kSAI_SampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ + kSAI_SampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ + kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ + kSAI_SampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ + kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ + kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ + kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ + kSAI_SampleRate96KHz = 96000U /*!< Sample rate 96000 Hz */ +} sai_sample_rate_t; + +/*! @brief Audio word width */ +typedef enum _sai_word_width +{ + kSAI_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ + kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ + kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ + kSAI_WordWidth32bits = 32U /*!< Audio data width 32 bits */ +} sai_word_width_t; + +/*! @brief sai transfer format */ +typedef struct _sai_transfer_format +{ + uint32_t sampleRate_Hz; /*!< Sample rate of audio data */ + uint32_t bitWidth; /*!< Data length of audio data, usually 8/16/24/32 bits */ + sai_mono_stereo_t stereo; /*!< Mono or stereo */ + uint32_t masterClockHz; /*!< Master clock frequency in Hz */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t watermark; /*!< Watermark value */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + uint8_t channel; /*!< Data channel used in transfer.*/ + sai_protocol_t protocol; /*!< Which audio protocol used */ +} sai_transfer_format_t; + +/*! @brief SAI transfer structure */ +typedef struct _sai_transfer +{ + uint8_t *data; /*!< Data start address to transfer. */ + size_t dataSize; /*!< Transfer size. */ +} sai_transfer_t; + +typedef struct _sai_handle sai_handle_t; + +/*! @brief SAI transfer callback prototype */ +typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData); + +/*! @brief SAI handle structure */ +struct _sai_handle +{ + uint32_t state; /*!< Transfer status */ + sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */ + uint8_t channel; /*!< Transfer channel */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t watermark; /*!< Watermark value */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the SAI Tx peripheral. + * + * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_TxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault + * because the clock is not enabled. + * + * @param base SAI base pointer + * @param config SAI configuration structure. +*/ +void SAI_TxInit(I2S_Type *base, const sai_config_t *config); + +/*! + * @brief Initializes the the SAI Rx peripheral. + * + * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_RxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault + * because the clock is not enabled. + * + * @param base SAI base pointer + * @param config SAI configuration structure. + */ +void SAI_RxInit(I2S_Type *base, const sai_config_t *config); + +/*! + * @brief Sets the SAI Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in SAI_TxConfig(). + * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified + * before calling SAI_TxConfig(). + * This is an example. + @code + sai_config_t config; + SAI_TxGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SAI_TxGetDefaultConfig(sai_config_t *config); + +/*! + * @brief Sets the SAI Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in SAI_RxConfig(). + * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified + * before calling SAI_RxConfig(). + * This is an example. + @code + sai_config_t config; + SAI_RxGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SAI_RxGetDefaultConfig(sai_config_t *config); + +/*! + * @brief De-initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit + * or SAI_RxInit is called to enable the clock. + * + * @param base SAI base pointer +*/ +void SAI_Deinit(I2S_Type *base); + +/*! + * @brief Resets the SAI Tx. + * + * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_TxReset(I2S_Type *base); + +/*! + * @brief Resets the SAI Rx. + * + * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_RxReset(I2S_Type *base); + +/*! + * @brief Enables/disables the SAI Tx. + * + * @param base SAI base pointer + * @param enable True means enable SAI Tx, false means disable. + */ +void SAI_TxEnable(I2S_Type *base, bool enable); + +/*! + * @brief Enables/disables the SAI Rx. + * + * @param base SAI base pointer + * @param enable True means enable SAI Rx, false means disable. + */ +void SAI_RxEnable(I2S_Type *base, bool enable); + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Tx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base) +{ + return base->TCSR; +} + +/*! + * @brief Clears the SAI Tx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following source if defined: + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Rx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base) +{ + return base->RCSR; +} + +/*! + * @brief Clears the SAI Rx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following sources if defined. + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Enables the SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Disables the SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! + * @brief Disables the SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the SAI Tx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be combination of the following sources if defined. + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Enables/disables the SAI Rx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Gets the SAI Tx data register address. + * + * This API is used to provide a transfer address for the SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->TDR)[channel]); +} + +/*! + * @brief Gets the SAI Rx data register address. + * + * This API is used to provide a transfer address for the SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->RDR)[channel]); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. +*/ +void SAI_TxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. +*/ +void SAI_RxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Sends data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Writes data into SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param data Data needs to be written. + */ +static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data) +{ + base->TDR[channel] = data; +} + +/*! + * @brief Receives data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Reads data from the SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @return Data in SAI FIFO. + */ +static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel) +{ + return base->RDR[channel]; +} + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI Tx handle. + * + * This function initializes the Tx handle for the SAI Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SAI base pointer + * @param handle SAI handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function + */ +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief Initializes the SAI Rx handle. + * + * This function initializes the Rx handle for the SAI Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function. + */ +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * @return Status of this function. Return value is the status_t. +*/ +status_t SAI_TransferTxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * @return Status of this function. Return value is one of status_t. +*/ +status_t SAI_TransferRxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Performs an interrupt non-blocking send transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param xfer Pointer to the sai_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_TxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param xfer Pointer to the sai_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_RxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Gets a set byte count. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param count Bytes count sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Gets a received byte count. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param count Bytes count received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the current send. + * + * @note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Aborts the the current IRQ receive. + * + * @note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* _FSL_SAI_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai_edma.c new file mode 100644 index 00000000000..dce5a87bfa1 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai_edma.c @@ -0,0 +1,413 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sai_edma.h" + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/* Used for 32byte aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU) + +/*handle; + + /* If finished a blcok, call the callback function */ + memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); + saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (saiHandle->callback) + { + (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_TxIdle, saiHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) + { + SAI_TransferAbortSendEDMA(privHandle->base, saiHandle); + } +} + +static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) +{ + sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData; + sai_edma_handle_t *saiHandle = privHandle->handle; + + /* If finished a blcok, call the callback function */ + memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); + saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (saiHandle->callback) + { + (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_RxIdle, saiHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) + { + SAI_TransferAbortReceiveEDMA(privHandle->base, saiHandle); + } +} + +void SAI_TransferTxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + uint32_t instance = SAI_GetInstance(base); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + /* Set sai base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SAI state to idle */ + handle->state = kSAI_Idle; + + s_edmaPrivateHandle[instance][0].base = base; + s_edmaPrivateHandle[instance][0].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, SAI_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); +} + +void SAI_TransferRxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + uint32_t instance = SAI_GetInstance(base); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + /* Set sai base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SAI state to idle */ + handle->state = kSAI_Idle; + + s_edmaPrivateHandle[instance][1].base = base; + s_edmaPrivateHandle[instance][1].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, SAI_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); +} + +void SAI_TransferTxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle && format); + + /* Configure the audio format to SAI registers */ + SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + /* Get the tranfer size from format, this should be used in EDMA configuration */ + if (format->bitWidth == 24U) + { + handle->bytesPerFrame = 4U; + } + else + { + handle->bytesPerFrame = format->bitWidth / 8U; + } + + /* Update the data channel SAI used */ + handle->channel = format->channel; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = FSL_FEATURE_SAI_FIFO_COUNT - format->watermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +void SAI_TransferRxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle && format); + + /* Configure the audio format to SAI registers */ + SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + /* Get the tranfer size from format, this should be used in EDMA configuration */ + if (format->bitWidth == 24U) + { + handle->bytesPerFrame = 4U; + } + else + { + handle->bytesPerFrame = format->bitWidth / 8U; + } + + /* Update the data channel SAI used */ + handle->channel = format->channel; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = format->watermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSAI_Busy; + + /* Update the queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, + handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ + handle->nbytes = handle->count * handle->bytesPerFrame; + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable SAI Tx clock */ + SAI_TxEnable(base, true); + + return kStatus_Success; +} + +status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSAI_Busy; + + /* Update queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, + handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ + handle->nbytes = handle->count * handle->bytesPerFrame; + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable SAI Rx clock */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); + + /* Disable Tx */ + SAI_TxEnable(base, false); + + /* Set the handle state */ + handle->state = kSAI_Idle; +} + +void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); + + /* Disable Rx */ + SAI_RxEnable(base, false); + + /* Set the handle state */ + handle->state = kSAI_Idle; +} + +status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + + return status; +} + +status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + + return status; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai_edma.h new file mode 100644 index 00000000000..9ae05db0e95 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai_edma.h @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SAI_EDMA_H_ +#define _FSL_SAI_EDMA_H_ + +#include "fsl_sai.h" +#include "fsl_edma.h" + +/*! + * @addtogroup sai_edma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +typedef struct _sai_edma_handle sai_edma_handle_t; + +/*! @brief SAI eDMA transfer callback function for finish and error */ +typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData); + +/*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/ +struct _sai_edma_handle +{ + edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint8_t bytesPerFrame; /*!< Bytes in a frame */ + uint8_t channel; /*!< Which data channel */ + uint8_t count; /*!< The transfer data count in a DMA request */ + uint32_t state; /*!< Internal state for SAI eDMA transfer */ + sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ + void *userData; /*!< User callback parameter */ + edma_tcd_t tcd[SAI_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI eDMA handle. + * + * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param base SAI peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferTxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); + +/*! + * @brief Initializes the SAI Rx eDMA handle. + * + * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param base SAI peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferRxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. +*/ +void SAI_TransferTxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master + * clock, this value should equal to masterClockHz in format. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. +*/ +void SAI_TransferRxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Performs a non-blocking SAI transfer using DMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to the DMA transfer structure. + * @retval kStatus_Success Start a SAI eDMA send successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_TxBusy SAI is busy sending data. + */ +status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SAI receive using eDMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a SAI eDMA receive successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_RxBusy SAI is busy receiving data. + */ +status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Aborts a SAI transfer using eDMA. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Aborts a SAI receive using eDMA. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Gets byte count sent by SAI. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param count Bytes count sent by SAI. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets byte count received by SAI. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @param count Bytes count received by SAI. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sdhc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sdhc.c new file mode 100644 index 00000000000..3151cd22ed9 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sdhc.c @@ -0,0 +1,1416 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sdhc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Clock setting */ +/* Max SD clock divisor from base clock */ +#define SDHC_MAX_DVS ((SDHC_SYSCTL_DVS_MASK >> SDHC_SYSCTL_DVS_SHIFT) + 1U) +#define SDHC_PREV_DVS(x) ((x) -= 1U) +#define SDHC_MAX_CLKFS ((SDHC_SYSCTL_SDCLKFS_MASK >> SDHC_SYSCTL_SDCLKFS_SHIFT) + 1U) +#define SDHC_PREV_CLKFS(x) ((x) >>= 1U) + +/* Typedef for interrupt handler. */ +typedef void (*sdhc_isr_t)(SDHC_Type *base, sdhc_handle_t *handle); + +/*! @brief ADMA table configuration */ +typedef struct _sdhc_adma_table_config +{ + uint32_t *admaTable; /*!< ADMA table address, can't be null if transfer way is ADMA1/ADMA2 */ + uint32_t admaTableWords; /*!< ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2 */ +} sdhc_adma_table_config_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance. + * + * @param base SDHC peripheral base address. + * @return Instance number. + */ +static uint32_t SDHC_GetInstance(SDHC_Type *base); + +/*! + * @brief Set transfer interrupt. + * + * @param base SDHC peripheral base address. + * @param usingInterruptSignal True to use IRQ signal. + */ +static void SDHC_SetTransferInterrupt(SDHC_Type *base, bool usingInterruptSignal); + +/*! + * @brief Start transfer according to current transfer state + * + * @param base SDHC peripheral base address. + * @param command Command to be sent. + * @param data Data to be transferred. + * @param DMA mode selection + */ +static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_data_t *data, sdhc_dma_mode_t dmaMode); + +/*! + * @brief Receive command response + * + * @param base SDHC peripheral base address. + * @param command Command to be sent. + */ +static status_t SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command); + +/*! + * @brief Read DATAPORT when buffer enable bit is set. + * + * @param base SDHC peripheral base address. + * @param data Data to be read. + * @param transferredWords The number of data words have been transferred last time transaction. + * @return The number of total data words have been transferred after this time transaction. + */ +static uint32_t SDHC_ReadDataPort(SDHC_Type *base, sdhc_data_t *data, uint32_t transferredWords); + +/*! + * @brief Read data by using DATAPORT polling way. + * + * @param base SDHC peripheral base address. + * @param data Data to be read. + * @retval kStatus_Fail Read DATAPORT failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDHC_ReadByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data); + +/*! + * @brief Write DATAPORT when buffer enable bit is set. + * + * @param base SDHC peripheral base address. + * @param data Data to be read. + * @param transferredWords The number of data words have been transferred last time. + * @return The number of total data words have been transferred after this time transaction. + */ +static uint32_t SDHC_WriteDataPort(SDHC_Type *base, sdhc_data_t *data, uint32_t transferredWords); + +/*! + * @brief Write data by using DATAPORT polling way. + * + * @param base SDHC peripheral base address. + * @param data Data to be transferred. + * @retval kStatus_Fail Write DATAPORT failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDHC_WriteByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data); + +/*! + * @brief Send command by using polling way. + * + * @param base SDHC peripheral base address. + * @param command Command to be sent. + * @retval kStatus_Fail Send command failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDHC_SendCommandBlocking(SDHC_Type *base, sdhc_command_t *command); + +/*! + * @brief Transfer data by DATAPORT and polling way. + * + * @param base SDHC peripheral base address. + * @param data Data to be transferred. + * @retval kStatus_Fail Transfer data failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDHC_TransferByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data); + +/*! + * @brief Transfer data by ADMA2 and polling way. + * + * @param base SDHC peripheral base address. + * @param data Data to be transferred. + * @retval kStatus_Fail Transfer data failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDHC_TransferByAdma2Blocking(SDHC_Type *base, sdhc_data_t *data); + +/*! + * @brief Transfer data by polling way. + * + * @param dmaMode DMA mode. + * @param base SDHC peripheral base address. + * @param data Data to be transferred. + * @retval kStatus_Fail Transfer data failed. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_Success Operate successfully. + */ +static status_t SDHC_TransferDataBlocking(sdhc_dma_mode_t dmaMode, SDHC_Type *base, sdhc_data_t *data); + +/*! + * @brief Handle card detect interrupt. + * + * @param handle SDHC handle. + * @param interruptFlags Card detect related interrupt flags. + */ +static void SDHC_TransferHandleCardDetect(sdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle command interrupt. + * + * @param base SDHC peripheral base address. + * @param handle SDHC handle. + * @param interruptFlags Command related interrupt flags. + */ +static void SDHC_TransferHandleCommand(SDHC_Type *base, sdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle data interrupt. + * + * @param base SDHC peripheral base address. + * @param handle SDHC handle. + * @param interruptFlags Data related interrupt flags. + */ +static void SDHC_TransferHandleData(SDHC_Type *base, sdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle SDIO card interrupt signal. + * + * @param handle SDHC handle. + */ +static void SDHC_TransferHandleSdioInterrupt(sdhc_handle_t *handle); + +/*! + * @brief Handle SDIO block gap event. + * + * @param handle SDHC handle. + */ +static void SDHC_TransferHandleSdioBlockGap(sdhc_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief SDHC internal handle pointer array */ +static sdhc_handle_t *s_sdhcHandle[FSL_FEATURE_SOC_SDHC_COUNT]; + +/*! @brief SDHC base pointer array */ +static SDHC_Type *const s_sdhcBase[] = SDHC_BASE_PTRS; + +/*! @brief SDHC IRQ name array */ +static const IRQn_Type s_sdhcIRQ[] = SDHC_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief SDHC clock array name */ +static const clock_ip_name_t s_sdhcClock[] = SDHC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* SDHC ISR for transactional APIs. */ +static sdhc_isr_t s_sdhcIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t SDHC_GetInstance(SDHC_Type *base) +{ + uint8_t instance = 0; + + while ((instance < ARRAY_SIZE(s_sdhcBase)) && (s_sdhcBase[instance] != base)) + { + instance++; + } + + assert(instance < ARRAY_SIZE(s_sdhcBase)); + + return instance; +} + +static void SDHC_SetTransferInterrupt(SDHC_Type *base, bool usingInterruptSignal) +{ + uint32_t interruptEnabled; /* The Interrupt status flags to be enabled */ + bool cardDetectDat3 = (bool)(base->PROCTL & SDHC_PROCTL_D3CD_MASK); + + /* Disable all interrupts */ + SDHC_DisableInterruptStatus(base, (uint32_t)kSDHC_AllInterruptFlags); + SDHC_DisableInterruptSignal(base, (uint32_t)kSDHC_AllInterruptFlags); + DisableIRQ(s_sdhcIRQ[SDHC_GetInstance(base)]); + + interruptEnabled = + (kSDHC_CommandIndexErrorFlag | kSDHC_CommandCrcErrorFlag | kSDHC_CommandEndBitErrorFlag | + kSDHC_CommandTimeoutFlag | kSDHC_CommandCompleteFlag | kSDHC_DataTimeoutFlag | kSDHC_DataCrcErrorFlag | + kSDHC_DataEndBitErrorFlag | kSDHC_DataCompleteFlag | kSDHC_AutoCommand12ErrorFlag | kSDHC_BufferReadReadyFlag | + kSDHC_BufferWriteReadyFlag | kSDHC_DmaErrorFlag | kSDHC_DmaCompleteFlag); + if (cardDetectDat3) + { + interruptEnabled |= (kSDHC_CardInsertionFlag | kSDHC_CardRemovalFlag); + } + + SDHC_EnableInterruptStatus(base, interruptEnabled); + if (usingInterruptSignal) + { + SDHC_EnableInterruptSignal(base, interruptEnabled); + } +} + +static void SDHC_StartTransfer(SDHC_Type *base, sdhc_command_t *command, sdhc_data_t *data, sdhc_dma_mode_t dmaMode) +{ + uint32_t flags = 0U; + sdhc_transfer_config_t sdhcTransferConfig = {0}; + + /* Define the flag corresponding to each response type. */ + switch (command->responseType) + { + case kCARD_ResponseTypeNone: + break; + case kCARD_ResponseTypeR1: /* Response 1 */ + flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag); + break; + case kCARD_ResponseTypeR1b: /* Response 1 with busy */ + flags |= (kSDHC_ResponseLength48BusyFlag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag); + break; + case kCARD_ResponseTypeR2: /* Response 2 */ + flags |= (kSDHC_ResponseLength136Flag | kSDHC_EnableCrcCheckFlag); + break; + case kCARD_ResponseTypeR3: /* Response 3 */ + flags |= (kSDHC_ResponseLength48Flag); + break; + case kCARD_ResponseTypeR4: /* Response 4 */ + flags |= (kSDHC_ResponseLength48Flag); + break; + case kCARD_ResponseTypeR5: /* Response 5 */ + flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag); + break; + case kCARD_ResponseTypeR5b: /* Response 5 with busy */ + flags |= (kSDHC_ResponseLength48BusyFlag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag); + break; + case kCARD_ResponseTypeR6: /* Response 6 */ + flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag); + break; + case kCARD_ResponseTypeR7: /* Response 7 */ + flags |= (kSDHC_ResponseLength48Flag | kSDHC_EnableCrcCheckFlag | kSDHC_EnableIndexCheckFlag); + break; + default: + break; + } + if (command->type == kCARD_CommandTypeAbort) + { + flags |= kSDHC_CommandTypeAbortFlag; + } + + if (data) + { + flags |= kSDHC_DataPresentFlag; + + if (dmaMode != kSDHC_DmaModeNo) + { + flags |= kSDHC_EnableDmaFlag; + } + if (data->rxData) + { + flags |= kSDHC_DataReadFlag; + } + if (data->blockCount > 1U) + { + flags |= (kSDHC_MultipleBlockFlag | kSDHC_EnableBlockCountFlag); + if (data->enableAutoCommand12) + { + /* Enable Auto command 12. */ + flags |= kSDHC_EnableAutoCommand12Flag; + } + } + + sdhcTransferConfig.dataBlockSize = data->blockSize; + sdhcTransferConfig.dataBlockCount = data->blockCount; + } + else + { + sdhcTransferConfig.dataBlockSize = 0U; + sdhcTransferConfig.dataBlockCount = 0U; + } + + sdhcTransferConfig.commandArgument = command->argument; + sdhcTransferConfig.commandIndex = command->index; + sdhcTransferConfig.flags = flags; + SDHC_SetTransferConfig(base, &sdhcTransferConfig); +} + +static status_t SDHC_ReceiveCommandResponse(SDHC_Type *base, sdhc_command_t *command) +{ + uint32_t i; + + if (command->responseType != kCARD_ResponseTypeNone) + { + command->response[0U] = SDHC_GetCommandResponse(base, 0U); + if (command->responseType == kCARD_ResponseTypeR2) + { + command->response[1U] = SDHC_GetCommandResponse(base, 1U); + command->response[2U] = SDHC_GetCommandResponse(base, 2U); + command->response[3U] = SDHC_GetCommandResponse(base, 3U); + + i = 4U; + /* R3-R2-R1-R0(lowest 8 bit is invalid bit) has the same format as R2 format in SD specification document + after removed internal CRC7 and end bit. */ + do + { + command->response[i - 1U] <<= 8U; + if (i > 1U) + { + command->response[i - 1U] |= ((command->response[i - 2U] & 0xFF000000U) >> 24U); + } + } while (i--); + } + } + /* check response error flag */ + if ((command->responseErrorFlags != 0U) && + ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) || + (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5))) + { + if (((command->responseErrorFlags) & (command->response[0U])) != 0U) + { + return kStatus_SDHC_SendCommandFailed; + } + } + + return kStatus_Success; +} + +static uint32_t SDHC_ReadDataPort(SDHC_Type *base, sdhc_data_t *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeRead; /* The words can be read at this time. */ + uint32_t readWatermark = ((base->WML & SDHC_WML_RDWML_MASK) >> SDHC_WML_RDWML_SHIFT); + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ + if (readWatermark >= totalWords) + { + wordsCanBeRead = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, + transfers watermark level words. */ + else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) + { + wordsCanBeRead = readWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers left + words. */ + else + { + wordsCanBeRead = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeRead) + { + data->rxData[transferredWords++] = SDHC_ReadData(base); + i++; + } + + return transferredWords; +} + +static status_t SDHC_ReadByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data) +{ + uint32_t totalWords; + uint32_t transferredWords = 0U; + status_t error = kStatus_Success; + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + while ((error == kStatus_Success) && (transferredWords < totalWords)) + { + while (!(SDHC_GetInterruptStatusFlags(base) & (kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag))) + { + } + + if (SDHC_GetInterruptStatusFlags(base) & kSDHC_DataErrorFlag) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + if (error == kStatus_Success) + { + transferredWords = SDHC_ReadDataPort(base, data, transferredWords); + } + /* clear buffer ready and error */ + SDHC_ClearInterruptStatusFlags(base, kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag); + } + + /* Clear data complete flag after the last read operation. */ + SDHC_ClearInterruptStatusFlags(base, kSDHC_DataCompleteFlag | kSDHC_DataErrorFlag); + + return error; +} + +static uint32_t SDHC_WriteDataPort(SDHC_Type *base, sdhc_data_t *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeWrote; /* Words can be wrote at this time. */ + uint32_t writeWatermark = ((base->WML & SDHC_WML_WRWML_MASK) >> SDHC_WML_WRWML_SHIFT); + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data.*/ + if (writeWatermark >= totalWords) + { + wordsCanBeWrote = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than watermark, + transfers watermark level words. */ + else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) + { + wordsCanBeWrote = writeWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than watermark, transfers left + words. */ + else + { + wordsCanBeWrote = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeWrote) + { + SDHC_WriteData(base, data->txData[transferredWords++]); + i++; + } + + return transferredWords; +} + +static status_t SDHC_WriteByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data) +{ + uint32_t totalWords; + uint32_t transferredWords = 0U; + status_t error = kStatus_Success; + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = (data->blockCount * data->blockSize) / sizeof(uint32_t); + + while ((error == kStatus_Success) && (transferredWords < totalWords)) + { + while (!(SDHC_GetInterruptStatusFlags(base) & (kSDHC_BufferWriteReadyFlag | kSDHC_DataErrorFlag))) + { + } + + if (SDHC_GetInterruptStatusFlags(base) & kSDHC_DataErrorFlag) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + if (error == kStatus_Success) + { + transferredWords = SDHC_WriteDataPort(base, data, transferredWords); + } + + /* Clear buffer enable flag to trigger transfer. Clear error flag when SDHC encounter error. */ + SDHC_ClearInterruptStatusFlags(base, (kSDHC_BufferWriteReadyFlag | kSDHC_DataErrorFlag)); + } + + /* Wait write data complete or data transfer error after the last writing operation. */ + while (!(SDHC_GetInterruptStatusFlags(base) & (kSDHC_DataCompleteFlag | kSDHC_DataErrorFlag))) + { + } + if (SDHC_GetInterruptStatusFlags(base) & kSDHC_DataErrorFlag) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + + SDHC_ClearInterruptStatusFlags(base, (kSDHC_DataCompleteFlag | kSDHC_DataErrorFlag)); + + return error; +} + +static status_t SDHC_SendCommandBlocking(SDHC_Type *base, sdhc_command_t *command) +{ + status_t error = kStatus_Success; + + /* Wait command complete or SDHC encounters error. */ + while (!(SDHC_GetInterruptStatusFlags(base) & (kSDHC_CommandCompleteFlag | kSDHC_CommandErrorFlag))) + { + } + + if (SDHC_GetInterruptStatusFlags(base) & kSDHC_CommandErrorFlag) + { + error = kStatus_Fail; + } + /* Receive response when command completes successfully. */ + if (error == kStatus_Success) + { + error = SDHC_ReceiveCommandResponse(base, command); + } + + SDHC_ClearInterruptStatusFlags(base, (kSDHC_CommandCompleteFlag | kSDHC_CommandErrorFlag)); + + return error; +} + +static status_t SDHC_TransferByDataPortBlocking(SDHC_Type *base, sdhc_data_t *data) +{ + status_t error = kStatus_Success; + + if (data->rxData) + { + error = SDHC_ReadByDataPortBlocking(base, data); + } + else + { + error = SDHC_WriteByDataPortBlocking(base, data); + } + + return error; +} + +static status_t SDHC_TransferByAdma2Blocking(SDHC_Type *base, sdhc_data_t *data) +{ + status_t error = kStatus_Success; + + /* Wait data complete or SDHC encounters error. */ + while (!(SDHC_GetInterruptStatusFlags(base) & (kSDHC_DataCompleteFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag))) + { + } + if (SDHC_GetInterruptStatusFlags(base) & (kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag)) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + SDHC_ClearInterruptStatusFlags( + base, (kSDHC_DataCompleteFlag | kSDHC_DmaCompleteFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag)); + return error; +} + +#if defined FSL_SDHC_ENABLE_ADMA1 +#define SDHC_TransferByAdma1Blocking(base, data) SDHC_TransferByAdma2Blocking(base, data) +#endif /* FSL_SDHC_ENABLE_ADMA1 */ + +static status_t SDHC_TransferDataBlocking(sdhc_dma_mode_t dmaMode, SDHC_Type *base, sdhc_data_t *data) +{ + status_t error = kStatus_Success; + + switch (dmaMode) + { + case kSDHC_DmaModeNo: + error = SDHC_TransferByDataPortBlocking(base, data); + break; +#if defined FSL_SDHC_ENABLE_ADMA1 + case kSDHC_DmaModeAdma1: + error = SDHC_TransferByAdma1Blocking(base, data); + break; +#endif /* FSL_SDHC_ENABLE_ADMA1 */ + case kSDHC_DmaModeAdma2: + error = SDHC_TransferByAdma2Blocking(base, data); + break; + default: + error = kStatus_InvalidArgument; + break; + } + + return error; +} + +static void SDHC_TransferHandleCardDetect(sdhc_handle_t *handle, uint32_t interruptFlags) +{ + if (interruptFlags & kSDHC_CardInsertionFlag) + { + if (handle->callback.CardInserted) + { + handle->callback.CardInserted(); + } + } + else + { + if (handle->callback.CardRemoved) + { + handle->callback.CardRemoved(); + } + } +} + +static void SDHC_TransferHandleCommand(SDHC_Type *base, sdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->command); + + if ((interruptFlags & kSDHC_CommandErrorFlag) && (!(handle->data)) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_SDHC_SendCommandFailed, handle->userData); + } + else + { + /* Receive response */ + SDHC_ReceiveCommandResponse(base, handle->command); + if ((!(handle->data)) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + } +} + +static void SDHC_TransferHandleData(SDHC_Type *base, sdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->data); + + if ((!(handle->data->enableIgnoreError)) && (interruptFlags & (kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag)) && + (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_SDHC_TransferDataFailed, handle->userData); + } + else + { + if (interruptFlags & kSDHC_BufferReadReadyFlag) + { + handle->transferredWords = SDHC_ReadDataPort(base, handle->data, handle->transferredWords); + } + else if (interruptFlags & kSDHC_BufferWriteReadyFlag) + { + handle->transferredWords = SDHC_WriteDataPort(base, handle->data, handle->transferredWords); + } + else + { + } + + if ((interruptFlags & kSDHC_DataCompleteFlag) && (handle->callback.TransferComplete)) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + else + { + /* Do nothing when DMA complete flag is set. Wait until data complete flag is set. */ + } + } +} + +static void SDHC_TransferHandleSdioInterrupt(sdhc_handle_t *handle) +{ + if (handle->callback.SdioInterrupt) + { + handle->callback.SdioInterrupt(); + } +} + +static void SDHC_TransferHandleSdioBlockGap(sdhc_handle_t *handle) +{ + if (handle->callback.SdioBlockGap) + { + handle->callback.SdioBlockGap(); + } +} + +void SDHC_Init(SDHC_Type *base, const sdhc_config_t *config) +{ + assert(config); +#if !defined FSL_SDHC_ENABLE_ADMA1 + assert(config->dmaMode != kSDHC_DmaModeAdma1); +#endif /* FSL_SDHC_ENABLE_ADMA1 */ + assert((config->writeWatermarkLevel >= 1U) && (config->writeWatermarkLevel <= 128U)); + assert((config->readWatermarkLevel >= 1U) && (config->readWatermarkLevel <= 128U)); + + uint32_t proctl; + uint32_t wml; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable SDHC clock. */ + CLOCK_EnableClock(s_sdhcClock[SDHC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset SDHC. */ + SDHC_Reset(base, kSDHC_ResetAll, 100); + + proctl = base->PROCTL; + wml = base->WML; + + proctl &= ~(SDHC_PROCTL_D3CD_MASK | SDHC_PROCTL_EMODE_MASK | SDHC_PROCTL_DMAS_MASK); + /* Set DAT3 as card detection pin */ + if (config->cardDetectDat3) + { + proctl |= SDHC_PROCTL_D3CD_MASK; + } + /* Endian mode and DMA mode */ + proctl |= (SDHC_PROCTL_EMODE(config->endianMode) | SDHC_PROCTL_DMAS(config->dmaMode)); + + /* Watermark level */ + wml &= ~(SDHC_WML_RDWML_MASK | SDHC_WML_WRWML_MASK); + wml |= (SDHC_WML_RDWML(config->readWatermarkLevel) | SDHC_WML_WRWML(config->writeWatermarkLevel)); + + base->WML = wml; + base->PROCTL = proctl; + + /* Disable all clock auto gated off feature because of DAT0 line logic(card buffer full status) can't be updated + correctly when clock auto gated off is enabled. */ + base->SYSCTL |= (SDHC_SYSCTL_PEREN_MASK | SDHC_SYSCTL_HCKEN_MASK | SDHC_SYSCTL_IPGEN_MASK); + + /* Enable interrupt status but doesn't enable interrupt signal. */ + SDHC_SetTransferInterrupt(base, false); +} + +void SDHC_Deinit(SDHC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable clock. */ + CLOCK_DisableClock(s_sdhcClock[SDHC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +bool SDHC_Reset(SDHC_Type *base, uint32_t mask, uint32_t timeout) +{ + base->SYSCTL |= (mask & (SDHC_SYSCTL_RSTA_MASK | SDHC_SYSCTL_RSTC_MASK | SDHC_SYSCTL_RSTD_MASK)); + /* Delay some time to wait reset success. */ + while ((base->SYSCTL & mask)) + { + if (!timeout) + { + break; + } + timeout--; + } + + return ((!timeout) ? false : true); +} + +void SDHC_GetCapability(SDHC_Type *base, sdhc_capability_t *capability) +{ + assert(capability); + + uint32_t htCapability; + uint32_t hostVer; + uint32_t maxBlockLength; + + hostVer = base->HOSTVER; + htCapability = base->HTCAPBLT; + + /* Get the capability of SDHC. */ + capability->specVersion = ((hostVer & SDHC_HOSTVER_SVN_MASK) >> SDHC_HOSTVER_SVN_SHIFT); + capability->vendorVersion = ((hostVer & SDHC_HOSTVER_VVN_MASK) >> SDHC_HOSTVER_VVN_SHIFT); + maxBlockLength = ((htCapability & SDHC_HTCAPBLT_MBL_MASK) >> SDHC_HTCAPBLT_MBL_SHIFT); + capability->maxBlockLength = (512U << maxBlockLength); + /* Other attributes not in HTCAPBLT register. */ + capability->maxBlockCount = SDHC_MAX_BLOCK_COUNT; + capability->flags = (htCapability & (kSDHC_SupportAdmaFlag | kSDHC_SupportHighSpeedFlag | kSDHC_SupportDmaFlag | + kSDHC_SupportSuspendResumeFlag | kSDHC_SupportV330Flag)); +#if defined FSL_FEATURE_SDHC_HAS_V300_SUPPORT && FSL_FEATURE_SDHC_HAS_V300_SUPPORT + capability->flags |= (htCapability & kSDHC_SupportV300Flag); +#endif +#if defined FSL_FEATURE_SDHC_HAS_V180_SUPPORT && FSL_FEATURE_SDHC_HAS_V180_SUPPORT + capability->flags |= (htCapability & kSDHC_SupportV180Flag); +#endif + /* eSDHC on all kinetis boards will support 4/8 bit data bus width. */ + capability->flags |= (kSDHC_Support4BitFlag | kSDHC_Support8BitFlag); +} + +uint32_t SDHC_SetSdClock(SDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz) +{ + assert(srcClock_Hz != 0U); + assert((busClock_Hz != 0U) && (busClock_Hz <= srcClock_Hz)); + + uint32_t totalDiv = 0U; + uint32_t divisor = 0U; + uint32_t prescaler = 0U; + uint32_t sysctl = 0U; + uint32_t nearestFrequency = 0U; + + /* calucate total divisor first */ + totalDiv = srcClock_Hz / busClock_Hz; + + if (totalDiv != 0U) + { + /* calucate the divisor (srcClock_Hz / divisor) <= busClock_Hz */ + if ((srcClock_Hz / totalDiv) > busClock_Hz) + { + totalDiv++; + } + + /* divide the total divisor to div and prescaler */ + if (totalDiv > SDHC_MAX_DVS) + { + prescaler = totalDiv / SDHC_MAX_DVS; + /* prescaler must be a value which equal 2^n and smaller than SDHC_MAX_CLKFS */ + while (((SDHC_MAX_CLKFS % prescaler) != 0U) || (prescaler == 1U)) + { + prescaler++; + } + /* calucate the divisor */ + divisor = totalDiv / prescaler; + /* fine tuning the divisor until divisor * prescaler >= totalDiv */ + while ((divisor * prescaler) < totalDiv) + { + divisor++; + } + nearestFrequency = srcClock_Hz / divisor / prescaler; + } + else + { + divisor = totalDiv; + prescaler = 0U; + nearestFrequency = srcClock_Hz / divisor; + } + } + /* in this condition , srcClock_Hz = busClock_Hz, */ + else + { + /* total divider = 1U */ + divisor = 0U; + prescaler = 0U; + nearestFrequency = srcClock_Hz; + } + + /* calucate the value write to register */ + if (divisor != 0U) + { + SDHC_PREV_DVS(divisor); + } + /* calucate the value write to register */ + if (prescaler != 0U) + { + SDHC_PREV_CLKFS(prescaler); + } + + /* Disable SD clock. It should be disabled before changing the SD clock frequency.*/ + base->SYSCTL &= ~SDHC_SYSCTL_SDCLKEN_MASK; + + /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */ + sysctl = base->SYSCTL; + sysctl &= ~(SDHC_SYSCTL_DVS_MASK | SDHC_SYSCTL_SDCLKFS_MASK | SDHC_SYSCTL_DTOCV_MASK); + sysctl |= (SDHC_SYSCTL_DVS(divisor) | SDHC_SYSCTL_SDCLKFS(prescaler) | SDHC_SYSCTL_DTOCV(0xEU)); + base->SYSCTL = sysctl; + + /* Wait until the SD clock is stable. */ + while (!(base->PRSSTAT & SDHC_PRSSTAT_SDSTB_MASK)) + { + } + /* Enable the SD clock. */ + base->SYSCTL |= SDHC_SYSCTL_SDCLKEN_MASK; + + return nearestFrequency; +} + +bool SDHC_SetCardActive(SDHC_Type *base, uint32_t timeout) +{ + base->SYSCTL |= SDHC_SYSCTL_INITA_MASK; + /* Delay some time to wait card become active state. */ + while (base->SYSCTL & SDHC_SYSCTL_INITA_MASK) + { + if (!timeout) + { + break; + } + timeout--; + } + + return ((!timeout) ? false : true); +} + +void SDHC_SetTransferConfig(SDHC_Type *base, const sdhc_transfer_config_t *config) +{ + assert(config); + assert(config->dataBlockSize <= (SDHC_BLKATTR_BLKSIZE_MASK >> SDHC_BLKATTR_BLKSIZE_SHIFT)); + assert(config->dataBlockCount <= (SDHC_BLKATTR_BLKCNT_MASK >> SDHC_BLKATTR_BLKCNT_SHIFT)); + + base->BLKATTR = ((base->BLKATTR & ~(SDHC_BLKATTR_BLKSIZE_MASK | SDHC_BLKATTR_BLKCNT_MASK)) | + (SDHC_BLKATTR_BLKSIZE(config->dataBlockSize) | SDHC_BLKATTR_BLKCNT(config->dataBlockCount))); + base->CMDARG = config->commandArgument; + base->XFERTYP = (((config->commandIndex << SDHC_XFERTYP_CMDINX_SHIFT) & SDHC_XFERTYP_CMDINX_MASK) | + (config->flags & (SDHC_XFERTYP_DMAEN_MASK | SDHC_XFERTYP_MSBSEL_MASK | SDHC_XFERTYP_DPSEL_MASK | + SDHC_XFERTYP_CMDTYP_MASK | SDHC_XFERTYP_BCEN_MASK | SDHC_XFERTYP_CICEN_MASK | + SDHC_XFERTYP_CCCEN_MASK | SDHC_XFERTYP_RSPTYP_MASK | SDHC_XFERTYP_DTDSEL_MASK | + SDHC_XFERTYP_AC12EN_MASK))); +} + +void SDHC_EnableSdioControl(SDHC_Type *base, uint32_t mask, bool enable) +{ + uint32_t proctl = base->PROCTL; + uint32_t vendor = base->VENDOR; + + if (enable) + { + if (mask & kSDHC_StopAtBlockGapFlag) + { + proctl |= SDHC_PROCTL_SABGREQ_MASK; + } + if (mask & kSDHC_ReadWaitControlFlag) + { + proctl |= SDHC_PROCTL_RWCTL_MASK; + } + if (mask & kSDHC_InterruptAtBlockGapFlag) + { + proctl |= SDHC_PROCTL_IABG_MASK; + } + if (mask & kSDHC_ExactBlockNumberReadFlag) + { + vendor |= SDHC_VENDOR_EXBLKNU_MASK; + } + } + else + { + if (mask & kSDHC_StopAtBlockGapFlag) + { + proctl &= ~SDHC_PROCTL_SABGREQ_MASK; + } + if (mask & kSDHC_ReadWaitControlFlag) + { + proctl &= ~SDHC_PROCTL_RWCTL_MASK; + } + if (mask & kSDHC_InterruptAtBlockGapFlag) + { + proctl &= ~SDHC_PROCTL_IABG_MASK; + } + if (mask & kSDHC_ExactBlockNumberReadFlag) + { + vendor &= ~SDHC_VENDOR_EXBLKNU_MASK; + } + } + + base->PROCTL = proctl; + base->VENDOR = vendor; +} + +void SDHC_SetMmcBootConfig(SDHC_Type *base, const sdhc_boot_config_t *config) +{ + assert(config); + assert(config->ackTimeoutCount <= (SDHC_MMCBOOT_DTOCVACK_MASK >> SDHC_MMCBOOT_DTOCVACK_SHIFT)); + assert(config->blockCount <= (SDHC_MMCBOOT_BOOTBLKCNT_MASK >> SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)); + + uint32_t mmcboot = 0U; + + mmcboot = (SDHC_MMCBOOT_DTOCVACK(config->ackTimeoutCount) | SDHC_MMCBOOT_BOOTMODE(config->bootMode) | + SDHC_MMCBOOT_BOOTBLKCNT(config->blockCount)); + if (config->enableBootAck) + { + mmcboot |= SDHC_MMCBOOT_BOOTACK_MASK; + } + if (config->enableBoot) + { + mmcboot |= SDHC_MMCBOOT_BOOTEN_MASK; + } + if (config->enableAutoStopAtBlockGap) + { + mmcboot |= SDHC_MMCBOOT_AUTOSABGEN_MASK; + } + base->MMCBOOT = mmcboot; +} + +status_t SDHC_SetAdmaTableConfig(SDHC_Type *base, + sdhc_dma_mode_t dmaMode, + uint32_t *table, + uint32_t tableWords, + const uint32_t *data, + uint32_t dataBytes) +{ + status_t error = kStatus_Success; + const uint32_t *startAddress = data; + uint32_t entries; + uint32_t i; +#if defined FSL_SDHC_ENABLE_ADMA1 + sdhc_adma1_descriptor_t *adma1EntryAddress; +#endif + sdhc_adma2_descriptor_t *adma2EntryAddress; + + if ((((!table) || (!tableWords)) && ((dmaMode == kSDHC_DmaModeAdma1) || (dmaMode == kSDHC_DmaModeAdma2))) || + (!data) || (!dataBytes) +#if !defined FSL_SDHC_ENABLE_ADMA1 + || (dmaMode == kSDHC_DmaModeAdma1) +#endif + ) + { + error = kStatus_InvalidArgument; + } + else if (((dmaMode == kSDHC_DmaModeAdma2) && (((uint32_t)startAddress % SDHC_ADMA2_LENGTH_ALIGN) != 0U)) +#if defined FSL_SDHC_ENABLE_ADMA1 + || ((dmaMode == kSDHC_DmaModeAdma1) && (((uint32_t)startAddress % SDHC_ADMA1_LENGTH_ALIGN) != 0U)) +#endif + ) + { + error = kStatus_SDHC_DMADataBufferAddrNotAlign; + } + else + { + switch (dmaMode) + { + case kSDHC_DmaModeNo: + break; +#if defined FSL_SDHC_ENABLE_ADMA1 + case kSDHC_DmaModeAdma1: + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (dataBytes % sizeof(uint32_t) != 0U) + { + dataBytes += + sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); /* make the data length as word-aligned */ + } + + /* Check if ADMA descriptor's number is enough. */ + entries = ((dataBytes / SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); + /* ADMA1 needs two descriptors to finish a transfer */ + entries <<= 1U; + if (entries > ((tableWords * sizeof(uint32_t)) / sizeof(sdhc_adma1_descriptor_t))) + { + error = kStatus_OutOfRange; + } + else + { + adma1EntryAddress = (sdhc_adma1_descriptor_t *)(table); + for (i = 0U; i < entries; i += 2U) + { + /* Each descriptor for ADMA1 is 32-bit in length */ + if ((dataBytes - sizeof(uint32_t) * (startAddress - data)) <= + SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + { + /* The last piece of data, setting end flag in descriptor */ + adma1EntryAddress[i] = ((uint32_t)(dataBytes - sizeof(uint32_t) * (startAddress - data)) + << SDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT); + adma1EntryAddress[i] |= kSDHC_Adma1DescriptorTypeSetLength; + adma1EntryAddress[i + 1U] = + ((uint32_t)(startAddress) << SDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT); + adma1EntryAddress[i + 1U] |= + (kSDHC_Adma1DescriptorTypeTransfer | kSDHC_Adma1DescriptorEndFlag); + } + else + { + adma1EntryAddress[i] = ((uint32_t)SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY + << SDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT); + adma1EntryAddress[i] |= kSDHC_Adma1DescriptorTypeSetLength; + adma1EntryAddress[i + 1U] = + ((uint32_t)(startAddress) << SDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT); + adma1EntryAddress[i + 1U] |= kSDHC_Adma1DescriptorTypeTransfer; + startAddress += SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY / sizeof(uint32_t); + } + } + + /* When use ADMA, disable simple DMA */ + base->DSADDR = 0U; + base->ADSADDR = (uint32_t)table; + /* disable the buffer ready flag in DMA mode */ + SDHC_DisableInterruptSignal(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); + SDHC_DisableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); + } + break; +#endif /* FSL_SDHC_ENABLE_ADMA1 */ + case kSDHC_DmaModeAdma2: + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (dataBytes % sizeof(uint32_t) != 0U) + { + dataBytes += + sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); /* make the data length as word-aligned */ + } + + /* Check if ADMA descriptor's number is enough. */ + entries = ((dataBytes / SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); + if (entries > ((tableWords * sizeof(uint32_t)) / sizeof(sdhc_adma2_descriptor_t))) + { + error = kStatus_OutOfRange; + } + else + { + adma2EntryAddress = (sdhc_adma2_descriptor_t *)(table); + for (i = 0U; i < entries; i++) + { + /* Each descriptor for ADMA2 is 64-bit in length */ + if ((dataBytes - sizeof(uint32_t) * (startAddress - data)) <= + SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + { + /* The last piece of data, setting end flag in descriptor */ + adma2EntryAddress[i].address = startAddress; + adma2EntryAddress[i].attribute = ((dataBytes - sizeof(uint32_t) * (startAddress - data)) + << SDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT); + adma2EntryAddress[i].attribute |= + (kSDHC_Adma2DescriptorTypeTransfer | kSDHC_Adma2DescriptorEndFlag); + } + else + { + adma2EntryAddress[i].address = startAddress; + adma2EntryAddress[i].attribute = + (((SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY / sizeof(uint32_t)) * sizeof(uint32_t)) + << SDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT); + adma2EntryAddress[i].attribute |= kSDHC_Adma2DescriptorTypeTransfer; + startAddress += (SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY / sizeof(uint32_t)); + } + } + + /* When use ADMA, disable simple DMA */ + base->DSADDR = 0U; + base->ADSADDR = (uint32_t)table; + /* disable the buffer read flag in DMA mode */ + SDHC_DisableInterruptSignal(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); + SDHC_DisableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); + } + break; + default: + break; + } + } + + return error; +} + +status_t SDHC_TransferBlocking(SDHC_Type *base, uint32_t *admaTable, uint32_t admaTableWords, sdhc_transfer_t *transfer) +{ + assert(transfer); + + status_t error = kStatus_Success; + sdhc_dma_mode_t dmaMode = (sdhc_dma_mode_t)((base->PROCTL & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT); + sdhc_command_t *command = transfer->command; + sdhc_data_t *data = transfer->data; + + /* make sure the cmd/block count is valid */ + if ((!command) || (data && (data->blockCount > SDHC_MAX_BLOCK_COUNT))) + { + return kStatus_InvalidArgument; + } + + /* Wait until command/data bus out of busy status. */ + while (SDHC_GetPresentStatusFlags(base) & kSDHC_CommandInhibitFlag) + { + } + while (data && (SDHC_GetPresentStatusFlags(base) & kSDHC_DataInhibitFlag)) + { + } + + /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ + if (data && (NULL != admaTable)) + { + error = + SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords, + (data->rxData ? data->rxData : data->txData), (data->blockCount * data->blockSize)); + /* in this situation , we disable the DMA instead of polling transfer mode */ + if (error == kStatus_SDHC_DMADataBufferAddrNotAlign) + { + dmaMode = kSDHC_DmaModeNo; + SDHC_EnableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); + } + else if (error != kStatus_Success) + { + return error; + } + else + { + } + } + + /* Send command and receive data. */ + SDHC_StartTransfer(base, command, data, dmaMode); + if (kStatus_Success != SDHC_SendCommandBlocking(base, command)) + { + return kStatus_SDHC_SendCommandFailed; + } + else if (data && (kStatus_Success != SDHC_TransferDataBlocking(dmaMode, base, data))) + { + return kStatus_SDHC_TransferDataFailed; + } + else + { + } + + return kStatus_Success; +} + +void SDHC_TransferCreateHandle(SDHC_Type *base, + sdhc_handle_t *handle, + const sdhc_transfer_callback_t *callback, + void *userData) +{ + assert(handle); + assert(callback); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the callback. */ + handle->callback.CardInserted = callback->CardInserted; + handle->callback.CardRemoved = callback->CardRemoved; + handle->callback.SdioInterrupt = callback->SdioInterrupt; + handle->callback.SdioBlockGap = callback->SdioBlockGap; + handle->callback.TransferComplete = callback->TransferComplete; + handle->userData = userData; + + /* Save the handle in global variables to support the double weak mechanism. */ + s_sdhcHandle[SDHC_GetInstance(base)] = handle; + + /* Enable interrupt in NVIC. */ + SDHC_SetTransferInterrupt(base, true); + + /* save IRQ handler */ + s_sdhcIsr = SDHC_TransferHandleIRQ; + + EnableIRQ(s_sdhcIRQ[SDHC_GetInstance(base)]); +} + +status_t SDHC_TransferNonBlocking( + SDHC_Type *base, sdhc_handle_t *handle, uint32_t *admaTable, uint32_t admaTableWords, sdhc_transfer_t *transfer) +{ + assert(transfer); + + sdhc_dma_mode_t dmaMode = (sdhc_dma_mode_t)((base->PROCTL & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT); + status_t error = kStatus_Success; + sdhc_command_t *command = transfer->command; + sdhc_data_t *data = transfer->data; + + /* make sure cmd/block count is valid */ + if ((!command) || (data && (data->blockCount > SDHC_MAX_BLOCK_COUNT))) + { + return kStatus_InvalidArgument; + } + + /* Wait until command/data bus out of busy status. */ + if ((SDHC_GetPresentStatusFlags(base) & kSDHC_CommandInhibitFlag) || + (data && (SDHC_GetPresentStatusFlags(base) & kSDHC_DataInhibitFlag))) + { + return kStatus_SDHC_BusyTransferring; + } + + /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ + if (data && (NULL != admaTable)) + { + error = + SDHC_SetAdmaTableConfig(base, dmaMode, admaTable, admaTableWords, + (data->rxData ? data->rxData : data->txData), (data->blockCount * data->blockSize)); + /* in this situation , we disable the DMA instead of polling transfer mode */ + if (error == kStatus_SDHC_DMADataBufferAddrNotAlign) + { + /* change to polling mode */ + dmaMode = kSDHC_DmaModeNo; + SDHC_EnableInterruptSignal(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); + SDHC_EnableInterruptStatus(base, kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag); + } + else if (error != kStatus_Success) + { + return error; + } + else + { + } + } + + /* Save command and data into handle before transferring. */ + handle->command = command; + handle->data = data; + handle->interruptFlags = 0U; + /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */ + handle->transferredWords = 0U; + + SDHC_StartTransfer(base, command, data, dmaMode); + + return kStatus_Success; +} + +void SDHC_TransferHandleIRQ(SDHC_Type *base, sdhc_handle_t *handle) +{ + assert(handle); + + uint32_t interruptFlags; + + interruptFlags = SDHC_GetInterruptStatusFlags(base); + handle->interruptFlags = interruptFlags; + + if (interruptFlags & kSDHC_CardDetectFlag) + { + SDHC_TransferHandleCardDetect(handle, (interruptFlags & kSDHC_CardDetectFlag)); + } + if (interruptFlags & kSDHC_CommandFlag) + { + SDHC_TransferHandleCommand(base, handle, (interruptFlags & kSDHC_CommandFlag)); + } + if (interruptFlags & kSDHC_DataFlag) + { + SDHC_TransferHandleData(base, handle, (interruptFlags & kSDHC_DataFlag)); + } + if (interruptFlags & kSDHC_CardInterruptFlag) + { + SDHC_TransferHandleSdioInterrupt(handle); + } + if (interruptFlags & kSDHC_BlockGapEventFlag) + { + SDHC_TransferHandleSdioBlockGap(handle); + } + + SDHC_ClearInterruptStatusFlags(base, interruptFlags); +} + +#if defined(SDHC) +void SDHC_DriverIRQHandler(void) +{ + assert(s_sdhcHandle[0]); + + s_sdhcIsr(SDHC, s_sdhcHandle[0]); +} +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sdhc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sdhc.h new file mode 100644 index 00000000000..336b9618e5b --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sdhc.h @@ -0,0 +1,1095 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SDHC_H_ +#define _FSL_SDHC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sdhc + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.1.5. */ +#define FSL_SDHC_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 5U)) +/*@}*/ + +/*! @brief Maximum block count can be set one time */ +#define SDHC_MAX_BLOCK_COUNT (SDHC_BLKATTR_BLKCNT_MASK >> SDHC_BLKATTR_BLKCNT_SHIFT) + +/*! @brief SDHC status */ +enum _sdhc_status +{ + kStatus_SDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_SDHC, 0U), /*!< Transfer is on-going */ + kStatus_SDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_SDHC, 1U), /*!< Set DMA descriptor failed */ + kStatus_SDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_SDHC, 2U), /*!< Send command failed */ + kStatus_SDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_SDHC, 3U), /*!< Transfer data failed */ + kStatus_SDHC_DMADataBufferAddrNotAlign = + MAKE_STATUS(kStatusGroup_SDHC, 4U), /*!< data buffer addr not align in DMA mode */ +}; + +/*! @brief Host controller capabilities flag mask */ +enum _sdhc_capability_flag +{ + kSDHC_SupportAdmaFlag = SDHC_HTCAPBLT_ADMAS_MASK, /*!< Support ADMA */ + kSDHC_SupportHighSpeedFlag = SDHC_HTCAPBLT_HSS_MASK, /*!< Support high-speed */ + kSDHC_SupportDmaFlag = SDHC_HTCAPBLT_DMAS_MASK, /*!< Support DMA */ + kSDHC_SupportSuspendResumeFlag = SDHC_HTCAPBLT_SRS_MASK, /*!< Support suspend/resume */ + kSDHC_SupportV330Flag = SDHC_HTCAPBLT_VS33_MASK, /*!< Support voltage 3.3V */ +#if defined FSL_FEATURE_SDHC_HAS_V300_SUPPORT && FSL_FEATURE_SDHC_HAS_V300_SUPPORT + kSDHC_SupportV300Flag = SDHC_HTCAPBLT_VS30_MASK, /*!< Support voltage 3.0V */ +#endif +#if defined FSL_FEATURE_SDHC_HAS_V180_SUPPORT && FSL_FEATURE_SDHC_HAS_V180_SUPPORT + kSDHC_SupportV180Flag = SDHC_HTCAPBLT_VS18_MASK, /*!< Support voltage 1.8V */ +#endif + /* Put additional two flags in HTCAPBLT_MBL's position. */ + kSDHC_Support4BitFlag = (SDHC_HTCAPBLT_MBL_SHIFT << 0U), /*!< Support 4 bit mode */ + kSDHC_Support8BitFlag = (SDHC_HTCAPBLT_MBL_SHIFT << 1U), /*!< Support 8 bit mode */ +}; + +/*! @brief Wakeup event mask */ +enum _sdhc_wakeup_event +{ + kSDHC_WakeupEventOnCardInt = SDHC_PROCTL_WECINT_MASK, /*!< Wakeup on card interrupt */ + kSDHC_WakeupEventOnCardInsert = SDHC_PROCTL_WECINS_MASK, /*!< Wakeup on card insertion */ + kSDHC_WakeupEventOnCardRemove = SDHC_PROCTL_WECRM_MASK, /*!< Wakeup on card removal */ + + kSDHC_WakeupEventsAll = (kSDHC_WakeupEventOnCardInt | kSDHC_WakeupEventOnCardInsert | + kSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */ +}; + +/*! @brief Reset type mask */ +enum _sdhc_reset +{ + kSDHC_ResetAll = SDHC_SYSCTL_RSTA_MASK, /*!< Reset all except card detection */ + kSDHC_ResetCommand = SDHC_SYSCTL_RSTC_MASK, /*!< Reset command line */ + kSDHC_ResetData = SDHC_SYSCTL_RSTD_MASK, /*!< Reset data line */ + + kSDHC_ResetsAll = (kSDHC_ResetAll | kSDHC_ResetCommand | kSDHC_ResetData), /*!< All reset types */ +}; + +/*! @brief Transfer flag mask */ +enum _sdhc_transfer_flag +{ + kSDHC_EnableDmaFlag = SDHC_XFERTYP_DMAEN_MASK, /*!< Enable DMA */ + + kSDHC_CommandTypeSuspendFlag = (SDHC_XFERTYP_CMDTYP(1U)), /*!< Suspend command */ + kSDHC_CommandTypeResumeFlag = (SDHC_XFERTYP_CMDTYP(2U)), /*!< Resume command */ + kSDHC_CommandTypeAbortFlag = (SDHC_XFERTYP_CMDTYP(3U)), /*!< Abort command */ + + kSDHC_EnableBlockCountFlag = SDHC_XFERTYP_BCEN_MASK, /*!< Enable block count */ + kSDHC_EnableAutoCommand12Flag = SDHC_XFERTYP_AC12EN_MASK, /*!< Enable auto CMD12 */ + kSDHC_DataReadFlag = SDHC_XFERTYP_DTDSEL_MASK, /*!< Enable data read */ + kSDHC_MultipleBlockFlag = SDHC_XFERTYP_MSBSEL_MASK, /*!< Multiple block data read/write */ + + kSDHC_ResponseLength136Flag = SDHC_XFERTYP_RSPTYP(1U), /*!< 136 bit response length */ + kSDHC_ResponseLength48Flag = SDHC_XFERTYP_RSPTYP(2U), /*!< 48 bit response length */ + kSDHC_ResponseLength48BusyFlag = SDHC_XFERTYP_RSPTYP(3U), /*!< 48 bit response length with busy status */ + + kSDHC_EnableCrcCheckFlag = SDHC_XFERTYP_CCCEN_MASK, /*!< Enable CRC check */ + kSDHC_EnableIndexCheckFlag = SDHC_XFERTYP_CICEN_MASK, /*!< Enable index check */ + kSDHC_DataPresentFlag = SDHC_XFERTYP_DPSEL_MASK, /*!< Data present flag */ +}; + +/*! @brief Present status flag mask */ +enum _sdhc_present_status_flag +{ + kSDHC_CommandInhibitFlag = SDHC_PRSSTAT_CIHB_MASK, /*!< Command inhibit */ + kSDHC_DataInhibitFlag = SDHC_PRSSTAT_CDIHB_MASK, /*!< Data inhibit */ + kSDHC_DataLineActiveFlag = SDHC_PRSSTAT_DLA_MASK, /*!< Data line active */ + kSDHC_SdClockStableFlag = SDHC_PRSSTAT_SDSTB_MASK, /*!< SD bus clock stable */ + kSDHC_WriteTransferActiveFlag = SDHC_PRSSTAT_WTA_MASK, /*!< Write transfer active */ + kSDHC_ReadTransferActiveFlag = SDHC_PRSSTAT_RTA_MASK, /*!< Read transfer active */ + kSDHC_BufferWriteEnableFlag = SDHC_PRSSTAT_BWEN_MASK, /*!< Buffer write enable */ + kSDHC_BufferReadEnableFlag = SDHC_PRSSTAT_BREN_MASK, /*!< Buffer read enable */ + kSDHC_CardInsertedFlag = SDHC_PRSSTAT_CINS_MASK, /*!< Card inserted */ + kSDHC_CommandLineLevelFlag = SDHC_PRSSTAT_CLSL_MASK, /*!< Command line signal level */ + kSDHC_Data0LineLevelFlag = (1U << 24U), /*!< Data0 line signal level */ + kSDHC_Data1LineLevelFlag = (1U << 25U), /*!< Data1 line signal level */ + kSDHC_Data2LineLevelFlag = (1U << 26U), /*!< Data2 line signal level */ + kSDHC_Data3LineLevelFlag = (1U << 27U), /*!< Data3 line signal level */ + kSDHC_Data4LineLevelFlag = (1U << 28U), /*!< Data4 line signal level */ + kSDHC_Data5LineLevelFlag = (1U << 29U), /*!< Data5 line signal level */ + kSDHC_Data6LineLevelFlag = (1U << 30U), /*!< Data6 line signal level */ + kSDHC_Data7LineLevelFlag = (1U << 31U), /*!< Data7 line signal level */ +}; + +/*! @brief Interrupt status flag mask */ +enum _sdhc_interrupt_status_flag +{ + kSDHC_CommandCompleteFlag = SDHC_IRQSTAT_CC_MASK, /*!< Command complete */ + kSDHC_DataCompleteFlag = SDHC_IRQSTAT_TC_MASK, /*!< Data complete */ + kSDHC_BlockGapEventFlag = SDHC_IRQSTAT_BGE_MASK, /*!< Block gap event */ + kSDHC_DmaCompleteFlag = SDHC_IRQSTAT_DINT_MASK, /*!< DMA interrupt */ + kSDHC_BufferWriteReadyFlag = SDHC_IRQSTAT_BWR_MASK, /*!< Buffer write ready */ + kSDHC_BufferReadReadyFlag = SDHC_IRQSTAT_BRR_MASK, /*!< Buffer read ready */ + kSDHC_CardInsertionFlag = SDHC_IRQSTAT_CINS_MASK, /*!< Card inserted */ + kSDHC_CardRemovalFlag = SDHC_IRQSTAT_CRM_MASK, /*!< Card removed */ + kSDHC_CardInterruptFlag = SDHC_IRQSTAT_CINT_MASK, /*!< Card interrupt */ + kSDHC_CommandTimeoutFlag = SDHC_IRQSTAT_CTOE_MASK, /*!< Command timeout error */ + kSDHC_CommandCrcErrorFlag = SDHC_IRQSTAT_CCE_MASK, /*!< Command CRC error */ + kSDHC_CommandEndBitErrorFlag = SDHC_IRQSTAT_CEBE_MASK, /*!< Command end bit error */ + kSDHC_CommandIndexErrorFlag = SDHC_IRQSTAT_CIE_MASK, /*!< Command index error */ + kSDHC_DataTimeoutFlag = SDHC_IRQSTAT_DTOE_MASK, /*!< Data timeout error */ + kSDHC_DataCrcErrorFlag = SDHC_IRQSTAT_DCE_MASK, /*!< Data CRC error */ + kSDHC_DataEndBitErrorFlag = SDHC_IRQSTAT_DEBE_MASK, /*!< Data end bit error */ + kSDHC_AutoCommand12ErrorFlag = SDHC_IRQSTAT_AC12E_MASK, /*!< Auto CMD12 error */ + kSDHC_DmaErrorFlag = SDHC_IRQSTAT_DMAE_MASK, /*!< DMA error */ + + kSDHC_CommandErrorFlag = (kSDHC_CommandTimeoutFlag | kSDHC_CommandCrcErrorFlag | kSDHC_CommandEndBitErrorFlag | + kSDHC_CommandIndexErrorFlag), /*!< Command error */ + kSDHC_DataErrorFlag = (kSDHC_DataTimeoutFlag | kSDHC_DataCrcErrorFlag | kSDHC_DataEndBitErrorFlag | + kSDHC_AutoCommand12ErrorFlag), /*!< Data error */ + kSDHC_ErrorFlag = (kSDHC_CommandErrorFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag), /*!< All error */ + kSDHC_DataFlag = (kSDHC_DataCompleteFlag | kSDHC_DmaCompleteFlag | kSDHC_BufferWriteReadyFlag | + kSDHC_BufferReadReadyFlag | kSDHC_DataErrorFlag | kSDHC_DmaErrorFlag), /*!< Data interrupts */ + kSDHC_CommandFlag = (kSDHC_CommandErrorFlag | kSDHC_CommandCompleteFlag), /*!< Command interrupts */ + kSDHC_CardDetectFlag = (kSDHC_CardInsertionFlag | kSDHC_CardRemovalFlag), /*!< Card detection interrupts */ + + kSDHC_AllInterruptFlags = (kSDHC_BlockGapEventFlag | kSDHC_CardInterruptFlag | kSDHC_CommandFlag | kSDHC_DataFlag | + kSDHC_ErrorFlag), /*!< All flags mask */ +}; + +/*! @brief Auto CMD12 error status flag mask */ +enum _sdhc_auto_command12_error_status_flag +{ + kSDHC_AutoCommand12NotExecutedFlag = SDHC_AC12ERR_AC12NE_MASK, /*!< Not executed error */ + kSDHC_AutoCommand12TimeoutFlag = SDHC_AC12ERR_AC12TOE_MASK, /*!< Timeout error */ + kSDHC_AutoCommand12EndBitErrorFlag = SDHC_AC12ERR_AC12EBE_MASK, /*!< End bit error */ + kSDHC_AutoCommand12CrcErrorFlag = SDHC_AC12ERR_AC12CE_MASK, /*!< CRC error */ + kSDHC_AutoCommand12IndexErrorFlag = SDHC_AC12ERR_AC12IE_MASK, /*!< Index error */ + kSDHC_AutoCommand12NotIssuedFlag = SDHC_AC12ERR_CNIBAC12E_MASK, /*!< Not issued error */ +}; + +/*! @brief ADMA error status flag mask */ +enum _sdhc_adma_error_status_flag +{ + kSDHC_AdmaLenghMismatchFlag = SDHC_ADMAES_ADMALME_MASK, /*!< Length mismatch error */ + kSDHC_AdmaDescriptorErrorFlag = SDHC_ADMAES_ADMADCE_MASK, /*!< Descriptor error */ +}; + +/*! + * @brief ADMA error state + * + * This state is the detail state when ADMA error has occurred. + */ +typedef enum _sdhc_adma_error_state +{ + kSDHC_AdmaErrorStateStopDma = 0x00U, /*!< Stop DMA */ + kSDHC_AdmaErrorStateFetchDescriptor = 0x01U, /*!< Fetch descriptor */ + kSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address */ + kSDHC_AdmaErrorStateTransferData = 0x03U, /*!< Transfer data */ +} sdhc_adma_error_state_t; + +/*! @brief Force event mask */ +enum _sdhc_force_event +{ + kSDHC_ForceEventAutoCommand12NotExecuted = SDHC_FEVT_AC12NE_MASK, /*!< Auto CMD12 not executed error */ + kSDHC_ForceEventAutoCommand12Timeout = SDHC_FEVT_AC12TOE_MASK, /*!< Auto CMD12 timeout error */ + kSDHC_ForceEventAutoCommand12CrcError = SDHC_FEVT_AC12CE_MASK, /*!< Auto CMD12 CRC error */ + kSDHC_ForceEventEndBitError = SDHC_FEVT_AC12EBE_MASK, /*!< Auto CMD12 end bit error */ + kSDHC_ForceEventAutoCommand12IndexError = SDHC_FEVT_AC12IE_MASK, /*!< Auto CMD12 index error */ + kSDHC_ForceEventAutoCommand12NotIssued = SDHC_FEVT_CNIBAC12E_MASK, /*!< Auto CMD12 not issued error */ + kSDHC_ForceEventCommandTimeout = SDHC_FEVT_CTOE_MASK, /*!< Command timeout error */ + kSDHC_ForceEventCommandCrcError = SDHC_FEVT_CCE_MASK, /*!< Command CRC error */ + kSDHC_ForceEventCommandEndBitError = SDHC_FEVT_CEBE_MASK, /*!< Command end bit error */ + kSDHC_ForceEventCommandIndexError = SDHC_FEVT_CIE_MASK, /*!< Command index error */ + kSDHC_ForceEventDataTimeout = SDHC_FEVT_DTOE_MASK, /*!< Data timeout error */ + kSDHC_ForceEventDataCrcError = SDHC_FEVT_DCE_MASK, /*!< Data CRC error */ + kSDHC_ForceEventDataEndBitError = SDHC_FEVT_DEBE_MASK, /*!< Data end bit error */ + kSDHC_ForceEventAutoCommand12Error = SDHC_FEVT_AC12E_MASK, /*!< Auto CMD12 error */ + kSDHC_ForceEventCardInt = SDHC_FEVT_CINT_MASK, /*!< Card interrupt */ + kSDHC_ForceEventDmaError = SDHC_FEVT_DMAE_MASK, /*!< Dma error */ + + kSDHC_ForceEventsAll = + (kSDHC_ForceEventAutoCommand12NotExecuted | kSDHC_ForceEventAutoCommand12Timeout | + kSDHC_ForceEventAutoCommand12CrcError | kSDHC_ForceEventEndBitError | kSDHC_ForceEventAutoCommand12IndexError | + kSDHC_ForceEventAutoCommand12NotIssued | kSDHC_ForceEventCommandTimeout | kSDHC_ForceEventCommandCrcError | + kSDHC_ForceEventCommandEndBitError | kSDHC_ForceEventCommandIndexError | kSDHC_ForceEventDataTimeout | + kSDHC_ForceEventDataCrcError | kSDHC_ForceEventDataEndBitError | kSDHC_ForceEventAutoCommand12Error | + kSDHC_ForceEventCardInt | kSDHC_ForceEventDmaError), /*!< All force event flags mask */ +}; + +/*! @brief Data transfer width */ +typedef enum _sdhc_data_bus_width +{ + kSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */ + kSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */ + kSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */ +} sdhc_data_bus_width_t; + +/*! @brief Endian mode */ +typedef enum _sdhc_endian_mode +{ + kSDHC_EndianModeBig = 0U, /*!< Big endian mode */ + kSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ + kSDHC_EndianModeLittle = 2U, /*!< Little endian mode */ +} sdhc_endian_mode_t; + +/*! @brief DMA mode */ +typedef enum _sdhc_dma_mode +{ + kSDHC_DmaModeNo = 0U, /*!< No DMA */ + kSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */ + kSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */ +} sdhc_dma_mode_t; + +/*! @brief SDIO control flag mask */ +enum _sdhc_sdio_control_flag +{ + kSDHC_StopAtBlockGapFlag = 0x01, /*!< Stop at block gap */ + kSDHC_ReadWaitControlFlag = 0x02, /*!< Read wait control */ + kSDHC_InterruptAtBlockGapFlag = 0x04, /*!< Interrupt at block gap */ + kSDHC_ExactBlockNumberReadFlag = 0x08, /*!< Exact block number read */ +}; + +/*! @brief MMC card boot mode */ +typedef enum _sdhc_boot_mode +{ + kSDHC_BootModeNormal = 0U, /*!< Normal boot */ + kSDHC_BootModeAlternative = 1U, /*!< Alternative boot */ +} sdhc_boot_mode_t; + +/*! @brief The command type */ +typedef enum _sdhc_card_command_type +{ + kCARD_CommandTypeNormal = 0U, /*!< Normal command */ + kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ + kCARD_CommandTypeResume = 2U, /*!< Resume command */ + kCARD_CommandTypeAbort = 3U, /*!< Abort command */ +} sdhc_card_command_type_t; + +/*! + * @brief The command response type. + * + * Define the command response type from card to host controller. + */ +typedef enum _sdhc_card_response_type +{ + kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ + kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ + kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ + kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ + kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ + kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ + kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ + kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ + kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ + kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ +} sdhc_card_response_type_t; + +/*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */ +#define SDHC_ADMA1_ADDRESS_ALIGN (4096U) +/*! @brief The alignment size for LENGTH field in ADMA1's descriptor */ +#define SDHC_ADMA1_LENGTH_ALIGN (4096U) +/*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */ +#define SDHC_ADMA2_ADDRESS_ALIGN (4U) +/*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */ +#define SDHC_ADMA2_LENGTH_ALIGN (4U) + +/* ADMA1 descriptor table + * |------------------------|---------|--------------------------| + * | Address/page field |Reserved | Attribute | + * |------------------------|---------|--------------------------| + * |31 12|11 6|05 |04 |03|02 |01 |00 | + * |------------------------|---------|----|----|--|---|---|-----| + * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid| + * |------------------------|---------|----|----|--|---|---|-----| + * + * + * |------|------|-----------------|-------|-------------| + * | Act2 | Act1 | Comment | 31-28 | 27 - 12 | + * |------|------|-----------------|---------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------|-------------| + * | 0 | 1 | Set data length | 0000 | Data Length | + * |------|------|-----------------|-------|-------------| + * | 1 | 0 | Transfer data | Data address | + * |------|------|-----------------|---------------------| + * | 1 | 1 | Link descriptor | Descriptor address | + * |------|------|-----------------|---------------------| + */ +/*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */ +#define SDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U) +/*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */ +#define SDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU) +/*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */ +#define SDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U) +/*! @brief The mask for LENGTH field in ADMA1's descriptor */ +#define SDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH filed in ADMA1's descriptor */ +#define SDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDHC_ADMA1_DESCRIPTOR_LENGTH_MASK + 1U) + +/*! @brief The mask for the control/status field in ADMA1 descriptor */ +enum _sdhc_adma1_descriptor_flag +{ + kSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */ + kSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */ + kSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */ + kSDHC_Adma1DescriptorTypeNop = (kSDHC_Adma1DescriptorValidFlag), /*!< No operation */ + kSDHC_Adma1DescriptorTypeTransfer = + (kSDHC_Adma1DescriptorActivity2Flag | kSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */ + kSDHC_Adma1DescriptorTypeLink = (kSDHC_Adma1DescriptorActivity1Flag | kSDHC_Adma1DescriptorActivity2Flag | + kSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */ + kSDHC_Adma1DescriptorTypeSetLength = + (kSDHC_Adma1DescriptorActivity1Flag | kSDHC_Adma1DescriptorValidFlag), /*!< Set data length */ +}; + +/* ADMA2 descriptor table + * |----------------|---------------|-------------|--------------------------| + * | Address field | Length | Reserved | Attribute | + * |----------------|---------------|-------------|--------------------------| + * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 | + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid| + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * + * + * | Act2 | Act1 | Comment | Operation | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 1 | Reserved | Read this line and go to next one | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 1 | Link descriptor | Link to another descriptor | + * |------|------|-----------------|-------------------------------------------------------------------| + */ +/*! @brief The bit shift for LENGTH field in ADMA2's descriptor */ +#define SDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U) +/*! @brief The bit mask for LENGTH field in ADMA2's descriptor */ +#define SDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH field in ADMA2's descriptor */ +#define SDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDHC_ADMA2_DESCRIPTOR_LENGTH_MASK) + +/*! @brief ADMA1 descriptor control and status mask */ +enum _sdhc_adma2_descriptor_flag +{ + kSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */ + kSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */ + kSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */ + + kSDHC_Adma2DescriptorTypeNop = (kSDHC_Adma2DescriptorValidFlag), /*!< No operation */ + kSDHC_Adma2DescriptorTypeReserved = + (kSDHC_Adma2DescriptorActivity1Flag | kSDHC_Adma2DescriptorValidFlag), /*!< Reserved */ + kSDHC_Adma2DescriptorTypeTransfer = + (kSDHC_Adma2DescriptorActivity2Flag | kSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */ + kSDHC_Adma2DescriptorTypeLink = (kSDHC_Adma2DescriptorActivity1Flag | kSDHC_Adma2DescriptorActivity2Flag | + kSDHC_Adma2DescriptorValidFlag), /*!< Link type */ +}; + +/*! @brief Defines the adma1 descriptor structure. */ +typedef uint32_t sdhc_adma1_descriptor_t; + +/*! @brief Defines the ADMA2 descriptor structure. */ +typedef struct _sdhc_adma2_descriptor +{ + uint32_t attribute; /*!< The control and status field */ + const uint32_t *address; /*!< The address field */ +} sdhc_adma2_descriptor_t; + +/*! + * @brief SDHC capability information. + * + * Defines a structure to save the capability information of SDHC. + */ +typedef struct _sdhc_capability +{ + uint32_t specVersion; /*!< Specification version */ + uint32_t vendorVersion; /*!< Vendor version */ + uint32_t maxBlockLength; /*!< Maximum block length united as byte */ + uint32_t maxBlockCount; /*!< Maximum block count can be set one time */ + uint32_t flags; /*!< Capability flags to indicate the support information(_sdhc_capability_flag) */ +} sdhc_capability_t; + +/*! @brief Card transfer configuration. + * + * Define structure to configure the transfer-related command index/argument/flags and data block + * size/data block numbers. This structure needs to be filled each time a command is sent to the card. + */ +typedef struct _sdhc_transfer_config +{ + size_t dataBlockSize; /*!< Data block size */ + uint32_t dataBlockCount; /*!< Data block count */ + uint32_t commandArgument; /*!< Command argument */ + uint32_t commandIndex; /*!< Command index */ + uint32_t flags; /*!< Transfer flags(_sdhc_transfer_flag) */ +} sdhc_transfer_config_t; + +/*! @brief Data structure to configure the MMC boot feature */ +typedef struct _sdhc_boot_config +{ + uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK. The available range is 0 ~ 15. */ + sdhc_boot_mode_t bootMode; /*!< Boot mode selection. */ + uint32_t blockCount; /*!< Stop at block gap value of automatic mode. Available range is 0 ~ 65535. */ + bool enableBootAck; /*!< Enable or disable boot ACK */ + bool enableBoot; /*!< Enable or disable fast boot */ + bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */ +} sdhc_boot_config_t; + +/*! @brief Data structure to initialize the SDHC */ +typedef struct _sdhc_config +{ + bool cardDetectDat3; /*!< Enable DAT3 as card detection pin */ + sdhc_endian_mode_t endianMode; /*!< Endian mode */ + sdhc_dma_mode_t dmaMode; /*!< DMA mode */ + uint32_t readWatermarkLevel; /*!< Watermark level for DMA read operation. Available range is 1 ~ 128. */ + uint32_t writeWatermarkLevel; /*!< Watermark level for DMA write operation. Available range is 1 ~ 128. */ +} sdhc_config_t; + +/*! + * @brief Card data descriptor + * + * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card + * driver + * want to ignore the error event to read/write all the data not to stop read/write immediately when error event + * happen for example bus testing procedure for MMC card. + */ +typedef struct _sdhc_data +{ + bool enableAutoCommand12; /*!< Enable auto CMD12 */ + bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */ + size_t blockSize; /*!< Block size */ + uint32_t blockCount; /*!< Block count */ + uint32_t *rxData; /*!< Buffer to save data read */ + const uint32_t *txData; /*!< Data buffer to write */ +} sdhc_data_t; + +/*! + * @brief Card command descriptor + * + * Define card command-related attribute. + */ +typedef struct _sdhc_command +{ + uint32_t index; /*!< Command index */ + uint32_t argument; /*!< Command argument */ + sdhc_card_command_type_t type; /*!< Command type */ + sdhc_card_response_type_t responseType; /*!< Command response type */ + uint32_t response[4U]; /*!< Response for this command */ + uint32_t responseErrorFlags; /*!< response error flag, the flag which need to check + the command reponse*/ +} sdhc_command_t; + +/*! @brief Transfer state */ +typedef struct _sdhc_transfer +{ + sdhc_data_t *data; /*!< Data to transfer */ + sdhc_command_t *command; /*!< Command to send */ +} sdhc_transfer_t; + +/*! @brief SDHC handle typedef */ +typedef struct _sdhc_handle sdhc_handle_t; + +/*! @brief SDHC callback functions. */ +typedef struct _sdhc_transfer_callback +{ + void (*CardInserted)(void); /*!< Card inserted occurs when DAT3/CD pin is for card detect */ + void (*CardRemoved)(void); /*!< Card removed occurs */ + void (*SdioInterrupt)(void); /*!< SDIO card interrupt occurs */ + void (*SdioBlockGap)(void); /*!< SDIO card stopped at block gap occurs */ + void (*TransferComplete)(SDHC_Type *base, + sdhc_handle_t *handle, + status_t status, + void *userData); /*!< Transfer complete callback */ +} sdhc_transfer_callback_t; + +/*! + * @brief SDHC handle + * + * Defines the structure to save the SDHC state information and callback function. The detailed interrupt status when + * sending a command or transfering data can be obtained from the interruptFlags field by using the mask defined in + * sdhc_interrupt_flag_t. + * + * @note All the fields except interruptFlags and transferredWords must be allocated by the user. + */ +struct _sdhc_handle +{ + /* Transfer parameter */ + sdhc_data_t *volatile data; /*!< Data to transfer */ + sdhc_command_t *volatile command; /*!< Command to send */ + + /* Transfer status */ + volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */ + volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */ + + /* Callback functions */ + sdhc_transfer_callback_t callback; /*!< Callback function */ + void *userData; /*!< Parameter for transfer complete callback */ +}; + +/*! @brief SDHC transfer function. */ +typedef status_t (*sdhc_transfer_function_t)(SDHC_Type *base, sdhc_transfer_t *content); + +/*! @brief SDHC host descriptor */ +typedef struct _sdhc_host +{ + SDHC_Type *base; /*!< SDHC peripheral base address */ + uint32_t sourceClock_Hz; /*!< SDHC source clock frequency united in Hz */ + sdhc_config_t config; /*!< SDHC configuration */ + sdhc_capability_t capability; /*!< SDHC capability information */ + sdhc_transfer_function_t transfer; /*!< SDHC transfer function */ +} sdhc_host_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief SDHC module initialization function. + * + * Configures the SDHC according to the user configuration. + * + * Example: + @code + sdhc_config_t config; + config.cardDetectDat3 = false; + config.endianMode = kSDHC_EndianModeLittle; + config.dmaMode = kSDHC_DmaModeAdma2; + config.readWatermarkLevel = 128U; + config.writeWatermarkLevel = 128U; + SDHC_Init(SDHC, &config); + @endcode + * + * @param base SDHC peripheral base address. + * @param config SDHC configuration information. + * @retval kStatus_Success Operate successfully. + */ +void SDHC_Init(SDHC_Type *base, const sdhc_config_t *config); + +/*! + * @brief Deinitializes the SDHC. + * + * @param base SDHC peripheral base address. + */ +void SDHC_Deinit(SDHC_Type *base); + +/*! + * @brief Resets the SDHC. + * + * @param base SDHC peripheral base address. + * @param mask The reset type mask(_sdhc_reset). + * @param timeout Timeout for reset. + * @retval true Reset successfully. + * @retval false Reset failed. + */ +bool SDHC_Reset(SDHC_Type *base, uint32_t mask, uint32_t timeout); + +/* @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Sets the ADMA descriptor table configuration. + * + * @param base SDHC peripheral base address. + * @param dmaMode DMA mode. + * @param table ADMA table address. + * @param tableWords ADMA table buffer length united as Words. + * @param data Data buffer address. + * @param dataBytes Data length united as bytes. + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t SDHC_SetAdmaTableConfig(SDHC_Type *base, + sdhc_dma_mode_t dmaMode, + uint32_t *table, + uint32_t tableWords, + const uint32_t *data, + uint32_t dataBytes); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt status. + * + * @param base SDHC peripheral base address. + * @param mask Interrupt status flags mask(_sdhc_interrupt_status_flag). + */ +static inline void SDHC_EnableInterruptStatus(SDHC_Type *base, uint32_t mask) +{ + base->IRQSTATEN |= mask; +} + +/*! + * @brief Disables the interrupt status. + * + * @param base SDHC peripheral base address. + * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag). + */ +static inline void SDHC_DisableInterruptStatus(SDHC_Type *base, uint32_t mask) +{ + base->IRQSTATEN &= ~mask; +} + +/*! + * @brief Enables the interrupt signal corresponding to the interrupt status flag. + * + * @param base SDHC peripheral base address. + * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag). + */ +static inline void SDHC_EnableInterruptSignal(SDHC_Type *base, uint32_t mask) +{ + base->IRQSIGEN |= mask; +} + +/*! + * @brief Disables the interrupt signal corresponding to the interrupt status flag. + * + * @param base SDHC peripheral base address. + * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag). + */ +static inline void SDHC_DisableInterruptSignal(SDHC_Type *base, uint32_t mask) +{ + base->IRQSIGEN &= ~mask; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the current interrupt status. + * + * @param base SDHC peripheral base address. + * @return Current interrupt status flags mask(_sdhc_interrupt_status_flag). + */ +static inline uint32_t SDHC_GetInterruptStatusFlags(SDHC_Type *base) +{ + return base->IRQSTAT; +} + +/*! + * @brief Clears a specified interrupt status. + * + * @param base SDHC peripheral base address. + * @param mask The interrupt status flags mask(_sdhc_interrupt_status_flag). + */ +static inline void SDHC_ClearInterruptStatusFlags(SDHC_Type *base, uint32_t mask) +{ + base->IRQSTAT = mask; +} + +/*! + * @brief Gets the status of auto command 12 error. + * + * @param base SDHC peripheral base address. + * @return Auto command 12 error status flags mask(_sdhc_auto_command12_error_status_flag). + */ +static inline uint32_t SDHC_GetAutoCommand12ErrorStatusFlags(SDHC_Type *base) +{ + return base->AC12ERR; +} + +/*! + * @brief Gets the status of the ADMA error. + * + * @param base SDHC peripheral base address. + * @return ADMA error status flags mask(_sdhc_adma_error_status_flag). + */ +static inline uint32_t SDHC_GetAdmaErrorStatusFlags(SDHC_Type *base) +{ + return base->ADMAES; +} + +/*! + * @brief Gets a present status. + * + * This function gets the present SDHC's status except for an interrupt status and an error status. + * + * @param base SDHC peripheral base address. + * @return Present SDHC's status flags mask(_sdhc_present_status_flag). + */ +static inline uint32_t SDHC_GetPresentStatusFlags(SDHC_Type *base) +{ + return base->PRSSTAT; +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Gets the capability information. + * + * @param base SDHC peripheral base address. + * @param capability Structure to save capability information. + */ +void SDHC_GetCapability(SDHC_Type *base, sdhc_capability_t *capability); + +/*! + * @brief Enables or disables the SD bus clock. + * + * @param base SDHC peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void SDHC_EnableSdClock(SDHC_Type *base, bool enable) +{ + if (enable) + { + base->SYSCTL |= SDHC_SYSCTL_SDCLKEN_MASK; + } + else + { + base->SYSCTL &= ~SDHC_SYSCTL_SDCLKEN_MASK; + } +} + +/*! + * @brief Sets the SD bus clock frequency. + * + * @param base SDHC peripheral base address. + * @param srcClock_Hz SDHC source clock frequency united in Hz. + * @param busClock_Hz SD bus clock frequency united in Hz. + * + * @return The nearest frequency of busClock_Hz configured to SD bus. + */ +uint32_t SDHC_SetSdClock(SDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz); + +/*! + * @brief Sends 80 clocks to the card to set it to the active state. + * + * This function must be called each time the card is inserted to ensure that the card can receive the command + * correctly. + * + * @param base SDHC peripheral base address. + * @param timeout Timeout to initialize card. + * @retval true Set card active successfully. + * @retval false Set card active failed. + */ +bool SDHC_SetCardActive(SDHC_Type *base, uint32_t timeout); + +/*! + * @brief Sets the data transfer width. + * + * @param base SDHC peripheral base address. + * @param width Data transfer width. + */ +static inline void SDHC_SetDataBusWidth(SDHC_Type *base, sdhc_data_bus_width_t width) +{ + base->PROCTL = ((base->PROCTL & ~SDHC_PROCTL_DTW_MASK) | SDHC_PROCTL_DTW(width)); +} + +/*! + * @brief Sets the card transfer-related configuration. + * + * This function fills the card transfer-related command argument/transfer flag/data size. The command and data are sent + by + * SDHC after calling this function. + * + * Example: + @code + sdhc_transfer_config_t transferConfig; + transferConfig.dataBlockSize = 512U; + transferConfig.dataBlockCount = 2U; + transferConfig.commandArgument = 0x01AAU; + transferConfig.commandIndex = 8U; + transferConfig.flags |= (kSDHC_EnableDmaFlag | kSDHC_EnableAutoCommand12Flag | kSDHC_MultipleBlockFlag); + SDHC_SetTransferConfig(SDHC, &transferConfig); + @endcode + * + * @param base SDHC peripheral base address. + * @param config Command configuration structure. + */ +void SDHC_SetTransferConfig(SDHC_Type *base, const sdhc_transfer_config_t *config); + +/*! + * @brief Gets the command response. + * + * @param base SDHC peripheral base address. + * @param index The index of response register, range from 0 to 3. + * @return Response register transfer. + */ +static inline uint32_t SDHC_GetCommandResponse(SDHC_Type *base, uint32_t index) +{ + assert(index < 4U); + + return base->CMDRSP[index]; +} + +/*! + * @brief Fills the the data port. + * + * This function is used to implement the data transfer by Data Port instead of DMA. + * + * @param base SDHC peripheral base address. + * @param data The data about to be sent. + */ +static inline void SDHC_WriteData(SDHC_Type *base, uint32_t data) +{ + base->DATPORT = data; +} + +/*! + * @brief Retrieves the data from the data port. + * + * This function is used to implement the data transfer by Data Port instead of DMA. + * + * @param base SDHC peripheral base address. + * @return The data has been read. + */ +static inline uint32_t SDHC_ReadData(SDHC_Type *base) +{ + return base->DATPORT; +} + +/*! + * @brief Enables or disables a wakeup event in low-power mode. + * + * @param base SDHC peripheral base address. + * @param mask Wakeup events mask(_sdhc_wakeup_event). + * @param enable True to enable, false to disable. + */ +static inline void SDHC_EnableWakeupEvent(SDHC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PROCTL |= mask; + } + else + { + base->PROCTL &= ~mask; + } +} + +/*! + * @brief Enables or disables the card detection level for testing. + * + * @param base SDHC peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void SDHC_EnableCardDetectTest(SDHC_Type *base, bool enable) +{ + if (enable) + { + base->PROCTL |= SDHC_PROCTL_CDSS_MASK; + } + else + { + base->PROCTL &= ~SDHC_PROCTL_CDSS_MASK; + } +} + +/*! + * @brief Sets the card detection test level. + * + * This function sets the card detection test level to indicate whether the card is inserted into the SDHC when DAT[3]/ + * CD pin is selected as a card detection pin. This function can also assert the pin logic when DAT[3]/CD pin is + * selected + * as the card detection pin. + * + * @param base SDHC peripheral base address. + * @param high True to set the card detect level to high. + */ +static inline void SDHC_SetCardDetectTestLevel(SDHC_Type *base, bool high) +{ + if (high) + { + base->PROCTL |= SDHC_PROCTL_CDTL_MASK; + } + else + { + base->PROCTL &= ~SDHC_PROCTL_CDTL_MASK; + } +} + +/*! + * @brief Enables or disables the SDIO card control. + * + * @param base SDHC peripheral base address. + * @param mask SDIO card control flags mask(_sdhc_sdio_control_flag). + * @param enable True to enable, false to disable. + */ +void SDHC_EnableSdioControl(SDHC_Type *base, uint32_t mask, bool enable); + +/*! + * @brief Restarts a transaction which has stopped at the block GAP for the SDIO card. + * + * @param base SDHC peripheral base address. + */ +static inline void SDHC_SetContinueRequest(SDHC_Type *base) +{ + base->PROCTL |= SDHC_PROCTL_CREQ_MASK; +} + +/*! + * @brief Configures the MMC boot feature. + * + * Example: + @code + sdhc_boot_config_t config; + config.ackTimeoutCount = 4; + config.bootMode = kSDHC_BootModeNormal; + config.blockCount = 5; + config.enableBootAck = true; + config.enableBoot = true; + config.enableAutoStopAtBlockGap = true; + SDHC_SetMmcBootConfig(SDHC, &config); + @endcode + * + * @param base SDHC peripheral base address. + * @param config The MMC boot configuration information. + */ +void SDHC_SetMmcBootConfig(SDHC_Type *base, const sdhc_boot_config_t *config); + +/*! + * @brief Forces generating events according to the given mask. + * + * @param base SDHC peripheral base address. + * @param mask The force events mask(_sdhc_force_event). + */ +static inline void SDHC_SetForceEvent(SDHC_Type *base, uint32_t mask) +{ + base->FEVT = mask; +} + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Transfers the command/data using a blocking method. + * + * This function waits until the command response/data is received or the SDHC encounters an error by polling the status + * flag. + * This function support non word align data addr transfer support, if data buffer addr is not align in DMA mode, + * the API will continue finish the transfer by polling IO directly + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * @note There is no need to call the API 'SDHC_TransferCreateHandle' when calling this API. + * + * @param base SDHC peripheral base address. + * @param admaTable ADMA table address, can't be null if transfer way is ADMA1/ADMA2. + * @param admaTableWords ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2. + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_SDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_SDHC_SendCommandFailed Send command failed. + * @retval kStatus_SDHC_TransferDataFailed Transfer data failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDHC_TransferBlocking(SDHC_Type *base, + uint32_t *admaTable, + uint32_t admaTableWords, + sdhc_transfer_t *transfer); + +/*! + * @brief Creates the SDHC handle. + * + * @param base SDHC peripheral base address. + * @param handle SDHC handle pointer. + * @param callback Structure pointer to contain all callback functions. + * @param userData Callback function parameter. + */ +void SDHC_TransferCreateHandle(SDHC_Type *base, + sdhc_handle_t *handle, + const sdhc_transfer_callback_t *callback, + void *userData); + +/*! + * @brief Transfers the command/data using an interrupt and an asynchronous method. + * + * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an + * error. + * This function support non word align data addr transfer support, if data buffer addr is not align in DMA mode, + * the API will continue finish the transfer by polling IO directly + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * @note Call the API 'SDHC_TransferCreateHandle' when calling this API. + * + * @param base SDHC peripheral base address. + * @param handle SDHC handle. + * @param admaTable ADMA table address, can't be null if transfer way is ADMA1/ADMA2. + * @param admaTableWords ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2. + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_SDHC_BusyTransferring Busy transferring. + * @retval kStatus_SDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_Success Operate successfully. + */ +status_t SDHC_TransferNonBlocking( + SDHC_Type *base, sdhc_handle_t *handle, uint32_t *admaTable, uint32_t admaTableWords, sdhc_transfer_t *transfer); + +/*! + * @brief IRQ handler for the SDHC. + * + * This function deals with the IRQs on the given host controller. + * + * @param base SDHC peripheral base address. + * @param handle SDHC handle. + */ +void SDHC_TransferHandleIRQ(SDHC_Type *base, sdhc_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ + +#endif /* _FSL_SDHC_H_*/ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sim.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sim.c new file mode 100644 index 00000000000..ade512f0306 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sim.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sim.h" + +/******************************************************************************* + * Codes + ******************************************************************************/ +#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask) +{ + SIM->SOPT1CFG |= (SIM_SOPT1CFG_URWE_MASK | SIM_SOPT1CFG_UVSWE_MASK | SIM_SOPT1CFG_USSWE_MASK); + + SIM->SOPT1 = (SIM->SOPT1 & ~kSIM_UsbVoltRegEnableInAllModes) | mask; +} +#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ + +void SIM_GetUniqueId(sim_uid_t *uid) +{ +#if defined(SIM_UIDH) + uid->H = SIM->UIDH; +#endif + uid->MH = SIM->UIDMH; + uid->ML = SIM->UIDML; + uid->L = SIM->UIDL; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sim.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sim.h new file mode 100644 index 00000000000..0a0e4fb3092 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sim.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SIM_H_ +#define _FSL_SIM_H_ + +#include "fsl_common.h" + +/*! @addtogroup sim */ +/*! @{*/ + + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SIM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Driver version 2.0.0 */ +/*@}*/ + +#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +/*!@brief USB voltage regulator enable setting. */ +enum _sim_usb_volt_reg_enable_mode +{ + kSIM_UsbVoltRegEnable = SIM_SOPT1_USBREGEN_MASK, /*!< Enable voltage regulator. */ + kSIM_UsbVoltRegEnableInLowPower = SIM_SOPT1_USBVSTBY_MASK, /*!< Enable voltage regulator in VLPR/VLPW modes. */ + kSIM_UsbVoltRegEnableInStop = SIM_SOPT1_USBSSTBY_MASK, /*!< Enable voltage regulator in STOP/VLPS/LLS/VLLS modes. */ + kSIM_UsbVoltRegEnableInAllModes = SIM_SOPT1_USBREGEN_MASK | SIM_SOPT1_USBSSTBY_MASK | + SIM_SOPT1_USBVSTBY_MASK /*!< Enable voltage regulator in all power modes. */ +}; +#endif /* (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) */ + +/*!@brief Unique ID. */ +typedef struct _sim_uid +{ +#if defined(SIM_UIDH) + uint32_t H; /*!< UIDH. */ +#endif + uint32_t MH; /*!< UIDMH. */ + uint32_t ML; /*!< UIDML. */ + uint32_t L; /*!< UIDL. */ +} sim_uid_t; + +/*!@brief Flash enable mode. */ +enum _sim_flash_mode +{ + kSIM_FlashDisableInWait = SIM_FCFG1_FLASHDOZE_MASK, /*!< Disable flash in wait mode. */ + kSIM_FlashDisable = SIM_FCFG1_FLASHDIS_MASK /*!< Disable flash in normal mode. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +#if (defined(FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) && FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR) +/*! + * @brief Sets the USB voltage regulator setting. + * + * This function configures whether the USB voltage regulator is enabled in + * normal RUN mode, STOP/VLPS/LLS/VLLS modes, and VLPR/VLPW modes. The configurations + * are passed in as mask value of \ref _sim_usb_volt_reg_enable_mode. For example, to enable + * USB voltage regulator in RUN/VLPR/VLPW modes and disable in STOP/VLPS/LLS/VLLS mode, + * use: + * + * SIM_SetUsbVoltRegulatorEnableMode(kSIM_UsbVoltRegEnable | kSIM_UsbVoltRegEnableInLowPower); + * + * @param mask USB voltage regulator enable setting. + */ +void SIM_SetUsbVoltRegulatorEnableMode(uint32_t mask); +#endif /* FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR */ + +/*! + * @brief Gets the unique identification register value. + * + * @param uid Pointer to the structure to save the UID value. + */ +void SIM_GetUniqueId(sim_uid_t *uid); + +/*! + * @brief Sets the flash enable mode. + * + * @param mode The mode to set; see \ref _sim_flash_mode for mode details. + */ +static inline void SIM_SetFlashMode(uint8_t mode) +{ + SIM->FCFG1 = mode; +} + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_SIM_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_smc.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_smc.c new file mode 100644 index 00000000000..dacf193476c --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_smc.c @@ -0,0 +1,400 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_smc.h" +#include "fsl_flash.h" + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +void SMC_GetParam(SMC_Type *base, smc_param_t *param) +{ + uint32_t reg = base->PARAM; + param->hsrunEnable = (bool)(reg & SMC_PARAM_EHSRUN_MASK); + param->llsEnable = (bool)(reg & SMC_PARAM_ELLS_MASK); + param->lls2Enable = (bool)(reg & SMC_PARAM_ELLS2_MASK); + param->vlls0Enable = (bool)(reg & SMC_PARAM_EVLLS0_MASK); +} +#endif /* FSL_FEATURE_SMC_HAS_PARAM */ + +void SMC_PreEnterStopModes(void) +{ + flash_prefetch_speculation_status_t speculationStatus = + { + kFLASH_prefetchSpeculationOptionDisable, /* Disable instruction speculation.*/ + kFLASH_prefetchSpeculationOptionDisable, /* Disable data speculation.*/ + }; + + __disable_irq(); + __ISB(); + + /* + * Before enter stop modes, the flash cache prefetch should be disabled. + * Otherwise the prefetch might be interrupted by stop, then the data and + * and instruction from flash are wrong. + */ + FLASH_PflashSetPrefetchSpeculation(&speculationStatus); +} + +void SMC_PostExitStopModes(void) +{ + flash_prefetch_speculation_status_t speculationStatus = + { + kFLASH_prefetchSpeculationOptionEnable, /* Enable instruction speculation.*/ + kFLASH_prefetchSpeculationOptionEnable, /* Enable data speculation.*/ + }; + + FLASH_PflashSetPrefetchSpeculation(&speculationStatus); + + __enable_irq(); + __ISB(); +} + +status_t SMC_SetPowerModeRun(SMC_Type *base) +{ + uint8_t reg; + + reg = base->PMCTRL; + /* configure Normal RUN mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= (kSMC_RunNormal << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) +status_t SMC_SetPowerModeHsrun(SMC_Type *base) +{ + uint8_t reg; + + reg = base->PMCTRL; + /* configure High Speed RUN mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= (kSMC_Hsrun << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + +status_t SMC_SetPowerModeWait(SMC_Type *base) +{ + /* configure Normal Wait mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); + + return kStatus_Success; +} + +status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option) +{ + uint8_t reg; + +#if (defined(FSL_FEATURE_SMC_HAS_PSTOPO) && FSL_FEATURE_SMC_HAS_PSTOPO) + /* configure the Partial Stop mode in Noraml Stop mode */ + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_PSTOPO_MASK; + reg |= ((uint32_t)option << SMC_STOPCTRL_PSTOPO_SHIFT); + base->STOPCTRL = reg; +#endif + + /* configure Normal Stop mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopNormal << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + + /* Set the SLEEPDEEP bit to enable deep sleep mode (stop mode) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __DSB(); + __WFI(); + __ISB(); + + /* check whether the power mode enter Stop mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} + +status_t SMC_SetPowerModeVlpr(SMC_Type *base +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) + , + bool wakeupMode +#endif + ) +{ + uint8_t reg; + + reg = base->PMCTRL; +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) + /* configure whether the system remains in VLP mode on an interrupt */ + if (wakeupMode) + { + /* exits to RUN mode on an interrupt */ + reg |= SMC_PMCTRL_LPWUI_MASK; + } + else + { + /* remains in VLP mode on an interrupt */ + reg &= ~SMC_PMCTRL_LPWUI_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ + + /* configure VLPR mode */ + reg &= ~SMC_PMCTRL_RUNM_MASK; + reg |= (kSMC_RunVlpr << SMC_PMCTRL_RUNM_SHIFT); + base->PMCTRL = reg; + + return kStatus_Success; +} + +status_t SMC_SetPowerModeVlpw(SMC_Type *base) +{ + /* configure VLPW mode */ + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); + + return kStatus_Success; +} + +status_t SMC_SetPowerModeVlps(SMC_Type *base) +{ + uint8_t reg; + + /* configure VLPS mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __DSB(); + __WFI(); + __ISB(); + + /* check whether the power mode enter VLPS mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} + +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) +status_t SMC_SetPowerModeLls(SMC_Type *base +#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) + , + const smc_power_mode_lls_config_t *config +#endif + ) +{ + uint8_t reg; + + /* configure to LLS mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopLls << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + +/* configure LLS sub-mode*/ +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_LLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); + base->STOPCTRL = reg; +#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + if (config->enableLpoClock) + { + base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; + } + else + { + base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __DSB(); + __WFI(); + __ISB(); + + /* check whether the power mode enter LLS mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config) +{ + uint8_t reg; + +#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + if (config->subMode == kSMC_StopSub0) +#endif + { + /* configure whether the Por Detect work in Vlls0 mode */ + if (config->enablePorDetectInVlls0) + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL &= ~SMC_VLLSCTRL_PORPO_MASK; +#else + base->STOPCTRL &= ~SMC_STOPCTRL_PORPO_MASK; +#endif + } + else + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL |= SMC_VLLSCTRL_PORPO_MASK; +#else + base->STOPCTRL |= SMC_STOPCTRL_PORPO_MASK; +#endif + } + } +#endif /* FSL_FEATURE_SMC_HAS_PORPO */ + +#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) + else if (config->subMode == kSMC_StopSub2) + { + /* configure whether the Por Detect work in Vlls0 mode */ + if (config->enableRam2InVlls2) + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL |= SMC_VLLSCTRL_RAM2PO_MASK; +#else + base->STOPCTRL |= SMC_STOPCTRL_RAM2PO_MASK; +#endif + } + else + { +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + base->VLLSCTRL &= ~SMC_VLLSCTRL_RAM2PO_MASK; +#else + base->STOPCTRL &= ~SMC_STOPCTRL_RAM2PO_MASK; +#endif + } + } + else + { + } +#endif /* FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION */ + + /* configure to VLLS mode */ + reg = base->PMCTRL; + reg &= ~SMC_PMCTRL_STOPM_MASK; + reg |= (kSMC_StopVlls << SMC_PMCTRL_STOPM_SHIFT); + base->PMCTRL = reg; + +/* configure the VLLS sub-mode */ +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) + reg = base->VLLSCTRL; + reg &= ~SMC_VLLSCTRL_VLLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_VLLSCTRL_VLLSM_SHIFT); + base->VLLSCTRL = reg; +#else +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_LLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_LLSM_SHIFT); + base->STOPCTRL = reg; +#else + reg = base->STOPCTRL; + reg &= ~SMC_STOPCTRL_VLLSM_MASK; + reg |= ((uint32_t)config->subMode << SMC_STOPCTRL_VLLSM_SHIFT); + base->STOPCTRL = reg; +#endif /* FSL_FEATURE_SMC_HAS_LLS_SUBMODE */ +#endif + +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + if (config->enableLpoClock) + { + base->STOPCTRL &= ~SMC_STOPCTRL_LPOPO_MASK; + } + else + { + base->STOPCTRL |= SMC_STOPCTRL_LPOPO_MASK; + } +#endif /* FSL_FEATURE_SMC_HAS_LPOPO */ + + /* Set the SLEEPDEEP bit to enable deep sleep mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* read back to make sure the configuration valid before enter stop mode */ + (void)base->PMCTRL; + __DSB(); + __WFI(); + __ISB(); + + /* check whether the power mode enter LLS mode succeed */ + if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK) + { + return kStatus_SMC_StopAbort; + } + else + { + return kStatus_Success; + } +} +#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_smc.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_smc.h new file mode 100644 index 00000000000..168ce835013 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_smc.h @@ -0,0 +1,456 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_SMC_H_ +#define _FSL_SMC_H_ + +#include "fsl_common.h" + +/*! @addtogroup smc */ +/*! @{ */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SMC driver version 2.0.3. */ +#define FSL_SMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/*! + * @brief Power Modes Protection + */ +typedef enum _smc_power_mode_protection +{ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_AllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-low-leakage Stop Mode. */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_AllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-leakage Stop Mode. */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + kSMC_AllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-power Mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_AllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High-speed Run mode. */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + kSMC_AllowPowerModeAll = (0U +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + | + SMC_PMPROT_AVLLS_MASK +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + | + SMC_PMPROT_ALLS_MASK +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + | + SMC_PMPROT_AVLP_MASK +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + | + kSMC_AllowPowerModeHsrun +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + ) /*!< Allow all power mode. */ +} smc_power_mode_protection_t; + +/*! + * @brief Power Modes in PMSTAT + */ +typedef enum _smc_power_state +{ + kSMC_PowerStateRun = 0x01U << 0U, /*!< 0000_0001 - Current power mode is RUN */ + kSMC_PowerStateStop = 0x01U << 1U, /*!< 0000_0010 - Current power mode is STOP */ + kSMC_PowerStateVlpr = 0x01U << 2U, /*!< 0000_0100 - Current power mode is VLPR */ + kSMC_PowerStateVlpw = 0x01U << 3U, /*!< 0000_1000 - Current power mode is VLPW */ + kSMC_PowerStateVlps = 0x01U << 4U, /*!< 0001_0000 - Current power mode is VLPS */ +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_PowerStateLls = 0x01U << 5U, /*!< 0010_0000 - Current power mode is LLS */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_PowerStateVlls = 0x01U << 6U, /*!< 0100_0000 - Current power mode is VLLS */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_PowerStateHsrun = 0x01U << 7U /*!< 1000_0000 - Current power mode is HSRUN */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ +} smc_power_state_t; + +/*! + * @brief Run mode definition + */ +typedef enum _smc_run_mode +{ + kSMC_RunNormal = 0U, /*!< Normal RUN mode. */ + kSMC_RunVlpr = 2U, /*!< Very-low-power RUN mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) + kSMC_Hsrun = 3U /*!< High-speed Run mode (HSRUN). */ +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ +} smc_run_mode_t; + +/*! + * @brief Stop mode definition + */ +typedef enum _smc_stop_mode +{ + kSMC_StopNormal = 0U, /*!< Normal STOP mode. */ + kSMC_StopVlps = 2U, /*!< Very-low-power STOP mode. */ +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) + kSMC_StopLls = 3U, /*!< Low-leakage Stop mode. */ +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) + kSMC_StopVlls = 4U /*!< Very-low-leakage Stop mode. */ +#endif +} smc_stop_mode_t; + +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) +/*! + * @brief VLLS/LLS stop sub mode definition + */ +typedef enum _smc_stop_submode +{ + kSMC_StopSub0 = 0U, /*!< Stop submode 0, for VLLS0/LLS0. */ + kSMC_StopSub1 = 1U, /*!< Stop submode 1, for VLLS1/LLS1. */ + kSMC_StopSub2 = 2U, /*!< Stop submode 2, for VLLS2/LLS2. */ + kSMC_StopSub3 = 3U /*!< Stop submode 3, for VLLS3/LLS3. */ +} smc_stop_submode_t; +#endif + +/*! + * @brief Partial STOP option + */ +typedef enum _smc_partial_stop_mode +{ + kSMC_PartialStop = 0U, /*!< STOP - Normal Stop mode*/ + kSMC_PartialStop1 = 1U, /*!< Partial Stop with both system and bus clocks disabled*/ + kSMC_PartialStop2 = 2U, /*!< Partial Stop with system clock disabled and bus clock enabled*/ +} smc_partial_stop_option_t; + +/*! + * @brief SMC configuration status. + */ +enum _smc_status +{ + kStatus_SMC_StopAbort = MAKE_STATUS(kStatusGroup_POWER, 0) /*!< Entering Stop mode is abort*/ +}; + +#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) +/*! + * @brief IP version ID definition. + */ +typedef struct _smc_version_id +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor version number. */ + uint8_t major; /*!< Major version number. */ +} smc_version_id_t; +#endif /* FSL_FEATURE_SMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +/*! + * @brief IP parameter definition. + */ +typedef struct _smc_param +{ + bool hsrunEnable; /*!< HSRUN mode enable. */ + bool llsEnable; /*!< LLS mode enable. */ + bool lls2Enable; /*!< LLS2 mode enable. */ + bool vlls0Enable; /*!< VLLS0 mode enable. */ +} smc_param_t; +#endif /* FSL_FEATURE_SMC_HAS_PARAM */ + +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) +/*! + * @brief SMC Low-Leakage Stop power mode configuration. + */ +typedef struct _smc_power_mode_lls_config +{ +#if (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + smc_stop_submode_t subMode; /*!< Low-leakage Stop sub-mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + bool enableLpoClock; /*!< Enable LPO clock in LLS mode */ +#endif +} smc_power_mode_lls_config_t; +#endif /* (FSL_FEATURE_SMC_HAS_LLS_SUBMODE || FSL_FEATURE_SMC_HAS_LPOPO) */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +/*! + * @brief SMC Very Low-Leakage Stop power mode configuration. + */ +typedef struct _smc_power_mode_vlls_config +{ +#if (defined(FSL_FEATURE_SMC_USE_VLLSCTRL_REG) && FSL_FEATURE_SMC_USE_VLLSCTRL_REG) || \ + (defined(FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) && FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM) || \ + (defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) + smc_stop_submode_t subMode; /*!< Very Low-leakage Stop sub-mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_PORPO) && FSL_FEATURE_SMC_HAS_PORPO) + bool enablePorDetectInVlls0; /*!< Enable Power on reset detect in VLLS mode */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) && FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION) + bool enableRam2InVlls2; /*!< Enable RAM2 power in VLLS2 */ +#endif +#if (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO) + bool enableLpoClock; /*!< Enable LPO clock in VLLS mode */ +#endif +} smc_power_mode_vlls_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name System mode controller APIs*/ +/*@{*/ + +#if (defined(FSL_FEATURE_SMC_HAS_VERID) && FSL_FEATURE_SMC_HAS_VERID) +/*! + * @brief Gets the SMC version ID. + * + * This function gets the SMC version ID, including major version number, + * minor version number, and feature specification number. + * + * @param base SMC peripheral base address. + * @param versionId Pointer to the version ID structure. + */ +static inline void SMC_GetVersionId(SMC_Type *base, smc_version_id_t *versionId) +{ + *((uint32_t *)versionId) = base->VERID; +} +#endif /* FSL_FEATURE_SMC_HAS_VERID */ + +#if (defined(FSL_FEATURE_SMC_HAS_PARAM) && FSL_FEATURE_SMC_HAS_PARAM) +/*! + * @brief Gets the SMC parameter. + * + * This function gets the SMC parameter including the enabled power mdoes. + * + * @param base SMC peripheral base address. + * @param param Pointer to the SMC param structure. + */ +void SMC_GetParam(SMC_Type *base, smc_param_t *param); +#endif + +/*! + * @brief Configures all power mode protection settings. + * + * This function configures the power mode protection settings for + * supported power modes in the specified chip family. The available power modes + * are defined in the smc_power_mode_protection_t. This should be done at an early + * system level initialization stage. See the reference manual for details. + * This register can only write once after the power reset. + * + * The allowed modes are passed as bit map. For example, to allow LLS and VLLS, + * use SMC_SetPowerModeProtection(kSMC_AllowPowerModeVlls | kSMC_AllowPowerModeVlps). + * To allow all modes, use SMC_SetPowerModeProtection(kSMC_AllowPowerModeAll). + * + * @param base SMC peripheral base address. + * @param allowedModes Bitmap of the allowed power modes. + */ +static inline void SMC_SetPowerModeProtection(SMC_Type *base, uint8_t allowedModes) +{ + base->PMPROT = allowedModes; +} + +/*! + * @brief Gets the current power mode status. + * + * This function returns the current power mode status. After the application + * switches the power mode, it should always check the status to check whether it + * runs into the specified mode or not. The application should check + * this mode before switching to a different mode. The system requires that + * only certain modes can switch to other specific modes. See the + * reference manual for details and the smc_power_state_t for information about + * the power status. + * + * @param base SMC peripheral base address. + * @return Current power mode status. + */ +static inline smc_power_state_t SMC_GetPowerModeState(SMC_Type *base) +{ + return (smc_power_state_t)base->PMSTAT; +} + +/*! + * @brief Prepares to enter stop modes. + * + * This function should be called before entering STOP/VLPS/LLS/VLLS modes. + */ +void SMC_PreEnterStopModes(void); + +/*! + * @brief Recovers after wake up from stop modes. + * + * This function should be called after wake up from STOP/VLPS/LLS/VLLS modes. + * It is used with @ref SMC_PreEnterStopModes. + */ +void SMC_PostExitStopModes(void); + +/*! + * @brief Prepares to enter wait modes. + * + * This function should be called before entering WAIT/VLPW modes. + */ +static inline void SMC_PreEnterWaitModes(void) +{ + __disable_irq(); + __ISB(); +} + +/*! + * @brief Recovers after wake up from stop modes. + * + * This function should be called after wake up from WAIT/VLPW modes. + * It is used with @ref SMC_PreEnterWaitModes. + */ +static inline void SMC_PostExitWaitModes(void) +{ + __enable_irq(); + __ISB(); +} + +/*! + * @brief Configures the system to RUN power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeRun(SMC_Type *base); + +#if (defined(FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) && FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE) +/*! + * @brief Configures the system to HSRUN power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeHsrun(SMC_Type *base); +#endif /* FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE */ + +/*! + * @brief Configures the system to WAIT power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeWait(SMC_Type *base); + +/*! + * @brief Configures the system to Stop power mode. + * + * @param base SMC peripheral base address. + * @param option Partial Stop mode option. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeStop(SMC_Type *base, smc_partial_stop_option_t option); + +#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI) +/*! + * @brief Configures the system to VLPR power mode. + * + * @param base SMC peripheral base address. + * @param wakeupMode Enter Normal Run mode if true, else stay in VLPR mode. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpr(SMC_Type *base, bool wakeupMode); +#else +/*! + * @brief Configures the system to VLPR power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpr(SMC_Type *base); +#endif /* FSL_FEATURE_SMC_HAS_LPWUI */ + +/*! + * @brief Configures the system to VLPW power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlpw(SMC_Type *base); + +/*! + * @brief Configures the system to VLPS power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlps(SMC_Type *base); + +#if (defined(FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE) +#if ((defined(FSL_FEATURE_SMC_HAS_LLS_SUBMODE) && FSL_FEATURE_SMC_HAS_LLS_SUBMODE) || \ + (defined(FSL_FEATURE_SMC_HAS_LPOPO) && FSL_FEATURE_SMC_HAS_LPOPO)) +/*! + * @brief Configures the system to LLS power mode. + * + * @param base SMC peripheral base address. + * @param config The LLS power mode configuration structure + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeLls(SMC_Type *base, const smc_power_mode_lls_config_t *config); +#else +/*! + * @brief Configures the system to LLS power mode. + * + * @param base SMC peripheral base address. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeLls(SMC_Type *base); +#endif +#endif /* FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE */ + +#if (defined(FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) && FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE) +/*! + * @brief Configures the system to VLLS power mode. + * + * @param base SMC peripheral base address. + * @param config The VLLS power mode configuration structure. + * @return SMC configuration error code. + */ +status_t SMC_SetPowerModeVlls(SMC_Type *base, const smc_power_mode_vlls_config_t *config); +#endif /* FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_SMC_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sysmpu.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sysmpu.c new file mode 100644 index 00000000000..b89a7b20e4e --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sysmpu.c @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_sysmpu.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +const clock_ip_name_t g_sysmpuClock[FSL_FEATURE_SOC_SYSMPU_COUNT] = SYSMPU_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +void SYSMPU_Init(SYSMPU_Type *base, const sysmpu_config_t *config) +{ + assert(config); + uint8_t count; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Un-gate SYSMPU clock */ + CLOCK_EnableClock(g_sysmpuClock[0]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Initializes the regions. */ + for (count = 1; count < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT; count++) + { + base->WORD[count][3] = 0; /* VLD/VID+PID. */ + base->WORD[count][0] = 0; /* Start address. */ + base->WORD[count][1] = 0; /* End address. */ + base->WORD[count][2] = 0; /* Access rights. */ + base->RGDAAC[count] = 0; /* Alternate access rights. */ + } + + /* SYSMPU configure. */ + while (config) + { + SYSMPU_SetRegionConfig(base, &(config->regionConfig)); + config = config->next; + } + /* Enable SYSMPU. */ + SYSMPU_Enable(base, true); +} + +void SYSMPU_Deinit(SYSMPU_Type *base) +{ + /* Disable SYSMPU. */ + SYSMPU_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the clock. */ + CLOCK_DisableClock(g_sysmpuClock[0]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void SYSMPU_GetHardwareInfo(SYSMPU_Type *base, sysmpu_hardware_info_t *hardwareInform) +{ + assert(hardwareInform); + + uint32_t cesReg = base->CESR; + + hardwareInform->hardwareRevisionLevel = (cesReg & SYSMPU_CESR_HRL_MASK) >> SYSMPU_CESR_HRL_SHIFT; + hardwareInform->slavePortsNumbers = (cesReg & SYSMPU_CESR_NSP_MASK) >> SYSMPU_CESR_NSP_SHIFT; + hardwareInform->regionsNumbers = (sysmpu_region_total_num_t)((cesReg & SYSMPU_CESR_NRGD_MASK) >> SYSMPU_CESR_NRGD_SHIFT); +} + +void SYSMPU_SetRegionConfig(SYSMPU_Type *base, const sysmpu_region_config_t *regionConfig) +{ + assert(regionConfig); + assert(regionConfig->regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT); + + uint32_t wordReg = 0; + uint8_t msPortNum; + uint8_t regNumber = regionConfig->regionNum; + + /* The start and end address of the region descriptor. */ + base->WORD[regNumber][0] = regionConfig->startAddress; + base->WORD[regNumber][1] = regionConfig->endAddress; + + /* Set the privilege rights for master 0 ~ master 3. */ + for (msPortNum = 0; msPortNum < SYSMPU_MASTER_RWATTRIBUTE_START_PORT; msPortNum++) + { + wordReg |= SYSMPU_REGION_RWXRIGHTS_MASTER( + msPortNum, (((uint32_t)regionConfig->accessRights1[msPortNum].superAccessRights << 3U) | + (uint32_t)regionConfig->accessRights1[msPortNum].userAccessRights)); + +#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER + wordReg |= + SYSMPU_REGION_RWXRIGHTS_MASTER_PE(msPortNum, regionConfig->accessRights1[msPortNum].processIdentifierEnable); +#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */ + } + +#if FSL_FEATURE_SYSMPU_MASTER_COUNT > SYSMPU_MASTER_RWATTRIBUTE_START_PORT + /* Set the normal read write rights for master 4 ~ master 7. */ + for (msPortNum = SYSMPU_MASTER_RWATTRIBUTE_START_PORT; msPortNum < FSL_FEATURE_SYSMPU_MASTER_COUNT; + msPortNum++) + { + wordReg |= SYSMPU_REGION_RWRIGHTS_MASTER(msPortNum, + ((uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].readEnable << 1U | + (uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].writeEnable)); + } +#endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > SYSMPU_MASTER_RWATTRIBUTE_START_PORT */ + + /* Set region descriptor access rights. */ + base->WORD[regNumber][2] = wordReg; + + wordReg = SYSMPU_WORD_VLD(1); +#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER + wordReg |= SYSMPU_WORD_PID(regionConfig->processIdentifier) | SYSMPU_WORD_PIDMASK(regionConfig->processIdMask); +#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */ + + base->WORD[regNumber][3] = wordReg; +} + +void SYSMPU_SetRegionAddr(SYSMPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr) +{ + assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT); + + base->WORD[regionNum][0] = startAddr; + base->WORD[regionNum][1] = endAddr; +} + +void SYSMPU_SetRegionRwxMasterAccessRights(SYSMPU_Type *base, + uint32_t regionNum, + uint32_t masterNum, + const sysmpu_rwxrights_master_access_control_t *accessRights) +{ + assert(accessRights); + assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT); + assert(masterNum < SYSMPU_MASTER_RWATTRIBUTE_START_PORT); + + uint32_t mask = SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(masterNum); + uint32_t right = base->RGDAAC[regionNum]; + +#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER + mask |= SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(masterNum); +#endif + + /* Build rights control value. */ + right &= ~mask; + right |= SYSMPU_REGION_RWXRIGHTS_MASTER( + masterNum, ((uint32_t)(accessRights->superAccessRights << 3U) | accessRights->userAccessRights)); +#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER + right |= SYSMPU_REGION_RWXRIGHTS_MASTER_PE(masterNum, accessRights->processIdentifierEnable); +#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */ + + /* Set low master region access rights. */ + base->RGDAAC[regionNum] = right; +} + +#if FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 +void SYSMPU_SetRegionRwMasterAccessRights(SYSMPU_Type *base, + uint32_t regionNum, + uint32_t masterNum, + const sysmpu_rwrights_master_access_control_t *accessRights) +{ + assert(accessRights); + assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT); + assert(masterNum >= SYSMPU_MASTER_RWATTRIBUTE_START_PORT); + assert(masterNum <= (FSL_FEATURE_SYSMPU_MASTER_COUNT - 1)); + + uint32_t mask = SYSMPU_REGION_RWRIGHTS_MASTER_MASK(masterNum); + uint32_t right = base->RGDAAC[regionNum]; + + /* Build rights control value. */ + right &= ~mask; + right |= + SYSMPU_REGION_RWRIGHTS_MASTER(masterNum, (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable)); + /* Set low master region access rights. */ + base->RGDAAC[regionNum] = right; +} +#endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 */ + +bool SYSMPU_GetSlavePortErrorStatus(SYSMPU_Type *base, sysmpu_slave_t slaveNum) +{ + uint8_t sperr; + + sperr = ((base->CESR & SYSMPU_CESR_SPERR_MASK) >> SYSMPU_CESR_SPERR_SHIFT) & (0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1)); + + return (sperr != 0) ? true : false; +} + +void SYSMPU_GetDetailErrorAccessInfo(SYSMPU_Type *base, sysmpu_slave_t slaveNum, sysmpu_access_err_info_t *errInform) +{ + assert(errInform); + + uint16_t value; + uint32_t cesReg; + + /* Error address. */ + errInform->address = base->SP[slaveNum].EAR; + + /* Error detail information. */ + value = (base->SP[slaveNum].EDR & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT; + if (!value) + { + errInform->accessControl = kSYSMPU_NoRegionHit; + } + else if (!(value & (uint16_t)(value - 1))) + { + errInform->accessControl = kSYSMPU_NoneOverlappRegion; + } + else + { + errInform->accessControl = kSYSMPU_OverlappRegion; + } + + value = base->SP[slaveNum].EDR; + errInform->master = (uint32_t)((value & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT); + errInform->attributes = (sysmpu_err_attributes_t)((value & SYSMPU_EDR_EATTR_MASK) >> SYSMPU_EDR_EATTR_SHIFT); + errInform->accessType = (sysmpu_err_access_type_t)((value & SYSMPU_EDR_ERW_MASK) >> SYSMPU_EDR_ERW_SHIFT); +#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER + errInform->processorIdentification = (uint8_t)((value & SYSMPU_EDR_EPID_MASK) >> SYSMPU_EDR_EPID_SHIFT); +#endif + + /* Clears error slave port bit. */ + cesReg = (base->CESR & ~SYSMPU_CESR_SPERR_MASK) | ((0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1)) << SYSMPU_CESR_SPERR_SHIFT); + base->CESR = cesReg; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sysmpu.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sysmpu.h new file mode 100644 index 00000000000..6341a31e9d1 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sysmpu.h @@ -0,0 +1,435 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_SYSMPU_H_ +#define _FSL_SYSMPU_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sysmpu + * @{ + */ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SYSMPU driver version 2.2.0. */ +#define FSL_SYSMPU_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +/*! @brief define the start master port with read and write attributes. */ +#define SYSMPU_MASTER_RWATTRIBUTE_START_PORT (4) + +/*! @brief SYSMPU the bit shift for masters with privilege rights: read write and execute. */ +#define SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n) (n * 6) + +/*! @brief SYSMPU masters with read, write and execute rights bit mask. */ +#define SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(n) (0x1Fu << SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n)) + +/*! @brief SYSMPU masters with read, write and execute rights bit width. */ +#define SYSMPU_REGION_RWXRIGHTS_MASTER_WIDTH 5 + +/*! @brief SYSMPU masters with read, write and execute rights priority setting. */ +#define SYSMPU_REGION_RWXRIGHTS_MASTER(n, x) \ + (((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))) & SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(n)) + +/*! @brief SYSMPU masters with read, write and execute rights process enable bit shift. */ +#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n) (n * 6 + SYSMPU_REGION_RWXRIGHTS_MASTER_WIDTH) + +/*! @brief SYSMPU masters with read, write and execute rights process enable bit mask. */ +#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n) (0x1u << SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n)) + +/*! @brief SYSMPU masters with read, write and execute rights process enable setting. */ +#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE(n, x) \ + (((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))) & SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n)) + +/*! @brief SYSMPU masters with normal read write permission bit shift. */ +#define SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n) ((n - SYSMPU_MASTER_RWATTRIBUTE_START_PORT) * 2 + 24) + +/*! @brief SYSMPU masters with normal read write rights bit mask. */ +#define SYSMPU_REGION_RWRIGHTS_MASTER_MASK(n) (0x3u << SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n)) + +/*! @brief SYSMPU masters with normal read write rights priority setting. */ +#define SYSMPU_REGION_RWRIGHTS_MASTER(n, x) \ + (((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n))) & SYSMPU_REGION_RWRIGHTS_MASTER_MASK(n)) + + +/*! @brief Describes the number of SYSMPU regions. */ +typedef enum _sysmpu_region_total_num +{ + kSYSMPU_8Regions = 0x0U, /*!< SYSMPU supports 8 regions. */ + kSYSMPU_12Regions = 0x1U, /*!< SYSMPU supports 12 regions. */ + kSYSMPU_16Regions = 0x2U /*!< SYSMPU supports 16 regions. */ +} sysmpu_region_total_num_t; + +/*! @brief SYSMPU slave port number. */ +typedef enum _sysmpu_slave +{ + kSYSMPU_Slave0 = 0U, /*!< SYSMPU slave port 0. */ + kSYSMPU_Slave1 = 1U, /*!< SYSMPU slave port 1. */ + kSYSMPU_Slave2 = 2U, /*!< SYSMPU slave port 2. */ + kSYSMPU_Slave3 = 3U, /*!< SYSMPU slave port 3. */ + kSYSMPU_Slave4 = 4U, /*!< SYSMPU slave port 4. */ +#if FSL_FEATURE_SYSMPU_SLAVE_COUNT > 5 + kSYSMPU_Slave5 = 5U, /*!< SYSMPU slave port 5. */ +#endif +#if FSL_FEATURE_SYSMPU_SLAVE_COUNT > 6 + kSYSMPU_Slave6 = 6U, /*!< SYSMPU slave port 6. */ +#endif +#if FSL_FEATURE_SYSMPU_SLAVE_COUNT > 7 + kSYSMPU_Slave7 = 7U, /*!< SYSMPU slave port 7. */ +#endif +} sysmpu_slave_t; + +/*! @brief SYSMPU error access control detail. */ +typedef enum _sysmpu_err_access_control +{ + kSYSMPU_NoRegionHit = 0U, /*!< No region hit error. */ + kSYSMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */ + kSYSMPU_OverlappRegion = 2U /*!< Access overlapping region error. */ +} sysmpu_err_access_control_t; + +/*! @brief SYSMPU error access type. */ +typedef enum _sysmpu_err_access_type +{ + kSYSMPU_ErrTypeRead = 0U, /*!< SYSMPU error access type --- read. */ + kSYSMPU_ErrTypeWrite = 1U /*!< SYSMPU error access type --- write. */ +} sysmpu_err_access_type_t; + +/*! @brief SYSMPU access error attributes.*/ +typedef enum _sysmpu_err_attributes +{ + kSYSMPU_InstructionAccessInUserMode = 0U, /*!< Access instruction error in user mode. */ + kSYSMPU_DataAccessInUserMode = 1U, /*!< Access data error in user mode. */ + kSYSMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */ + kSYSMPU_DataAccessInSupervisorMode = 3U /*!< Access data error in supervisor mode. */ +} sysmpu_err_attributes_t; + +/*! @brief SYSMPU access rights in supervisor mode for bus master 0 ~ 3. */ +typedef enum _sysmpu_supervisor_access_rights +{ + kSYSMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */ + kSYSMPU_SupervisorReadExecute = 1U, /*!< Read and execute operations are allowed in supervisor mode. */ + kSYSMPU_SupervisorReadWrite = 2U, /*!< Read write operations are allowed in supervisor mode. */ + kSYSMPU_SupervisorEqualToUsermode = 3U /*!< Access permission equal to user mode. */ +} sysmpu_supervisor_access_rights_t; + +/*! @brief SYSMPU access rights in user mode for bus master 0 ~ 3. */ +typedef enum _sysmpu_user_access_rights +{ + kSYSMPU_UserNoAccessRights = 0U, /*!< No access allowed in user mode. */ + kSYSMPU_UserExecute = 1U, /*!< Execute operation is allowed in user mode. */ + kSYSMPU_UserWrite = 2U, /*!< Write operation is allowed in user mode. */ + kSYSMPU_UserWriteExecute = 3U, /*!< Write and execute operations are allowed in user mode. */ + kSYSMPU_UserRead = 4U, /*!< Read is allowed in user mode. */ + kSYSMPU_UserReadExecute = 5U, /*!< Read and execute operations are allowed in user mode. */ + kSYSMPU_UserReadWrite = 6U, /*!< Read and write operations are allowed in user mode. */ + kSYSMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */ +} sysmpu_user_access_rights_t; + +/*! @brief SYSMPU hardware basic information. */ +typedef struct _sysmpu_hardware_info +{ + uint8_t hardwareRevisionLevel; /*!< Specifies the SYSMPU's hardware and definition reversion level. */ + uint8_t slavePortsNumbers; /*!< Specifies the number of slave ports connected to SYSMPU. */ + sysmpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */ +} sysmpu_hardware_info_t; + +/*! @brief SYSMPU detail error access information. */ +typedef struct _sysmpu_access_err_info +{ + uint32_t master; /*!< Access error master. */ + sysmpu_err_attributes_t attributes; /*!< Access error attributes. */ + sysmpu_err_access_type_t accessType; /*!< Access error type. */ + sysmpu_err_access_control_t accessControl; /*!< Access error control. */ + uint32_t address; /*!< Access error address. */ +#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER + uint8_t processorIdentification; /*!< Access error processor identification. */ +#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */ +} sysmpu_access_err_info_t; + +/*! @brief SYSMPU read/write/execute rights control for bus master 0 ~ 3. */ +typedef struct _sysmpu_rwxrights_master_access_control +{ + sysmpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */ + sysmpu_user_access_rights_t userAccessRights; /*!< Master access rights in user mode. */ +#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER + bool processIdentifierEnable; /*!< Enables or disables process identifier. */ +#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */ +} sysmpu_rwxrights_master_access_control_t; + +/*! @brief SYSMPU read/write access control for bus master 4 ~ 7. */ +typedef struct _sysmpu_rwrights_master_access_control +{ + bool writeEnable; /*!< Enables or disables write permission. */ + bool readEnable; /*!< Enables or disables read permission. */ +} sysmpu_rwrights_master_access_control_t; + +/*! + * @brief SYSMPU region configuration structure. + * + * This structure is used to configure the regionNum region. + * The accessRights1[0] ~ accessRights1[3] are used to configure the bus master + * 0 ~ 3 with the privilege rights setting. The accessRights2[0] ~ accessRights2[3] + * are used to configure the high master 4 ~ 7 with the normal read write permission. + * The master port assignment is the chip configuration. Normally, the core is the + * master 0, debugger is the master 1. + * Note that the SYSMPU assigns a priority scheme where the debugger is treated as the highest + * priority master followed by the core and then all the remaining masters. + * SYSMPU protection does not allow writes from the core to affect the "regionNum 0" start + * and end address nor the permissions associated with the debugger. It can only write + * the permission fields associated with the other masters. This protection guarantees that + * the debugger always has access to the entire address space and those rights can't + * be changed by the core or any other bus master. Prepare + * the region configuration when regionNum is 0. + */ +typedef struct _sysmpu_region_config +{ + uint32_t regionNum; /*!< SYSMPU region number, range form 0 ~ FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1. */ + uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by SYSMPU. The actual + start address is 0-modulo-32 byte address. */ + uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by SYSMPU. The actual end + address is 31-modulo-32 byte address. */ + sysmpu_rwxrights_master_access_control_t accessRights1[4]; /*!< Masters with read, write and execute rights setting. */ + sysmpu_rwrights_master_access_control_t accessRights2[4]; /*!< Masters with normal read write rights setting. */ +#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER + uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */ + uint8_t + processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */ +#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */ +} sysmpu_region_config_t; + +/*! + * @brief The configuration structure for the SYSMPU initialization. + * + * This structure is used when calling the SYSMPU_Init function. + */ +typedef struct _sysmpu_config +{ + sysmpu_region_config_t regionConfig; /*!< Region access permission. */ + struct _sysmpu_config *next; /*!< Pointer to the next structure. */ +} sysmpu_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the SYSMPU with the user configuration structure. + * + * This function configures the SYSMPU module with the user-defined configuration. + * + * @param base SYSMPU peripheral base address. + * @param config The pointer to the configuration structure. + */ +void SYSMPU_Init(SYSMPU_Type *base, const sysmpu_config_t *config); + +/*! + * @brief Deinitializes the SYSMPU regions. + * + * @param base SYSMPU peripheral base address. + */ +void SYSMPU_Deinit(SYSMPU_Type *base); + +/* @}*/ + +/*! + * @name Basic Control Operations + * @{ + */ + +/*! + * @brief Enables/disables the SYSMPU globally. + * + * Call this API to enable or disable the SYSMPU module. + * + * @param base SYSMPU peripheral base address. + * @param enable True enable SYSMPU, false disable SYSMPU. + */ +static inline void SYSMPU_Enable(SYSMPU_Type *base, bool enable) +{ + if (enable) + { + /* Enable the SYSMPU globally. */ + base->CESR |= SYSMPU_CESR_VLD_MASK; + } + else + { /* Disable the SYSMPU globally. */ + base->CESR &= ~SYSMPU_CESR_VLD_MASK; + } +} + +/*! + * @brief Enables/disables the SYSMPU for a special region. + * + * When SYSMPU is enabled, call this API to disable an unused region + * of an enabled SYSMPU. Call this API to minimize the power dissipation. + * + * @param base SYSMPU peripheral base address. + * @param number SYSMPU region number. + * @param enable True enable the special region SYSMPU, false disable the special region SYSMPU. + */ +static inline void SYSMPU_RegionEnable(SYSMPU_Type *base, uint32_t number, bool enable) +{ + if (enable) + { + /* Enable the #number region SYSMPU. */ + base->WORD[number][3] |= SYSMPU_WORD_VLD_MASK; + } + else + { /* Disable the #number region SYSMPU. */ + base->WORD[number][3] &= ~SYSMPU_WORD_VLD_MASK; + } +} + +/*! + * @brief Gets the SYSMPU basic hardware information. + * + * @param base SYSMPU peripheral base address. + * @param hardwareInform The pointer to the SYSMPU hardware information structure. See "sysmpu_hardware_info_t". + */ +void SYSMPU_GetHardwareInfo(SYSMPU_Type *base, sysmpu_hardware_info_t *hardwareInform); + +/*! + * @brief Sets the SYSMPU region. + * + * Note: Due to the SYSMPU protection, the region number 0 does not allow writes from + * core to affect the start and end address nor the permissions associated with + * the debugger. It can only write the permission fields associated + * with the other masters. + * + * @param base SYSMPU peripheral base address. + * @param regionConfig The pointer to the SYSMPU user configuration structure. See "sysmpu_region_config_t". + */ +void SYSMPU_SetRegionConfig(SYSMPU_Type *base, const sysmpu_region_config_t *regionConfig); + +/*! + * @brief Sets the region start and end address. + * + * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by SYSMPU. + * The actual start address by SYSMPU is 0-modulo-32 byte address. + * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by SYSMPU. + * The end address used by the SYSMPU is 31-modulo-32 byte address. + * Note: Due to the SYSMPU protection, the startAddr and endAddr can't be + * changed by the core when regionNum is 0. + * + * @param base SYSMPU peripheral base address. + * @param regionNum SYSMPU region number. The range is from 0 to + * FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1. + * @param startAddr Region start address. + * @param endAddr Region end address. + */ +void SYSMPU_SetRegionAddr(SYSMPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr); + +/*! + * @brief Sets the SYSMPU region access rights for masters with read, write, and execute rights. + * The SYSMPU access rights depend on two board classifications of bus masters. + * The privilege rights masters and the normal rights masters. + * The privilege rights masters have the read, write, and execute access rights. + * Except the normal read and write rights, the execute rights are also + * allowed for these masters. The privilege rights masters normally range from + * bus masters 0 - 3. However, the maximum master number is device-specific. + * See the "SYSMPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX". + * The normal rights masters access rights control see + * "SYSMPU_SetRegionRwMasterAccessRights()". + * + * @param base SYSMPU peripheral base address. + * @param regionNum SYSMPU region number. Should range from 0 to + * FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1. + * @param masterNum SYSMPU bus master number. Should range from 0 to + * SYSMPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX. + * @param accessRights The pointer to the SYSMPU access rights configuration. See "sysmpu_rwxrights_master_access_control_t". + */ +void SYSMPU_SetRegionRwxMasterAccessRights(SYSMPU_Type *base, + uint32_t regionNum, + uint32_t masterNum, + const sysmpu_rwxrights_master_access_control_t *accessRights); +#if FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 +/*! + * @brief Sets the SYSMPU region access rights for masters with read and write rights. + * The SYSMPU access rights depend on two board classifications of bus masters. + * The privilege rights masters and the normal rights masters. + * The normal rights masters only have the read and write access permissions. + * The privilege rights access control see "SYSMPU_SetRegionRwxMasterAccessRights". + * + * @param base SYSMPU peripheral base address. + * @param regionNum SYSMPU region number. The range is from 0 to + * FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1. + * @param masterNum SYSMPU bus master number. Should range from SYSMPU_MASTER_RWATTRIBUTE_START_PORT + * to ~ FSL_FEATURE_SYSMPU_MASTER_COUNT - 1. + * @param accessRights The pointer to the SYSMPU access rights configuration. See "sysmpu_rwrights_master_access_control_t". + */ +void SYSMPU_SetRegionRwMasterAccessRights(SYSMPU_Type *base, + uint32_t regionNum, + uint32_t masterNum, + const sysmpu_rwrights_master_access_control_t *accessRights); +#endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 */ +/*! + * @brief Gets the numbers of slave ports where errors occur. + * + * @param base SYSMPU peripheral base address. + * @param slaveNum SYSMPU slave port number. + * @return The slave ports error status. + * true - error happens in this slave port. + * false - error didn't happen in this slave port. + */ +bool SYSMPU_GetSlavePortErrorStatus(SYSMPU_Type *base, sysmpu_slave_t slaveNum); + +/*! + * @brief Gets the SYSMPU detailed error access information. + * + * @param base SYSMPU peripheral base address. + * @param slaveNum SYSMPU slave port number. + * @param errInform The pointer to the SYSMPU access error information. See "sysmpu_access_err_info_t". + */ +void SYSMPU_GetDetailErrorAccessInfo(SYSMPU_Type *base, sysmpu_slave_t slaveNum, sysmpu_access_err_info_t *errInform); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SYSMPU_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_uart.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_uart.c new file mode 100644 index 00000000000..17d9260027b --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_uart.c @@ -0,0 +1,1230 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* UART transfer state. */ +enum _uart_tansfer_states +{ + kUART_TxIdle, /* TX idle. */ + kUART_TxBusy, /* TX busy. */ + kUART_RxIdle, /* RX idle. */ + kUART_RxBusy, /* RX busy. */ + kUART_RxFramingError, /* Rx framing error */ + kUART_RxParityError /* Rx parity error */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the UART instance from peripheral base address. + * + * @param base UART peripheral base address. + * @return UART instance. + */ +uint32_t UART_GetInstance(UART_Type *base); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle UART handle pointer. + * @return Length of received data in RX ring buffer. + */ +static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle); + +/*! + * @brief Check whether the RX ring buffer is full. + * + * @param handle UART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @param data Start addresss of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start addresss of the data to write. + * @param length Size of the buffer to be sent. + */ +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of UART handle. */ +#if (defined(UART5)) +#define UART_HANDLE_ARRAY_SIZE 6 +#else /* UART5 */ +#if (defined(UART4)) +#define UART_HANDLE_ARRAY_SIZE 5 +#else /* UART4 */ +#if (defined(UART3)) +#define UART_HANDLE_ARRAY_SIZE 4 +#else /* UART3 */ +#if (defined(UART2)) +#define UART_HANDLE_ARRAY_SIZE 3 +#else /* UART2 */ +#if (defined(UART1)) +#define UART_HANDLE_ARRAY_SIZE 2 +#else /* UART1 */ +#if (defined(UART0)) +#define UART_HANDLE_ARRAY_SIZE 1 +#else /* UART0 */ +#error No UART instance. +#endif /* UART 0 */ +#endif /* UART 1 */ +#endif /* UART 2 */ +#endif /* UART 3 */ +#endif /* UART 4 */ +#endif /* UART 5 */ +static uart_handle_t *s_uartHandle[UART_HANDLE_ARRAY_SIZE]; +/* Array of UART peripheral base address. */ +static UART_Type *const s_uartBases[] = UART_BASE_PTRS; + +/* Array of UART IRQ number. */ +static const IRQn_Type s_uartIRQ[] = UART_RX_TX_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of UART clock name. */ +static const clock_ip_name_t s_uartClock[] = UART_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* UART ISR for transactional APIs. */ +static uart_isr_t s_uartIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t UART_GetInstance(UART_Type *base) +{ + uint32_t instance; + uint32_t uartArrayCount = (sizeof(s_uartBases) / sizeof(s_uartBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < uartArrayCount; instance++) + { + if (s_uartBases[instance] == base) + { + break; + } + } + + assert(instance < uartArrayCount); + + return instance; +} + +static size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle) +{ + assert(handle); + + size_t size; + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + + return size; +} + +static bool UART_TransferIsRxRingBufferFull(uart_handle_t *handle) +{ + assert(handle); + + bool full; + + if (UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + + return full; +} + +status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz) +{ + assert(config); + assert(config->baudRate_Bps); +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->txFifoWatermark); + assert(FSL_FEATURE_UART_FIFO_SIZEn(base) >= config->rxFifoWatermark); +#endif + + uint16_t sbr = 0; + uint8_t temp = 0; + uint32_t baudDiff = 0; + + /* Calculate the baud rate modulo divisor, sbr*/ + sbr = srcClock_Hz / (config->baudRate_Bps * 16); + /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */ + if (sbr == 0) + { + sbr = 1; + } +#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT + /* Determine if a fractional divider is needed to fine tune closer to the + * desired baud, each value of brfa is in 1/32 increments, + * hence the multiply-by-32. */ + uint32_t tempBaud = 0; + + uint16_t brfa = (2 * srcClock_Hz / (config->baudRate_Bps)) - 32 * sbr; + + /* Calculate the baud rate based on the temporary SBR values and BRFA */ + tempBaud = (srcClock_Hz * 2 / ((sbr * 32 + brfa))); + baudDiff = + (tempBaud > config->baudRate_Bps) ? (tempBaud - config->baudRate_Bps) : (config->baudRate_Bps - tempBaud); + +#else + /* Calculate the baud rate based on the temporary SBR values */ + baudDiff = (srcClock_Hz / (sbr * 16)) - config->baudRate_Bps; + + /* Select the better value between sbr and (sbr + 1) */ + if (baudDiff > (config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1))))) + { + baudDiff = config->baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1))); + sbr++; + } +#endif + + /* next, check to see if actual baud rate is within 3% of desired baud rate + * based on the calculate SBR value */ + if (baudDiff > ((config->baudRate_Bps / 100) * 3)) + { + /* Unacceptable baud rate difference of more than 3%*/ + return kStatus_UART_BaudrateNotSupport; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable uart clock */ + CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable UART TX RX before setting. */ + base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); + + /* Write the sbr value to the BDH and BDL registers*/ + base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8); + base->BDL = (uint8_t)sbr; + +#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT + /* Write the brfa value to the register*/ + base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); +#endif + + /* Set bit count and parity mode. */ + temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); + + if (kUART_ParityDisabled != config->parityMode) + { + temp |= (UART_C1_M_MASK | (uint8_t)config->parityMode); + } + + base->C1 = temp; + +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + /* Set stop bit per char */ + base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Set tx/rx FIFO watermark */ + base->TWFIFO = config->txFifoWatermark; + base->RWFIFO = config->rxFifoWatermark; + + /* Enable tx/rx FIFO */ + base->PFIFO |= (UART_PFIFO_TXFE_MASK | UART_PFIFO_RXFE_MASK); + + /* Flush FIFO */ + base->CFIFO |= (UART_CFIFO_TXFLUSH_MASK | UART_CFIFO_RXFLUSH_MASK); +#endif + + /* Enable TX/RX base on configure structure. */ + temp = base->C2; + + if (config->enableTx) + { + temp |= UART_C2_TE_MASK; + } + + if (config->enableRx) + { + temp |= UART_C2_RE_MASK; + } + + base->C2 = temp; + + return kStatus_Success; +} + +void UART_Deinit(UART_Type *base) +{ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0 != base->TCFIFO) + { + } +#endif + /* Wait last char shoft out */ + while (0 == (base->S1 & UART_S1_TC_MASK)) + { + } + + /* Disable the module. */ + base->C2 = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable uart clock */ + CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void UART_GetDefaultConfig(uart_config_t *config) +{ + assert(config); + + config->baudRate_Bps = 115200U; + config->parityMode = kUART_ParityDisabled; +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + config->txFifoWatermark = 0; + config->rxFifoWatermark = 1; +#endif + config->enableTx = false; + config->enableRx = false; +} + +status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + assert(baudRate_Bps); + + uint16_t sbr = 0; + uint32_t baudDiff = 0; + uint8_t oldCtrl; + + /* Calculate the baud rate modulo divisor, sbr*/ + sbr = srcClock_Hz / (baudRate_Bps * 16); + /* set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate */ + if (sbr == 0) + { + sbr = 1; + } +#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT + /* Determine if a fractional divider is needed to fine tune closer to the + * desired baud, each value of brfa is in 1/32 increments, + * hence the multiply-by-32. */ + uint32_t tempBaud = 0; + + uint16_t brfa = (2 * srcClock_Hz / (baudRate_Bps)) - 32 * sbr; + + /* Calculate the baud rate based on the temporary SBR values and BRFA */ + tempBaud = (srcClock_Hz * 2 / ((sbr * 32 + brfa))); + baudDiff = (tempBaud > baudRate_Bps) ? (tempBaud - baudRate_Bps) : (baudRate_Bps - tempBaud); +#else + /* Calculate the baud rate based on the temporary SBR values */ + baudDiff = (srcClock_Hz / (sbr * 16)) - baudRate_Bps; + + /* Select the better value between sbr and (sbr + 1) */ + if (baudDiff > (baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1))))) + { + baudDiff = baudRate_Bps - (srcClock_Hz / (16 * (sbr + 1))); + sbr++; + } +#endif + + /* next, check to see if actual baud rate is within 3% of desired baud rate + * based on the calculate SBR value */ + if (baudDiff < ((baudRate_Bps / 100) * 3)) + { + /* Store C2 before disable Tx and Rx */ + oldCtrl = base->C2; + + /* Disable UART TX RX before setting. */ + base->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK); + + /* Write the sbr value to the BDH and BDL registers*/ + base->BDH = (base->BDH & ~UART_BDH_SBR_MASK) | (uint8_t)(sbr >> 8); + base->BDL = (uint8_t)sbr; + +#if defined(FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT) && FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT + /* Write the brfa value to the register*/ + base->C4 = (base->C4 & ~UART_C4_BRFA_MASK) | (brfa & UART_C4_BRFA_MASK); +#endif + /* Restore C2. */ + base->C2 = oldCtrl; + + return kStatus_Success; + } + else + { + /* Unacceptable baud rate difference of more than 3%*/ + return kStatus_UART_BaudrateNotSupport; + } +} + +void UART_EnableInterrupts(UART_Type *base, uint32_t mask) +{ + mask &= kUART_AllInterruptsEnable; + + /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH)) + */ + base->BDH |= mask; + base->C2 |= (mask >> 8); + base->C3 |= (mask >> 16); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + base->CFIFO |= (mask >> 24); +#endif +} + +void UART_DisableInterrupts(UART_Type *base, uint32_t mask) +{ + mask &= kUART_AllInterruptsEnable; + + /* The interrupt mask is combined by control bits from several register: ((CFIFO<<24) | (C3<<16) | (C2<<8) |(BDH)) + */ + base->BDH &= ~mask; + base->C2 &= ~(mask >> 8); + base->C3 &= ~(mask >> 16); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + base->CFIFO &= ~(mask >> 24); +#endif +} + +uint32_t UART_GetEnabledInterrupts(UART_Type *base) +{ + uint32_t temp; + + temp = base->BDH | ((uint32_t)(base->C2) << 8) | ((uint32_t)(base->C3) << 16); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + temp |= ((uint32_t)(base->CFIFO) << 24); +#endif + + return temp & kUART_AllInterruptsEnable; +} + +uint32_t UART_GetStatusFlags(UART_Type *base) +{ + uint32_t status_flag; + + status_flag = base->S1 | ((uint32_t)(base->S2) << 8); + +#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS + status_flag |= ((uint32_t)(base->ED) << 16); +#endif + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + status_flag |= ((uint32_t)(base->SFIFO) << 24); +#endif + + return status_flag; +} + +status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask) +{ + uint8_t reg = base->S2; + status_t status; + +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + reg &= ~(UART_S2_RXEDGIF_MASK | UART_S2_LBKDIF_MASK); +#else + reg &= ~UART_S2_RXEDGIF_MASK; +#endif + + base->S2 = reg | (uint8_t)(mask >> 8); + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + base->SFIFO = (uint8_t)(mask >> 24); +#endif + + if (mask & (kUART_IdleLineFlag | kUART_NoiseErrorFlag | kUART_FramingErrorFlag | kUART_ParityErrorFlag)) + { + /* Read base->D to clear the flags. */ + (void)base->S1; + (void)base->D; + } + + if (mask & kUART_RxOverrunFlag) + { + /* Read base->D to clear the flags and Flush all data in FIFO. */ + (void)base->S1; + (void)base->D; +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */ + base->CFIFO |= UART_CFIFO_RXFLUSH_MASK; +#endif + } + + /* If some flags still pending. */ + if (mask & UART_GetStatusFlags(base)) + { + /* Some flags can only clear or set by the hardware itself, these flags are: kUART_TxDataRegEmptyFlag, + kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, + kUART_ParityErrorInRxDataRegFlag, kUART_TxFifoEmptyFlag, kUART_RxFifoEmptyFlag. */ + status = kStatus_UART_FlagCannotClearManually; + } + else + { + status = kStatus_Success; + } + + return status; +} + +void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + /* This API can only ensure that the data is written into the data buffer but can't + ensure all data in the data buffer are sent into the transmit shift buffer. */ + while (length--) + { + while (!(base->S1 & UART_S1_TDRE_MASK)) + { + } + base->D = *(data++); + } +} + +static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length) +{ + assert(data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->D = data[i]; + } +} + +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + assert(data); + + uint32_t statusFlag; + + while (length--) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + while (!base->RCFIFO) +#else + while (!(base->S1 & UART_S1_RDRF_MASK)) +#endif + { + statusFlag = UART_GetStatusFlags(base); + + if (statusFlag & kUART_RxOverrunFlag) + { + return kStatus_UART_RxHardwareOverrun; + } + + if (statusFlag & kUART_NoiseErrorFlag) + { + return kStatus_UART_NoiseError; + } + + if (statusFlag & kUART_FramingErrorFlag) + { + return kStatus_UART_FramingError; + } + + if (statusFlag & kUART_ParityErrorFlag) + { + return kStatus_UART_ParityError; + } + } + *(data++) = base->D; + } + + return kStatus_Success; +} + +static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length) +{ + assert(data); + + size_t i; + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + data[i] = base->D; + } +} + +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the TX/RX state. */ + handle->rxState = kUART_RxIdle; + handle->txState = kUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->RWFIFO = 1U; +#endif + + /* Get instance from peripheral base address. */ + instance = UART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_uartHandle[instance] = handle; + + s_uartIsr = UART_TransferHandleIRQ; + /* Enable interrupt in NVIC. */ + EnableIRQ(s_uartIRQ[instance]); +} + +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + assert(handle); + assert(ringBuffer); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + UART_EnableInterrupts( + base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | kUART_FramingErrorInterruptEnable); + /* Enable parity error interrupt when parity mode is enable*/ + if (UART_C1_PE_MASK & base->C1) + { + UART_EnableInterrupts(base, kUART_ParityErrorInterruptEnable); + } +} + +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + if (handle->rxState == kUART_RxIdle) + { + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | + kUART_FramingErrorInterruptEnable); + /* Disable parity error interrupt when parity mode is enable*/ + if (UART_C1_PE_MASK & base->C1) + { + UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable); + } + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + assert(xfer->dataSize); + assert(xfer->data); + + status_t status; + + /* Return error if current TX busy. */ + if (kUART_TxBusy == handle->txState) + { + status = kStatus_UART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kUART_TxBusy; + + /* Enable transmiter interrupt. */ + UART_EnableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + UART_DisableInterrupts(base, kUART_TxDataRegEmptyInterruptEnable | kUART_TransmissionCompleteInterruptEnable); + + handle->txDataSize = 0; + handle->txState = kUART_TxIdle; +} + +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(count); + + if (kUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes) +{ + assert(handle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + + if (kUART_RxBusy == handle->rxState) + { + status = kStatus_UART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable UART RX IRQ, protect ring buffer. */ + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = UART_TransferGetRxRingBufferLength(handle); + + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUART_RxBusy; + } + + /* Enable UART RX IRQ if previously enabled. */ + UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable); + + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUART_RxBusy; + + /* Enable RX/Rx overrun/framing error interrupt. */ + UART_EnableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | + kUART_FramingErrorInterruptEnable); + /* Enable parity error interrupt when parity mode is enable*/ + if (UART_C1_PE_MASK & base->C1) + { + UART_EnableInterrupts(base, kUART_ParityErrorInterruptEnable); + } + } + + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | + kUART_FramingErrorInterruptEnable); + /* Disable parity error interrupt when parity mode is enable*/ + if (UART_C1_PE_MASK & base->C1) + { + UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable); + } + } + + handle->rxDataSize = 0U; + handle->rxState = kUART_RxIdle; +} + +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(count); + + if (kUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle) +{ + assert(handle); + + uint8_t count; + uint8_t tempCount; + + /* If RX framing error */ + if (UART_S1_FE_MASK & base->S1) + { + /* Read base->D to clear framing error flag, otherwise the RX does not work. */ + while (base->S1 & UART_S1_RDRF_MASK) + { + (void)base->D; + } +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */ + base->CFIFO |= UART_CFIFO_RXFLUSH_MASK; +#endif + + handle->rxState = kUART_RxFramingError; + handle->rxDataSize = 0U; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_FramingError, handle->userData); + } + } + + /* If RX parity error */ + if (UART_S1_PF_MASK & base->S1) + { + /* Read base->D to clear parity error flag, otherwise the RX does not work. */ + while (base->S1 & UART_S1_RDRF_MASK) + { + (void)base->D; + } +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */ + base->CFIFO |= UART_CFIFO_RXFLUSH_MASK; +#endif + + handle->rxState = kUART_RxParityError; + handle->rxDataSize = 0U; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_ParityError, handle->userData); + } + } + + /* If RX overrun. */ + if (UART_S1_OR_MASK & base->S1) + { + /* Read base->D to clear overrun flag, otherwise the RX does not work. */ + while (base->S1 & UART_S1_RDRF_MASK) + { + (void)base->D; + } +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Flush FIFO date, otherwise FIFO pointer will be in unknown state. */ + base->CFIFO |= UART_CFIFO_RXFLUSH_MASK; +#endif + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data register full */ + if ((UART_S1_RDRF_MASK & base->S1) && (UART_C2_RIE_MASK & base->C2)) + { +/* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + count = base->RCFIFO; +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((count) && (handle->rxDataSize)) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + tempCount = MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + UART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kUART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (handle->rxRingBuffer) + { + while (count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overrided. */ + if (UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->D; + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + + else if (!handle->rxDataSize) + { + /* Disable RX interrupt/overrun interrupt/fram error interrupt */ + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | + kUART_FramingErrorInterruptEnable); + + /* Disable parity error interrupt when parity mode is enable*/ + if (UART_C1_PE_MASK & base->C1) + { + UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable); + } + } + else + { + } + } + + /* If framing error or parity error happened, stop the RX interrupt when ues no ring buffer */ + if (((handle->rxState == kUART_RxFramingError) || (handle->rxState == kUART_RxParityError)) && + (!handle->rxRingBuffer)) + { + UART_DisableInterrupts(base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | + kUART_FramingErrorInterruptEnable); + + /* Disable parity error interrupt when parity mode is enable*/ + if (UART_C1_PE_MASK & base->C1) + { + UART_DisableInterrupts(base, kUART_ParityErrorInterruptEnable); + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((base->S1 & UART_S1_TDRE_MASK) && (base->C2 & UART_C2_TIE_MASK)) + { +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + count = FSL_FEATURE_UART_FIFO_SIZEn(base) - base->TCFIFO; +#else + count = 1; +#endif + + while ((count) && (handle->txDataSize)) + { +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + tempCount = MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + UART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData += tempCount; + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, TX finished. */ + if (!handle->txDataSize) + { + handle->txState = kUART_TxIdle; + + /* Disable TX register empty interrupt. */ + base->C2 = (base->C2 & ~UART_C2_TIE_MASK); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData); + } + } + } + } +} + +void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle) +{ + /* To be implemented by User. */ +} + +#if defined(UART0) +#if ((!(defined(FSL_FEATURE_SOC_LPSCI_COUNT))) || \ + ((defined(FSL_FEATURE_SOC_LPSCI_COUNT)) && (FSL_FEATURE_SOC_LPSCI_COUNT == 0))) +void UART0_DriverIRQHandler(void) +{ + s_uartIsr(UART0, s_uartHandle[0]); +} + +void UART0_RX_TX_DriverIRQHandler(void) +{ + UART0_DriverIRQHandler(); +} +#endif +#endif + +#if defined(UART1) +void UART1_DriverIRQHandler(void) +{ + s_uartIsr(UART1, s_uartHandle[1]); +} + +void UART1_RX_TX_DriverIRQHandler(void) +{ + UART1_DriverIRQHandler(); +} +#endif + +#if defined(UART2) +void UART2_DriverIRQHandler(void) +{ + s_uartIsr(UART2, s_uartHandle[2]); +} + +void UART2_RX_TX_DriverIRQHandler(void) +{ + UART2_DriverIRQHandler(); +} +#endif + +#if defined(UART3) +void UART3_DriverIRQHandler(void) +{ + s_uartIsr(UART3, s_uartHandle[3]); +} + +void UART3_RX_TX_DriverIRQHandler(void) +{ + UART3_DriverIRQHandler(); +} +#endif + +#if defined(UART4) +void UART4_DriverIRQHandler(void) +{ + s_uartIsr(UART4, s_uartHandle[4]); +} + +void UART4_RX_TX_DriverIRQHandler(void) +{ + UART4_DriverIRQHandler(); +} +#endif + +#if defined(UART5) +void UART5_DriverIRQHandler(void) +{ + s_uartIsr(UART5, s_uartHandle[5]); +} + +void UART5_RX_TX_DriverIRQHandler(void) +{ + UART5_DriverIRQHandler(); +} +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_uart.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_uart.h new file mode 100644 index 00000000000..451baa9ffd3 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_uart.h @@ -0,0 +1,777 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_UART_H_ +#define _FSL_UART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup uart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief UART driver version 2.1.4. */ +#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*@}*/ + +/*! @brief Error codes for the UART driver. */ +enum _uart_status +{ + kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_UART, 0), /*!< Transmitter is busy. */ + kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_UART, 1), /*!< Receiver is busy. */ + kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_UART, 2), /*!< UART transmitter is idle. */ + kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_UART, 3), /*!< UART receiver is idle. */ + kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 4), /*!< TX FIFO watermark too large */ + kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 5), /*!< RX FIFO watermark too large */ + kStatus_UART_FlagCannotClearManually = + MAKE_STATUS(kStatusGroup_UART, 6), /*!< UART flag can't be manually cleared. */ + kStatus_UART_Error = MAKE_STATUS(kStatusGroup_UART, 7), /*!< Error happens on UART. */ + kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_UART, 8), /*!< UART RX software ring buffer overrun. */ + kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_UART, 9), /*!< UART RX receiver overrun. */ + kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_UART, 10), /*!< UART noise error. */ + kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_UART, 11), /*!< UART framing error. */ + kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_UART, 12), /*!< UART parity error. */ + kStatus_UART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_UART, 13), /*!< Baudrate is not support in current clock source */ +}; + +/*! @brief UART parity mode. */ +typedef enum _uart_parity_mode +{ + kUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} uart_parity_mode_t; + +/*! @brief UART stop bit count. */ +typedef enum _uart_stop_bit_count +{ + kUART_OneStopBit = 0U, /*!< One stop bit */ + kUART_TwoStopBit = 1U, /*!< Two stop bits */ +} uart_stop_bit_count_t; + +/*! + * @brief UART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the UART interrupt configurations. + */ +enum _uart_interrupt_enable +{ +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + kUART_LinBreakInterruptEnable = (UART_BDH_LBKDIE_MASK), /*!< LIN break detect interrupt. */ +#endif + kUART_RxActiveEdgeInterruptEnable = (UART_BDH_RXEDGIE_MASK), /*!< RX active edge interrupt. */ + kUART_TxDataRegEmptyInterruptEnable = (UART_C2_TIE_MASK << 8), /*!< Transmit data register empty interrupt. */ + kUART_TransmissionCompleteInterruptEnable = (UART_C2_TCIE_MASK << 8), /*!< Transmission complete interrupt. */ + kUART_RxDataRegFullInterruptEnable = (UART_C2_RIE_MASK << 8), /*!< Receiver data register full interrupt. */ + kUART_IdleLineInterruptEnable = (UART_C2_ILIE_MASK << 8), /*!< Idle line interrupt. */ + kUART_RxOverrunInterruptEnable = (UART_C3_ORIE_MASK << 16), /*!< Receiver overrun interrupt. */ + kUART_NoiseErrorInterruptEnable = (UART_C3_NEIE_MASK << 16), /*!< Noise error flag interrupt. */ + kUART_FramingErrorInterruptEnable = (UART_C3_FEIE_MASK << 16), /*!< Framing error flag interrupt. */ + kUART_ParityErrorInterruptEnable = (UART_C3_PEIE_MASK << 16), /*!< Parity error flag interrupt. */ +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + kUART_RxFifoOverflowInterruptEnable = (UART_CFIFO_RXOFE_MASK << 24), /*!< RX FIFO overflow interrupt. */ + kUART_TxFifoOverflowInterruptEnable = (UART_CFIFO_TXOFE_MASK << 24), /*!< TX FIFO overflow interrupt. */ + kUART_RxFifoUnderflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */ +#endif + kUART_AllInterruptsEnable = +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + kUART_LinBreakInterruptEnable | +#endif + kUART_RxActiveEdgeInterruptEnable | kUART_TxDataRegEmptyInterruptEnable | + kUART_TransmissionCompleteInterruptEnable | kUART_RxDataRegFullInterruptEnable | kUART_IdleLineInterruptEnable | + kUART_RxOverrunInterruptEnable | kUART_NoiseErrorInterruptEnable | kUART_FramingErrorInterruptEnable | + kUART_ParityErrorInterruptEnable +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + | + kUART_RxFifoOverflowInterruptEnable | kUART_TxFifoOverflowInterruptEnable | kUART_RxFifoUnderflowInterruptEnable +#endif + , +}; + +/*! + * @brief UART status flags. + * + * This provides constants for the UART status flags for use in the UART functions. + */ +enum _uart_flags +{ + kUART_TxDataRegEmptyFlag = (UART_S1_TDRE_MASK), /*!< TX data register empty flag. */ + kUART_TransmissionCompleteFlag = (UART_S1_TC_MASK), /*!< Transmission complete flag. */ + kUART_RxDataRegFullFlag = (UART_S1_RDRF_MASK), /*!< RX data register full flag. */ + kUART_IdleLineFlag = (UART_S1_IDLE_MASK), /*!< Idle line detect flag. */ + kUART_RxOverrunFlag = (UART_S1_OR_MASK), /*!< RX overrun flag. */ + kUART_NoiseErrorFlag = (UART_S1_NF_MASK), /*!< RX takes 3 samples of each received bit. + If any of these samples differ, noise flag sets */ + kUART_FramingErrorFlag = (UART_S1_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected + where stop bit expected */ + kUART_ParityErrorFlag = (UART_S1_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ +#if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + kUART_LinBreakFlag = + (UART_S2_LBKDIF_MASK + << 8), /*!< LIN break detect interrupt flag, sets when + LIN break char detected and LIN circuit enabled */ +#endif + kUART_RxActiveEdgeFlag = + (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag, + sets when active edge detected */ + kUART_RxActiveFlag = + (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF), + sets at beginning of valid start bit */ +#if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS + kUART_NoiseErrorInRxDataRegFlag = (UART_ED_NOISY_MASK << 16), /*!< Noisy bit, sets if noise detected. */ + kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Paritye bit, sets if parity error detected. */ +#endif +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + kUART_TxFifoEmptyFlag = (UART_SFIFO_TXEMPT_MASK << 24), /*!< TXEMPT bit, sets if TX buffer is empty */ + kUART_RxFifoEmptyFlag = (UART_SFIFO_RXEMPT_MASK << 24), /*!< RXEMPT bit, sets if RX buffer is empty */ + kUART_TxFifoOverflowFlag = (UART_SFIFO_TXOF_MASK << 24), /*!< TXOF bit, sets if TX buffer overflow occurred */ + kUART_RxFifoOverflowFlag = (UART_SFIFO_RXOF_MASK << 24), /*!< RXOF bit, sets if receive buffer overflow */ + kUART_RxFifoUnderflowFlag = (UART_SFIFO_RXUF_MASK << 24), /*!< RXUF bit, sets if receive buffer underflow */ +#endif +}; + +/*! @brief UART configuration structure. */ +typedef struct _uart_config +{ + uint32_t baudRate_Bps; /*!< UART baud rate */ + uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} uart_config_t; + +/*! @brief UART transfer structure. */ +typedef struct _uart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} uart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _uart_handle uart_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData); + +/*! @brief UART handle structure. */ +struct _uart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + uart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a UART instance with a user configuration structure and peripheral clock. + * + * This function configures the UART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the UART_GetDefaultConfig() function. + * The example below shows how to use this API to configure UART. + * @code + * uart_config_t uartConfig; + * uartConfig.baudRate_Bps = 115200U; + * uartConfig.parityMode = kUART_ParityDisabled; + * uartConfig.stopBitCount = kUART_OneStopBit; + * uartConfig.txFifoWatermark = 0; + * uartConfig.rxFifoWatermark = 1; + * UART_Init(UART1, &uartConfig, 20000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param config Pointer to the user-defined configuration structure. + * @param srcClock_Hz UART clock source frequency in HZ. + * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Status UART initialize succeed + */ +status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a UART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the UART clock. + * + * @param base UART peripheral base address. + */ +void UART_Deinit(UART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the UART configuration structure to a default value. The default + * values are as follows. + * uartConfig->baudRate_Bps = 115200U; + * uartConfig->bitCountPerChar = kUART_8BitsPerChar; + * uartConfig->parityMode = kUART_ParityDisabled; + * uartConfig->stopBitCount = kUART_OneStopBit; + * uartConfig->txFifoWatermark = 0; + * uartConfig->rxFifoWatermark = 1; + * uartConfig->enableTx = false; + * uartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void UART_GetDefaultConfig(uart_config_t *config); + +/*! + * @brief Sets the UART instance baud rate. + * + * This function configures the UART module baud rate. This function is used to update + * the UART module baud rate after the UART module is initialized by the UART_Init. + * @code + * UART_SetBaudRate(UART1, 115200U, 20000000U); + * @endcode + * + * @param base UART peripheral base address. + * @param baudRate_Bps UART baudrate to be set. + * @param srcClock_Hz UART clock source freqency in Hz. + * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets UART status flags. + * + * This function gets all UART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _uart_flags. To check a specific status, + * compare the return value with enumerators in @ref _uart_flags. + * For example, to check whether the TX is empty, do the following. + * @code + * if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1)) + * { + * ... + * } + * @endcode + * + * @param base UART peripheral base address. + * @return UART status flags which are ORed by the enumerators in the _uart_flags. + */ +uint32_t UART_GetStatusFlags(UART_Type *base); + +/*! + * @brief Clears status flags with the provided mask. + * + * This function clears UART status flags with a provided mask. An automatically cleared flag + * can't be cleared by this function. + * These flags can only be cleared or set by hardware. + * kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, + * kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag, + * kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag + * Note that this API should be called when the Tx/Rx is idle. Otherwise it has no effect. + * + * @param base UART peripheral base address. + * @param mask The status flags to be cleared; it is logical OR value of @ref _uart_flags. + * @retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask is cleared. + */ +status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables UART interrupts according to the provided mask. + * + * This function enables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt, do the following. + * @code + * UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_EnableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Disables the UART interrupts according to the provided mask. + * + * This function disables the UART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. + * For example, to disable TX empty interrupt and RX full interrupt do the following. + * @code + * UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base UART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _uart_interrupt_enable. + */ +void UART_DisableInterrupts(UART_Type *base, uint32_t mask); + +/*! + * @brief Gets the enabled UART interrupts. + * + * This function gets the enabled UART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check + * a specific interrupts enable status, compare the return value with enumerators + * in @ref _uart_interrupt_enable. + * For example, to check whether TX empty interrupt is enabled, do the following. + * @code + * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1); + * + * if (kUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base UART peripheral base address. + * @return UART interrupt flags which are logical OR of the enumerators in @ref _uart_interrupt_enable. + */ +uint32_t UART_GetEnabledInterrupts(UART_Type *base); + +/* @} */ + +#if defined(FSL_FEATURE_UART_HAS_DMA_SELECT) && FSL_FEATURE_UART_HAS_DMA_SELECT +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Gets the UART data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base UART peripheral base address. + * @return UART data register addresses which are used both by the transmitter and the receiver. + */ +static inline uint32_t UART_GetDataRegisterAddress(UART_Type *base) +{ + return (uint32_t) & (base->D); +} + +/*! + * @brief Enables or disables the UART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, S1[TDRE], to generate the DMA requests. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTxDMA(UART_Type *base, bool enable) +{ + if (enable) + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 |= UART_C4_TDMAS_MASK; +#else + base->C5 |= UART_C5_TDMAS_MASK; +#endif + base->C2 |= UART_C2_TIE_MASK; + } + else + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 &= ~UART_C4_TDMAS_MASK; +#else + base->C5 &= ~UART_C5_TDMAS_MASK; +#endif + base->C2 &= ~UART_C2_TIE_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver DMA. + * + * This function enables or disables the receiver data register full flag, S1[RDRF], to generate DMA requests. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRxDMA(UART_Type *base, bool enable) +{ + if (enable) + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 |= UART_C4_RDMAS_MASK; +#else + base->C5 |= UART_C5_RDMAS_MASK; +#endif + base->C2 |= UART_C2_RIE_MASK; + } + else + { +#if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) + base->C4 &= ~UART_C4_RDMAS_MASK; +#else + base->C5 &= ~UART_C5_RDMAS_MASK; +#endif + base->C2 &= ~UART_C2_RIE_MASK; + } +} + +/* @} */ +#endif /* FSL_FEATURE_UART_HAS_DMA_SELECT */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the UART transmitter. + * + * This function enables or disables the UART transmitter. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableTx(UART_Type *base, bool enable) +{ + if (enable) + { + base->C2 |= UART_C2_TE_MASK; + } + else + { + base->C2 &= ~UART_C2_TE_MASK; + } +} + +/*! + * @brief Enables or disables the UART receiver. + * + * This function enables or disables the UART receiver. + * + * @param base UART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void UART_EnableRx(UART_Type *base, bool enable) +{ + if (enable) + { + base->C2 |= UART_C2_RE_MASK; + } + else + { + base->C2 &= ~UART_C2_RE_MASK; + } +} + +/*! + * @brief Writes to the TX register. + * + * This function writes data to the TX register directly. The upper layer must ensure + * that the TX register is empty or TX FIFO has empty room before calling this function. + * + * @param base UART peripheral base address. + * @param data The byte to write. + */ +static inline void UART_WriteByte(UART_Type *base, uint8_t data) +{ + base->D = data; +} + +/*! + * @brief Reads the RX register directly. + * + * This function reads data from the RX register directly. The upper layer must + * ensure that the RX register is full or that the TX FIFO has data before calling this function. + * + * @param base UART peripheral base address. + * @return The byte read from UART data register. + */ +static inline uint8_t UART_ReadByte(UART_Type *base) +{ + return base->D; +} + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @note This function does not check whether all data is sent out to the bus. + * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is + * finished. + * + * @param base UART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data, and reads data from the TX register. + * + * @param base UART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data. + * @retval kStatus_UART_NoiseError A noise error occurred while receiving data. + * @retval kStatus_UART_FramingError A framing error occurred while receiving data. + * @retval kStatus_UART_ParityError A parity error occurred while receiving data. + * @retval kStatus_Success Successfully received all data. + */ +status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle. + * + * This function initializes the UART handle which can be used for other UART + * transactional APIs. Usually, for a specified UART instance, + * call this API once to get the initialized handle. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void UART_TransferCreateHandle(UART_Type *base, + uart_handle_t *handle, + uart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize Size of the ring buffer. + */ +void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * + * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX, + * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure. See #uart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument The parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the UART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART transfer structure, see #uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_UART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_TransferReceiveNonBlocking(UART_Type *base, + uart_handle_t *handle, + uart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); + +/*! + * @brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle); + +/*! + * @brief UART Error IRQ handle function. + * + * This function handles the UART error IRQ request. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + */ +void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_uart_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_uart_edma.c new file mode 100644 index 00000000000..c51e4934639 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_uart_edma.c @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_uart_edma.h" +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Array of UART handle. */ +#if (defined(UART5)) +#define UART_HANDLE_ARRAY_SIZE 6 +#else /* UART5 */ +#if (defined(UART4)) +#define UART_HANDLE_ARRAY_SIZE 5 +#else /* UART4 */ +#if (defined(UART3)) +#define UART_HANDLE_ARRAY_SIZE 4 +#else /* UART3 */ +#if (defined(UART2)) +#define UART_HANDLE_ARRAY_SIZE 3 +#else /* UART2 */ +#if (defined(UART1)) +#define UART_HANDLE_ARRAY_SIZE 2 +#else /* UART1 */ +#if (defined(UART0)) +#define UART_HANDLE_ARRAY_SIZE 1 +#else /* UART0 */ +#error No UART instance. +#endif /* UART 0 */ +#endif /* UART 1 */ +#endif /* UART 2 */ +#endif /* UART 3 */ +#endif /* UART 4 */ +#endif /* UART 5 */ + +/*base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_TxIdle, + uartPrivateHandle->handle->userData); + } + } +} + +static void UART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + assert(param); + + uart_edma_private_handle_t *uartPrivateHandle = (uart_edma_private_handle_t *)param; + + /* Avoid warning for unused parameters. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Disable transfer. */ + UART_TransferAbortReceiveEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, kStatus_UART_RxIdle, + uartPrivateHandle->handle->userData); + } + } +} + +void UART_TransferCreateHandleEDMA(UART_Type *base, + uart_edma_handle_t *handle, + uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(handle); + + uint32_t instance = UART_GetInstance(base); + + s_edmaPrivateHandle[instance].base = base; + s_edmaPrivateHandle[instance].handle = handle; + + memset(handle, 0, sizeof(*handle)); + + handle->rxState = kUART_RxIdle; + handle->txState = kUART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO + /* Note: + Take care of the RX FIFO, EDMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + EDMA transfer because the water mark is 2. + */ + if (rxEdmaHandle) + { + base->RWFIFO = 1U; + } +#endif + + /* Configure TX. */ + if (txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, UART_SendEDMACallback, &s_edmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, UART_ReceiveEDMACallback, &s_edmaPrivateHandle[instance]); + } +} + +status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer) +{ + assert(handle); + assert(handle->txEdmaHandle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous TX not finished. */ + if (kUART_TxBusy == handle->txState) + { + status = kStatus_UART_TxBusy; + } + else + { + handle->txState = kUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), (void *)UART_GetDataRegisterAddress(base), + sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the UART handle */ + handle->nbytes = sizeof(uint8_t); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable UART TX EDMA. */ + UART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer) +{ + assert(handle); + assert(handle->rxEdmaHandle); + assert(xfer); + assert(xfer->data); + assert(xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous RX not finished. */ + if (kUART_RxBusy == handle->rxState) + { + status = kStatus_UART_RxBusy; + } + else + { + handle->rxState = kUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)UART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data, + sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the UART handle */ + handle->nbytes = sizeof(uint8_t); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable UART RX EDMA. */ + UART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle) +{ + assert(handle); + assert(handle->txEdmaHandle); + + /* Disable UART TX EDMA. */ + UART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->txEdmaHandle); + + handle->txState = kUART_TxIdle; +} + +void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle) +{ + assert(handle); + assert(handle->rxEdmaHandle); + + /* Disable UART RX EDMA. */ + UART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxEdmaHandle); + + handle->rxState = kUART_RxIdle; +} + +status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(handle->rxEdmaHandle); + assert(count); + + if (kUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); + + return kStatus_Success; +} + +status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count) +{ + assert(handle); + assert(handle->txEdmaHandle); + assert(count); + + if (kUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); + + return kStatus_Success; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_uart_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_uart_edma.h new file mode 100644 index 00000000000..e411ffd7a44 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_uart_edma.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_UART_EDMA_H_ +#define _FSL_UART_EDMA_H_ + +#include "fsl_uart.h" +#include "fsl_dmamux.h" +#include "fsl_edma.h" + +/*! + * @addtogroup uart_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Forward declaration of the handle typedef. */ +typedef struct _uart_edma_handle uart_edma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*uart_edma_transfer_callback_t)(UART_Type *base, + uart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! +* @brief UART eDMA handle +*/ +struct _uart_edma_handle +{ + uart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle which is used in transactional functions. + * @param base UART peripheral base address. + * @param handle Pointer to the uart_edma_handle_t structure. + * @param callback UART callback, NULL means no callback. + * @param userData User callback function data. + * @param rxEdmaHandle User-requested DMA handle for RX DMA transfer. + * @param txEdmaHandle User-requested DMA handle for TX DMA transfer. + */ +void UART_TransferCreateHandleEDMA(UART_Type *base, + uart_edma_handle_t *handle, + uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param xfer UART eDMA transfer structure. See #uart_transfer_t. + * @retval kStatus_Success if succeeded; otherwise failed. + * @retval kStatus_UART_TxBusy Previous transfer ongoing. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_SendEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base UART peripheral base address. + * @param handle Pointer to the uart_edma_handle_t structure. + * @param xfer UART eDMA transfer structure. See #uart_transfer_t. + * @retval kStatus_Success if succeeded; otherwise failed. + * @retval kStatus_UART_RxBusy Previous transfer ongoing. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t UART_ReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle, uart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using eDMA. + * + * This function aborts sent data using eDMA. + * + * @param base UART peripheral base address. + * @param handle Pointer to the uart_edma_handle_t structure. + */ +void UART_TransferAbortSendEDMA(UART_Type *base, uart_edma_handle_t *handle); + +/*! + * @brief Aborts the receive data using eDMA. + * + * This function aborts receive data using eDMA. + * + * @param base UART peripheral base address. + * @param handle Pointer to the uart_edma_handle_t structure. + */ +void UART_TransferAbortReceiveEDMA(UART_Type *base, uart_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been written to UART TX register. + * + * This function gets the number of bytes that have been written to UART TX + * register by DMA. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetSendCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * @param base UART peripheral base address. + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t UART_TransferGetReceiveCountEDMA(UART_Type *base, uart_edma_handle_t *handle, uint32_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_EDMA_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_vref.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_vref.c new file mode 100644 index 00000000000..24f2d1dc280 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_vref.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_vref.h" + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base VREF peripheral base address + * + * @return The VREF instance + */ +static uint32_t VREF_GetInstance(VREF_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to VREF bases for each instance. */ +static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to VREF clocks for each instance. */ +static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t VREF_GetInstance(VREF_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_vrefBases); instance++) + { + if (s_vrefBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_vrefBases)); + + return instance; +} + +void VREF_Init(VREF_Type *base, const vref_config_t *config) +{ + assert(config != NULL); + + uint8_t reg = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate clock for VREF */ + CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* Configure VREF to a known state */ +#if defined(FSL_FEATURE_VREF_HAS_CHOP_OSC) && FSL_FEATURE_VREF_HAS_CHOP_OSC + /* Set chop oscillator bit */ + base->TRM |= VREF_TRM_CHOPEN_MASK; +#endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */ + /* Get current SC register */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + reg = base->VREFH_SC; +#else + reg = base->SC; +#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + /* Clear old buffer mode selection bits */ + reg &= ~VREF_SC_MODE_LV_MASK; + /* Set buffer Mode selection and Regulator enable bit */ + reg |= VREF_SC_MODE_LV(config->bufferMode) | VREF_SC_REGEN(1U); +#if defined(FSL_FEATURE_VREF_HAS_COMPENSATION) && FSL_FEATURE_VREF_HAS_COMPENSATION + /* Set second order curvature compensation enable bit */ + reg |= VREF_SC_ICOMPEN(1U); +#endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */ + /* Enable VREF module */ + reg |= VREF_SC_VREFEN(1U); + /* Update bit-field from value to Status and Control register */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + base->VREFH_SC = reg; +#else + base->SC = reg; +#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + reg = base->VREFL_TRM; + /* Clear old select external voltage reference and VREFL (0.4 V) reference buffer enable bits */ + reg &= ~(VREF_VREFL_TRM_VREFL_EN_MASK | VREF_VREFL_TRM_VREFL_SEL_MASK); + /* Select external voltage reference and set VREFL (0.4 V) reference buffer enable */ + reg |= VREF_VREFL_TRM_VREFL_SEL(config->enableExternalVoltRef) | VREF_VREFL_TRM_VREFL_EN(config->enableLowRef); + base->VREFL_TRM = reg; +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + +#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4 + reg = base->TRM4; + /* Clear old select internal voltage reference bit (2.1V) */ + reg &= ~VREF_TRM4_VREF2V1_EN_MASK; + /* Select internal voltage reference (2.1V) */ + reg |= VREF_TRM4_VREF2V1_EN(config->enable2V1VoltRef); + base->TRM4 = reg; +#endif /* FSL_FEATURE_VREF_HAS_TRM4 */ + + /* Wait until internal voltage stable */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0) +#else + while ((base->SC & VREF_SC_VREFST_MASK) == 0) +#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + { + } +} + +void VREF_Deinit(VREF_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock for VREF */ + CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void VREF_GetDefaultConfig(vref_config_t *config) +{ + assert(config); + +/* Set High power buffer mode in */ +#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE + config->bufferMode = kVREF_ModeHighPowerBuffer; +#else + config->bufferMode = kVREF_ModeTightRegulationBuffer; +#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */ + +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + /* Select internal voltage reference */ + config->enableExternalVoltRef = false; + /* Set VREFL (0.4 V) reference buffer disable */ + config->enableLowRef = false; +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + +#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4 + /* Disable internal voltage reference (2.1V) */ + config->enable2V1VoltRef = false; +#endif /* FSL_FEATURE_VREF_HAS_TRM4 */ +} + +void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue) +{ + uint8_t reg = 0U; + + /* Set TRIM bits value in voltage reference */ + reg = base->TRM; + reg = ((reg & ~VREF_TRM_TRIM_MASK) | VREF_TRM_TRIM(trimValue)); + base->TRM = reg; + /* Wait until internal voltage stable */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0) +#else + while ((base->SC & VREF_SC_VREFST_MASK) == 0) +#endif/* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + { + } +} + +#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4 +void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue) +{ + uint8_t reg = 0U; + + /* Set TRIM bits value in voltage reference (2V1) */ + reg = base->TRM4; + reg = ((reg & ~VREF_TRM4_TRIM2V1_MASK) | VREF_TRM4_TRIM2V1(trimValue)); + base->TRM4 = reg; + /* Wait until internal voltage stable */ + while ((base->SC & VREF_SC_VREFST_MASK) == 0) + { + } +} +#endif /* FSL_FEATURE_VREF_HAS_TRM4 */ + +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE +void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue) +{ + /* The values 111b and 110b are NOT valid/allowed */ + assert((trimValue != 0x7U) && (trimValue != 0x6U)); + + uint8_t reg = 0U; + + /* Set TRIM bits value in low voltage reference */ + reg = base->VREFL_TRM; + reg = ((reg & ~VREF_VREFL_TRM_VREFL_TRIM_MASK) | VREF_VREFL_TRM_VREFL_TRIM(trimValue)); + base->VREFL_TRM = reg; + /* Wait until internal voltage stable */ + + while ((base->VREFH_SC & VREF_SC_VREFST_MASK) == 0) + { + } +} +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_vref.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_vref.h new file mode 100644 index 00000000000..6c6c014b913 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_vref.h @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_VREF_H_ +#define _FSL_VREF_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup vref + * @{ + */ + + +/****************************************************************************** + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ +/*@}*/ + +/* Those macros below defined to support SoC family which have VREFL (0.4V) reference */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE +#define VREF_SC_MODE_LV VREF_VREFH_SC_MODE_LV +#define VREF_SC_REGEN VREF_VREFH_SC_REGEN +#define VREF_SC_VREFEN VREF_VREFH_SC_VREFEN +#define VREF_SC_ICOMPEN VREF_VREFH_SC_ICOMPEN +#define VREF_SC_REGEN_MASK VREF_VREFH_SC_REGEN_MASK +#define VREF_SC_VREFST_MASK VREF_VREFH_SC_VREFST_MASK +#define VREF_SC_VREFEN_MASK VREF_VREFH_SC_VREFEN_MASK +#define VREF_SC_MODE_LV_MASK VREF_VREFH_SC_MODE_LV_MASK +#define VREF_SC_ICOMPEN_MASK VREF_VREFH_SC_ICOMPEN_MASK +#define TRM VREFH_TRM +#define VREF_TRM_TRIM VREF_VREFH_TRM_TRIM +#define VREF_TRM_CHOPEN_MASK VREF_VREFH_TRM_CHOPEN_MASK +#define VREF_TRM_TRIM_MASK VREF_VREFH_TRM_TRIM_MASK +#define VREF_TRM_CHOPEN_SHIFT VREF_VREFH_TRM_CHOPEN_SHIFT +#define VREF_TRM_TRIM_SHIFT VREF_VREFH_TRM_TRIM_SHIFT +#define VREF_SC_MODE_LV_SHIFT VREF_VREFH_SC_MODE_LV_SHIFT +#define VREF_SC_REGEN_SHIFT VREF_VREFH_SC_REGEN_SHIFT +#define VREF_SC_VREFST_SHIFT VREF_VREFH_SC_VREFST_SHIFT +#define VREF_SC_ICOMPEN_SHIFT VREF_VREFH_SC_ICOMPEN_SHIFT +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + +/*! + * @brief VREF modes. + */ +typedef enum _vref_buffer_mode +{ + kVREF_ModeBandgapOnly = 0U, /*!< Bandgap on only, for stabilization and startup */ +#if defined(FSL_FEATURE_VREF_MODE_LV_TYPE) && FSL_FEATURE_VREF_MODE_LV_TYPE + kVREF_ModeHighPowerBuffer = 1U, /*!< High-power buffer mode enabled */ + kVREF_ModeLowPowerBuffer = 2U /*!< Low-power buffer mode enabled */ +#else + kVREF_ModeTightRegulationBuffer = 2U /*!< Tight regulation buffer enabled */ +#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */ +} vref_buffer_mode_t; + +/*! + * @brief The description structure for the VREF module. + */ +typedef struct _vref_config +{ + vref_buffer_mode_t bufferMode; /*!< Buffer mode selection */ +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + bool enableLowRef; /*!< Set VREFL (0.4 V) reference buffer enable or disable */ + bool enableExternalVoltRef; /*!< Select external voltage reference or not (internal) */ +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ +#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4 + bool enable2V1VoltRef; /*!< Enable Internal Voltage Reference (2.1V) */ +#endif /* FSL_FEATURE_VREF_HAS_TRM4 */ +} vref_config_t; + +/****************************************************************************** + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name VREF functional operation + * @{ + */ + +/*! + * @brief Enables the clock gate and configures the VREF module according to the configuration structure. + * + * This function must be called before calling all other VREF driver functions, + * read/write registers, and configurations with user-defined settings. + * The example below shows how to set up vref_config_t parameters and + * how to call the VREF_Init function by passing in these parameters. + * This is an example. + * @code + * vref_config_t vrefConfig; + * vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer; + * vrefConfig.enableExternalVoltRef = false; + * vrefConfig.enableLowRef = false; + * VREF_Init(VREF, &vrefConfig); + * @endcode + * + * @param base VREF peripheral address. + * @param config Pointer to the configuration structure. + */ +void VREF_Init(VREF_Type *base, const vref_config_t *config); + +/*! + * @brief Stops and disables the clock for the VREF module. + * + * This function should be called to shut down the module. + * This is an example. + * @code + * vref_config_t vrefUserConfig; + * VREF_Init(VREF); + * VREF_GetDefaultConfig(&vrefUserConfig); + * ... + * VREF_Deinit(VREF); + * @endcode + * + * @param base VREF peripheral address. + */ +void VREF_Deinit(VREF_Type *base); + +/*! + * @brief Initializes the VREF configuration structure. + * + * This function initializes the VREF configuration structure to default values. + * This is an example. + * @code + * vrefConfig->bufferMode = kVREF_ModeHighPowerBuffer; + * vrefConfig->enableExternalVoltRef = false; + * vrefConfig->enableLowRef = false; + * @endcode + * + * @param config Pointer to the initialization structure. + */ +void VREF_GetDefaultConfig(vref_config_t *config); + +/*! + * @brief Sets a TRIM value for the reference voltage. + * + * This function sets a TRIM value for the reference voltage. + * Note that the TRIM value maximum is 0x3F. + * + * @param base VREF peripheral address. + * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). + */ +void VREF_SetTrimVal(VREF_Type *base, uint8_t trimValue); + +/*! + * @brief Reads the value of the TRIM meaning output voltage. + * + * This function gets the TRIM value from the TRM register. + * + * @param base VREF peripheral address. + * @return Six-bit value of trim setting. + */ +static inline uint8_t VREF_GetTrimVal(VREF_Type *base) +{ + return (base->TRM & VREF_TRM_TRIM_MASK); +} + +#if defined(FSL_FEATURE_VREF_HAS_TRM4) && FSL_FEATURE_VREF_HAS_TRM4 +/*! + * @brief Sets a TRIM value for the reference voltage (2V1). + * + * This function sets a TRIM value for the reference voltage (2V1). + * Note that the TRIM value maximum is 0x3F. + * + * @param base VREF peripheral address. + * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). + */ +void VREF_SetTrim2V1Val(VREF_Type *base, uint8_t trimValue); + +/*! + * @brief Reads the value of the TRIM meaning output voltage (2V1). + * + * This function gets the TRIM value from the VREF_TRM4 register. + * + * @param base VREF peripheral address. + * @return Six-bit value of trim setting. + */ +static inline uint8_t VREF_GetTrim2V1Val(VREF_Type *base) +{ + return (base->TRM4 & VREF_TRM4_TRIM2V1_MASK); +} +#endif /* FSL_FEATURE_VREF_HAS_TRM4 */ + +#if defined(FSL_FEATURE_VREF_HAS_LOW_REFERENCE) && FSL_FEATURE_VREF_HAS_LOW_REFERENCE + +/*! + * @brief Sets the TRIM value for the low voltage reference. + * + * This function sets the TRIM value for low reference voltage. + * Note the following. + * - The TRIM value maximum is 0x05U + * - The values 111b and 110b are not valid/allowed. + * + * @param base VREF peripheral address. + * @param trimValue Value of the trim register to set output low reference voltage (maximum 0x05U (3-bit)). + */ +void VREF_SetLowReferenceTrimVal(VREF_Type *base, uint8_t trimValue); + +/*! + * @brief Reads the value of the TRIM meaning output voltage. + * + * This function gets the TRIM value from the VREFL_TRM register. + * + * @param base VREF peripheral address. + * @return Three-bit value of the trim setting. + */ +static inline uint8_t VREF_GetLowReferenceTrimVal(VREF_Type *base) +{ + return (base->VREFL_TRM & VREF_VREFL_TRM_VREFL_TRIM_MASK); +} +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_VREF_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_wdog.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_wdog.c new file mode 100644 index 00000000000..781ac133c1a --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_wdog.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_wdog.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +void WDOG_GetDefaultConfig(wdog_config_t *config) +{ + assert(config); + + config->enableWdog = true; + config->clockSource = kWDOG_LpoClockSource; + config->prescaler = kWDOG_ClockPrescalerDivide1; +#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN + config->workMode.enableWait = true; +#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */ + config->workMode.enableStop = false; + config->workMode.enableDebug = false; + config->enableUpdate = true; + config->enableInterrupt = false; + config->enableWindowMode = false; + config->windowValue = 0U; + config->timeoutValue = 0xFFFFU; +} + +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + uint32_t primaskValue = 0U; + + value = WDOG_STCTRLH_WDOGEN(config->enableWdog) | WDOG_STCTRLH_CLKSRC(config->clockSource) | + WDOG_STCTRLH_IRQRSTEN(config->enableInterrupt) | WDOG_STCTRLH_WINEN(config->enableWindowMode) | + WDOG_STCTRLH_ALLOWUPDATE(config->enableUpdate) | WDOG_STCTRLH_DBGEN(config->workMode.enableDebug) | + WDOG_STCTRLH_STOPEN(config->workMode.enableStop) | +#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN + WDOG_STCTRLH_WAITEN(config->workMode.enableWait) | +#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */ + WDOG_STCTRLH_DISTESTWDOG(1U); + + /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence + * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ + primaskValue = DisableGlobalIRQ(); + WDOG_Unlock(base); + /* Wait one bus clock cycle */ + base->RSTCNT = 0U; + /* Set configruation */ + base->PRESC = WDOG_PRESC_PRESCVAL(config->prescaler); + base->WINH = (uint16_t)((config->windowValue >> 16U) & 0xFFFFU); + base->WINL = (uint16_t)((config->windowValue) & 0xFFFFU); + base->TOVALH = (uint16_t)((config->timeoutValue >> 16U) & 0xFFFFU); + base->TOVALL = (uint16_t)((config->timeoutValue) & 0xFFFFU); + base->STCTRLH = value; + EnableGlobalIRQ(primaskValue); +} + +void WDOG_Deinit(WDOG_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupts */ + primaskValue = DisableGlobalIRQ(); + WDOG_Unlock(base); + /* Wait one bus clock cycle */ + base->RSTCNT = 0U; + WDOG_Disable(base); + EnableGlobalIRQ(primaskValue); + WDOG_ClearResetCount(base); +} + +void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + uint32_t primaskValue = 0U; + + value = WDOG_STCTRLH_DISTESTWDOG(0U) | WDOG_STCTRLH_TESTWDOG(1U) | WDOG_STCTRLH_TESTSEL(config->testMode) | + WDOG_STCTRLH_BYTESEL(config->testedByte) | WDOG_STCTRLH_IRQRSTEN(0U) | WDOG_STCTRLH_WDOGEN(1U) | + WDOG_STCTRLH_ALLOWUPDATE(1U); + + /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence + * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ + primaskValue = DisableGlobalIRQ(); + WDOG_Unlock(base); + /* Wait one bus clock cycle */ + base->RSTCNT = 0U; + /* Set configruation */ + base->TOVALH = (uint16_t)((config->timeoutValue >> 16U) & 0xFFFFU); + base->TOVALL = (uint16_t)((config->timeoutValue) & 0xFFFFU); + base->STCTRLH = value; + EnableGlobalIRQ(primaskValue); +} + +uint32_t WDOG_GetStatusFlags(WDOG_Type *base) +{ + uint32_t status_flag = 0U; + + status_flag |= (base->STCTRLH & WDOG_STCTRLH_WDOGEN_MASK); + status_flag |= (base->STCTRLL & WDOG_STCTRLL_INTFLG_MASK); + + return status_flag; +} + +void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask) +{ + if (mask & kWDOG_TimeoutFlag) + { + base->STCTRLL |= WDOG_STCTRLL_INTFLG_MASK; + } +} + +void WDOG_Refresh(WDOG_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->REFRESH = WDOG_FIRST_WORD_OF_REFRESH; + base->REFRESH = WDOG_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_wdog.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_wdog.h new file mode 100644 index 00000000000..580adb95a0f --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_wdog.h @@ -0,0 +1,433 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_WDOG_H_ +#define _FSL_WDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wdog + * @{ + */ + + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WDOG driver version 2.0.0. */ +#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @name Unlock sequence */ +/*@{*/ +#define WDOG_FIRST_WORD_OF_UNLOCK (0xC520U) /*!< First word of unlock sequence */ +#define WDOG_SECOND_WORD_OF_UNLOCK (0xD928U) /*!< Second word of unlock sequence */ +/*@}*/ + +/*! @name Refresh sequence */ +/*@{*/ +#define WDOG_FIRST_WORD_OF_REFRESH (0xA602U) /*!< First word of refresh sequence */ +#define WDOG_SECOND_WORD_OF_REFRESH (0xB480U) /*!< Second word of refresh sequence */ +/*@}*/ + +/*! @brief Describes WDOG clock source. */ +typedef enum _wdog_clock_source +{ + kWDOG_LpoClockSource = 0U, /*!< WDOG clock sourced from LPO*/ + kWDOG_AlternateClockSource = 1U, /*!< WDOG clock sourced from alternate clock source*/ +} wdog_clock_source_t; + +/*! @brief Defines WDOG work mode. */ +typedef struct _wdog_work_mode +{ +#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN + bool enableWait; /*!< Enables or disables WDOG in wait mode */ +#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */ + bool enableStop; /*!< Enables or disables WDOG in stop mode */ + bool enableDebug; /*!< Enables or disables WDOG in debug mode */ +} wdog_work_mode_t; + +/*! @brief Describes the selection of the clock prescaler. */ +typedef enum _wdog_clock_prescaler +{ + kWDOG_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */ + kWDOG_ClockPrescalerDivide2 = 0x1U, /*!< Divided by 2 */ + kWDOG_ClockPrescalerDivide3 = 0x2U, /*!< Divided by 3 */ + kWDOG_ClockPrescalerDivide4 = 0x3U, /*!< Divided by 4 */ + kWDOG_ClockPrescalerDivide5 = 0x4U, /*!< Divided by 5 */ + kWDOG_ClockPrescalerDivide6 = 0x5U, /*!< Divided by 6 */ + kWDOG_ClockPrescalerDivide7 = 0x6U, /*!< Divided by 7 */ + kWDOG_ClockPrescalerDivide8 = 0x7U, /*!< Divided by 8 */ +} wdog_clock_prescaler_t; + +/*! @brief Describes WDOG configuration structure. */ +typedef struct _wdog_config +{ + bool enableWdog; /*!< Enables or disables WDOG */ + wdog_clock_source_t clockSource; /*!< Clock source select */ + wdog_clock_prescaler_t prescaler; /*!< Clock prescaler value */ + wdog_work_mode_t workMode; /*!< Configures WDOG work mode in debug stop and wait mode */ + bool enableUpdate; /*!< Update write-once register enable */ + bool enableInterrupt; /*!< Enables or disables WDOG interrupt */ + bool enableWindowMode; /*!< Enables or disables WDOG window mode */ + uint32_t windowValue; /*!< Window value */ + uint32_t timeoutValue; /*!< Timeout value */ +} wdog_config_t; + +/*! @brief Describes WDOG test mode. */ +typedef enum _wdog_test_mode +{ + kWDOG_QuickTest = 0U, /*!< Selects quick test */ + kWDOG_ByteTest = 1U, /*!< Selects byte test */ +} wdog_test_mode_t; + +/*! @brief Describes WDOG tested byte selection in byte test mode. */ +typedef enum _wdog_tested_byte +{ + kWDOG_TestByte0 = 0U, /*!< Byte 0 selected in byte test mode */ + kWDOG_TestByte1 = 1U, /*!< Byte 1 selected in byte test mode */ + kWDOG_TestByte2 = 2U, /*!< Byte 2 selected in byte test mode */ + kWDOG_TestByte3 = 3U, /*!< Byte 3 selected in byte test mode */ +} wdog_tested_byte_t; + +/*! @brief Describes WDOG test mode configuration structure. */ +typedef struct _wdog_test_config +{ + wdog_test_mode_t testMode; /*!< Selects test mode */ + wdog_tested_byte_t testedByte; /*!< Selects tested byte in byte test mode */ + uint32_t timeoutValue; /*!< Timeout value */ +} wdog_test_config_t; + +/*! + * @brief WDOG interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the WDOG interrupt configurations. + */ +enum _wdog_interrupt_enable_t +{ + kWDOG_InterruptEnable = WDOG_STCTRLH_IRQRSTEN_MASK, /*!< WDOG timeout generates an interrupt before reset*/ +}; + +/*! + * @brief WDOG status flags. + * + * This structure contains the WDOG status flags for use in the WDOG functions. + */ +enum _wdog_status_flags_t +{ + kWDOG_RunningFlag = WDOG_STCTRLH_WDOGEN_MASK, /*!< Running flag, set when WDOG is enabled*/ + kWDOG_TimeoutFlag = WDOG_STCTRLL_INTFLG_MASK, /*!< Interrupt flag, set when an exception occurs*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WDOG Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes the WDOG configuration sturcture. + * + * This function initializes the WDOG configuration structure to default values. The default + * values are as follows. + * @code + * wdogConfig->enableWdog = true; + * wdogConfig->clockSource = kWDOG_LpoClockSource; + * wdogConfig->prescaler = kWDOG_ClockPrescalerDivide1; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableUpdate = true; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enableWindowMode = false; + * wdogConfig->windowValue = 0; + * wdogConfig->timeoutValue = 0xFFFFU; + * @endcode + * + * @param config Pointer to the WDOG configuration structure. + * @see wdog_config_t + */ +void WDOG_GetDefaultConfig(wdog_config_t *config); + +/*! + * @brief Initializes the WDOG. + * + * This function initializes the WDOG. When called, the WDOG runs according to the configuration. + * To reconfigure WDOG without forcing a reset first, enableUpdate must be set to true + * in the configuration. + * + * This is an example. + * @code + * wdog_config_t config; + * WDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * config.enableUpdate = true; + * WDOG_Init(wdog_base,&config); + * @endcode + * + * @param base WDOG peripheral base address + * @param config The configuration of WDOG + */ +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config); + +/*! + * @brief Shuts down the WDOG. + * + * This function shuts down the WDOG. + * Ensure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which indicates that the register update is enabled. + */ +void WDOG_Deinit(WDOG_Type *base); + +/*! + * @brief Configures the WDOG functional test. + * + * This function is used to configure the WDOG functional test. When called, the WDOG goes into test mode + * and runs according to the configuration. + * Ensure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled. + * + * This is an example. + * @code + * wdog_test_config_t test_config; + * test_config.testMode = kWDOG_QuickTest; + * test_config.timeoutValue = 0xfffffu; + * WDOG_SetTestModeConfig(wdog_base, &test_config); + * @endcode + * @param base WDOG peripheral base address + * @param config The functional test configuration of WDOG + */ +void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config); + +/* @} */ + +/*! + * @name WDOG Functional Operation + * @{ + */ + +/*! + * @brief Enables the WDOG module. + * + * This function write value into WDOG_STCTRLH register to enable the WDOG, it is a write-once register, + * make sure that the WCT window is still open and this register has not been written in this WCT + * while this function is called. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_Enable(WDOG_Type *base) +{ + base->STCTRLH |= WDOG_STCTRLH_WDOGEN_MASK; +} + +/*! + * @brief Disables the WDOG module. + * + * This function writes a value into the WDOG_STCTRLH register to disable the WDOG. It is a write-once register. + * Ensure that the WCT window is still open and that register has not been written to in this WCT + * while the function is called. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_Disable(WDOG_Type *base) +{ + base->STCTRLH &= ~WDOG_STCTRLH_WDOGEN_MASK; +} + +/*! + * @brief Enables the WDOG interrupt. + * + * This function writes a value into the WDOG_STCTRLH register to enable the WDOG interrupt. It is a write-once register. + * Ensure that the WCT window is still open and the register has not been written to in this WCT + * while the function is called. + * + * @param base WDOG peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined. + * @arg kWDOG_InterruptEnable + */ +static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint32_t mask) +{ + base->STCTRLH |= mask; +} + +/*! + * @brief Disables the WDOG interrupt. + * + * This function writes a value into the WDOG_STCTRLH register to disable the WDOG interrupt. It is a write-once register. + * Ensure that the WCT window is still open and the register has not been written to in this WCT + * while the function is called. + * + * @param base WDOG peripheral base address + * @param mask The interrupts to disable + * The parameter can be combination of the following source if defined. + * @arg kWDOG_InterruptEnable + */ +static inline void WDOG_DisableInterrupts(WDOG_Type *base, uint32_t mask) +{ + base->STCTRLH &= ~mask; +} + +/*! + * @brief Gets the WDOG all status flags. + * + * This function gets all status flags. + * + * This is an example for getting the Running Flag. + * @code + * uint32_t status; + * status = WDOG_GetStatusFlags (wdog_base) & kWDOG_RunningFlag; + * @endcode + * @param base WDOG peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags_t + * - true: a related status flag has been set. + * - false: a related status flag is not set. + */ +uint32_t WDOG_GetStatusFlags(WDOG_Type *base); + +/*! + * @brief Clears the WDOG flag. + * + * This function clears the WDOG status flag. + * + * This is an example for clearing the timeout (interrupt) flag. + * @code + * WDOG_ClearStatusFlags(wdog_base,kWDOG_TimeoutFlag); + * @endcode + * @param base WDOG peripheral base address + * @param mask The status flags to clear. + * The parameter could be any combination of the following values. + * kWDOG_TimeoutFlag + */ +void WDOG_ClearStatusFlags(WDOG_Type *base, uint32_t mask); + +/*! + * @brief Sets the WDOG timeout value. + * + * This function sets the timeout value. + * It should be ensured that the time-out value for the WDOG is always greater than + * 2xWCT time + 20 bus clock cycles. + * This function writes a value into WDOG_TOVALH and WDOG_TOVALL registers which are wirte-once. + * Ensure the WCT window is still open and the two registers have not been written to in this WCT + * while the function is called. + * + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value; count of WDOG clock tick. + */ +static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint32_t timeoutCount) +{ + base->TOVALH = (uint16_t)((timeoutCount >> 16U) & 0xFFFFU); + base->TOVALL = (uint16_t)((timeoutCount)&0xFFFFU); +} + +/*! + * @brief Sets the WDOG window value. + * + * This function sets the WDOG window value. + * This function writes a value into WDOG_WINH and WDOG_WINL registers which are wirte-once. + * Ensure the WCT window is still open and the two registers have not been written to in this WCT + * while the function is called. + * + * @param base WDOG peripheral base address + * @param windowValue WDOG window value. + */ +static inline void WDOG_SetWindowValue(WDOG_Type *base, uint32_t windowValue) +{ + base->WINH = (uint16_t)((windowValue >> 16U) & 0xFFFFU); + base->WINL = (uint16_t)((windowValue)&0xFFFFU); +} + +/*! + * @brief Unlocks the WDOG register written. + * + * This function unlocks the WDOG register written. + * Before starting the unlock sequence and following congfiguration, disable the global interrupts. + * Otherwise, an interrupt may invalidate the unlocking sequence and the WCT may expire. + * After the configuration finishes, re-enable the global interrupts. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_Unlock(WDOG_Type *base) +{ + base->UNLOCK = WDOG_FIRST_WORD_OF_UNLOCK; + base->UNLOCK = WDOG_SECOND_WORD_OF_UNLOCK; +} + +/*! + * @brief Refreshes the WDOG timer. + * + * This function feeds the WDOG. + * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WDOG peripheral base address + */ +void WDOG_Refresh(WDOG_Type *base); + +/*! + * @brief Gets the WDOG reset count. + * + * This function gets the WDOG reset count value. + * + * @param base WDOG peripheral base address + * @return WDOG reset count value. + */ +static inline uint16_t WDOG_GetResetCount(WDOG_Type *base) +{ + return base->RSTCNT; +} +/*! + * @brief Clears the WDOG reset count. + * + * This function clears the WDOG reset count value. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_ClearResetCount(WDOG_Type *base) +{ + base->RSTCNT |= UINT16_MAX; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WDOG_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/flash_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/flash_api.c new file mode 100644 index 00000000000..a7c585515ac --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/flash_api.c @@ -0,0 +1,87 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" +#include "flash_data.h" +#include "mbed_critical.h" + +// This file is automagically generated + +// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM +static uint32_t FLASH_ALGO[] = { + 0xb5104938, 0x60084449, 0xf24c4837, 0x81c15120, 0x1128f64d, 0x880181c1, 0x0101f021, 0x48348001, + 0x44484932, 0x1280f44f, 0x21006001, 0x1201e9c0, 0x52a0f04f, 0xf44f6142, 0x61824280, 0x1020f880, + 0x62411e49, 0xf939f000, 0xd0002800, 0xbd102001, 0x47702000, 0x4a27b508, 0x9200447a, 0x02cff3c1, + 0x48234601, 0x44482300, 0xf92cf000, 0xd0002800, 0xbd082001, 0x491fb508, 0x481d4479, 0x44483920, + 0xf89ff000, 0xd10f2800, 0x4478481a, 0x38324b1a, 0x9000447b, 0x22084816, 0x6181f44f, 0xf0004448, + 0x2800f959, 0x2001d000, 0x4b12bd08, 0x4601447b, 0x3b54480f, 0x5280f44f, 0xf0004448, 0xb508b8b6, + 0x1dc94613, 0x0207f021, 0x4479490a, 0x91003972, 0x48074601, 0xf0004448, 0x2800f93d, 0x2001d000, + 0x0000bd08, 0x00000004, 0x40052000, 0x40020000, 0x00000008, 0x000000a1, 0x0000037c, 0x4604b570, + 0x25006800, 0x061b7803, 0x2370d5fc, 0x20007003, 0x280ce03a, 0xe8dfd236, 0x0a06f000, 0x1a16120e, + 0x2a26221e, 0x6826322e, 0x71f37813, 0x6826e02a, 0x71b37853, 0x6826e026, 0x71737893, 0x6826e022, + 0x713378d3, 0x6826e01e, 0x72f37913, 0x6826e01a, 0x72b37953, 0x6826e016, 0x72737993, 0x6826e012, + 0x723379d3, 0x6826e00e, 0x73f37a13, 0x6826e00a, 0x73b37a53, 0x6826e006, 0x73737a93, 0x6826e002, + 0x73337ad3, 0xb2c01c40, 0xd9c24288, 0x20806821, 0xe0037008, 0x1c416a60, 0x4780d000, 0x78006820, + 0xd5f70600, 0x78006820, 0xd5010681, 0xe0062504, 0xd50106c1, 0xe0022508, 0xd00007c0, 0x46282510, + 0xb508bd70, 0x460b2244, 0x2000f88d, 0x2100466a, 0xbd084798, 0x4614b538, 0xd002070a, 0x7080f44f, + 0x6843bd38, 0xd803428b, 0x441a6882, 0xd80c428a, 0x428b68c3, 0x6902d803, 0x428a441a, 0x2002d801, + 0x1ac9bd38, 0x0100f501, 0x1ac9e000, 0xf88d2208, 0x0c0a2000, 0x2001f88d, 0xf88d0a0a, 0xf88d2002, + 0x466a1003, 0x47a02103, 0xe92dbd38, 0x460745f8, 0x46164698, 0x2000687b, 0x428b198a, 0x68bcd803, + 0x4294441c, 0x68fbd20e, 0xd803428b, 0x441c693c, 0xd2024294, 0xe8bd2002, 0x1acc85f8, 0x0400f504, + 0xe0022500, 0xf44f1acc, 0xfbb45580, 0xfb05f1f5, 0xb1114111, 0x7080f44f, 0xfbb6e7ed, 0xfb05f1f5, + 0xb1a96111, 0xe7e62001, 0xa000f88d, 0xf88d0c20, 0x0a200001, 0x0002f88d, 0x4003f88d, 0x2103466a, + 0x46434638, 0x28004798, 0x1b76d1d5, 0xe001442c, 0x0a09f04f, 0xd1e72e00, 0x4601e7cd, 0x61082000, + 0x477061c8, 0x41fce92d, 0x9d086846, 0x1402eb01, 0xd803428e, 0x44376887, 0xd80a428f, 0x428f68c7, + 0xf8d0d804, 0x4467c010, 0xd802428f, 0xe8bd2002, 0x42a681fc, 0x6887d805, 0x42a74437, 0x1b89d301, + 0x68c6e009, 0xd90342a6, 0x44376907, 0xd3ed42a7, 0xf5011b89, 0x24100100, 0xf6f4fbb1, 0x1416fb04, + 0xf44fb114, 0xe7e27080, 0xf88d2401, 0x0c0c4000, 0x4001f88d, 0xf88d0a0c, 0xf88d4002, 0x0a111003, + 0x1004f88d, 0x2005f88d, 0x3006f88d, 0x2106466a, 0xe7cc47a8, 0x43fee92d, 0x46074616, 0x2000461c, + 0xf8dd198a, 0x074b8028, 0xf44fd003, 0xe8bd7080, 0x077383fe, 0x2001d001, 0x687be7f9, 0xd803428b, + 0x441d68bd, 0xd20c4295, 0x428b68fb, 0x693dd803, 0x4295441d, 0x2002d201, 0x1acde7e9, 0x0500f505, + 0x1acde02e, 0x2007e02c, 0x0000f88d, 0xf88d0c28, 0x0a280001, 0x0002f88d, 0x5003f88d, 0xf88d78e0, + 0x78a00004, 0x0005f88d, 0xf88d7860, 0x78200006, 0x0007f88d, 0xf88d79e0, 0x79a00008, 0x0009f88d, + 0xf88d7960, 0x7920000a, 0x000bf88d, 0x210b466a, 0x46434638, 0x28004798, 0x3508d1b9, 0x34083e08, + 0xd1d02e00, 0x0000e7b3, 0xfffffffe, 0x00000000, 0xffffffff, 0xfffffffe, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000 +}; + +static const flash_algo_t flash_algo_config = { + .init = 0x1, + .uninit = 0x51, + .erase_sector = 0xab, + .program_page = 0xbf, + .static_base = 0x418, + .algo_blob = FLASH_ALGO +}; + +static const sector_info_t sectors_info[] = { + {0x0, 0x1000}, +}; + +static const flash_target_config_t flash_target_config = { + .page_size = 0x200, + .flash_start = 0x0, + .flash_size = 0x100000, + .sectors = sectors_info, + .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t) +}; + +void flash_set_target_config(flash_t *obj) +{ + obj->flash_algo = &flash_algo_config; + obj->target_config = &flash_target_config; +} diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/peripheral_clock_defines.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/peripheral_clock_defines.h new file mode 100644 index 00000000000..e78b331e346 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/peripheral_clock_defines.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_PERIPHERAL_CLOCK_H_ +#define _FSL_PERIPHERAL_CLOCK_H_ + +#include "fsl_clock.h" + +/* Array for UART module clocks */ +#define UART_CLOCK_FREQS \ + { \ + UART0_CLK_SRC, UART1_CLK_SRC, UART2_CLK_SRC, UART3_CLK_SRC, UART4_CLK_SRC, UART5_CLK_SRC \ + } + +/* Array for I2C module clocks */ +#define I2C_CLOCK_FREQS \ + { \ + I2C0_CLK_SRC, I2C1_CLK_SRC, I2C2_CLK_SRC \ + } + +/* Array for DSPI module clocks */ +#define SPI_CLOCK_FREQS \ + { \ + DSPI0_CLK_SRC, DSPI1_CLK_SRC, DSPI2_CLK_SRC \ + } + +#endif /* _FSL_PERIPHERAL_CLOCK_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/pwmout_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/pwmout_api.c new file mode 100644 index 00000000000..f7a9ba0ba9c --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/pwmout_api.c @@ -0,0 +1,153 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pwmout_api.h" + +#if DEVICE_PWMOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "fsl_ftm.h" +#include "PeripheralPins.h" + +static float pwm_clock_mhz; +/* Array of FTM peripheral base address. */ +static FTM_Type *const ftm_addrs[] = FTM_BASE_PTRS; + +void pwmout_init(pwmout_t* obj, PinName pin) +{ + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(pwm != (PWMName)NC); + + obj->pwm_name = pwm; + + uint32_t pwm_base_clock; + pwm_base_clock = CLOCK_GetFreq(kCLOCK_BusClk); + float clkval = (float)pwm_base_clock / 1000000.0f; + uint32_t clkdiv = 0; + while (clkval > 1) { + clkdiv++; + clkval /= 2.0f; + if (clkdiv == 7) { + break; + } + } + + pwm_clock_mhz = clkval; + uint32_t channel = pwm & 0xF; + uint32_t instance = pwm >> TPM_SHIFT; + ftm_config_t ftmInfo; + + FTM_GetDefaultConfig(&ftmInfo); + ftmInfo.prescale = (ftm_clock_prescale_t)clkdiv; + /* Initialize FTM module */ + FTM_Init(ftm_addrs[instance], &ftmInfo); + + ftm_addrs[instance]->CONF |= FTM_CONF_NUMTOF(3); + + ftm_chnl_pwm_signal_param_t config = { + .chnlNumber = (ftm_chnl_t)channel, + .level = kFTM_HighTrue, + .dutyCyclePercent = 0, + .firstEdgeDelayPercent = 0 + }; + // default to 20ms: standard for servos, and fine for e.g. brightness control + FTM_SetupPwm(ftm_addrs[instance], &config, 1, kFTM_EdgeAlignedPwm, 50, pwm_base_clock); + + FTM_StartTimer(ftm_addrs[instance], kFTM_SystemClock); + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); +} + +void pwmout_free(pwmout_t* obj) +{ + FTM_Deinit(ftm_addrs[obj->pwm_name >> TPM_SHIFT]); +} + +void pwmout_write(pwmout_t* obj, float value) +{ + if (value < 0.0f) { + value = 0.0f; + } else if (value > 1.0f) { + value = 1.0f; + } + + FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; + uint16_t mod = base->MOD & FTM_MOD_MOD_MASK; + uint32_t new_count = (uint32_t)((float)(mod) * value); + // Update of CnV register + base->CONTROLS[obj->pwm_name & 0xF].CnV = new_count; + base->CNT = 0; + /* Software trigger to update registers */ + FTM_SetSoftwareTrigger(base, true); +} + +float pwmout_read(pwmout_t* obj) +{ + FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; + uint16_t count = (base->CONTROLS[obj->pwm_name & 0xF].CnV) & FTM_CnV_VAL_MASK; + uint16_t mod = base->MOD & FTM_MOD_MOD_MASK; + + if (mod == 0) + return 0.0; + float v = (float)(count) / (float)(mod); + return (v > 1.0f) ? (1.0f) : (v); +} + +void pwmout_period(pwmout_t* obj, float seconds) +{ + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) +{ + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) +{ + FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; + float dc = pwmout_read(obj); + + // Stop FTM clock to ensure instant update of MOD register + base->MOD = FTM_MOD_MOD((pwm_clock_mhz * (float)us) - 1); + pwmout_write(obj, dc); +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) +{ + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) +{ + FTM_Type *base = ftm_addrs[obj->pwm_name >> TPM_SHIFT]; + uint32_t value = (uint32_t)(pwm_clock_mhz * (float)us); + + // Update of CnV register + base->CONTROLS[obj->pwm_name & 0xF].CnV = value; + /* Software trigger to update registers */ + FTM_SetSoftwareTrigger(base, true); +} + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/serial_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/serial_api.c new file mode 100644 index 00000000000..b706932e943 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/serial_api.c @@ -0,0 +1,706 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "serial_api.h" + +#if DEVICE_SERIAL + +// math.h required for floating point operations for baud rate calculation +#include +#include "mbed_assert.h" + +#include + +#include "cmsis.h" +#include "pinmap.h" +#include "fsl_uart.h" +#include "peripheral_clock_defines.h" +#include "PeripheralPins.h" +#include "dma_reqs.h" +#include "fsl_clock_config.h" + +static uint32_t serial_irq_ids[FSL_FEATURE_SOC_UART_COUNT] = {0}; +static uart_irq_handler irq_handler; +/* Array of UART peripheral base address. */ +static UART_Type *const uart_addrs[] = UART_BASE_PTRS; +/* Array of UART bus clock frequencies */ +static clock_name_t const uart_clocks[] = UART_CLOCK_FREQS; + +/* UART transfer states */ +#define kUART_TxIdle 0 +#define kUART_TxBusy 1 +#define kUART_RxIdle 2 +#define kUART_RxBusy 3 + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + obj->serial.index = pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->serial.index != NC); + + uart_config_t config; + + UART_GetDefaultConfig(&config); + config.baudRate_Bps = 9600; + config.enableTx = false; + config.enableRx = false; + + UART_Init(uart_addrs[obj->serial.index], &config, CLOCK_GetFreq(uart_clocks[obj->serial.index])); + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (tx != NC) { + UART_EnableTx(uart_addrs[obj->serial.index], true); + pin_mode(tx, PullUp); + } + if (rx != NC) { + UART_EnableRx(uart_addrs[obj->serial.index], true); + pin_mode(rx, PullUp); + } + + if (obj->serial.index == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } + + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;; + obj->serial.txstate = kUART_TxIdle; + obj->serial.rxstate = kUART_RxIdle; + + /* Zero the handle. */ + memset(&(obj->serial.uart_transfer_handle), 0, sizeof(obj->serial.uart_transfer_handle)); +} + +void serial_free(serial_t *obj) +{ + UART_Deinit(uart_addrs[obj->serial.index]); + serial_irq_ids[obj->serial.index] = 0; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + UART_SetBaudRate(uart_addrs[obj->serial.index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->serial.index])); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + UART_Type *base = uart_addrs[obj->serial.index]; + uint8_t temp; + /* Set bit count and parity mode. */ + temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); + if (parity != ParityNone) + { + /* Enable Parity */ + temp |= (UART_C1_PE_MASK | UART_C1_M_MASK); + if (parity == ParityOdd) { + temp |= UART_C1_PT_MASK; + } else if (parity == ParityEven) { + // PT=0 so nothing more to do + } else { + // Hardware does not support forced parity + MBED_ASSERT(0); + } + } + base->C1 = temp; +#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT + /* Set stop bit per char */ + base->BDH = (base->BDH & ~UART_BDH_SBNS_MASK) | UART_BDH_SBNS((uint8_t)--stop_bits); +#endif +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ +static inline void uart_irq(uint32_t transmit_empty, uint32_t receive_full, uint32_t index) +{ + UART_Type *base = uart_addrs[index]; + + /* If RX overrun. */ + if (UART_S1_OR_MASK & base->S1) + { + /* Read base->D, otherwise the RX does not work. */ + (void)base->D; + } + + if (serial_irq_ids[index] != 0) { + if (transmit_empty) + irq_handler(serial_irq_ids[index], TxIrq); + + if (receive_full) + irq_handler(serial_irq_ids[index], RxIrq); + } +} + +void uart0_irq() +{ + uint32_t status_flags = UART0->S1; + uart_irq((status_flags & kUART_TxDataRegEmptyFlag), (status_flags & kUART_RxDataRegFullFlag), 0); +} + +void uart1_irq() +{ + uint32_t status_flags = UART1->S1; + uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 1); +} + +void uart2_irq() +{ + uint32_t status_flags = UART2->S1; + uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 2); +} + +void uart3_irq() +{ + uint32_t status_flags = UART3->S1; + uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 3); +} + +void uart4_irq() +{ + uint32_t status_flags = UART4->S1; + uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 4); +} + +void uart5_irq() +{ + uint32_t status_flags = UART5->S1; + uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 5); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + irq_handler = handler; + serial_irq_ids[obj->serial.index] = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + IRQn_Type uart_irqs[] = UART_RX_TX_IRQS; + uint32_t vector = 0; + + switch (obj->serial.index) { + case 0: + vector = (uint32_t)&uart0_irq; + break; + case 1: + vector = (uint32_t)&uart1_irq; + break; + case 2: + vector = (uint32_t)&uart2_irq; + break; + case 3: + vector = (uint32_t)&uart3_irq; + break; + case 4: + vector = (uint32_t)&uart4_irq; + break; + case 5: + vector = (uint32_t)&uart5_irq; + break; + default: + break; + } + + if (enable) { + switch (irq) { + case RxIrq: + UART_EnableInterrupts(uart_addrs[obj->serial.index], kUART_RxDataRegFullInterruptEnable); + break; + case TxIrq: + UART_EnableInterrupts(uart_addrs[obj->serial.index], kUART_TxDataRegEmptyInterruptEnable); + break; + default: + break; + } + NVIC_SetVector(uart_irqs[obj->serial.index], vector); + NVIC_EnableIRQ(uart_irqs[obj->serial.index]); + + } else { // disable + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + switch (irq) { + case RxIrq: + UART_DisableInterrupts(uart_addrs[obj->serial.index], kUART_RxDataRegFullInterruptEnable); + break; + case TxIrq: + UART_DisableInterrupts(uart_addrs[obj->serial.index], kUART_TxDataRegEmptyInterruptEnable); + break; + default: + break; + } + switch (other_irq) { + case RxIrq: + all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->serial.index]) & kUART_RxDataRegFullInterruptEnable) == 0); + break; + case TxIrq: + all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->serial.index]) & kUART_TxDataRegEmptyInterruptEnable) == 0); + break; + default: + break; + } + if (all_disabled) + NVIC_DisableIRQ(uart_irqs[obj->serial.index]); + } +} + +int serial_getc(serial_t *obj) +{ + while (!serial_readable(obj)); + uint8_t data; + data = UART_ReadByte(uart_addrs[obj->serial.index]); + + return data; +} + +void serial_putc(serial_t *obj, int c) +{ + while (!serial_writable(obj)); + UART_WriteByte(uart_addrs[obj->serial.index], (uint8_t)c); +} + +int serial_readable(serial_t *obj) +{ + uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->serial.index]); + if (status_flags & kUART_RxOverrunFlag) + UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_RxOverrunFlag); + return (status_flags & kUART_RxDataRegFullFlag); +} + +int serial_writable(serial_t *obj) +{ + uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->serial.index]); + if (status_flags & kUART_RxOverrunFlag) + UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_RxOverrunFlag); + return (status_flags & kUART_TxDataRegEmptyFlag); +} + +void serial_clear(serial_t *obj) +{ +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + uart_addrs[obj->serial.index]->C2 |= UART_C2_SBK_MASK; +} + +void serial_break_clear(serial_t *obj) +{ + uart_addrs[obj->serial.index]->C2 &= ~UART_C2_SBK_MASK; +} + +#if DEVICE_SERIAL_FC + +/* + * Only hardware flow control is implemented in this API. + */ +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + switch(type) { + case FlowControlRTS: + pinmap_pinout(rxflow, PinMap_UART_RTS); + uart_addrs[obj->serial.index]->MODEM &= ~UART_MODEM_TXCTSE_MASK; + uart_addrs[obj->serial.index]->MODEM |= UART_MODEM_RXRTSE_MASK; + break; + + case FlowControlCTS: + pinmap_pinout(txflow, PinMap_UART_CTS); + uart_addrs[obj->serial.index]->MODEM &= ~UART_MODEM_RXRTSE_MASK; + uart_addrs[obj->serial.index]->MODEM |= UART_MODEM_TXCTSE_MASK; + break; + + case FlowControlRTSCTS: + pinmap_pinout(rxflow, PinMap_UART_RTS); + pinmap_pinout(txflow, PinMap_UART_CTS); + uart_addrs[obj->serial.index]->MODEM |= UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK; + break; + + case FlowControlNone: + uart_addrs[obj->serial.index]->MODEM &= ~(UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK); + break; + + default: + break; + } +} + +#endif + +static void serial_send_asynch(serial_t *obj) +{ + uart_transfer_t sendXfer; + + /*Setup send transfer*/ + sendXfer.data = obj->tx_buff.buffer; + sendXfer.dataSize = obj->tx_buff.length; + + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || + obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + UART_SendEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle, &sendXfer); + } else { + UART_TransferSendNonBlocking(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, &sendXfer); + } +} + +static void serial_receive_asynch(serial_t *obj) +{ + uart_transfer_t receiveXfer; + + /*Setup send transfer*/ + receiveXfer.data = obj->rx_buff.buffer; + receiveXfer.dataSize = obj->rx_buff.length; + + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || + obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + UART_ReceiveEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle, &receiveXfer); + } else { + UART_TransferReceiveNonBlocking(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, &receiveXfer, NULL); + } +} + +static bool serial_allocate_dma(serial_t *obj, uint32_t handler) +{ + dma_request_source_t dma_rx_requests[] = UART_DMA_RX_REQUEST_NUMBERS; + dma_request_source_t dma_tx_requests[] = UART_DMA_TX_REQUEST_NUMBERS; + edma_config_t userConfig; + + /* Allocate the UART RX DMA channel */ + obj->serial.uartDmaRx.dmaChannel = dma_channel_allocate(dma_rx_requests[obj->serial.index]); + if (obj->serial.uartDmaRx.dmaChannel == DMA_ERROR_OUT_OF_CHANNELS) { + return false; + } + + /* Allocate the UART TX DMA channel */ + obj->serial.uartDmaTx.dmaChannel = dma_channel_allocate(dma_tx_requests[obj->serial.index]); + if (obj->serial.uartDmaTx.dmaChannel == DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->serial.uartDmaRx.dmaChannel); + return false; + } + + /* EDMA init*/ + /* + * userConfig.enableRoundRobinArbitration = false; + * userConfig.enableHaltOnError = true; + * userConfig.enableContinuousLinkMode = false; + * userConfig.enableDebugMode = false; + */ + EDMA_GetDefaultConfig(&userConfig); + + EDMA_Init(DMA0, &userConfig); + + memset(&(obj->serial.uartDmaTx.handle), 0, sizeof(obj->serial.uartDmaTx.handle)); + memset(&(obj->serial.uartDmaRx.handle), 0, sizeof(obj->serial.uartDmaRx.handle)); + + EDMA_CreateHandle(&(obj->serial.uartDmaRx.handle), DMA0, obj->serial.uartDmaRx.dmaChannel); + EDMA_CreateHandle(&(obj->serial.uartDmaTx.handle), DMA0, obj->serial.uartDmaTx.dmaChannel); + + UART_TransferCreateHandleEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle, (uart_edma_transfer_callback_t)handler, + NULL, &obj->serial.uartDmaTx.handle, &obj->serial.uartDmaRx.handle); + + return true; +} + +void serial_enable_dma(serial_t *obj, uint32_t handler, DMAUsage state) +{ + dma_init(); + + if (state == DMA_USAGE_ALWAYS && obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_ALLOCATED) { + /* Try to allocate channels */ + if (serial_allocate_dma(obj, handler)) { + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_ALLOCATED; + } else { + obj->serial.uartDmaRx.dmaUsageState = state; + } + } else if (state == DMA_USAGE_OPPORTUNISTIC) { + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED) { + /* Channels have already been allocated previously by an ALWAYS state, so after this transfer, we will release them */ + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_TEMPORARY_ALLOCATED; + } else { + /* Try to allocate channels */ + if (serial_allocate_dma(obj, handler)) { + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_TEMPORARY_ALLOCATED; + } else { + obj->serial.uartDmaRx.dmaUsageState = state; + } + } + } else if (state == DMA_USAGE_NEVER) { + /* If channels are allocated, get rid of them */ + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED) { + dma_channel_free(obj->serial.uartDmaRx.dmaChannel); + dma_channel_free(obj->serial.uartDmaRx.dmaChannel); + } + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_NEVER; + } +} + +void serial_enable_event(serial_t *obj, int event, uint8_t enable) +{ + // Keep track of the requested events. + if (enable) { + obj->serial.events |= event; + } else { + obj->serial.events &= ~event; + } +} + +static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width) { + (void)width; + + // Exit if a transmit is already on-going + if (serial_tx_active(obj)) { + return; + } + + obj->tx_buff.buffer = tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; +} + +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + // Check that a buffer has indeed been set up + MBED_ASSERT(tx != (void*)0); + + if (tx_length == 0) return 0; + + if (serial_tx_active(obj)) { + return 0; + } + + // Set up buffer + serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); + + // Set up events + serial_enable_event(obj, SERIAL_EVENT_TX_ALL, false); + serial_enable_event(obj, event, true); + + /* If using DMA, allocate channels only if they have not already been allocated */ + if (hint != DMA_USAGE_NEVER) { + /* User requested to transfer using DMA */ + serial_enable_dma(obj, handler, hint); + + /* Check if DMA setup was successful */ + if (obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_ALLOCATED && obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_TEMPORARY_ALLOCATED) { + /* Set up an interrupt transfer as DMA is unavailable */ + if (obj->serial.uart_transfer_handle.callback == 0) { + UART_TransferCreateHandle(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, (uart_transfer_callback_t)handler, NULL); + } + } + } else { + /* User requested to transfer using interrupts */ + /* Disable the DMA */ + serial_enable_dma(obj, handler, hint); + + /* Set up the interrupt transfer */ + if (obj->serial.uart_transfer_handle.callback == 0) { + UART_TransferCreateHandle(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, (uart_transfer_callback_t)handler, NULL); + } + } + + obj->serial.txstate = kUART_TxBusy; + + /* Start the transfer */ + serial_send_asynch(obj); + + return 0; +} + +void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width) +{ + // We only support byte buffers for now + MBED_ASSERT(width == 8); + + if (serial_rx_active(obj)) return; + + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; + + return; +} + +/* Character match is currently not supported */ +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) +{ + // Check that a buffer has indeed been set up + MBED_ASSERT(rx != (void*)0); + if (rx_length == 0) return; + + if (serial_rx_active(obj)) { + return; + } + + // Set up buffer + serial_rx_buffer_set(obj,(void*) rx, rx_length, rx_width); + + // Set up events + serial_enable_event(obj, SERIAL_EVENT_RX_ALL, false); + serial_enable_event(obj, event, true); + + //obj->char_match = char_match; + + /* If using DMA, allocate channels only if they have not already been allocated */ + if (hint != DMA_USAGE_NEVER) { + /* User requested to transfer using DMA */ + serial_enable_dma(obj, handler, hint); + + /* Check if DMA setup was successful */ + if (obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_ALLOCATED && obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_TEMPORARY_ALLOCATED) { + /* Set up an interrupt transfer as DMA is unavailable */ + if (obj->serial.uart_transfer_handle.callback == 0) { + UART_TransferCreateHandle(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, (uart_transfer_callback_t)handler, NULL); + } + } + + } else { + /* User requested to transfer using interrupts */ + /* Disable the DMA */ + serial_enable_dma(obj, handler, hint); + + /* Set up the interrupt transfer */ + if (obj->serial.uart_transfer_handle.callback == 0) { + UART_TransferCreateHandle(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, (uart_transfer_callback_t)handler, NULL); + } + } + + obj->serial.rxstate = kUART_RxBusy; + + /* Start the transfer */ + serial_receive_asynch(obj); +} + +uint8_t serial_tx_active(serial_t *obj) +{ + if (obj->serial.txstate == kUART_TxIdle) { + return 0; + } + + return 1; +} + +uint8_t serial_rx_active(serial_t *obj) +{ + if (obj->serial.rxstate == kUART_RxIdle) { + return 0; + } + + return 1; +} + +int serial_irq_handler_asynch(serial_t *obj) +{ + int status = 0; + //uint8_t *buf = (uint8_t*)obj->rx_buff.buffer; + uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->serial.index]); + + /* Determine whether the current scenario is DMA or IRQ, and act accordingly */ + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + /* DMA implementation */ + if ((obj->serial.txstate != kUART_TxIdle) && (obj->serial.uart_dma_handle.txState == kUART_TxIdle)) { + obj->serial.txstate = kUART_TxIdle; + status |= SERIAL_EVENT_TX_COMPLETE; + } + + if ((obj->serial.rxstate != kUART_RxIdle) && (obj->serial.uart_dma_handle.rxState == kUART_RxIdle)) { + obj->serial.rxstate = kUART_RxIdle; + status |= SERIAL_EVENT_RX_COMPLETE; + } + + /* Release the dma channels if they were opportunistically allocated */ + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + /* Ensure both TX and RX channels are idle before freeing them */ + if ((obj->serial.uart_dma_handle.txState == kUART_TxIdle) && (obj->serial.uart_dma_handle.rxState == kUART_RxIdle)) { + dma_channel_free(obj->serial.uartDmaRx.dmaChannel); + dma_channel_free(obj->serial.uartDmaTx.dmaChannel); + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; + } + } + } else { + /* Interrupt implementation */ + if ((obj->serial.txstate != kUART_TxIdle) && (obj->serial.uart_transfer_handle.txState == kUART_TxIdle)) { + obj->serial.txstate = kUART_TxIdle; + status |= SERIAL_EVENT_TX_COMPLETE; + } + + if ((obj->serial.rxstate != kUART_RxIdle) && (obj->serial.uart_transfer_handle.rxState == kUART_RxIdle)) { + obj->serial.rxstate = kUART_RxIdle; + status |= SERIAL_EVENT_RX_COMPLETE; + } + } + + if (status_flags & kUART_RxOverrunFlag) { + UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_RxOverrunFlag); + status |= SERIAL_EVENT_RX_OVERRUN_ERROR; + } + + if (status_flags & kUART_FramingErrorFlag) { + UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_FramingErrorFlag); + status |= SERIAL_EVENT_RX_FRAMING_ERROR; + } + + if (status_flags & kUART_ParityErrorFlag) { + UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_ParityErrorFlag); + status |= SERIAL_EVENT_RX_PARITY_ERROR; + } + + return status & obj->serial.events; +} + +void serial_tx_abort_asynch(serial_t *obj) +{ + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + UART_TransferAbortSendEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle); + /* Release the dma channels if they were opportunistically allocated */ + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + /* Ensure both TX and RX channels are idle before freeing them */ + if ((obj->serial.uart_dma_handle.txState == kUART_TxIdle) && (obj->serial.uart_dma_handle.rxState == kUART_RxIdle)) { + dma_channel_free(obj->serial.uartDmaRx.dmaChannel); + dma_channel_free(obj->serial.uartDmaTx.dmaChannel); + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; + } + } + } else { + UART_TransferAbortSend(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle); + } +} + +void serial_rx_abort_asynch(serial_t *obj) +{ + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + UART_TransferAbortReceiveEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle); + /* Release the dma channels if they were opportunistically allocated */ + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + /* Ensure both TX and RX channels are idle before freeing them */ + if ((obj->serial.uart_dma_handle.txState == kUART_TxIdle) && (obj->serial.uart_dma_handle.rxState == kUART_RxIdle)) { + dma_channel_free(obj->serial.uartDmaRx.dmaChannel); + dma_channel_free(obj->serial.uartDmaTx.dmaChannel); + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; + } + } + } else { + UART_TransferAbortReceive(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle); + } +} + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/spi_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/spi_api.c new file mode 100644 index 00000000000..bc5bb459bc6 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/spi_api.c @@ -0,0 +1,433 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "mbed_assert.h" + +#include "spi_api.h" + +#if DEVICE_SPI + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "fsl_dspi.h" +#include "peripheral_clock_defines.h" +#include "dma_reqs.h" +#include "PeripheralPins.h" + +/* Array of SPI peripheral base address. */ +static SPI_Type *const spi_address[] = SPI_BASE_PTRS; +/* Array of SPI bus clock frequencies */ +static clock_name_t const spi_clocks[] = SPI_CLOCK_FREQS; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // determine the SPI to use + uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); + uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); + uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); + + obj->spi.instance = pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->spi.instance != NC); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } + + /* Set the transfer status to idle */ + obj->spi.status = kDSPI_Idle; + + obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; +} + +void spi_free(spi_t *obj) +{ + DSPI_Deinit(spi_address[obj->spi.instance]); +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + dspi_master_config_t master_config; + dspi_slave_config_t slave_config; + + /* Bits: values between 4 and 16 are valid */ + MBED_ASSERT(bits >= 4 && bits <= 16); + obj->spi.bits = bits; + + if (slave) { + /* Slave config */ + DSPI_SlaveGetDefaultConfig(&slave_config); + slave_config.whichCtar = kDSPI_Ctar0; + slave_config.ctarConfig.bitsPerFrame = (uint32_t)bits;; + slave_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh; + slave_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge; + + DSPI_SlaveInit(spi_address[obj->spi.instance], &slave_config); + } else { + /* Master config */ + DSPI_MasterGetDefaultConfig(&master_config); + master_config.ctarConfig.bitsPerFrame = (uint32_t)bits;; + master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh; + master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge; + master_config.ctarConfig.direction = kDSPI_MsbFirst; + master_config.ctarConfig.pcsToSckDelayInNanoSec = 0; + + DSPI_MasterInit(spi_address[obj->spi.instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->spi.instance])); + } +} + +void spi_frequency(spi_t *obj, int hz) +{ + uint32_t busClock = CLOCK_GetFreq(spi_clocks[obj->spi.instance]); + DSPI_MasterSetBaudRate(spi_address[obj->spi.instance], kDSPI_Ctar0, (uint32_t)hz, busClock); + //Half clock period delay after SPI transfer + DSPI_MasterSetDelayTimes(spi_address[obj->spi.instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz); +} + +static inline int spi_readable(spi_t * obj) +{ + return (DSPI_GetStatusFlags(spi_address[obj->spi.instance]) & kDSPI_RxFifoDrainRequestFlag); +} + +int spi_master_write(spi_t *obj, int value) +{ + dspi_command_data_config_t command; + uint32_t rx_data; + DSPI_GetDefaultDataCommandConfig(&command); + command.isEndOfQueue = true; + + DSPI_MasterWriteDataBlocking(spi_address[obj->spi.instance], &command, (uint16_t)value); + + DSPI_ClearStatusFlags(spi_address[obj->spi.instance], kDSPI_TxFifoFillRequestFlag); + + // wait rx buffer full + while (!spi_readable(obj)); + rx_data = DSPI_ReadData(spi_address[obj->spi.instance]); + DSPI_ClearStatusFlags(spi_address[obj->spi.instance], kDSPI_RxFifoDrainRequestFlag | kDSPI_EndOfQueueFlag); + return rx_data & 0xffff; +} + +int spi_slave_receive(spi_t *obj) +{ + return spi_readable(obj); +} + +int spi_slave_read(spi_t *obj) +{ + uint32_t rx_data; + + while (!spi_readable(obj)); + rx_data = DSPI_ReadData(spi_address[obj->spi.instance]); + DSPI_ClearStatusFlags(spi_address[obj->spi.instance], kDSPI_RxFifoDrainRequestFlag); + return rx_data & 0xffff; +} + +void spi_slave_write(spi_t *obj, int value) +{ + DSPI_SlaveWriteDataBlocking(spi_address[obj->spi.instance], (uint32_t)value); +} + +static int32_t spi_master_transfer_asynch(spi_t *obj) +{ + dspi_transfer_t masterXfer; + int32_t status; + uint32_t transferSize; + + /*Start master transfer*/ + masterXfer.txData = obj->tx_buff.buffer; + masterXfer.rxData = obj->rx_buff.buffer; + masterXfer.dataSize = obj->tx_buff.length; + masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous; + /* Busy transferring */ + obj->spi.status = kDSPI_Busy; + + if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED || + obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + status = DSPI_MasterTransferEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle, &masterXfer); + if (status == kStatus_DSPI_OutOfRange) { + if (obj->spi.bits > 8) { + transferSize = 1022; + } else { + transferSize = 511; + } + masterXfer.dataSize = transferSize; + /* Save amount of TX done by DMA */ + obj->tx_buff.pos += transferSize; + obj->rx_buff.pos += transferSize; + /* Try again */ + status = DSPI_MasterTransferEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle, &masterXfer); + } + } else { + status = DSPI_MasterTransferNonBlocking(spi_address[obj->spi.instance], &obj->spi.spi_master_handle, &masterXfer); + } + + return status; +} + +static bool spi_allocate_dma(spi_t *obj, uint32_t handler) +{ + dma_request_source_t dma_rx_requests[] = SPI_DMA_RX_REQUEST_NUMBERS; + dma_request_source_t dma_tx_requests[] = SPI_DMA_TX_REQUEST_NUMBERS; + edma_config_t userConfig; + + /* Allocate the DMA channels */ + /* Allocate the RX channel */ + obj->spi.spiDmaMasterRx.dmaChannel = dma_channel_allocate(dma_rx_requests[obj->spi.instance]); + if (obj->spi.spiDmaMasterRx.dmaChannel == DMA_ERROR_OUT_OF_CHANNELS) { + return false; + } + + /* Check if we have separate DMA requests for TX & RX */ + if (dma_tx_requests[obj->spi.instance] != dma_rx_requests[obj->spi.instance]) { + /* Allocate the TX channel with the DMA TX request number set as source */ + obj->spi.spiDmaMasterTx.dmaChannel = dma_channel_allocate(dma_tx_requests[obj->spi.instance]); + } else { + /* Allocate the TX channel without setting source */ + obj->spi.spiDmaMasterTx.dmaChannel = dma_channel_allocate(kDmaRequestMux0Disable); + } + if (obj->spi.spiDmaMasterTx.dmaChannel == DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->spi.spiDmaMasterRx.dmaChannel); + return false; + } + + /* Allocate an intermediary DMA channel */ + obj->spi.spiDmaMasterIntermediary.dmaChannel = dma_channel_allocate(kDmaRequestMux0Disable); + if (obj->spi.spiDmaMasterIntermediary.dmaChannel == DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->spi.spiDmaMasterRx.dmaChannel); + dma_channel_free(obj->spi.spiDmaMasterTx.dmaChannel); + return false; + } + + /* EDMA init*/ + /* + * userConfig.enableRoundRobinArbitration = false; + * userConfig.enableHaltOnError = true; + * userConfig.enableContinuousLinkMode = false; + * userConfig.enableDebugMode = false; + */ + EDMA_GetDefaultConfig(&userConfig); + + EDMA_Init(DMA0, &userConfig); + + /* Set up dspi master */ + memset(&(obj->spi.spiDmaMasterRx.handle), 0, sizeof(obj->spi.spiDmaMasterRx.handle)); + memset(&(obj->spi.spiDmaMasterTx.handle), 0, sizeof(obj->spi.spiDmaMasterTx.handle)); + memset(&(obj->spi.spiDmaMasterIntermediary.handle), 0, sizeof(obj->spi.spiDmaMasterIntermediary.handle)); + + EDMA_CreateHandle(&(obj->spi.spiDmaMasterRx.handle), DMA0, obj->spi.spiDmaMasterRx.dmaChannel); + EDMA_CreateHandle(&(obj->spi.spiDmaMasterIntermediary.handle), DMA0, + obj->spi.spiDmaMasterIntermediary.dmaChannel); + EDMA_CreateHandle(&(obj->spi.spiDmaMasterTx.handle), DMA0, obj->spi.spiDmaMasterTx.dmaChannel); + + DSPI_MasterTransferCreateHandleEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle, (dspi_master_edma_transfer_callback_t)handler, + NULL, &obj->spi.spiDmaMasterRx.handle, + &obj->spi.spiDmaMasterIntermediary.handle, + &obj->spi.spiDmaMasterTx.handle); + return true; +} + +static void spi_enable_dma(spi_t *obj, uint32_t handler, DMAUsage state) +{ + dma_init(); + + if (state == DMA_USAGE_ALWAYS && obj->spi.spiDmaMasterRx.dmaUsageState != DMA_USAGE_ALLOCATED) { + /* Try to allocate channels */ + if (spi_allocate_dma(obj, handler)) { + obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_ALLOCATED; + } else { + obj->spi.spiDmaMasterRx.dmaUsageState = state; + } + } else if (state == DMA_USAGE_OPPORTUNISTIC) { + if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED) { + /* Channels have already been allocated previously by an ALWAYS state, so after this transfer, we will release them */ + obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_TEMPORARY_ALLOCATED; + } else { + /* Try to allocate channels */ + if (spi_allocate_dma(obj, handler)) { + obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_TEMPORARY_ALLOCATED; + } else { + obj->spi.spiDmaMasterRx.dmaUsageState = state; + } + } + } else if (state == DMA_USAGE_NEVER) { + /* If channels are allocated, get rid of them */ + if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED) { + dma_channel_free(obj->spi.spiDmaMasterRx.dmaChannel); + dma_channel_free(obj->spi.spiDmaMasterTx.dmaChannel); + dma_channel_free(obj->spi.spiDmaMasterIntermediary.dmaChannel); + } + obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_NEVER; + } +} + +static void spi_buffer_set(spi_t *obj, const void *tx, uint32_t tx_length, void *rx, uint32_t rx_length, uint8_t bit_width) +{ + obj->tx_buff.buffer = (void *)tx; + obj->rx_buff.buffer = rx; + obj->tx_buff.length = tx_length; + obj->rx_buff.length = rx_length; + obj->tx_buff.pos = 0; + obj->rx_buff.pos = 0; + obj->tx_buff.width = bit_width; + obj->rx_buff.width = bit_width; +} + +void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + if(spi_active(obj)) { + return; + } + + /* check corner case */ + if(tx_length == 0) { + tx_length = rx_length; + tx = (void*) 0; + } + + /* First, set the buffer */ + spi_buffer_set(obj, tx, tx_length, rx, rx_length, bit_width); + + /* If using DMA, allocate channels only if they have not already been allocated */ + if (hint != DMA_USAGE_NEVER) { + /* User requested to transfer using DMA */ + spi_enable_dma(obj, handler, hint); + + /* Check if DMA setup was successful */ + if (obj->spi.spiDmaMasterRx.dmaUsageState != DMA_USAGE_ALLOCATED && obj->spi.spiDmaMasterRx.dmaUsageState != DMA_USAGE_TEMPORARY_ALLOCATED) { + /* Set up an interrupt transfer as DMA is unavailable */ + DSPI_MasterTransferCreateHandle(spi_address[obj->spi.instance], &obj->spi.spi_master_handle, (dspi_master_transfer_callback_t)handler, NULL); + } + + } else { + /* User requested to transfer using interrupts */ + /* Disable the DMA */ + spi_enable_dma(obj, handler, hint); + + /* Set up the interrupt transfer */ + DSPI_MasterTransferCreateHandle(spi_address[obj->spi.instance], &obj->spi.spi_master_handle, (dspi_master_transfer_callback_t)handler, NULL); + } + + /* Start the transfer */ + if (spi_master_transfer_asynch(obj) != kStatus_Success) { + obj->spi.status = kDSPI_Idle; + } +} + +uint32_t spi_irq_handler_asynch(spi_t *obj) +{ + uint32_t transferSize; + dspi_transfer_t masterXfer; + + /* Determine whether the current scenario is DMA or IRQ, and act accordingly */ + if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED || obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + /* DMA implementation */ + /* Check If there is still data in the TX buffer */ + if (obj->tx_buff.pos < obj->tx_buff.length) { + /* Setup a new DMA transfer. */ + if (obj->spi.bits > 8) { + transferSize = 1022; + } else { + transferSize = 511; + } + + /* Update the TX buffer only if it is used */ + if (obj->tx_buff.buffer) { + masterXfer.txData = ((uint8_t *)obj->tx_buff.buffer) + obj->tx_buff.pos; + } else { + masterXfer.txData = 0; + } + + /* Update the RX buffer only if it is used */ + if (obj->rx_buff.buffer) { + masterXfer.rxData = ((uint8_t *)obj->rx_buff.buffer) + obj->rx_buff.pos; + } else { + masterXfer.rxData = 0; + } + + /* Check how much data is remaining in the buffer */ + if ((obj->tx_buff.length - obj->tx_buff.pos) > transferSize) { + masterXfer.dataSize = transferSize; + } else { + masterXfer.dataSize = obj->tx_buff.length - obj->tx_buff.pos; + } + masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous; + + /* Save amount of TX done by DMA */ + obj->tx_buff.pos += masterXfer.dataSize; + obj->rx_buff.pos += masterXfer.dataSize; + + /* Start another transfer */ + DSPI_MasterTransferEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle, &masterXfer); + return 0; + } else { + /* Release the dma channels if they were opportunistically allocated */ + if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + dma_channel_free(obj->spi.spiDmaMasterRx.dmaChannel); + dma_channel_free(obj->spi.spiDmaMasterTx.dmaChannel); + dma_channel_free(obj->spi.spiDmaMasterIntermediary.dmaChannel); + obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; + } + obj->spi.status = kDSPI_Idle; + + return SPI_EVENT_COMPLETE; + } + } else { + /* Interrupt implementation */ + obj->spi.status = kDSPI_Idle; + + return SPI_EVENT_COMPLETE; + } +} + +void spi_abort_asynch(spi_t *obj) +{ + // If we're not currently transferring, then there's nothing to do here + if(spi_active(obj) == 0) { + return; + } + + // Determine whether we're running DMA or interrupt + if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_ALLOCATED || + obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + DSPI_MasterTransferAbortEDMA(spi_address[obj->spi.instance], &obj->spi.spi_dma_master_handle); + /* Release the dma channels if they were opportunistically allocated */ + if (obj->spi.spiDmaMasterRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + dma_channel_free(obj->spi.spiDmaMasterRx.dmaChannel); + dma_channel_free(obj->spi.spiDmaMasterTx.dmaChannel); + dma_channel_free(obj->spi.spiDmaMasterIntermediary.dmaChannel); + obj->spi.spiDmaMasterRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; + } + } else { + /* Interrupt implementation */ + DSPI_MasterTransferAbort(spi_address[obj->spi.instance], &obj->spi.spi_master_handle); + } + + obj->spi.status = kDSPI_Idle; +} + +uint8_t spi_active(spi_t *obj) +{ + return obj->spi.status; +} + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/trng_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/trng_api.c new file mode 100644 index 00000000000..890fc50224f --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/trng_api.c @@ -0,0 +1,86 @@ +/* + * Hardware entropy collector for the K64F, using Freescale's RNGA + * + * Copyright (C) 2006-2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +/* + * Reference: "K64 Sub-Family Reference Manual, Rev. 2", chapter 34 + */ + +#if defined(DEVICE_TRNG) + +#include +#include "cmsis.h" +#include "fsl_common.h" +#include "fsl_clock.h" +#include "trng_api.h" + +void trng_init(trng_t *obj) +{ + (void)obj; + CLOCK_EnableClock(kCLOCK_Rnga0); + CLOCK_DisableClock(kCLOCK_Rnga0); + CLOCK_EnableClock(kCLOCK_Rnga0); +} + +void trng_free(trng_t *obj) +{ + (void)obj; + CLOCK_DisableClock(kCLOCK_Rnga0); +} + +/* + * Get one byte of entropy from the RNG, assuming it is up and running. + * As recommended (34.1.1), get only one bit of each output. + */ +static void trng_get_byte(unsigned char *byte) +{ + size_t bit; + + /* 34.5 Steps 3-4-5: poll SR and read from OR when ready */ + for( bit = 0; bit < 8; bit++ ) + { + while((RNG->SR & RNG_SR_OREG_LVL_MASK) == 0 ); + *byte |= (RNG->OR & 1) << bit; + } +} + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) +{ + (void)obj; + size_t i; + + /* Set "Interrupt Mask", "High Assurance" and "Go", + * unset "Clear interrupt" and "Sleep" */ + RNG->CR = RNG_CR_INTM_MASK | RNG_CR_HA_MASK | RNG_CR_GO_MASK; + + for (i = 0; i < length; i++) { + trng_get_byte(output + i); + } + + /* Just be extra sure that we didn't do it wrong */ + if ((RNG->SR & RNG_SR_SECV_MASK) != 0) { + return -1; + } + + *output_length = length; + + return 0; +} + +#endif diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c new file mode 100644 index 00000000000..2c7d3945870 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c @@ -0,0 +1,92 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "fsl_pit.h" +#include "fsl_clock_config.h" + +static int us_ticker_inited = 0; + +void us_ticker_init(void) +{ + if (us_ticker_inited) { + return; + } + us_ticker_inited = 1; + //Common for ticker/timer + uint32_t busClock; + // Structure to initialize PIT + pit_config_t pitConfig; + + PIT_GetDefaultConfig(&pitConfig); + PIT_Init(PIT, &pitConfig); + + busClock = CLOCK_GetFreq(kCLOCK_BusClk); + + //Timer + PIT_SetTimerPeriod(PIT, kPIT_Chnl_0, busClock / 1000000 - 1); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_1, 0xFFFFFFFF); + PIT_SetTimerChainMode(PIT, kPIT_Chnl_1, true); + PIT_StartTimer(PIT, kPIT_Chnl_0); + PIT_StartTimer(PIT, kPIT_Chnl_1); + + //Ticker + PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); + PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); + NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_EnableIRQ(PIT3_IRQn); +} + + +uint32_t us_ticker_read() +{ + if (!us_ticker_inited) { + us_ticker_init(); + } + + return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1)); +} + +void us_ticker_disable_interrupt(void) +{ + PIT_DisableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); +} + +void us_ticker_clear_interrupt(void) +{ + PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + int delta = (int)(timestamp - us_ticker_read()); + if (delta <= 0) { + // This event was in the past. + // Set the interrupt as pending, but don't process it here. + // This prevents a recurive loop under heavy load + // which can lead to a stack overflow. + NVIC_SetPendingIRQ(PIT3_IRQn); + return; + } + + PIT_StopTimer(PIT, kPIT_Chnl_3); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta); + PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); + PIT_StartTimer(PIT, kPIT_Chnl_3); + PIT_StartTimer(PIT, kPIT_Chnl_2); +} diff --git a/targets/TARGET_Freescale/mbed_rtx.h b/targets/TARGET_Freescale/mbed_rtx.h index 90060bcd206..43a913e652f 100644 --- a/targets/TARGET_Freescale/mbed_rtx.h +++ b/targets/TARGET_Freescale/mbed_rtx.h @@ -247,6 +247,26 @@ #define OS_CLOCK 120000000 #endif +#elif defined(TARGET_RO359B) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20030000UL) +#endif + +#if defined(__CC_ARM) || defined(__GNUC__) +#define ISR_STACK_SIZE (0x1000) +#endif + +#ifndef OS_TASKCNT +#define OS_TASKCNT 14 +#endif +#ifndef OS_MAINSTKSIZE +#define OS_MAINSTKSIZE 256 +#endif +#ifndef OS_CLOCK +#define OS_CLOCK 96000000 +#endif + #endif #endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c index 143969229a5..8a9e7bb4221 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32630/gpio_irq_api.c @@ -100,15 +100,15 @@ int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint3 /* register handlers */ irq_handler = handler; - NVIC_SetVector(GPIO_P0_IRQn, gpio_irq_0); - NVIC_SetVector(GPIO_P1_IRQn, gpio_irq_1); - NVIC_SetVector(GPIO_P2_IRQn, gpio_irq_2); - NVIC_SetVector(GPIO_P3_IRQn, gpio_irq_3); - NVIC_SetVector(GPIO_P4_IRQn, gpio_irq_4); - NVIC_SetVector(GPIO_P5_IRQn, gpio_irq_5); - NVIC_SetVector(GPIO_P6_IRQn, gpio_irq_6); - NVIC_SetVector(GPIO_P7_IRQn, gpio_irq_7); - NVIC_SetVector(GPIO_P8_IRQn, gpio_irq_8); + NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0); + NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1); + NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2); + NVIC_SetVector(GPIO_P3_IRQn, (uint32_t)gpio_irq_3); + NVIC_SetVector(GPIO_P4_IRQn, (uint32_t)gpio_irq_4); + NVIC_SetVector(GPIO_P5_IRQn, (uint32_t)gpio_irq_5); + NVIC_SetVector(GPIO_P6_IRQn, (uint32_t)gpio_irq_6); + NVIC_SetVector(GPIO_P7_IRQn, (uint32_t)gpio_irq_7); + NVIC_SetVector(GPIO_P8_IRQn, (uint32_t)gpio_irq_8); /* disable the interrupt locally */ MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4)); diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.c b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.c index 098e953b54e..4bd18960b3b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.c +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.c @@ -76,7 +76,7 @@ void NVIC_SetRAM(void) } /* ************************************************************************* */ -int NVIC_SetVector(IRQn_Type irqn, void(*irq_handler)(void)) +int NVIC_SetVector(IRQn_Type irqn, uint32_t irq_handler) { int index = irqn + 16; /* offset for externals */ @@ -85,7 +85,7 @@ int NVIC_SetVector(IRQn_Type irqn, void(*irq_handler)(void)) NVIC_SetRAM(); } - ramVectorTable[index] = irq_handler; + ramVectorTable[index] = (void(*)(void))irq_handler; NVIC_EnableIRQ(irqn); return 0; diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.h index 5e7daa9c207..385253802d8 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.h +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/nvic_table.h @@ -71,7 +71,7 @@ typedef void (*irq_fn)(void); * @param irqn ARM external IRQ number, see #IRQn_Type * @param irq_handler Function to be called at IRQ context */ -int NVIC_SetVector(IRQn_Type irqn, irq_fn irq_handler); +int NVIC_SetVector(IRQn_Type irqn, uint32_t irq_handler); /** * @brief Copy NVIC vector table to RAM and set NVIC to RAM based table. diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c index 2b411c26c31..703ea7954c4 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c @@ -71,9 +71,9 @@ void rtc_init(void) CLKMAN_SetClkScale(CLKMAN_CLK_SYNC, CLKMAN_SCALE_DIV_1); // Prepare interrupt handlers - NVIC_SetVector(RTC0_IRQn, lp_ticker_irq_handler); + NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler); NVIC_EnableIRQ(RTC0_IRQn); - NVIC_SetVector(RTC3_IRQn, overflow_handler); + NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler); NVIC_EnableIRQ(RTC3_IRQn); // Enable wakeup on RTC rollover diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c index a84df5a297c..543dfa7cda6 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32630/serial_api.c @@ -202,19 +202,19 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { switch (obj->index) { case 0: - NVIC_SetVector(UART0_IRQn, uart0_handler); + NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); NVIC_EnableIRQ(UART0_IRQn); break; case 1: - NVIC_SetVector(UART1_IRQn, uart1_handler); + NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler); NVIC_EnableIRQ(UART1_IRQn); break; case 2: - NVIC_SetVector(UART2_IRQn, uart2_handler); + NVIC_SetVector(UART2_IRQn, (uint32_t)uart2_handler); NVIC_EnableIRQ(UART2_IRQn); break; case 3: - NVIC_SetVector(UART3_IRQn, uart3_handler); + NVIC_SetVector(UART3_IRQn, (uint32_t)uart3_handler); NVIC_EnableIRQ(UART3_IRQn); break; default: diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c index dad1ce2339f..5da2417d897 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c +++ b/targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c @@ -140,7 +140,7 @@ void us_ticker_init(void) cfg.compareCount = 0xFFFFFFFF; TMR32_Config(US_TIMER, &cfg); - NVIC_SetVector(US_TIMER_IRQn, tmr_handler); + NVIC_SetVector(US_TIMER_IRQn, (uint32_t)tmr_handler); NVIC_EnableIRQ(US_TIMER_IRQn); TMR32_EnableINT(US_TIMER); diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk_patch/sdk_config.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk_patch/sdk_config.h new file mode 100644 index 00000000000..8ee54778fcc --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk_patch/sdk_config.h @@ -0,0 +1,19 @@ +#ifndef _SDK_CONFIG_H_ +#define _SDK_CONFIG_H_ + +#include "nrf_drv_config.h" + +#define UART_DEFAULT_CONFIG_BAUDRATE UART0_CONFIG_BAUDRATE +#define UART_DEFAULT_CONFIG_PARITY UART0_CONFIG_PARITY +#define UART_DEFAULT_CONFIG_HWFC UART0_CONFIG_HWFC +#define CTS_PIN_NUMBER UART0_CONFIG_PSEL_CTS +#define RTS_PIN_NUMBER UART0_CONFIG_PSEL_RTS + +#define SPIS_DEFAULT_ORC NRF_DRV_SPIS_DEFAULT_ORC +#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY SPIS1_CONFIG_IRQ_PRIORITY; +#define SPIS_DEFAULT_ORC NRF_DRV_SPIS_DEFAULT_ORC +#define SPIS_DEFAULT_DEF NRF_DRV_SPIS_DEFAULT_DEF + +#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY SPI1_CONFIG_IRQ_PRIORITY + +#endif \ No newline at end of file diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/analogin_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/analogin_api.c deleted file mode 100644 index d33effecdf2..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/analogin_api.c +++ /dev/null @@ -1,91 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "mbed_assert.h" -#include "analogin_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "app_util_platform.h" -#include "nrf_drv_saadc.h" - -#ifdef DEVICE_ANALOGIN - -#define ADC_12BIT_RANGE 0xFFF -#define ADC_RANGE ADC_12BIT_RANGE - -static void analog_in_event_handler(nrf_drv_saadc_evt_t const *p_event)// type of nrf_drv_saadc_event_handler_t -{ - (void) p_event; -} - -static const nrf_drv_saadc_config_t saadc_config = -{ - .resolution = NRF_SAADC_RESOLUTION_12BIT, - .oversample = NRF_SAADC_OVERSAMPLE_DISABLED, - .interrupt_priority = SAADC_CONFIG_IRQ_PRIORITY -}; - -void SAADC_IRQHandler(void); - -void analogin_init(analogin_t *obj, PinName pin) -{ - ret_code_t ret_code; - - NVIC_SetVector(SAADC_IRQn, (uint32_t)SAADC_IRQHandler); - - ret_code = nrf_drv_saadc_init(&saadc_config, analog_in_event_handler); - MBED_ASSERT(((ret_code == NRF_SUCCESS) || (ret_code == NRF_ERROR_INVALID_STATE))); //NRF_ERROR_INVALID_STATE expected for multiple channels used. - - uint8_t saadcIn = nrf_drv_saadc_gpio_to_ain(pin); - MBED_ASSERT(saadcIn != NRF_SAADC_INPUT_DISABLED); - - obj->adc = ADC0_0; // only one instance of ADC in nRF52 SoC - obj->adc_pin = saadcIn - 1; - - nrf_saadc_channel_config_t channel_config = - NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_SE(saadcIn); //Single ended, negative input to ADC shorted to GND. - - ret_code = nrf_drv_saadc_channel_init(obj->adc_pin, &channel_config); - MBED_ASSERT(ret_code == NRF_SUCCESS); -} - - -uint16_t analogin_read_u16(analogin_t *obj) -{ - int16_t adc_value; - ret_code_t ret_code; - - ret_code = nrf_drv_saadc_sample_convert(obj->adc_pin, &adc_value); - MBED_ASSERT(ret_code == NRF_SUCCESS); - - if (adc_value < 0) - { - // Even in the single ended mode measured value can be {-0}. Saturation for avoid casting to a big integer. - return 0; - } - else - { - return (uint16_t) adc_value; - } -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = analogin_read_u16(obj); - return (float)value * (1.0f / (float)ADC_RANGE); -} - -#endif // DEVICE_ANALOGIN diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/pwmout_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/pwmout_api.c deleted file mode 100644 index 97e29f256db..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/pwmout_api.c +++ /dev/null @@ -1,399 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "mbed_assert.h" -#include "mbed_error.h" -#include "pwmout_api.h" -#include "cmsis.h" -#include "pinmap.h" - -#if DEVICE_PWMOUT - -#include "app_util_platform.h" -#include "nrf_drv_pwm.h" - -#define MAX_PWM_COUNTERTOP (0x7FFF) // 0x7FFF is the max of COUNTERTOP value for the PWM peripherial of the nRF52. -#define MAX_PWM_PERIOD_US (MAX_PWM_COUNTERTOP * 8) // PWM hw is driven by 16 MHz clock, hence the tick is 1_us/16, - // and 128 is the max prescaler value. -#define MAX_PWM_PERIOD_MS ((MAX_PWM_PERIOD_US / 1000) + 1) // approximations advance -#define MAX_PWM_PERIOD_S ((MAX_PWM_PERIOD_US / 1000000) + 1) // approximations advance - - -#define PWM_INSTANCE_COUNT (PWM_COUNT) // import from the nrf_drv_config.h file - -///> instances of nRF52 PWM driver -static const nrf_drv_pwm_t m_pwm_driver[PWM_INSTANCE_COUNT] = -{ -#if PWM0_ENABLED - NRF_DRV_PWM_INSTANCE(0), -#endif -#if PWM1_ENABLED - NRF_DRV_PWM_INSTANCE(1), -#endif -#if PWM2_ENABLED - NRF_DRV_PWM_INSTANCE(2) -#endif -}; - -typedef struct -{ - uint32_t period_us; - uint32_t duty_us; - float duty; -} pwm_signal_t; /// PWM signal description type - -typedef struct -{ - nrf_drv_pwm_t * p_pwm_driver; - pwm_signal_t signal; - volatile nrf_pwm_values_common_t seq_values[1]; -} pwm_t; /// internal PWM instance support type - -static pwm_t m_pwm[PWM_INSTANCE_COUNT] = -{ -#if PWM0_ENABLED - {.p_pwm_driver = NULL}, -#endif -#if PWM1_ENABLED - {.p_pwm_driver = NULL}, -#endif -#if PWM2_ENABLED - {.p_pwm_driver = NULL} -#endif -}; /// Array of internal PWM instances. - -typedef struct -{ - uint16_t period_hwu; // unit related to pwm_clk - uint16_t duty_hwu; // unit related to pwm_clk - nrf_pwm_clk_t pwm_clk; -} pulsewidth_set_t; /// helper type for timing calculations - - -static void internal_pwmout_exe(pwmout_t *obj, bool new_period, bool initialization); - -// extern PWM nIRQ handler implementations -void PWM0_IRQHandler(void); -void PWM1_IRQHandler(void); -void PWM2_IRQHandler(void); - -static const peripheral_handler_desc_t pwm_handlers[PWM_INSTANCE_COUNT] = -{ - { - PWM0_IRQn, - (uint32_t)PWM0_IRQHandler - }, - { - PWM1_IRQn, - (uint32_t)PWM1_IRQHandler - }, - { - PWM2_IRQn, - (uint32_t)PWM2_IRQHandler - } -}; - -void pwmout_init(pwmout_t *obj, PinName pin) -{ - uint32_t i; - - for (i = 0; PWM_INSTANCE_COUNT; i++) - { - if (m_pwm[i].p_pwm_driver == NULL) // a driver instance not assigned to the obj? - { - NVIC_SetVector(pwm_handlers[i].IRQn, pwm_handlers[i].vector); - - obj->pin = pin; - - obj->pwm_channel = i; - - m_pwm[i].p_pwm_driver = (nrf_drv_pwm_t *) &m_pwm_driver[i]; - m_pwm[i].signal.period_us = 200000; // 0.02 s - m_pwm[i].signal.duty_us = 100000; - m_pwm[i].signal.duty = 0.5f; - - obj->pwm_struct = &m_pwm[i]; - - internal_pwmout_exe(obj, true, true); - - break; - } - } - - MBED_ASSERT(i != PWM_INSTANCE_COUNT); // assert if free instance was not found. -} - -void pwmout_free(pwmout_t *obj) -{ - nrf_drv_pwm_uninit( (nrf_drv_pwm_t*) obj->pwm_struct ); - - m_pwm[obj->pwm_channel].p_pwm_driver = NULL; -} - -void pwmout_write(pwmout_t *obj, float percent) -{ - - if (percent < 0) - { - percent = 0; - } - else if (percent > 1) - { - percent = 1; - } - - pwm_signal_t * p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal); - - p_pwm_signal->duty = percent; - - int us = (((int)p_pwm_signal->period_us) * percent); - - pwmout_pulsewidth_us(obj, us); -} - -float pwmout_read(pwmout_t *obj) -{ - pwm_signal_t * p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal); - - return (float)p_pwm_signal->duty_us / (float)p_pwm_signal->period_us; -} - -void pwmout_period(pwmout_t *obj, float seconds) -{ - // raught saturation < 0, quasi-max> - if (seconds > MAX_PWM_PERIOD_S) - { - seconds = MAX_PWM_PERIOD_S; - } - else if (seconds < 0) - { - seconds = 0; // f. pwmout_period_us will set period to min. value - } - - int us = seconds * 1000000; - - pwmout_period_us(obj, us); -} - -void pwmout_period_ms(pwmout_t *obj, int ms) -{ - // reught saturation < 0, quasi-max> - if (ms > MAX_PWM_PERIOD_MS) - { - ms = MAX_PWM_PERIOD_MS; - } - else if (ms < 0) - { - ms = 0; // f. pwmout_period_us will set period to min. value - } - - int us = ms * 1000; - - pwmout_period_us(obj, us); -} - - -void pwmout_period_us(pwmout_t *obj, int us) -{ - pwm_signal_t * p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal); - - // saturation <1, real-max> - if (us > MAX_PWM_PERIOD_US) - { - us = MAX_PWM_PERIOD_US; - } - else if (us < 1) - { - us = 1; - } - - p_pwm_signal->duty_us = (int)((float)us * p_pwm_signal->duty); - - p_pwm_signal->period_us = us; - - internal_pwmout_exe(obj, true, false); -} - -void pwmout_pulsewidth(pwmout_t *obj, float seconds) -{ - // raught saturation < 0, quasi-max> - if (seconds > MAX_PWM_PERIOD_S) - { - seconds = MAX_PWM_PERIOD_S; - } - else if (seconds < 0) - { - seconds = 0; - } - - int us = seconds * 1000000; - - pwmout_pulsewidth_us(obj,us); -} - -void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) -{ - // raught saturation < 0, quasi-max> - if (ms > MAX_PWM_PERIOD_MS) - { - ms = MAX_PWM_PERIOD_MS; - } - else if (ms < 0) - { - ms = 0; - } - - int us = ms * 1000; - - pwmout_pulsewidth_us(obj, us); -} - -void pwmout_pulsewidth_us(pwmout_t *obj, int us) -{ - // saturation <0, real-max> - if (us > MAX_PWM_PERIOD_US) - { - us = MAX_PWM_PERIOD_US; - } - else if (us < 0) - { - us = 0; - } - - pwm_signal_t * p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal); - - p_pwm_signal->duty_us = us; - p_pwm_signal->duty = us / p_pwm_signal->period_us; - - internal_pwmout_exe(obj, false, false); -} - - - - - - -static ret_code_t pulsewidth_us_set_get(int period_hwu, int duty_hwu, pulsewidth_set_t * p_settings) -{ - uint16_t div; - nrf_pwm_clk_t pwm_clk = NRF_PWM_CLK_16MHz; - - for(div = 1; div <= 128 ; div <<= 1) // 128 is the maximum of clock prescaler for PWM peripherial - { - if (MAX_PWM_COUNTERTOP >= period_hwu) - { - p_settings->period_hwu = period_hwu; // unit [us/16 * div] - p_settings->duty_hwu = duty_hwu; // unit [us/16 * div] - p_settings->pwm_clk = pwm_clk; - - return NRF_SUCCESS; - } - - period_hwu >>= 1; - duty_hwu >>= 1; - pwm_clk++; - } - - return NRF_ERROR_INVALID_PARAM; -} - - -static void internal_pwmout_exe(pwmout_t *obj, bool new_period, bool initialization) -{ - pulsewidth_set_t pulsewidth_set; - pwm_signal_t * p_pwm_signal; - nrf_drv_pwm_t * p_pwm_driver; - ret_code_t ret_code; - - p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal); - - if (NRF_SUCCESS == pulsewidth_us_set_get(p_pwm_signal->period_us * 16, // base clk for PWM is 16 MHz - p_pwm_signal->duty_us * 16, // base clk for PWM is 16 MHz - &pulsewidth_set)) - { - p_pwm_driver = (((pwm_t*)obj->pwm_struct)->p_pwm_driver); - - const nrf_pwm_sequence_t seq = - { - .values.p_common = (nrf_pwm_values_common_t*) (((pwm_t*)obj->pwm_struct)->seq_values), - .length = 1, - .repeats = 0, - .end_delay = 0 - }; - - (((pwm_t*)obj->pwm_struct)->seq_values)[0] = pulsewidth_set.duty_hwu | 0x8000; - - if (new_period) - { - nrf_drv_pwm_config_t config0 = - { - .output_pins = - { - obj->pin | NRF_DRV_PWM_PIN_INVERTED, // channel 0 - NRF_DRV_PWM_PIN_NOT_USED, // channel 1 - NRF_DRV_PWM_PIN_NOT_USED, // channel 2 - NRF_DRV_PWM_PIN_NOT_USED, // channel 3 - }, - .irq_priority = PWM0_CONFIG_IRQ_PRIORITY, - .base_clock = pulsewidth_set.pwm_clk, - .count_mode = NRF_PWM_MODE_UP, - .top_value = pulsewidth_set.period_hwu, - .load_mode = NRF_PWM_LOAD_COMMON, - .step_mode = NRF_PWM_STEP_AUTO - }; - - if (!initialization) - { - nrf_drv_pwm_uninit(p_pwm_driver); - } - - ret_code = nrf_drv_pwm_init( p_pwm_driver, &config0, NULL); - - MBED_ASSERT(ret_code == NRF_SUCCESS); // assert if free instance was not found. - } - - nrf_drv_pwm_simple_playback(p_pwm_driver, &seq, 0, NRF_DRV_PWM_FLAG_LOOP); - } - else - { - MBED_ASSERT(0); // force assertion - } - -} - -#endif // DEVICE_PWMOUT diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk_patch/sdk_config.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk_patch/sdk_config.h new file mode 100644 index 00000000000..e9a63353a9f --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk_patch/sdk_config.h @@ -0,0 +1,21 @@ +#ifndef _SDK_CONFIG_H_ +#define _SDK_CONFIG_H_ + +#include "nrf_drv_config.h" + +#define UART_DEFAULT_CONFIG_BAUDRATE UART0_CONFIG_BAUDRATE +#define UART_DEFAULT_CONFIG_PARITY UART0_CONFIG_PARITY +#define UART_DEFAULT_CONFIG_HWFC UART0_CONFIG_HWFC +#define CTS_PIN_NUMBER UART0_CONFIG_PSEL_CTS +#define RTS_PIN_NUMBER UART0_CONFIG_PSEL_RTS + +#define SPIS_DEFAULT_ORC NRF_DRV_SPIS_DEFAULT_ORC +#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY SPIS1_CONFIG_IRQ_PRIORITY; +#define SPIS_DEFAULT_ORC NRF_DRV_SPIS_DEFAULT_ORC +#define SPIS_DEFAULT_DEF NRF_DRV_SPIS_DEFAULT_DEF + +#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY SPI1_CONFIG_IRQ_PRIORITY + +#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY PWM0_CONFIG_IRQ_PRIORITY + +#endif \ No newline at end of file diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/PeripheralNames.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/PeripheralNames.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/PeripheralNames.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/PeripheralNames.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/PortNames.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/PortNames.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/PortNames.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/PortNames.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/PinNames.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/PinNames.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/PinNames.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/device.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/device.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/device.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/device.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/nRF52832.sct diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/sys.cpp similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/sys.cpp rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/sys.cpp diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/startup_NRF52832.S diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52832.icf b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52832.icf similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52832.icf rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/nRF52832.icf diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/cmsis.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/cmsis.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/cmsis.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/cmsis.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/cmsis_nvic.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/cmsis_nvic.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/cmsis_nvic.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/cmsis_nvic.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/cmsis_nvic.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/cmsis_nvic.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/cmsis_nvic.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/cmsis_nvic.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/system_nrf52840.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/system_nrf52840.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/system_nrf52840.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/system_nrf52840.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/system_nrf52840.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/system_nrf52840.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/device/system_nrf52840.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/system_nrf52840.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/sdk_config.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/sdk_config.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/sdk_config.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/sdk_config.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf52/nrf_mbr.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf52/nrf_mbr.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf52/nrf_mbr.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf52/nrf_mbr.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble.h index 86d4d9adffc..60b18442bc4 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble.h @@ -49,13 +49,13 @@ #ifndef BLE_H__ #define BLE_H__ -#include "ble_ranges.h" -#include "ble_types.h" -#include "ble_gap.h" -#include "ble_l2cap.h" -#include "ble_gatt.h" -#include "ble_gattc.h" -#include "ble_gatts.h" +#include "nrf_ble_ranges.h" +#include "nrf_ble_types.h" +#include "nrf_ble_gap.h" +#include "nrf_ble_l2cap.h" +#include "nrf_ble_gatt.h" +#include "nrf_ble_gattc.h" +#include "nrf_ble_gatts.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_err.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_err.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_err.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_err.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gap.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gap.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gap.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gap.h index 7748702e822..8f651e21dd8 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gap.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gap.h @@ -45,8 +45,8 @@ #ifndef BLE_GAP_H__ #define BLE_GAP_H__ -#include "ble_types.h" -#include "ble_ranges.h" +#include "nrf_ble_types.h" +#include "nrf_ble_ranges.h" #include "nrf_svc.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gatt.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gatt.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gatt.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gatt.h index cfa3860b5fa..ceafee8a460 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gatt.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gatt.h @@ -45,8 +45,8 @@ #ifndef BLE_GATT_H__ #define BLE_GATT_H__ -#include "ble_types.h" -#include "ble_ranges.h" +#include "nrf_ble_types.h" +#include "nrf_ble_ranges.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gattc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gattc.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gattc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gattc.h index c36a4d7e348..eb1f7753d76 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gattc.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gattc.h @@ -45,9 +45,9 @@ #ifndef BLE_GATTC_H__ #define BLE_GATTC_H__ -#include "ble_gatt.h" -#include "ble_types.h" -#include "ble_ranges.h" +#include "nrf_ble_gatt.h" +#include "nrf_ble_types.h" +#include "nrf_ble_ranges.h" #include "nrf_svc.h" #include "nrf_error.h" #include "nrf.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gatts.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gatts.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gatts.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gatts.h index b85735ec31c..588edcc0029 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_gatts.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gatts.h @@ -45,11 +45,11 @@ #ifndef BLE_GATTS_H__ #define BLE_GATTS_H__ -#include "ble_types.h" -#include "ble_ranges.h" -#include "ble_l2cap.h" -#include "ble_gap.h" -#include "ble_gatt.h" +#include "nrf_ble_types.h" +#include "nrf_ble_ranges.h" +#include "nrf_ble_l2cap.h" +#include "nrf_ble_gap.h" +#include "nrf_ble_gatt.h" #include "nrf_svc.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_hci.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_hci.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_hci.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_hci.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_l2cap.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_l2cap.h similarity index 98% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_l2cap.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_l2cap.h index eaad7e50fc9..d3cc747b100 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_l2cap.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_l2cap.h @@ -45,9 +45,9 @@ #ifndef BLE_L2CAP_H__ #define BLE_L2CAP_H__ -#include "ble_types.h" -#include "ble_ranges.h" -#include "ble_err.h" +#include "nrf_ble_types.h" +#include "nrf_ble_ranges.h" +#include "nrf_ble_err.h" #include "nrf_svc.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_ranges.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_ranges.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_ranges.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_ranges.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_types.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/ble_types.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_types.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error_sdm.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error_sdm.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error_sdm.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error_sdm.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error_soc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error_soc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error_soc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_error_soc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_nvic.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_nvic.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_nvic.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_nvic.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_sd_def.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_sd_def.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_sd_def.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_sd_def.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_sdm.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_sdm.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_sdm.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_sdm.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_soc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_soc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_soc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_soc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_svc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_svc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_svc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_svc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/hex/s140_nrf52840_5.0.0-1.alpha_softdevice.hex b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/hex/s140_nrf52840_5.0.0-1.alpha_softdevice.hex similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/TARGET_MCU_NRF52840/sdk/softdevice/s140/hex/s140_nrf52840_5.0.0-1.alpha_softdevice.hex rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/hex/s140_nrf52840_5.0.0-1.alpha_softdevice.hex diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/analogin_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_NRF52_COMMON/analogin_api.c similarity index 96% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/analogin_api.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_NRF52_COMMON/analogin_api.c index dcc0f44f0dd..8dec19a34bf 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/analogin_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_NRF52_COMMON/analogin_api.c @@ -13,6 +13,8 @@ * See the License for the specific language governing permissions and * limitations under the License. */ + +#ifndef TARGET_MCU_NRF51822 #include "mbed_assert.h" #include "analogin_api.h" @@ -26,7 +28,9 @@ #define ADC_12BIT_RANGE 0xFFF #define ADC_RANGE ADC_12BIT_RANGE +#ifdef TARGET_SDK13 __STATIC_INLINE nrf_saadc_input_t nrf_drv_saadc_gpio_to_ain(uint32_t pin); +#endif static void analog_in_event_handler(nrf_drv_saadc_evt_t const *p_event)// type of nrf_drv_saadc_event_handler_t @@ -91,7 +95,7 @@ float analogin_read(analogin_t *obj) return (float)value * (1.0f / (float)ADC_RANGE); } - +#ifdef TARGET_SDK13 /** * @brief Function for converting a GPIO pin number to an analog input pin number used in the channel * configuration. @@ -119,5 +123,8 @@ __STATIC_INLINE nrf_saadc_input_t nrf_drv_saadc_gpio_to_ain(uint32_t pin) return NRF_SAADC_INPUT_DISABLED; } } +#endif // TARGET_SDK13 #endif // DEVICE_ANALOGIN + +#endif // !TARGET_MCU_NRF51822 diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/pwmout_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_NRF52_COMMON/pwmout_api.c similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/pwmout_api.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_NRF52_COMMON/pwmout_api.c index 230ca3e9fe6..08e86a3d1e0 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/pwmout_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_NRF52_COMMON/pwmout_api.c @@ -35,12 +35,15 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ - + +#ifndef TARGET_MCU_NRF51822 + #include "mbed_assert.h" #include "mbed_error.h" #include "pwmout_api.h" #include "cmsis.h" #include "pinmap.h" +#include "sdk_config.h" #if DEVICE_PWMOUT @@ -397,3 +400,5 @@ static void internal_pwmout_exe(pwmout_t *obj, bool new_period, bool initializat } #endif // DEVICE_PWMOUT + +#endif \ No newline at end of file diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_advertising/ble_advertising.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_advertising/ble_advertising.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_advertising/ble_advertising.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_advertising/ble_advertising.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_advertising/ble_advertising.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_advertising/ble_advertising.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_advertising/ble_advertising.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_advertising/ble_advertising.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_db_discovery/ble_db_discovery.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_db_discovery/ble_db_discovery.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_db_discovery/ble_db_discovery.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_db_discovery/ble_db_discovery.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_db_discovery/ble_db_discovery.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_db_discovery/ble_db_discovery.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_db_discovery/ble_db_discovery.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_db_discovery/ble_db_discovery.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_debug_assert_handler/ble_debug_assert_handler.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_debug_assert_handler/ble_debug_assert_handler.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_debug_assert_handler/ble_debug_assert_handler.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_debug_assert_handler/ble_debug_assert_handler.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_dtm/ble_dtm.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_dtm/ble_dtm.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_dtm/ble_dtm.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_dtm/ble_dtm.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_dtm/ble_dtm.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_dtm/ble_dtm.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_dtm/ble_dtm.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_dtm/ble_dtm.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_error_log/ble_error_log.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_error_log/ble_error_log.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_error_log/ble_error_log.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_error_log/ble_error_log.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_racp/ble_racp.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_racp/ble_racp.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_racp/ble_racp.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_racp/ble_racp.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_racp/ble_racp.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_racp/ble_racp.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_racp/ble_racp.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_racp/ble_racp.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_radio_notification/ble_radio_notification.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_radio_notification/ble_radio_notification.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_radio_notification/ble_radio_notification.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_radio_notification/ble_radio_notification.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_radio_notification/ble_radio_notification.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_radio_notification/ble_radio_notification.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_radio_notification/ble_radio_notification.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_radio_notification/ble_radio_notification.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_services/ble_dfu/ble_dfu.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_services/ble_dfu/ble_dfu.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_services/ble_dfu/ble_dfu.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_services/ble_dfu/ble_dfu.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_services/ble_dfu/ble_dfu.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_services/ble_dfu/ble_dfu.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_services/ble_dfu/ble_dfu.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_services/ble_dfu/ble_dfu.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_advdata.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_advdata.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_advdata.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_advdata.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_advdata.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_advdata.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_advdata.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_advdata.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_params.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_conn_params.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_params.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_conn_params.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_state.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_conn_state.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_state.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_conn_state.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_state.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_conn_state.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_state.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_conn_state.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_date_time.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_date_time.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_date_time.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_date_time.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_gatt_db.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_gatt_db.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_gatt_db.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_gatt_db.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_sensor_location.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_sensor_location.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_sensor_location.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_sensor_location.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_srv_common.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_srv_common.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_srv_common.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_srv_common.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_srv_common.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_srv_common.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_srv_common.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/common/ble_srv_common.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/config/device_manager_cnfg.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/device_manager/config/device_manager_cnfg.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/config/device_manager_cnfg.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/device_manager/config/device_manager_cnfg.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/device_manager.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/device_manager/device_manager.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/device_manager.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/device_manager/device_manager.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/device_manager_peripheral.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/device_manager/device_manager_peripheral.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/device_manager_peripheral.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/device_manager/device_manager_peripheral.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatt_cache_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatt_cache_manager.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatt_cache_manager.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatt_cache_manager.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatt_cache_manager.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatt_cache_manager.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatt_cache_manager.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatt_cache_manager.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gattc_cache_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gattc_cache_manager.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gattc_cache_manager.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gattc_cache_manager.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatts_cache_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatts_cache_manager.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatts_cache_manager.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatts_cache_manager.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/id_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/id_manager.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/id_manager.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/id_manager.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_data.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_data.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_data.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_data.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data_storage.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_data_storage.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data_storage.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_data_storage.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data_storage.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_data_storage.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data_storage.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_data_storage.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_database.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_database.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_database.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_database.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_database.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_database.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_database.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_database.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_id.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_id.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_id.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_id.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_id.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_id.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_id.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_id.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_manager.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_manager.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_manager.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_manager.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager_internal.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_manager_internal.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager_internal.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_manager_internal.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_manager_types.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager_types.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/peer_manager_types.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_buffer.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/pm_buffer.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_buffer.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/pm_buffer.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_buffer.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/pm_buffer.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_buffer.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/pm_buffer.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_mutex.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/pm_mutex.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_mutex.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/pm_mutex.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_mutex.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/pm_mutex.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_mutex.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/pm_mutex.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_dispatcher.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/security_dispatcher.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_dispatcher.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/security_dispatcher.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_dispatcher.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/security_dispatcher.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_dispatcher.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/security_dispatcher.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/security_manager.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_manager.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/security_manager.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_manager.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/security_manager.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_manager.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/security_manager.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/compiler_abstraction.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/compiler_abstraction.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/compiler_abstraction.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/compiler_abstraction.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf51.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf51.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_bitfields.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf51_bitfields.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_bitfields.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf51_bitfields.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_deprecated.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf51_deprecated.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_deprecated.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf51_deprecated.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_to_nrf52.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf51_to_nrf52.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_to_nrf52.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf51_to_nrf52.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_bitfields.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_bitfields.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_bitfields.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_bitfields.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_name_change.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_name_change.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_name_change.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_name_change.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ble_flash/ble_flash.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/ble_flash/ble_flash.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ble_flash/ble_flash.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/ble_flash/ble_flash.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ble_flash/ble_flash.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/ble_flash/ble_flash.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ble_flash/ble_flash.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/ble_flash/ble_flash.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/clock/nrf_drv_clock.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/clock/nrf_drv_clock.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/clock/nrf_drv_clock.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/clock/nrf_drv_clock.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/clock/nrf_drv_clock.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/clock/nrf_drv_clock.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/clock/nrf_drv_clock.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/clock/nrf_drv_clock.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/common/nrf_drv_common.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/common/nrf_drv_common.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/common/nrf_drv_common.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/common/nrf_drv_common.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/common/nrf_drv_common.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/common/nrf_drv_common.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/common/nrf_drv_common.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/common/nrf_drv_common.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/config/nrf_drv_config_validation.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/config/nrf_drv_config_validation.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/config/nrf_drv_config_validation.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/config/nrf_drv_config_validation.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/delay/nrf_delay.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/delay/nrf_delay.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/delay/nrf_delay.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/delay/nrf_delay.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/delay/nrf_delay.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/delay/nrf_delay.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/delay/nrf_delay.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/delay/nrf_delay.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/gpiote/nrf_drv_gpiote.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/gpiote/nrf_drv_gpiote.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/gpiote/nrf_drv_gpiote.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/gpiote/nrf_drv_gpiote.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_adc.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_adc.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_adc.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_adc.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_adc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_adc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_adc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_adc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_clock.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_clock.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_clock.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_clock.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ecb.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_ecb.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ecb.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_ecb.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ecb.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_ecb.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ecb.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_ecb.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_gpio.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_gpio.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_gpio.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_gpio.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_gpiote.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_gpiote.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_gpiote.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_gpiote.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_nvmc.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_nvmc.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_nvmc.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_nvmc.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_nvmc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_nvmc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_nvmc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_nvmc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_pdm.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_pdm.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_pdm.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_pdm.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ppi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_ppi.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ppi.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_ppi.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_pwm.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_pwm.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_pwm.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_pwm.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_rtc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_rtc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_rtc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_rtc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_saadc.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_saadc.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_saadc.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_saadc.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_saadc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_saadc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_saadc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_saadc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_spi.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spi.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_spi.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spim.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_spim.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spim.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_spim.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spis.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_spis.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spis.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_spis.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_temp.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_temp.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_temp.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_temp.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_timer.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_timer.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_timer.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_timer.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_twi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_twi.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_twi.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_twi.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_uart.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_uart.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_uart.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_uart.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_wdt.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_wdt.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_wdt.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_wdt.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ppi/nrf_drv_ppi.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/ppi/nrf_drv_ppi.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ppi/nrf_drv_ppi.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/ppi/nrf_drv_ppi.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ppi/nrf_drv_ppi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/ppi/nrf_drv_ppi.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ppi/nrf_drv_ppi.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/ppi/nrf_drv_ppi.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/config/pstorage_platform.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/pstorage/config/pstorage_platform.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/config/pstorage_platform.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/pstorage/config/pstorage_platform.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/pstorage.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/pstorage/pstorage.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/pstorage.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/pstorage/pstorage.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/pstorage.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/pstorage/pstorage.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/pstorage.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/pstorage/pstorage.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_master/nrf_drv_spi.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/spi_master/nrf_drv_spi.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_master/nrf_drv_spi.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/spi_master/nrf_drv_spi.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_master/nrf_drv_spi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/spi_master/nrf_drv_spi.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_master/nrf_drv_spi.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/spi_master/nrf_drv_spi.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_slave/nrf_drv_spis.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/spi_slave/nrf_drv_spis.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_slave/nrf_drv_spis.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/spi_slave/nrf_drv_spis.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_slave/nrf_drv_spis.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/spi_slave/nrf_drv_spis.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_slave/nrf_drv_spis.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/spi_slave/nrf_drv_spis.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/timer/nrf_drv_timer.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/timer/nrf_drv_timer.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/timer/nrf_drv_timer.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/timer/nrf_drv_timer.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/timer/nrf_drv_timer.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/timer/nrf_drv_timer.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/timer/nrf_drv_timer.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/timer/nrf_drv_timer.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/bootloader.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/bootloader.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_settings.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/bootloader_settings.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_settings.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/bootloader_settings.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/bootloader_types.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_types.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/bootloader_types.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_util.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/bootloader_util.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_util.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/bootloader_util.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_util.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/bootloader_util.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_util.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/bootloader_util.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_app_handler.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_app_handler.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_app_handler.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_app_handler.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_app_handler.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_app_handler.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_app_handler.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_app_handler.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_bank_internal.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_bank_internal.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_bank_internal.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_bank_internal.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_ble_svc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_ble_svc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_ble_svc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_ble_svc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_ble_svc_internal.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_ble_svc_internal.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_ble_svc_internal.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_ble_svc_internal.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_init.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_init.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_init.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_init.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_init_template.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_init_template.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_init_template.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_init_template.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_transport.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_transport.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_transport.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_transport.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_types.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_types.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_types.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/hci_transport/hci_transport_config.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/hci_transport/hci_transport_config.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/hci_transport/hci_transport_config.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/hci_transport/hci_transport_config.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/crc16/crc16.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/crc16/crc16.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/crc16/crc16.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/crc16/crc16.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/crc16/crc16.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/crc16/crc16.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/crc16/crc16.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/crc16/crc16.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/experimental_section_vars/section_vars.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/experimental_section_vars/section_vars.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/experimental_section_vars/section_vars.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/experimental_section_vars/section_vars.h index abd489b06c6..8b0bf6152ba 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/experimental_section_vars/section_vars.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/experimental_section_vars/section_vars.h @@ -242,7 +242,7 @@ #elif defined(__ICCARM__) #define NRF_SECTION_VARS_ADD(section_name, type_def) \ - __root type_def @ #section_name + static __root type_def @ #section_name #endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/config/fds_config.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fds/config/fds_config.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/config/fds_config.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fds/config/fds_config.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fds/fds.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fds/fds.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fds/fds.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fds/fds.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds_internal_defs.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fds/fds_internal_defs.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds_internal_defs.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fds/fds_internal_defs.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/config/fstorage_config.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fstorage/config/fstorage_config.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/config/fstorage_config.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fstorage/config/fstorage_config.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fstorage/fstorage.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fstorage/fstorage.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fstorage/fstorage.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fstorage/fstorage.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage_internal_defs.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fstorage/fstorage_internal_defs.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage_internal_defs.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fstorage/fstorage_internal_defs.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage_nosd.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fstorage/fstorage_nosd.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage_nosd.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/fstorage/fstorage_nosd.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/config/hci_mem_pool_internal.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/hci/config/hci_mem_pool_internal.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/config/hci_mem_pool_internal.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/hci/config/hci_mem_pool_internal.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/config/hci_transport_config.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/hci/config/hci_transport_config.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/config/hci_transport_config.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/hci/config/hci_transport_config.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/hci_mem_pool.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/hci/hci_mem_pool.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/hci_mem_pool.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/hci/hci_mem_pool.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/hci_mem_pool.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/hci/hci_mem_pool.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/hci_mem_pool.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/hci/hci_mem_pool.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/pwm/app_pwm.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/pwm/app_pwm.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/pwm/app_pwm.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/pwm/app_pwm.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/pwm/app_pwm.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/pwm/app_pwm.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/pwm/app_pwm.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/pwm/app_pwm.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/scheduler/app_scheduler.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/scheduler/app_scheduler.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/scheduler/app_scheduler.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/scheduler/app_scheduler.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/scheduler/app_scheduler.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/scheduler/app_scheduler.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/scheduler/app_scheduler.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/scheduler/app_scheduler.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/trace/app_trace.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/trace/app_trace.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/trace/app_trace.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/trace/app_trace.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/trace/app_trace.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/trace/app_trace.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/trace/app_trace.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/trace/app_trace.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_error.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_error.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_error.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_error.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error_weak.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_error_weak.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error_weak.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_error_weak.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error_weak.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_error_weak.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error_weak.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_error_weak.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_util.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_util.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_bds.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_util_bds.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_bds.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_util_bds.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_platform.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_util_platform.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_platform.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_util_platform.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_platform.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_util_platform.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_platform.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/app_util_platform.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/common.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/common.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/common.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/common.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nordic_common.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/nordic_common.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nordic_common.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/nordic_common.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_assert.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/nrf_assert.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_assert.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/nrf_assert.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_assert.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/nrf_assert.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_assert.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/nrf_assert.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_log.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/nrf_log.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_log.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/nrf_log.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_log.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/nrf_log.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_log.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/nrf_log.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_common.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_common.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_common.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_common.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_errors.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_errors.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_errors.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_errors.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_macros.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_macros.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_macros.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_macros.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_mapped_flags.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_mapped_flags.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_mapped_flags.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_mapped_flags.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_mapped_flags.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_mapped_flags.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_mapped_flags.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_mapped_flags.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_os.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_os.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_os.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_os.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_resources.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_resources.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_resources.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/util/sdk_resources.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/ant_stack_handler_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ant_stack_handler_types.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/ant_stack_handler_types.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ant_stack_handler_types.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/app_ram_base.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/app_ram_base.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/app_ram_base.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/app_ram_base.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/ble_stack_handler_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ble_stack_handler_types.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/ble_stack_handler_types.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/ble_stack_handler_types.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/softdevice_handler.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/softdevice_handler.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/softdevice_handler.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/softdevice_handler.h index 588ce1626a6..439dffa8b32 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/softdevice_handler.h @@ -232,7 +232,7 @@ uint32_t softdevice_enable(ble_enable_params_t * p_ble_enable_params); /**@cond NO_DOXYGEN */ void intern_softdevice_events_execute(void); - +#define softdevice_handler_is_enabled softdevice_handler_isEnabled /**@endcond */ #endif // SOFTDEVICE_HANDLER_H__ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/softdevice_handler_appsh.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/softdevice_handler_appsh.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/softdevice_handler_appsh.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/softdevice/common/softdevice_handler/softdevice_handler_appsh.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_advertising/ble_advertising.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_advertising/ble_advertising.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_advertising/ble_advertising.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_advertising/ble_advertising.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_advertising/ble_advertising.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_advertising/ble_advertising.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_advertising/ble_advertising.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_advertising/ble_advertising.h index af409e8f18b..9b436d7a08f 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_advertising/ble_advertising.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_advertising/ble_advertising.h @@ -62,8 +62,8 @@ #include #include "nrf_error.h" -#include "headers/ble.h" -#include "ble_gattc.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gattc.h" #include "ble_advdata.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_db_discovery/ble_db_discovery.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_db_discovery/ble_db_discovery.c similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_db_discovery/ble_db_discovery.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_db_discovery/ble_db_discovery.c index eba5b3285de..96bbe91a224 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_db_discovery/ble_db_discovery.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_db_discovery/ble_db_discovery.c @@ -40,7 +40,7 @@ #if NRF_MODULE_ENABLED(BLE_DB_DISCOVERY) #include "ble_db_discovery.h" #include -#include "headers\ble.h" +#include "headers/nrf_ble.h" #include "ble_srv_common.h" #define NRF_LOG_MODULE_NAME "BLE_DB_DISC" #include "nrf_log.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_db_discovery/ble_db_discovery.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_db_discovery/ble_db_discovery.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_db_discovery/ble_db_discovery.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_db_discovery/ble_db_discovery.h index 0372a68fad4..dccfe70ad60 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_db_discovery/ble_db_discovery.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_db_discovery/ble_db_discovery.h @@ -70,8 +70,8 @@ #include #include "nrf_error.h" -#include "headers\ble.h" -#include "ble_gattc.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gattc.h" #include "ble_srv_common.h" #include "ble_gatt_db.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_debug_assert_handler/ble_debug_assert_handler.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_debug_assert_handler/ble_debug_assert_handler.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_debug_assert_handler/ble_debug_assert_handler.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_debug_assert_handler/ble_debug_assert_handler.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_dtm/ble_dtm.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_dtm/ble_dtm.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_dtm/ble_dtm.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_dtm/ble_dtm.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_dtm/ble_dtm.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_dtm/ble_dtm.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_dtm/ble_dtm.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_dtm/ble_dtm.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_dtm/ble_dtm_hw.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_dtm/ble_dtm_hw.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_dtm/ble_dtm_hw.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_dtm/ble_dtm_hw.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_dtm/ble_dtm_hw_nrf52.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_dtm/ble_dtm_hw_nrf52.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_dtm/ble_dtm_hw_nrf52.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_dtm/ble_dtm_hw_nrf52.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_error_log/ble_error_log.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_error_log/ble_error_log.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_error_log/ble_error_log.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_error_log/ble_error_log.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_racp/ble_racp.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_racp/ble_racp.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_racp/ble_racp.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_racp/ble_racp.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_racp/ble_racp.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_racp/ble_racp.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_racp/ble_racp.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_racp/ble_racp.h index a6a60614ce2..97b8f56d4c9 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_racp/ble_racp.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_racp/ble_racp.h @@ -49,8 +49,8 @@ #include #include -#include "headers\ble.h" -#include "ble_types.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_types.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_radio_notification/ble_radio_notification.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_radio_notification/ble_radio_notification.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_radio_notification/ble_radio_notification.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_radio_notification/ble_radio_notification.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_radio_notification/ble_radio_notification.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_radio_notification/ble_radio_notification.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/ble_radio_notification/ble_radio_notification.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_radio_notification/ble_radio_notification.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_advdata.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_advdata.c similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_advdata.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_advdata.c index f114952fba3..9dcc8201cff 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_advdata.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_advdata.c @@ -37,7 +37,7 @@ */ #include "ble_advdata.h" -#include "ble_gap.h" +#include "headers/nrf_ble_gap.h" #include "ble_srv_common.h" #include "sdk_common.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_advdata.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_advdata.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_advdata.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_advdata.h index d67ca5fab7a..d9bb01a7699 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_advdata.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_advdata.h @@ -51,7 +51,7 @@ #include #include #include -#include "headers/ble.h" +#include "headers/nrf_ble.h" #include "app_util.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_conn_params.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_conn_params.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_conn_params.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_conn_params.h index eaf7d84a719..f9ff64c12d3 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_conn_params.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_conn_params.h @@ -48,7 +48,7 @@ #define BLE_CONN_PARAMS_H__ #include -#include "headers/ble.h" +#include "headers/nrf_ble.h" #include "ble_srv_common.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_conn_state.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_conn_state.c similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_conn_state.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_conn_state.c index 6303b50f2cb..b4fb337a2ed 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_conn_state.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_conn_state.c @@ -40,7 +40,7 @@ #include #include #include -#include "headers/ble.h" +#include "headers/nrf_ble.h" #include "sdk_mapped_flags.h" #include "app_error.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_conn_state.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_conn_state.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_conn_state.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_conn_state.h index 8a4417df19a..e310f7b3b5f 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_conn_state.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_conn_state.h @@ -68,7 +68,7 @@ #include #include -#include "headers/ble.h" +#include "headers/nrf_ble.h" #include "sdk_mapped_flags.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_date_time.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_date_time.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_date_time.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_date_time.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_gatt_db.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_gatt_db.h similarity index 98% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_gatt_db.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_gatt_db.h index 712e0520d11..9d6f0e87f63 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_gatt_db.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_gatt_db.h @@ -47,8 +47,8 @@ #define BLE_GATT_DB_H__ #include -#include "headers/ble.h" -#include "ble_gattc.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gattc.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_sensor_location.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_sensor_location.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_sensor_location.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_sensor_location.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_srv_common.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_srv_common.c similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_srv_common.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_srv_common.c index 5f3dd17df3a..8b821cdbc66 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_srv_common.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_srv_common.c @@ -45,7 +45,7 @@ #include #include "nordic_common.h" #include "app_error.h" -#include "headers/ble.h" +#include "headers/nrf_ble.h" bool ble_srv_is_notification_enabled(uint8_t const * p_encoded_data) { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_srv_common.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_srv_common.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_srv_common.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_srv_common.h index 660e9bf7f5f..85df97e00bc 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/common/ble_srv_common.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/common/ble_srv_common.h @@ -49,11 +49,11 @@ #include #include -#include "ble_types.h" +#include "headers/nrf_ble_types.h" #include "app_util.h" -#include "headers/ble.h" -#include "ble_gap.h" -#include "ble_gatt.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gap.h" +#include "headers/nrf_ble_gatt.h" #ifdef __cplusplus extern "C" { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatt_cache_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatt_cache_manager.c similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatt_cache_manager.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatt_cache_manager.c index ba19efadd35..0e2f2a1835b 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatt_cache_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatt_cache_manager.c @@ -40,7 +40,7 @@ #if NRF_MODULE_ENABLED(PEER_MANAGER) #include "gatt_cache_manager.h" -#include "ble_gap.h" +#include "headers/nrf_ble_gap.h" #include "ble_conn_state.h" #include "peer_manager_types.h" #include "peer_manager_internal.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatt_cache_manager.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatt_cache_manager.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatt_cache_manager.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatt_cache_manager.h index fe95dba5452..79d4d718364 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatt_cache_manager.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatt_cache_manager.h @@ -42,8 +42,8 @@ #include #include "sdk_errors.h" -#include "headers/ble.h" -#include "ble_gap.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gap.h" #include "peer_manager_types.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatts_cache_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.c similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatts_cache_manager.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.c index 3f6b89c8bc1..3f4ac470606 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatts_cache_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.c @@ -41,7 +41,7 @@ #include "gatts_cache_manager.h" #include -#include "ble_gap.h" +#include "headers/nrf_ble_gap.h" #include "peer_manager_types.h" #include "peer_manager_internal.h" #include "peer_database.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatts_cache_manager.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatts_cache_manager.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.h index 628276ceab3..48c314d215f 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/gatts_cache_manager.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.h @@ -42,8 +42,8 @@ #include #include "sdk_errors.h" -#include "headers/ble.h" -#include "ble_gap.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gap.h" #include "peer_manager_types.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/id_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.c similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/id_manager.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.c index b999a852770..03cf432591d 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/id_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.c @@ -41,8 +41,8 @@ #include "id_manager.h" #include -#include "headers/ble.h" -#include "ble_gap.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gap.h" #include "ble_conn_state.h" #include "peer_manager_types.h" #include "peer_database.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/id_manager.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/id_manager.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.h index e680f410898..2268884460e 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/id_manager.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.h @@ -42,8 +42,8 @@ #include #include "sdk_errors.h" -#include "headers/ble.h" -#include "ble_gap.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gap.h" #include "peer_manager_types.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_data.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_data.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_data.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_data.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data_storage.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_data_storage.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data_storage.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_data_storage.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data_storage.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_data_storage.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data_storage.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_data_storage.h index f9b63499245..0b6343e7a4d 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_data_storage.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_data_storage.h @@ -43,7 +43,7 @@ #include #include "sdk_errors.h" -#include "ble_gap.h" +#include "headers/nrf_ble_gap.h" #include "peer_manager_types.h" #include "peer_manager_internal.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_database.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_database.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_database.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_database.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_database.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_database.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_database.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_database.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_id.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_id.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_id.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_id.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_id.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_id.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_id.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_id.h index 0c1116c8cb0..1e05ac5a9e3 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_id.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_id.h @@ -43,7 +43,7 @@ #include #include "sdk_errors.h" -#include "ble_gap.h" +#include "headers/nrf_ble_gap.h" #include "peer_manager_types.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_manager.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_manager.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_manager.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_manager.h index b5cc5af7819..ee257546748 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_manager.h @@ -62,8 +62,8 @@ #include #include #include "sdk_common.h" -#include "headers/ble.h" -#include "ble_gap.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gap.h" #include "peer_manager_types.h" #include "peer_database.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager_internal.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_manager_internal.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager_internal.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_manager_internal.h index 79551404e9c..c66bd3dd530 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager_internal.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_manager_internal.h @@ -42,8 +42,8 @@ #include #include "sdk_errors.h" -#include "headers/ble.h" -#include "ble_gap.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gap.h" #include "peer_manager_types.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_manager_types.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager_types.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_manager_types.h index 7e085b26c2d..a934e14c72c 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/peer_manager_types.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/peer_manager_types.h @@ -51,8 +51,8 @@ #include #include #include "nrf.h" -#include "ble_gap.h" -#include "ble_hci.h" +#include "headers/nrf_ble_gap.h" +#include "headers/nrf_ble_hci.h" #include "ble_gatt_db.h" #include "app_util.h" #include "app_util_platform.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/pm_buffer.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/pm_buffer.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/pm_buffer.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/pm_buffer.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/pm_buffer.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/pm_buffer.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/pm_buffer.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/pm_buffer.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/pm_mutex.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/pm_mutex.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/pm_mutex.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/pm_mutex.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/pm_mutex.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/pm_mutex.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/pm_mutex.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/pm_mutex.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_dispatcher.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/security_dispatcher.c similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_dispatcher.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/security_dispatcher.c index a87030bf340..723a6a9777c 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_dispatcher.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/security_dispatcher.c @@ -41,8 +41,8 @@ #include "security_dispatcher.h" #include -#include "headers/ble.h" -#include "ble_gap.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gap.h" #include "ble_conn_state.h" #include "peer_manager_types.h" #include "peer_database.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_dispatcher.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/security_dispatcher.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_dispatcher.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/security_dispatcher.h index 7d0b45dc46e..92f8365b64b 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_dispatcher.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/security_dispatcher.h @@ -42,8 +42,8 @@ #include #include "sdk_errors.h" -#include "headers/ble.h" -#include "ble_gap.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gap.h" #include "peer_manager_types.h" #ifdef __cplusplus diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/security_manager.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_manager.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/security_manager.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_manager.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/security_manager.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_manager.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/security_manager.h index c1043a6a3da..73cb69c1c89 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/ble/peer_manager/security_manager.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/security_manager.h @@ -42,8 +42,8 @@ #include #include "sdk_errors.h" -#include "headers/ble.h" -#include "ble_gap.h" +#include "headers/nrf_ble.h" +#include "headers/nrf_ble_gap.h" #include "peer_manager_types.h" #include "security_dispatcher.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/arduino_primo.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/arduino_primo.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/arduino_primo.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/arduino_primo.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/boards.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/boards.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/boards.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/boards.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/boards.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/boards.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/boards.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/boards.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/d52_starterkit.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/d52_starterkit.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/d52_starterkit.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/d52_starterkit.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/n5_starterkit.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/n5_starterkit.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/n5_starterkit.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/n5_starterkit.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/nrf6310.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/nrf6310.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/nrf6310.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/nrf6310.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10000.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10000.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10000.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10000.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10001.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10001.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10001.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10001.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10003.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10003.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10003.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10003.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10028.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10028.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10028.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10028.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10031.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10031.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10031.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10031.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10036.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10036.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10036.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10036.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10040.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10040.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10040.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10040.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10056.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10056.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca10056.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca10056.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca20006.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca20006.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/pca20006.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/pca20006.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/wt51822.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/wt51822.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/boards/wt51822.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/boards/wt51822.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/compiler_abstraction.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/compiler_abstraction.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/compiler_abstraction.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/compiler_abstraction.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51422_peripherals.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51422_peripherals.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51422_peripherals.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51422_peripherals.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51802_peripherals.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51802_peripherals.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51802_peripherals.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51802_peripherals.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51822_peripherals.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51822_peripherals.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51822_peripherals.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51822_peripherals.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51_bitfields.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51_bitfields.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51_bitfields.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51_bitfields.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51_deprecated.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51_deprecated.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51_deprecated.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51_deprecated.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51_to_nrf52.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51_to_nrf52.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51_to_nrf52.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51_to_nrf52.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51_to_nrf52840.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51_to_nrf52840.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf51_to_nrf52840.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf51_to_nrf52840.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52832_peripherals.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52832_peripherals.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52832_peripherals.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52832_peripherals.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52840.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52840.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52840_bitfields.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_bitfields.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52840_bitfields.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_bitfields.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52840_peripherals.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_peripherals.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52840_peripherals.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_peripherals.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52_bitfields.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_bitfields.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52_bitfields.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_bitfields.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52_name_change.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_name_change.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52_name_change.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_name_change.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52_to_nrf52840.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_to_nrf52840.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/device/nrf52_to_nrf52840.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_to_nrf52840.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/ble_flash/ble_flash.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/ble_flash/ble_flash.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/ble_flash/ble_flash.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/ble_flash/ble_flash.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/ble_flash/ble_flash.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/ble_flash/ble_flash.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/ble_flash/ble_flash.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/ble_flash/ble_flash.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/clock/nrf_drv_clock.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/clock/nrf_drv_clock.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/clock/nrf_drv_clock.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/clock/nrf_drv_clock.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/clock/nrf_drv_clock.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/clock/nrf_drv_clock.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/clock/nrf_drv_clock.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/clock/nrf_drv_clock.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/common/nrf_drv_common.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/common/nrf_drv_common.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/common/nrf_drv_common.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/common/nrf_drv_common.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/common/nrf_drv_common.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/common/nrf_drv_common.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/common/nrf_drv_common.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/common/nrf_drv_common.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/comp/nrf_drv_comp.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/comp/nrf_drv_comp.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/comp/nrf_drv_comp.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/comp/nrf_drv_comp.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/comp/nrf_drv_comp.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/comp/nrf_drv_comp.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/comp/nrf_drv_comp.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/comp/nrf_drv_comp.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/delay/nrf_delay.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/delay/nrf_delay.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/delay/nrf_delay.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/delay/nrf_delay.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/gpiote/nrf_drv_gpiote.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/gpiote/nrf_drv_gpiote.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/gpiote/nrf_drv_gpiote.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/gpiote/nrf_drv_gpiote.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_clock.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_clock.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_clock.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_clock.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_comp.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_comp.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_comp.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_comp.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_ecb.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_ecb.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_ecb.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_ecb.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_ecb.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_ecb.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_ecb.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_ecb.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_egu.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_egu.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_egu.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_egu.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_gpio.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_gpio.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_gpio.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_gpio.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_gpiote.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_gpiote.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_gpiote.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_gpiote.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_i2s.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_i2s.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_i2s.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_i2s.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_lpcomp.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_lpcomp.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_lpcomp.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_lpcomp.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_nvmc.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_nvmc.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_nvmc.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_nvmc.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_nvmc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_nvmc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_nvmc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_nvmc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_pdm.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_pdm.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_pdm.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_pdm.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_peripherals.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_peripherals.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_peripherals.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_peripherals.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_power.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_power.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_power.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_power.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_ppi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_ppi.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_ppi.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_ppi.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_pwm.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_pwm.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_pwm.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_pwm.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_qdec.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_qdec.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_qdec.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_qdec.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_rng.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_rng.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_rng.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_rng.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_rtc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_rtc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_rtc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_rtc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_saadc.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_saadc.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_saadc.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_saadc.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_saadc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_saadc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_saadc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_saadc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_spi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_spi.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_spi.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_spi.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_spim.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_spim.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_spim.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_spim.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_spis.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_spis.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_spis.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_spis.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_temp.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_temp.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_temp.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_temp.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_timer.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_timer.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_timer.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_timer.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_twi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_twi.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_twi.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_twi.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_twim.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_twim.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_twim.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_twim.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_twis.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_twis.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_twis.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_twis.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_uart.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_uart.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_uart.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_uart.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_uarte.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_uarte.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_uarte.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_uarte.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_wdt.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_wdt.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/hal/nrf_wdt.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/hal/nrf_wdt.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/i2s/nrf_drv_i2s.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/i2s/nrf_drv_i2s.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/i2s/nrf_drv_i2s.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/i2s/nrf_drv_i2s.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/i2s/nrf_drv_i2s.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/i2s/nrf_drv_i2s.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/i2s/nrf_drv_i2s.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/i2s/nrf_drv_i2s.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/lpcomp/nrf_drv_lpcomp.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/lpcomp/nrf_drv_lpcomp.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/lpcomp/nrf_drv_lpcomp.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/lpcomp/nrf_drv_lpcomp.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/lpcomp/nrf_drv_lpcomp.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/lpcomp/nrf_drv_lpcomp.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/lpcomp/nrf_drv_lpcomp.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/lpcomp/nrf_drv_lpcomp.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/pdm/nrf_drv_pdm.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/pdm/nrf_drv_pdm.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/pdm/nrf_drv_pdm.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/pdm/nrf_drv_pdm.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/pdm/nrf_drv_pdm.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/pdm/nrf_drv_pdm.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/pdm/nrf_drv_pdm.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/pdm/nrf_drv_pdm.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/power/nrf_drv_power.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/power/nrf_drv_power.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/power/nrf_drv_power.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/power/nrf_drv_power.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/power/nrf_drv_power.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/power/nrf_drv_power.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/power/nrf_drv_power.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/power/nrf_drv_power.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/ppi/nrf_drv_ppi.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/ppi/nrf_drv_ppi.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/ppi/nrf_drv_ppi.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/ppi/nrf_drv_ppi.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/ppi/nrf_drv_ppi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/ppi/nrf_drv_ppi.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/ppi/nrf_drv_ppi.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/ppi/nrf_drv_ppi.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/pwm/nrf_drv_pwm.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/pwm/nrf_drv_pwm.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/pwm/nrf_drv_pwm.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/pwm/nrf_drv_pwm.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/pwm/nrf_drv_pwm.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/pwm/nrf_drv_pwm.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/pwm/nrf_drv_pwm.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/pwm/nrf_drv_pwm.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/qdec/nrf_drv_qdec.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/qdec/nrf_drv_qdec.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/qdec/nrf_drv_qdec.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/qdec/nrf_drv_qdec.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/qdec/nrf_drv_qdec.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/qdec/nrf_drv_qdec.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/qdec/nrf_drv_qdec.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/qdec/nrf_drv_qdec.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/radio_config/radio_config.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/radio_config/radio_config.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/radio_config/radio_config.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/radio_config/radio_config.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/radio_config/radio_config.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/radio_config/radio_config.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/radio_config/radio_config.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/radio_config/radio_config.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/rng/nrf_drv_rng.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/rng/nrf_drv_rng.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/rng/nrf_drv_rng.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/rng/nrf_drv_rng.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/rng/nrf_drv_rng.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/rng/nrf_drv_rng.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/rng/nrf_drv_rng.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/rng/nrf_drv_rng.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/rtc/nrf_drv_rtc.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/rtc/nrf_drv_rtc.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/rtc/nrf_drv_rtc.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/rtc/nrf_drv_rtc.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/rtc/nrf_drv_rtc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/rtc/nrf_drv_rtc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/rtc/nrf_drv_rtc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/rtc/nrf_drv_rtc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/saadc/nrf_drv_saadc.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/saadc/nrf_drv_saadc.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/saadc/nrf_drv_saadc.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/saadc/nrf_drv_saadc.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/saadc/nrf_drv_saadc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/saadc/nrf_drv_saadc.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/saadc/nrf_drv_saadc.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/saadc/nrf_drv_saadc.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/sdio/config/sdio_config.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/sdio/config/sdio_config.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/sdio/config/sdio_config.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/sdio/config/sdio_config.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/sdio/sdio.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/sdio/sdio.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/sdio/sdio.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/sdio/sdio.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/sdio/sdio.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/sdio/sdio.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/sdio/sdio.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/sdio/sdio.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/spi_master/nrf_drv_spi.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/spi_master/nrf_drv_spi.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/spi_master/nrf_drv_spi.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/spi_master/nrf_drv_spi.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/spi_master/nrf_drv_spi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/spi_master/nrf_drv_spi.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/spi_master/nrf_drv_spi.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/spi_master/nrf_drv_spi.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/spi_slave/nrf_drv_spis.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/spi_slave/nrf_drv_spis.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/spi_slave/nrf_drv_spis.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/spi_slave/nrf_drv_spis.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/spi_slave/nrf_drv_spis.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/spi_slave/nrf_drv_spis.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/spi_slave/nrf_drv_spis.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/spi_slave/nrf_drv_spis.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/timer/nrf_drv_timer.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/timer/nrf_drv_timer.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/timer/nrf_drv_timer.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/timer/nrf_drv_timer.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/timer/nrf_drv_timer.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/timer/nrf_drv_timer.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/timer/nrf_drv_timer.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/timer/nrf_drv_timer.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twi_master/nrf_drv_twi.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/twi_master/nrf_drv_twi.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twi_master/nrf_drv_twi.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/twi_master/nrf_drv_twi.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twi_master/nrf_drv_twi.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/twi_master/nrf_drv_twi.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twi_master/nrf_drv_twi.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/twi_master/nrf_drv_twi.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twis_slave/nrf_drv_twis.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/twis_slave/nrf_drv_twis.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twis_slave/nrf_drv_twis.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/twis_slave/nrf_drv_twis.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twis_slave/nrf_drv_twis.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/twis_slave/nrf_drv_twis.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twis_slave/nrf_drv_twis.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/twis_slave/nrf_drv_twis.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twis_slave/nrf_drv_twis_inst.def b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/twis_slave/nrf_drv_twis_inst.def similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/twis_slave/nrf_drv_twis_inst.def rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/twis_slave/nrf_drv_twis_inst.def diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/wdt/nrf_drv_wdt.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/wdt/nrf_drv_wdt.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/wdt/nrf_drv_wdt.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/wdt/nrf_drv_wdt.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/wdt/nrf_drv_wdt.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/wdt/nrf_drv_wdt.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/drivers_nrf/wdt/nrf_drv_wdt.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/drivers_nrf/wdt/nrf_drv_wdt.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_flash.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/bootloader/dfu/nrf_dfu_flash.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_flash.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/bootloader/dfu/nrf_dfu_flash.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_flash.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/bootloader/dfu/nrf_dfu_flash.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_flash.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/bootloader/dfu/nrf_dfu_flash.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_req_handler.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/bootloader/dfu/nrf_dfu_req_handler.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_req_handler.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/bootloader/dfu/nrf_dfu_req_handler.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_transport.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/bootloader/dfu/nrf_dfu_transport.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_transport.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/bootloader/dfu/nrf_dfu_transport.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_transport.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/bootloader/dfu/nrf_dfu_transport.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_transport.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/bootloader/dfu/nrf_dfu_transport.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/bootloader/dfu/nrf_dfu_types.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/bootloader/dfu/nrf_dfu_types.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/bootloader/dfu/nrf_dfu_types.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/crc16/crc16.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/crc16/crc16.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/crc16/crc16.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/crc16/crc16.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/crc16/crc16.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/crc16/crc16.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/crc16/crc16.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/crc16/crc16.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/crc32/crc32.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/crc32/crc32.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/crc32/crc32.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/crc32/crc32.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/crc32/crc32.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/crc32/crc32.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/crc32/crc32.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/crc32/crc32.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/experimental_section_vars/section_vars.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/experimental_section_vars/section_vars.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/experimental_section_vars/section_vars.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/experimental_section_vars/section_vars.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fds/fds.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fds/fds.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fds/fds.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fds/fds.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fds/fds.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fds/fds.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fds/fds.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fds/fds.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fds/fds_internal_defs.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fds/fds_internal_defs.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fds/fds_internal_defs.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fds/fds_internal_defs.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fstorage/fstorage.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fstorage/fstorage.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fstorage/fstorage.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fstorage/fstorage.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fstorage/fstorage.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fstorage/fstorage.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fstorage/fstorage.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fstorage/fstorage.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fstorage/fstorage_internal_defs.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fstorage/fstorage_internal_defs.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fstorage/fstorage_internal_defs.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fstorage/fstorage_internal_defs.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fstorage/fstorage_nosd.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fstorage/fstorage_nosd.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/fstorage/fstorage_nosd.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/fstorage/fstorage_nosd.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/hci/hci_mem_pool.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/hci/hci_mem_pool.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/hci/hci_mem_pool.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/hci/hci_mem_pool.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/hci/hci_mem_pool.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/hci/hci_mem_pool.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/hci/hci_mem_pool.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/hci/hci_mem_pool.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/nrf_log.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/nrf_log.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/nrf_log.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/nrf_log.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/nrf_log_backend.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/nrf_log_backend.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/nrf_log_backend.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/nrf_log_backend.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/nrf_log_ctrl.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/nrf_log_ctrl.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/nrf_log_ctrl.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/nrf_log_ctrl.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/src/nrf_log_backend_serial.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/src/nrf_log_backend_serial.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/src/nrf_log_backend_serial.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/src/nrf_log_backend_serial.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/src/nrf_log_ctrl_internal.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/src/nrf_log_ctrl_internal.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/src/nrf_log_ctrl_internal.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/src/nrf_log_ctrl_internal.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/src/nrf_log_frontend.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/src/nrf_log_frontend.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/src/nrf_log_frontend.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/src/nrf_log_frontend.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/src/nrf_log_internal.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/src/nrf_log_internal.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/log/src/nrf_log_internal.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/log/src/nrf_log_internal.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/pwm/app_pwm.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/pwm/app_pwm.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/pwm/app_pwm.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/pwm/app_pwm.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/pwm/app_pwm.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/pwm/app_pwm.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/pwm/app_pwm.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/pwm/app_pwm.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/queue/nrf_queue.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/queue/nrf_queue.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/queue/nrf_queue.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/queue/nrf_queue.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/queue/nrf_queue.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/queue/nrf_queue.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/queue/nrf_queue.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/queue/nrf_queue.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/scheduler/app_scheduler.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/scheduler/app_scheduler.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/scheduler/app_scheduler.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/scheduler/app_scheduler.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/scheduler/app_scheduler.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/scheduler/app_scheduler.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/scheduler/app_scheduler.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/scheduler/app_scheduler.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_error.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_error.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_error.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_error.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_error.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_error.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_error.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_error.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_error_weak.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_error_weak.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_error_weak.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_error_weak.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_error_weak.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_error_weak.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_error_weak.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_error_weak.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_util.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_util.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_util.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_util.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_util_bds.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_util_bds.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_util_bds.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_util_bds.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_util_platform.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_util_platform.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_util_platform.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_util_platform.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_util_platform.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_util_platform.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/app_util_platform.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/app_util_platform.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/nordic_common.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/nordic_common.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/nordic_common.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/nordic_common.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/nrf_assert.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/nrf_assert.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/nrf_assert.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/nrf_assert.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/nrf_assert.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/nrf_assert.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/nrf_assert.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/nrf_assert.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/nrf_bitmask.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/nrf_bitmask.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/nrf_bitmask.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/nrf_bitmask.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_common.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_common.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_common.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_common.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_errors.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_errors.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_errors.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_errors.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_macros.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_macros.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_macros.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_macros.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_mapped_flags.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_mapped_flags.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_mapped_flags.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_mapped_flags.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_mapped_flags.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_mapped_flags.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_mapped_flags.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_mapped_flags.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_os.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_os.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_os.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_os.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_resources.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_resources.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/libraries/util/sdk_resources.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/libraries/util/sdk_resources.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/sdk_validation.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/sdk_validation.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/sdk_validation.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/sdk_validation.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/ant_stack_handler_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/ant_stack_handler_types.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/ant_stack_handler_types.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/ant_stack_handler_types.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/app_ram_base.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/app_ram_base.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/app_ram_base.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/app_ram_base.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/ble_stack_handler_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/ble_stack_handler_types.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/ble_stack_handler_types.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/ble_stack_handler_types.h index 7be7850f581..30da33c7569 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/ble_stack_handler_types.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/ble_stack_handler_types.h @@ -55,7 +55,7 @@ extern "C" { #ifdef BLE_STACK_SUPPORT_REQD #include -#include "headers/ble.h" +#include "headers/nrf_ble.h" #include "nrf_sdm.h" #include "app_error.h" #include "app_util.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/softdevice_handler.c similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/softdevice_handler.c index 34e534e9f65..868532b4851 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/softdevice_handler.c @@ -62,7 +62,7 @@ #elif defined(ANT_STACK_SUPPORT_REQD) #include "ant_interface.h" #elif defined(BLE_STACK_SUPPORT_REQD) - #include "headers/ble.h" + #include "headers/nrf_ble.h" #endif #define RAM_START_ADDRESS 0x20000000 diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/softdevice_handler.h similarity index 99% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/softdevice_handler.h index 59bc60f3d5a..64d4465be03 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/softdevice_handler.h @@ -66,7 +66,7 @@ #include "ble_stack_handler_types.h" #include "ant_stack_handler_types.h" #if defined(BLE_STACK_SUPPORT_REQD) - #include "headers/ble.h" + #include "headers/nrf_ble.h" #endif #include "app_ram_base.h" diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/softdevice_handler_appsh.c similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.c rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/softdevice_handler_appsh.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/softdevice_handler_appsh.h similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.h rename to targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/softdevice/common/softdevice_handler/softdevice_handler_appsh.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c index a5c6c850c21..ec73afa6a3f 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c @@ -22,8 +22,12 @@ #if defined(TARGET_MCU_NRF51822) #define GPIO_PIN_COUNT 31 -#else +#elif defined(TARGET_MCU_NRF52832) #define GPIO_PIN_COUNT 32 +#elif defined(TARGET_MCU_NRF52840) + #define GPIO_PIN_COUNT 48 +#else + #error not recognized gpio count for mcu #endif typedef struct { @@ -36,8 +40,14 @@ typedef struct { bool irq_rise : 1; } gpio_cfg_t; -uint32_t m_gpio_initialized; -gpio_cfg_t m_gpio_cfg[GPIO_PIN_COUNT]; +#if GPIO_PIN_COUNT > 32 + typedef uint64_t gpio_mask_t; +#else + typedef uint32_t gpio_mask_t; +#endif + +static gpio_mask_t m_gpio_initialized; +static gpio_cfg_t m_gpio_cfg[GPIO_PIN_COUNT]; /*********** @@ -46,7 +56,7 @@ gpio_cfg_t m_gpio_cfg[GPIO_PIN_COUNT]; static gpio_irq_handler m_irq_handler; static uint32_t m_channel_ids[GPIO_PIN_COUNT] = {0}; -uint32_t m_gpio_irq_enabled; +static gpio_mask_t m_gpio_irq_enabled; static void gpiote_irq_handler(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t action) @@ -54,7 +64,7 @@ static void gpiote_irq_handler(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t a nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin); gpio_irq_event event = (sense == NRF_GPIO_PIN_SENSE_LOW) ? IRQ_RISE : IRQ_FALL; - if (m_gpio_irq_enabled & (1UL << pin)) { + if (m_gpio_irq_enabled & ((gpio_mask_t)1 << pin)) { if (((event == IRQ_RISE) && m_gpio_cfg[pin].irq_rise) || ((event == IRQ_FALL) && m_gpio_cfg[pin].irq_fall)) { m_irq_handler(m_channel_ids[pin], event); @@ -79,12 +89,19 @@ void gpio_init(gpio_t *obj, PinName pin) m_gpio_cfg[obj->pin].used_as_gpio = true; } +#ifdef TARGET_SDK11 +// implement polyfill of gpio hal for the nRF5 SDK v11 +__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin) +{ + return (NRF_GPIO->OUTSET & (1UL << (pin))); +} +#endif int gpio_read(gpio_t *obj) { MBED_ASSERT(obj->pin != (PinName)NC); if (m_gpio_cfg[obj->pin].direction == PIN_OUTPUT) { - return ((NRF_GPIO->OUTSET & (1UL << obj->pin)) ? 1 : 0); + return (nrf_gpio_pin_out_read(obj->pin) ? 1 : 0); } else { return nrf_gpio_pin_read(obj->pin); } @@ -92,7 +109,7 @@ int gpio_read(gpio_t *obj) static void gpiote_pin_uninit(uint8_t pin) { - if (m_gpio_initialized & (1UL << pin)) { + if (m_gpio_initialized & ((gpio_mask_t)1UL << pin)) { if ((m_gpio_cfg[pin].direction == PIN_OUTPUT) && (!m_gpio_cfg[pin].used_as_irq)) { nrf_drv_gpiote_out_uninit(pin); } @@ -116,7 +133,7 @@ static void gpio_apply_config(uint8_t pin) if (m_gpio_cfg[pin].used_as_irq) { cfg.pull = NRF_GPIO_PIN_PULLUP; nrf_drv_gpiote_in_init(pin, &cfg, gpiote_irq_handler); - if ((m_gpio_irq_enabled & (1 << pin)) + if ((m_gpio_irq_enabled & ((gpio_mask_t)1 << pin)) && (m_gpio_cfg[pin].irq_rise || m_gpio_cfg[pin].irq_fall)) { nrf_drv_gpiote_in_event_enable(pin, true); @@ -142,17 +159,17 @@ static void gpio_apply_config(uint8_t pin) nrf_drv_gpiote_out_config_t cfg = GPIOTE_CONFIG_OUT_SIMPLE(m_gpio_cfg[pin].init_high); nrf_drv_gpiote_out_init(pin, &cfg); } - m_gpio_initialized |= (1UL << pin); + m_gpio_initialized |= ((gpio_mask_t)1UL << pin); } else { - m_gpio_initialized &= ~(1UL << pin); + m_gpio_initialized &= ~((gpio_mask_t)1UL << pin); } } void gpio_mode(gpio_t *obj, PinMode mode) { - MBED_ASSERT(obj->pin <= GPIO_PIN_COUNT); + MBED_ASSERT(obj->pin != (PinName)NC); gpiote_pin_uninit(obj->pin); // try to uninitialize gpio before a change. @@ -163,7 +180,7 @@ void gpio_mode(gpio_t *obj, PinMode mode) void gpio_dir(gpio_t *obj, PinDirection direction) { - MBED_ASSERT(obj->pin <= GPIO_PIN_COUNT); + MBED_ASSERT(obj->pin != (PinName)NC); gpiote_pin_uninit(obj->pin); // try to uninitialize gpio before a change. @@ -211,7 +228,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { gpio_cfg_t* cfg = &m_gpio_cfg[obj->ch]; bool irq_enabled_before = - (m_gpio_irq_enabled & (1 << obj->ch)) && + (m_gpio_irq_enabled & ((gpio_mask_t)1 << obj->ch)) && (cfg->irq_rise || cfg->irq_fall); if (event == IRQ_RISE) { @@ -235,7 +252,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) void gpio_irq_enable(gpio_irq_t *obj) { - m_gpio_irq_enabled |= (1 << obj->ch); + m_gpio_irq_enabled |= ((gpio_mask_t)1 << obj->ch); if (m_gpio_cfg[obj->ch].irq_rise || m_gpio_cfg[obj->ch].irq_fall) { nrf_drv_gpiote_in_event_enable(obj->ch, true); } @@ -244,6 +261,6 @@ void gpio_irq_enable(gpio_irq_t *obj) void gpio_irq_disable(gpio_irq_t *obj) { - m_gpio_irq_enabled &= ~(1 << obj->ch); + m_gpio_irq_enabled &= ~((gpio_mask_t)1 << obj->ch); nrf_drv_gpiote_in_event_disable(obj->ch); } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c index 66063b4c499..723a406dd23 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c @@ -45,7 +45,7 @@ #include "mbed_error.h" #include "nrf_twi.h" #include "nrf_drv_common.h" -#include "nrf_drv_config.h" +#include "sdk_config.h" #include "app_util_platform.h" #include "nrf_gpio.h" #include "nrf_delay.h" @@ -62,6 +62,11 @@ #endif #define TWI_INFO(obj) (&m_twi_info[TWI_IDX(obj)]) +#ifdef TARGET_SDK13 + #define TWI0_INSTANCE_INDEX 0 + #define TWI1_INSTANCE_INDEX TWI0_INSTANCE_INDEX+TWI0_ENABLED +#endif + typedef struct { bool initialized; uint32_t pselsda; @@ -98,22 +103,22 @@ void SPI1_TWI1_IRQHandler(void); static const peripheral_handler_desc_t twi_handlers[TWI_COUNT] = { - #if TWI0_ENABLED +#if TWI0_ENABLED { SPI0_TWI0_IRQn, (uint32_t) SPI0_TWI0_IRQHandler }, - #endif - #if TWI1_ENABLED +#endif +#if TWI1_ENABLED { SPI1_TWI1_IRQn, (uint32_t) SPI1_TWI1_IRQHandler } - #endif +#endif }; #ifdef NRF51 #define TWI_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#elif defined(NRF52) +#elif defined(NRF52) || defined(NRF52840_XXAA) #define TWI_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST #endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/objects.h b/targets/TARGET_NORDIC/TARGET_NRF5/objects.h index 209134b7d15..4ae7530509f 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/objects.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/objects.h @@ -57,9 +57,6 @@ struct spi_s { }; struct port_s { - __IO uint32_t *reg_cnf; - __IO uint32_t *reg_out; - __I uint32_t *reg_in; PortName port; uint32_t mask; }; diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/pinmap.c b/targets/TARGET_NORDIC/TARGET_NRF5/pinmap.c index 989fbf209bc..f723a5837e1 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/pinmap.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/pinmap.c @@ -16,6 +16,7 @@ #include "mbed_assert.h" #include "mbed_error.h" #include "pinmap.h" +#include "nrf_gpio.h" void pin_function(PinName pin, int function) { @@ -29,7 +30,12 @@ void pin_mode(PinName pin, PinMode mode) MBED_ASSERT(pin != (PinName)NC); uint32_t pin_number = (uint32_t)pin; - - NRF_GPIO->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_PULL_Msk; - NRF_GPIO->PIN_CNF[pin_number] |= (mode << GPIO_PIN_CNF_PULL_Pos); + +#ifdef TARGET_SDK11 + NRF_GPIO_Type * reg = NRF_GPIO; +#else + NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); +#endif + reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_PULL_Msk; + reg->PIN_CNF[pin_number] |= (mode << GPIO_PIN_CNF_PULL_Pos); } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/port_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/port_api.c index ad3be048166..e8c57184a5a 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/port_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/port_api.c @@ -38,23 +38,42 @@ #include "port_api.h" #include "pinmap.h" -#include "gpio_api.h" + +#if defined(TARGET_MCU_NRF51822) || defined(TARGET_MCU_NRF52832) + #define GPIO_REG_LIST {NRF_GPIO} +#endif + +static NRF_GPIO_Type * const m_ports[] = GPIO_REG_LIST; + +#if defined(TARGET_MCU_NRF51822) + static const uint32_t m_gpio_pin_count[] = {31}; +#elif defined(TARGET_MCU_NRF52832) + static const uint32_t m_gpio_pin_count[] = {32}; +#elif defined(TARGET_MCU_NRF52840) + static const uint32_t m_gpio_pin_count[] = {32, 16}; +#else + #error not recognized gpio count for mcu +#endif + +#define GPIO_PORT_COUNT (sizeof(m_gpio_pin_count)/sizeof(m_gpio_pin_count[0])) + PinName port_pin(PortName port, int pin_n) { - (void) port; - return (PinName)(pin_n); +#if defined(TARGET_MCU_NRF51822) || defined(TARGET_MCU_NRF52832) + return (PinName)pin_n; +#else + return (PinName)NRF_GPIO_PIN_MAP(port, pin_n); +#endif } void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { + MBED_ASSERT((uint32_t)port < GPIO_PORT_COUNT); + obj->port = port; obj->mask = mask; - obj->reg_out = &NRF_GPIO->OUT; - obj->reg_in = &NRF_GPIO->IN; - obj->reg_cnf = NRF_GPIO->PIN_CNF; - port_dir(obj, dir); } @@ -71,38 +90,45 @@ void port_mode(port_t *obj, PinMode mode) void port_dir(port_t *obj, PinDirection dir) { - int i; + uint32_t i; + + volatile uint32_t *reg_cnf = (volatile uint32_t*) m_ports[obj->port]->PIN_CNF; + switch (dir) { - case PIN_INPUT: - for (i = 0; i<31; i++) { - if (obj->mask & (1 << i)) { - obj->reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); + case PIN_INPUT: + + for (i = 0; i < m_gpio_pin_count[obj->port]; i++) { + if (obj->mask & (1 << i)) { + reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); + } } - } - break; - case PIN_OUTPUT: - for (i = 0; i<31; i++) { - if (obj->mask & (1 << i)) { - obj->reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + break; + + case PIN_OUTPUT: + + for (i = 0; i < m_gpio_pin_count[obj->port]; i++) { + if (obj->mask & (1 << i)) { + reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) + | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); + } } - } - break; + break; } } void port_write(port_t *obj, int value) { - *obj->reg_out = value; + m_ports[obj->port]->OUTSET = value & obj->mask; + m_ports[obj->port]->OUTCLR = (~value) & obj->mask; } int port_read(port_t *obj) { - return (*obj->reg_in); + return ((m_ports[obj->port]->IN) & obj->mask); } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/porting_tools/copyright_header.txt b/targets/TARGET_NORDIC/TARGET_NRF5/porting_tools/copyright_header.txt similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/porting_tools/copyright_header.txt rename to targets/TARGET_NORDIC/TARGET_NRF5/porting_tools/copyright_header.txt diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/porting_tools/replace_headers.py b/targets/TARGET_NORDIC/TARGET_NRF5/porting_tools/replace_headers.py similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/porting_tools/replace_headers.py rename to targets/TARGET_NORDIC/TARGET_NRF5/porting_tools/replace_headers.py diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/porting_tools/sdk_update.py b/targets/TARGET_NORDIC/TARGET_NRF5/porting_tools/sdk_update.py similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/porting_tools/sdk_update.py rename to targets/TARGET_NORDIC/TARGET_NRF5/porting_tools/sdk_update.py diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/porting_tools/update_desc.json b/targets/TARGET_NORDIC/TARGET_NRF5/porting_tools/update_desc.json similarity index 100% rename from targets/TARGET_NORDIC/TARGET_NRF5_SDK13/porting_tools/update_desc.json rename to targets/TARGET_NORDIC/TARGET_NRF5/porting_tools/update_desc.json diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c index 13ab6d3bb51..0835c517652 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c @@ -45,9 +45,9 @@ #include "mbed_error.h" #include "nrf_uart.h" #include "nrf_drv_common.h" -#include "nrf_drv_config.h" #include "app_util_platform.h" #include "nrf_gpio.h" +#include "sdk_config.h" #define UART_INSTANCE_COUNT 1 #define UART_INSTANCE NRF_UART0 @@ -56,8 +56,8 @@ #define UART_INSTANCE_ID 0 #define UART_CB uart_cb[UART_INSTANCE_ID] -#define UART_DEFAULT_BAUDRATE UART0_CONFIG_BAUDRATE -#define UART_DEFAULT_PARITY UART0_CONFIG_PARITY +#define UART_DEFAULT_BAUDRATE UART_DEFAULT_CONFIG_BAUDRATE +#define UART_DEFAULT_PARITY UART_DEFAULT_CONFIG_PARITY // expected the macro from mbed configuration system #ifndef MBED_CONF_NORDIC_UART_HWFC @@ -66,17 +66,17 @@ #endif #if MBED_CONF_NORDIC_UART_HWFC == 1 - #define UART_DEFAULT_HWFC UART0_CONFIG_HWFC + #define UART_DEFAULT_HWFC UART_DEFAULT_CONFIG_HWFC #else #define UART_DEFAULT_HWFC NRF_UART_HWFC_DISABLED #endif -#define UART_DEFAULT_CTS UART0_CONFIG_PSEL_CTS -#define UART_DEFAULT_RTS UART0_CONFIG_PSEL_RTS +#define UART_DEFAULT_CTS CTS_PIN_NUMBER +#define UART_DEFAULT_RTS RTS_PIN_NUMBER #ifdef NRF51 #define NRFx_MBED_UART_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#elif defined(NRF52) +#elif defined(NRF52) || defined(NRF52840_XXAA) #define NRFx_MBED_UART_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST #endif @@ -556,7 +556,7 @@ static void internal_set_hwfc(FlowControl type, nrf_gpio_cfg_input(UART_CB.pselcts, NRF_GPIO_PIN_NOPULL); } - UART_CB.hwfc = (type == FlowControlNone)? NRF_UART_HWFC_DISABLED : UART0_CONFIG_HWFC; + UART_CB.hwfc = (nrf_uart_hwfc_t)((type == FlowControlNone)? NRF_UART_HWFC_DISABLED : UART_DEFAULT_CONFIG_HWFC); nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc); nrf_uart_hwfc_pins_set(UART_INSTANCE, UART_CB.pselrts, UART_CB.pselcts); diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c b/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c index 29020dc934a..f806e7a0a65 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c @@ -33,7 +33,7 @@ void hal_sleep(void) // the processor from disabled interrupts. SCB->SCR |= SCB_SCR_SEVONPEND_Msk; -#ifdef NRF52 +#if defined(NRF52) || defined(NRF52840_XXAA) /* Clear exceptions and PendingIRQ from the FPU unit */ __set_FPSCR(__get_FPSCR() & ~(FPU_EXCEPTION_MASK)); (void) __get_FPSCR(); @@ -41,7 +41,7 @@ void hal_sleep(void) #endif // If the SoftDevice is enabled, its API must be used to go to sleep. - if (softdevice_handler_isEnabled()) { + if (softdevice_handler_is_enabled()) { sd_power_mode_set(NRF_POWER_MODE_LOWPWR); sd_app_evt_wait(); } else { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/spi_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/spi_api.c index 2c07af5e8b5..79b73d89fe3 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/spi_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/spi_api.c @@ -48,6 +48,7 @@ #include "nrf_drv_spi.h" #include "nrf_drv_spis.h" #include "app_util_platform.h" +#include "sdk_config.h" #if DEVICE_SPI_ASYNCH #define SPI_IDX(obj) ((obj)->spi.spi_idx) @@ -186,7 +187,7 @@ static void slave_event_handler(uint8_t spi_idx, // And prepare for the next transfer. // Previous data set in 'spi_slave_write' (if any) has been transmitted, // now use the default one, until some new is set by 'spi_slave_write'. - p_spi_info->tx_buf = NRF_DRV_SPIS_DEFAULT_ORC; + p_spi_info->tx_buf = SPIS_DEFAULT_ORC; nrf_drv_spis_buffers_set(&m_instances[spi_idx].slave, (uint8_t const *)&p_spi_info->tx_buf, 1, (uint8_t *)&p_spi_info->rx_buf, 1); @@ -228,7 +229,7 @@ static void prepare_master_config(nrf_drv_spi_config_t *p_config, p_config->frequency = p_spi_info->frequency; p_config->mode = (nrf_drv_spi_mode_t)p_spi_info->spi_mode; - p_config->irq_priority = SPI1_CONFIG_IRQ_PRIORITY; + p_config->irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY; p_config->orc = 0xFF; p_config->bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST; } @@ -242,9 +243,9 @@ static void prepare_slave_config(nrf_drv_spis_config_t *p_config, p_config->csn_pin = p_spi_info->ss_pin; p_config->mode = (nrf_drv_spis_mode_t)p_spi_info->spi_mode; - p_config->irq_priority = SPIS1_CONFIG_IRQ_PRIORITY; - p_config->orc = NRF_DRV_SPIS_DEFAULT_ORC; - p_config->def = NRF_DRV_SPIS_DEFAULT_DEF; + p_config->irq_priority = SPIS_DEFAULT_CONFIG_IRQ_PRIORITY; + p_config->orc = SPIS_DEFAULT_ORC; + p_config->def = SPIS_DEFAULT_DEF; p_config->bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST; p_config->csn_pullup = NRF_DRV_SPIS_DEFAULT_CSN_PULLUP; p_config->miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE; @@ -379,7 +380,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) m_slave_event_handlers[SPI_IDX(obj)]); // Prepare the slave for transfer. - p_spi_info->tx_buf = NRF_DRV_SPIS_DEFAULT_ORC; + p_spi_info->tx_buf = SPIS_DEFAULT_ORC; nrf_drv_spis_buffers_set(SLAVE_INST(obj), (uint8_t const *)&p_spi_info->tx_buf, 1, (uint8_t *)&p_spi_info->rx_buf, 1); diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c b/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c index 84bf8022a3a..bde1be74734 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c @@ -40,10 +40,12 @@ #include "common_rtc.h" #include "app_util.h" #include "nrf_drv_common.h" -#include "nrf_drv_config.h" #include "lp_ticker_api.h" #include "mbed_critical.h" +#if defined(NRF52_ERRATA_20) + #include "softdevice_handler.h" +#endif //------------------------------------------------------------------------------ // Common stuff used also by lp_ticker and rtc_api (see "common_rtc.h"). @@ -82,7 +84,23 @@ void COMMON_RTC_IRQ_HANDLER(void) lp_ticker_irq_handler(); } #endif +} +// Function for fix errata 20: RTC Register values are invalid +__STATIC_INLINE void errata_20(void) +{ +#if defined(NRF52_ERRATA_20) + if (!softdevice_handler_is_enabled()) + { + NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; + NRF_CLOCK->TASKS_LFCLKSTART = 1; + + while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) + { + } + } + NRF_RTC1->TASKS_STOP = 0; +#endif } #if (defined (__ICCARM__)) && defined(TARGET_MCU_NRF51822)//IAR @@ -96,6 +114,8 @@ void common_rtc_init(void) return; } + errata_20(); + NVIC_SetVector(RTC1_IRQn, (uint32_t)RTC1_IRQHandler); // RTC is driven by the low frequency (32.768 kHz) clock, a proper request @@ -118,9 +138,9 @@ void common_rtc_init(void) // events will be enabled or disabled as needed (such approach is more // energy efficient). nrf_rtc_int_enable(COMMON_RTC_INSTANCE, - #if DEVICE_LOWPOWERTIMER +#if DEVICE_LOWPOWERTIMER LP_TICKER_INT_MASK | - #endif +#endif US_TICKER_INT_MASK | NRF_RTC_INT_OVERFLOW_MASK); @@ -129,18 +149,18 @@ void common_rtc_init(void) nrf_rtc_event_enable(COMMON_RTC_INSTANCE, NRF_RTC_INT_OVERFLOW_MASK); // All other relevant events are initially disabled. nrf_rtc_event_disable(COMMON_RTC_INSTANCE, - #if defined(TARGET_MCU_NRF51822) +#if defined(TARGET_MCU_NRF51822) OS_TICK_INT_MASK | - #endif - #if DEVICE_LOWPOWERTIMER +#endif +#if DEVICE_LOWPOWERTIMER LP_TICKER_INT_MASK | - #endif +#endif US_TICKER_INT_MASK); nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE), #ifdef NRF51 APP_IRQ_PRIORITY_LOW -#elif defined(NRF52) +#elif defined(NRF52) || defined(NRF52840_XXAA) APP_IRQ_PRIORITY_LOWEST #endif ); @@ -291,7 +311,9 @@ static uint32_t previous_tick_cc_value = 0; */ MBED_WEAK uint32_t const os_trv; MBED_WEAK uint32_t const os_clockrate; -MBED_WEAK void OS_Tick_Handler() { } +MBED_WEAK void OS_Tick_Handler(void) +{ +} #if defined (__CC_ARM) /* ARMCC Compiler */ @@ -432,7 +454,8 @@ __stackless __task void COMMON_RTC_IRQ_HANDLER(void) * Return the next number of clock cycle needed for the next tick. * @note This function has been carrefuly optimized for a systick occuring every 1000us. */ -static uint32_t get_next_tick_cc_delta() { +static uint32_t get_next_tick_cc_delta() +{ uint32_t delta = 0; if (os_clockrate != 1000) { @@ -468,7 +491,8 @@ static uint32_t get_next_tick_cc_delta() { return delta; } -static inline void clear_tick_interrupt() { +static inline void clear_tick_interrupt() +{ nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT); nrf_rtc_event_disable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK); } @@ -480,7 +504,8 @@ static inline void clear_tick_interrupt() { * @param val value to check * @return true if the value is included in the range and false otherwise. */ -static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val) { +static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val) +{ // regular case, begin < end // return true if begin <= val < end if (begin < end) { @@ -504,7 +529,8 @@ static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t va /** * Register the next tick. */ -static void register_next_tick() { +static void register_next_tick() +{ previous_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL); uint32_t delta = get_next_tick_cc_delta(); uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL; @@ -563,8 +589,9 @@ void os_tick_irqack(void) * @note This function is exposed by RTX kernel. * @return 1 if the timer has overflowed and 0 otherwise. */ -uint32_t os_tick_ovf(void) { - uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); +uint32_t os_tick_ovf(void) +{ + uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL); return is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter) ? 0 : 1; @@ -579,8 +606,9 @@ uint32_t os_tick_ovf(void) { * descending order, even if the internal counter used is an ascending one. * @return the value of the alternative hardware timer. */ -uint32_t os_tick_val(void) { - uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); +uint32_t os_tick_val(void) +{ + uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL); // do not use os_tick_ovf because its counter value can be different diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/LF_Clock_config.md b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/LF_Clock_config.md deleted file mode 100644 index 22852ae261a..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/LF_Clock_config.md +++ /dev/null @@ -1,97 +0,0 @@ - -# LF Clock configuration using mbed configuration system - -In order to provide the configuration for a low frequency (LF) clock, add a description of the LF clock inside a mbed configuration JSON file. -For example at application level the description might be added in a mbed_app.json file and on target level the description might be added in the hal/target.json file. -LF clock source configuration is used for MCU startup initialization and the BLE SoftDevice LF clock configuration (if BLE libraries is used). Advanced configurations are used only for the BLE SoftDevice LF clock configuration. - - -## Usage: - -1. Clock source - -Default clock source is XTAL oscillator. It is defined at the target level configuration as the target.lf_clock_src key. -There are three options that can be configured as the clock source: - - NRF_LF_SRC_XTAL - - NRF_LF_SRC_RC - - NRF_LF_SRC_SYNTH - -In order to override this configuration use targed_override section in configuration file (e.g mbed_app.json) - -```json -{ - "target_overrides": { - "*": { - "target.lf_clock_src": "NRF_LF_SRC_XTAL" - } - } -} -``` - -2a. Advanced configuration of the LFCLK RC oscillator: - -```json -{ - "config": { - "lf_clock_rc_calib_timer_interval": { - "value": 16, - "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL" - }, - "lf_clock_rc_calib_mode_config": { - "value": 1, - "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG" - } - } -} - -``` - -"lf_clock_rc_calib_timer_interval" - Calibration timer interval in 250 ms. It is equivalent to nrf_clock_lf_cfg_t::rc_ctiv. -This item generates macro MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL. -By default, such configuration is set to 16. - -"lf_clock_rc_calib_mode_config" - This value configures how often the RC oscillator will be calibrated, in number of calibration intervals. -It is equivalent to nrf_clock_lf_cfg_t::rc_temp_ctiv. -For further information, see the documentation for the [API of a SoftDevice 13x version 2.0.0](http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.s132.api.v2.0.0/structnrf__clock__lf__cfg__t.html) -This item generates macro MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG. -By default, such configuration is set to 1. - -2b. Advanced configuration of the LFCLK XTAL oscillator: - -Accuracy of the clock source can be set. In order to do so macro MBED_CONF_NORDIC_LF_CLOCK_XTAL_ACCURACY should been provided (e.g. in mbed_app.json). -By default such configuration is set to NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM. -For further information, see the documentation for the [API of a SoftDevice 13x version 2.0.0](https://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.s132.api.v2.0.0%2Fgroup___n_r_f___s_d_m___d_e_f_i_n_e_s.html) - -```json -{ - "config": { - "lf_clock_xtal_accuracy": { - "value": "NRF_CLOCK_LF_XTAL_ACCURACY_250_PPM", - "macro_name": "MBED_CONF_NORDIC_LF_CLOCK_XTAL_ACCURACY" - } - } -} - -``` - - - -2c. Advance configuration of the LFCLK Synthesized from HFCLK: - -Accuracy of the clock source can be set. In order to do so macro MBED_CONF_NORDIC_LF_CLOCK_SYNTH_ACCURACY should been provided (e.g. in mbed_app.json). -By default, such configuration is set to NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM. -For further information, see the documentation for the [API of a SoftDevice 13x version 2.0.0](https://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.s132.api.v2.0.0%2Fgroup___n_r_f___s_d_m___d_e_f_i_n_e_s.html) - -```json -{ - "config": { - "lf_clock_synth_accuracy": { - "value": "NRF_CLOCK_LF_SYNTH_ACCURACY_250_PPM", - "macro_name": "MBED_CONF_NORDIC_LF_CLOCK_XTAL_ACCURACY" - } - } -} - -``` - - diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/common_rtc.h b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/common_rtc.h deleted file mode 100644 index f15ff83a589..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/common_rtc.h +++ /dev/null @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef COMMON_RTC_H -#define COMMON_RTC_H - -#include "nrf_rtc.h" - -#define RTC_COUNTER_BITS 24u - -// Instance 0 is reserved for SoftDevice. -// Instance 1 is used as a common one for us_ticker, lp_ticker and (in case -// of NRF51) as an alternative tick source for RTOS. -// ["us_ticker.c" uses hard coded addresses of the 'NRF_RTC1->EVENT_COMPARE[1]' -// register in inline assembly implementations of COMMON_RTC_IRQ_HANDLER, -// please remember to update those in case of doing changes here] -#define COMMON_RTC_INSTANCE NRF_RTC1 -#define COMMON_RTC_IRQ_HANDLER RTC1_IRQHandler -#define US_TICKER_CC_CHANNEL 0 -#define OS_TICK_CC_CHANNEL 1 -#define LP_TICKER_CC_CHANNEL 2 - -#define COMMON_RTC_EVENT_COMPARE(channel) \ - CONCAT_2(NRF_RTC_EVENT_COMPARE_, channel) -#define COMMON_RTC_INT_COMPARE_MASK(channel) \ - CONCAT_3(NRF_RTC_INT_COMPARE, channel, _MASK) - -#define US_TICKER_EVENT COMMON_RTC_EVENT_COMPARE(US_TICKER_CC_CHANNEL) -#define US_TICKER_INT_MASK COMMON_RTC_INT_COMPARE_MASK(US_TICKER_CC_CHANNEL) -#define OS_TICK_EVENT COMMON_RTC_EVENT_COMPARE(OS_TICK_CC_CHANNEL) -#define OS_TICK_INT_MASK COMMON_RTC_INT_COMPARE_MASK(OS_TICK_CC_CHANNEL) -#define LP_TICKER_EVENT COMMON_RTC_EVENT_COMPARE(LP_TICKER_CC_CHANNEL) -#define LP_TICKER_INT_MASK COMMON_RTC_INT_COMPARE_MASK(LP_TICKER_CC_CHANNEL) - -extern bool m_common_rtc_enabled; -extern uint32_t volatile m_common_rtc_overflows; - -void common_rtc_init(void); -uint32_t common_rtc_32bit_ticks_get(void); -uint64_t common_rtc_64bit_us_get(void); -void common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel, - uint32_t int_mask); - -#endif // COMMON_RTC_H diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/gpio_api.c b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/gpio_api.c deleted file mode 100644 index 4931b5330e8..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/gpio_api.c +++ /dev/null @@ -1,283 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "nrf_drv_gpiote.h" - -#if defined(TARGET_MCU_NRF51822) - #define GPIO_PIN_COUNT 31 -#elif defined(TARGET_MCU_NRF52832) - #define GPIO_PIN_COUNT 32 -#elif defined(TARGET_MCU_NRF52840) - #define GPIO_PIN_COUNT 48 -#else - #error not recognized gpio count for mcu -#endif - -typedef struct -{ - bool used_as_gpio : 1; - PinDirection direction : 1; - bool init_high : 1; - PinMode pull : 2; - bool used_as_irq : 1; - bool irq_fall : 1; - bool irq_rise : 1; -} gpio_cfg_t; - -#if GPIO_PIN_COUNT > 32 - typedef uint64_t gpio_mask_t; -#else - typedef uint32_t gpio_mask_t; -#endif - -static gpio_mask_t m_gpio_initialized; -static gpio_cfg_t m_gpio_cfg[GPIO_PIN_COUNT]; - - -/*********** - GPIO IRQ -***********/ - -static gpio_irq_handler m_irq_handler; -static uint32_t m_channel_ids[GPIO_PIN_COUNT] = {0}; -static gpio_mask_t m_gpio_irq_enabled; - - -static void gpiote_irq_handler(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t action) -{ - nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin); - gpio_irq_event event = (sense == NRF_GPIO_PIN_SENSE_LOW) ? IRQ_RISE : IRQ_FALL; - - if (m_gpio_irq_enabled & ((gpio_mask_t)1 << pin)) - { - if (((event == IRQ_RISE) && m_gpio_cfg[pin].irq_rise) - || ((event == IRQ_FALL) && m_gpio_cfg[pin].irq_fall)) - { - m_irq_handler(m_channel_ids[pin], event); - } - } -} - -void GPIOTE_IRQHandler(void);// exported from nrf_drv_gpiote.c - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) - { - return; - } - MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT); - - NVIC_SetVector(GPIOTE_IRQn, (uint32_t) GPIOTE_IRQHandler); - - (void) nrf_drv_gpiote_init(); - - m_gpio_cfg[obj->pin].used_as_gpio = true; -} - - -int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (m_gpio_cfg[obj->pin].direction == PIN_OUTPUT) - { - return (nrf_gpio_pin_out_read(obj->pin) ? 1 : 0); - } - else - { - return nrf_gpio_pin_read(obj->pin); - } -} - -static void gpiote_pin_uninit(uint8_t pin) -{ - if (m_gpio_initialized & ((gpio_mask_t)1 << pin)) - { - if ((m_gpio_cfg[pin].direction == PIN_OUTPUT) && (!m_gpio_cfg[pin].used_as_irq)) - { - nrf_drv_gpiote_out_uninit(pin); - } - else - { - nrf_drv_gpiote_in_uninit(pin); - } - } -} - -static void gpio_apply_config(uint8_t pin) -{ - if (m_gpio_cfg[pin].used_as_gpio || m_gpio_cfg[pin].used_as_irq) - { - if ((m_gpio_cfg[pin].direction == PIN_INPUT) - || (m_gpio_cfg[pin].used_as_irq)) - { - //Configure as input. - nrf_drv_gpiote_in_config_t cfg; - - cfg.hi_accuracy = false; - cfg.is_watcher = false; - cfg.sense = NRF_GPIOTE_POLARITY_TOGGLE; - if (m_gpio_cfg[pin].used_as_irq) - { - cfg.pull = NRF_GPIO_PIN_PULLUP; - nrf_drv_gpiote_in_init(pin, &cfg, gpiote_irq_handler); - if ((m_gpio_irq_enabled & ((gpio_mask_t)1 << pin)) - && (m_gpio_cfg[pin].irq_rise || m_gpio_cfg[pin].irq_fall)) - { - nrf_drv_gpiote_in_event_enable(pin, true); - } - } - else - { - switch (m_gpio_cfg[pin].pull) - { - case PullUp: - cfg.pull = NRF_GPIO_PIN_PULLUP; - break; - case PullDown: - cfg.pull = NRF_GPIO_PIN_PULLDOWN; - break; - default: - cfg.pull = NRF_GPIO_PIN_NOPULL; - break; - } - nrf_drv_gpiote_in_init(pin, &cfg, NULL); - } - } - else - { - // Configure as output. - nrf_drv_gpiote_out_config_t cfg = GPIOTE_CONFIG_OUT_SIMPLE(m_gpio_cfg[pin].init_high); - nrf_drv_gpiote_out_init(pin, &cfg); - } - m_gpio_initialized |= ((gpio_mask_t)1 << pin); - } - else - { - m_gpio_initialized &= ~((gpio_mask_t)1 << pin); - } -} - - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - - gpiote_pin_uninit(obj->pin); // try to uninitialize gpio before a change. - - m_gpio_cfg[obj->pin].pull = mode; - gpio_apply_config(obj->pin); -} - - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - - gpiote_pin_uninit(obj->pin); // try to uninitialize gpio before a change. - - m_gpio_cfg[obj->pin].direction = direction; - gpio_apply_config(obj->pin); -} - - -/*********** - GPIO IRQ -***********/ - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - if (pin == NC) - { - return -1; - } - MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT); - (void) nrf_drv_gpiote_init(); - - gpiote_pin_uninit(pin); // try to uninitialize gpio before a change. - - m_gpio_cfg[pin].used_as_irq = true; - m_channel_ids[pin] = id; - obj->ch = pin; - m_irq_handler = handler; - m_channel_ids[pin] = id; - - gpio_apply_config(pin); - return 1; -} - - -void gpio_irq_free(gpio_irq_t *obj) -{ - nrf_drv_gpiote_in_uninit(obj->ch); - m_gpio_cfg[obj->ch].used_as_irq = false; - m_channel_ids[obj->ch] = 0; - - gpio_apply_config(obj->ch); -} - - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - gpio_cfg_t* cfg = &m_gpio_cfg[obj->ch]; - bool irq_enabled_before = - (m_gpio_irq_enabled & ((gpio_mask_t)1 << obj->ch)) && - (cfg->irq_rise || cfg->irq_fall); - - if (event == IRQ_RISE) - { - cfg->irq_rise = enable ? true : false; - } - else if (event == IRQ_FALL) - { - cfg->irq_fall = enable ? true : false; - } - - bool irq_enabled_after = cfg->irq_rise || cfg->irq_fall; - - if (irq_enabled_before != irq_enabled_after) - { - if (irq_enabled_after) - { - gpio_irq_enable(obj); - } - else - { - gpio_irq_disable(obj); - } - } -} - - -void gpio_irq_enable(gpio_irq_t *obj) -{ - m_gpio_irq_enabled |= ((gpio_mask_t)1 << obj->ch); - if (m_gpio_cfg[obj->ch].irq_rise || m_gpio_cfg[obj->ch].irq_fall) - { - nrf_drv_gpiote_in_event_enable(obj->ch, true); - } -} - - -void gpio_irq_disable(gpio_irq_t *obj) -{ - m_gpio_irq_enabled &= ~((gpio_mask_t)1 << obj->ch); - nrf_drv_gpiote_in_event_disable(obj->ch); -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/gpio_object.h b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/gpio_object.h deleted file mode 100644 index 9a6db55284d..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/gpio_object.h +++ /dev/null @@ -1,54 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#include "nrf_gpio.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct -{ - PinName pin; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) - { - nrf_gpio_pin_set(obj->pin); - } - else - { - nrf_gpio_pin_clear(obj->pin); - } -} - -static inline int gpio_is_connected(const gpio_t *obj) -{ - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/i2c_api.c b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/i2c_api.c deleted file mode 100644 index 69a94770baf..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/i2c_api.c +++ /dev/null @@ -1,784 +0,0 @@ -/* - * Copyright (c) 2017 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "mbed_assert.h" -#include "mbed_error.h" -#include "nrf_twi.h" -#include "nrf_drv_common.h" -#include "sdk_config.h" -#include "app_util_platform.h" -#include "nrf_gpio.h" -#include "nrf_delay.h" - -// An arbitrary value used as the counter in loops waiting for given event -// (e.g. STOPPED), needed to avoid infinite loops (and not involve any timers -// or tickers). -#define TIMEOUT_VALUE 1000 - -#if DEVICE_I2C_ASYNCH - #define TWI_IDX(obj) ((obj)->i2c.twi_idx) -#else - #define TWI_IDX(obj) ((obj)->twi_idx) -#endif -#define TWI_INFO(obj) (&m_twi_info[TWI_IDX(obj)]) - -#define TWI0_INSTANCE_INDEX 0 -#define TWI1_INSTANCE_INDEX TWI0_INSTANCE_INDEX+TWI0_ENABLED - -typedef struct { - bool initialized; - uint32_t pselsda; - uint32_t pselscl; - nrf_twi_frequency_t frequency; - bool start_twi; - -#if DEVICE_I2C_ASYNCH - volatile bool active; - uint8_t const *tx; - size_t tx_length; - uint8_t *rx; - size_t rx_length; - bool stop; - - volatile uint32_t events; - void (*handler)(void); - uint32_t evt_mask; -#endif // DEVICE_I2C_ASYNCH -} twi_info_t; -static twi_info_t m_twi_info[TWI_COUNT]; - -static NRF_TWI_Type * const m_twi_instances[TWI_COUNT] = { -#if TWI0_ENABLED - NRF_TWI0, -#endif -#if TWI1_ENABLED - NRF_TWI1, -#endif -}; - -void SPI0_TWI0_IRQHandler(void); -void SPI1_TWI1_IRQHandler(void); - -static const peripheral_handler_desc_t twi_handlers[TWI_COUNT] = -{ -#if TWI0_ENABLED - { - SPI0_TWI0_IRQn, - (uint32_t) SPI0_TWI0_IRQHandler - }, -#endif -#if TWI1_ENABLED - { - SPI1_TWI1_IRQn, - (uint32_t) SPI1_TWI1_IRQHandler - } -#endif -}; -#ifdef NRF51 - #define TWI_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#elif defined(NRF52) || defined(NRF52840_XXAA) - #define TWI_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST -#endif - - -#if DEVICE_I2C_ASYNCH -static void start_asynch_rx(twi_info_t *twi_info, NRF_TWI_Type *twi) -{ - if (twi_info->rx_length == 1 && twi_info->stop) - { - nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK); - } - else - { - nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_SUSPEND_MASK); - } - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTRX); -} - -static void twi_irq_handler(uint8_t instance_idx) -{ - twi_info_t *twi_info = &m_twi_info[instance_idx]; - - NRF_TWI_Type *twi = m_twi_instances[instance_idx]; - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR)) - { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - - // In case of an error, force STOP. - // The current transfer may be suspended (if it is RX), so it must be - // resumed before the STOP task is triggered. - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP); - - uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi); - twi_info->events |= I2C_EVENT_ERROR; - if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) - { - twi_info->events |= I2C_EVENT_ERROR_NO_SLAVE; - } - if (errorsrc & NRF_TWI_ERROR_DATA_NACK) - { - twi_info->events |= I2C_EVENT_TRANSFER_EARLY_NACK; - } - } - - bool finished = false; - - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_TXDSENT)) - { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT); - - MBED_ASSERT(twi_info->tx_length > 0); - --(twi_info->tx_length); - // Send next byte if there is still something to be sent. - if (twi_info->tx_length > 0) - { - nrf_twi_txd_set(twi, *(twi_info->tx)); - ++(twi_info->tx); - // It TX is done, start RX if requested. - } - else if (twi_info->rx_length > 0) - { - start_asynch_rx(twi_info, twi); - // If there is nothing more to do, finalize the transfer. - } - else - { - if (twi_info->stop) - { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP); - } - else - { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND); - finished = true; - } - twi_info->events |= I2C_EVENT_TRANSFER_COMPLETE; - } - } - - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_RXDREADY)) - { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY); - - MBED_ASSERT(twi_info->rx_length > 0); - *(twi_info->rx) = nrf_twi_rxd_get(twi); - ++(twi_info->rx); - --(twi_info->rx_length); - - if (twi_info->rx_length > 0) - { - // If more bytes should be received, resume the transfer - // (in case the stop condition should be generated after the next - // byte, change the shortcuts configuration first). - if (twi_info->rx_length == 1 && twi_info->stop) - { - nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK); - } - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - } - else - { - // If all requested bytes were received, finalize the transfer. - finished = true; - twi_info->events |= I2C_EVENT_TRANSFER_COMPLETE; - } - } - - if (finished || - nrf_twi_event_check(twi, NRF_TWI_EVENT_STOPPED) || - (nrf_twi_int_enable_check(twi, NRF_TWI_INT_SUSPENDED_MASK) && - nrf_twi_event_check(twi, NRF_TWI_EVENT_SUSPENDED))) - { - // There is no need to clear the STOPPED and SUSPENDED events here, - // they will no longer generate the interrupt - see below. - - nrf_twi_shorts_set(twi, 0); - // Disable all interrupt sources. - nrf_twi_int_disable(twi, UINT32_MAX); - twi_info->active = false; - - if (twi_info->handler) - { - twi_info->handler(); - } - } -} - -#if TWI0_ENABLED -static void irq_handler_twi0(void) -{ - twi_irq_handler(TWI0_INSTANCE_INDEX); -} -#endif -#if TWI1_ENABLED -static void irq_handler_twi1(void) -{ - twi_irq_handler(TWI1_INSTANCE_INDEX); -} -#endif -static nrf_drv_irq_handler_t const m_twi_irq_handlers[TWI_COUNT] = -{ -#if TWI0_ENABLED - irq_handler_twi0, -#endif -#if TWI1_ENABLED - irq_handler_twi1, -#endif -}; -#endif // DEVICE_I2C_ASYNCH - - -static void configure_twi_pin(uint32_t pin, nrf_gpio_pin_dir_t dir) -{ - nrf_gpio_cfg(pin, - dir, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_PULLUP, - NRF_GPIO_PIN_S0D1, - NRF_GPIO_PIN_NOSENSE); -} - -static void twi_clear_bus(twi_info_t *twi_info) -{ - // Try to set SDA high, and check if no slave tries to drive it low. - nrf_gpio_pin_set(twi_info->pselsda); - configure_twi_pin(twi_info->pselsda, NRF_GPIO_PIN_DIR_OUTPUT); - // In case SDA is low, make up to 9 cycles on SCL line to help the slave - // that pulls SDA low release it. - if (!nrf_gpio_pin_read(twi_info->pselsda)) - { - nrf_gpio_pin_set(twi_info->pselscl); - configure_twi_pin(twi_info->pselscl, NRF_GPIO_PIN_DIR_OUTPUT); - nrf_delay_us(4); - - for (int i = 0; i < 9; i++) - { - if (nrf_gpio_pin_read(twi_info->pselsda)) - { - break; - } - nrf_gpio_pin_clear(twi_info->pselscl); - nrf_delay_us(4); - nrf_gpio_pin_set(twi_info->pselscl); - nrf_delay_us(4); - } - - // Finally, generate STOP condition to put the bus into initial state. - nrf_gpio_pin_clear(twi_info->pselsda); - nrf_delay_us(4); - nrf_gpio_pin_set(twi_info->pselsda); - } -} - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - int i; - - for (i = 0; i < TWI_COUNT; ++i) - { - if (m_twi_info[i].initialized && - m_twi_info[i].pselsda == (uint32_t)sda && - m_twi_info[i].pselscl == (uint32_t)scl) - { - TWI_IDX(obj) = i; - TWI_INFO(obj)->frequency = NRF_TWI_FREQ_100K; - i2c_reset(obj); - return; - } - } - - for (i = 0; i < TWI_COUNT; ++i) - { - if (!m_twi_info[i].initialized) - { - TWI_IDX(obj) = i; - - twi_info_t *twi_info = TWI_INFO(obj); - twi_info->initialized = true; - twi_info->pselsda = (uint32_t)sda; - twi_info->pselscl = (uint32_t)scl; - twi_info->frequency = NRF_TWI_FREQ_100K; - twi_info->start_twi = false; -#if DEVICE_I2C_ASYNCH - twi_info->active = false; -#endif - - twi_clear_bus(twi_info); - - configure_twi_pin(twi_info->pselsda, NRF_GPIO_PIN_DIR_INPUT); - configure_twi_pin(twi_info->pselscl, NRF_GPIO_PIN_DIR_INPUT); - - i2c_reset(obj); - -#if DEVICE_I2C_ASYNCH - nrf_drv_common_per_res_acquire(m_twi_instances[i], - m_twi_irq_handlers[i]); - NVIC_SetVector(twi_handlers[i].IRQn, twi_handlers[i].vector); - nrf_drv_common_irq_enable(twi_handlers[i].IRQn, TWI_IRQ_PRIORITY); -#endif - - return; - } - } - - error("No available I2C peripheral\r\n"); -} - -void i2c_reset(i2c_t *obj) -{ - twi_info_t *twi_info = TWI_INFO(obj); - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - - nrf_twi_disable(twi); - nrf_twi_pins_set(twi, twi_info->pselscl, twi_info->pselsda); - nrf_twi_frequency_set(twi, twi_info->frequency); - nrf_twi_enable(twi); -} - -int i2c_start(i2c_t *obj) -{ - twi_info_t *twi_info = TWI_INFO(obj); -#if DEVICE_I2C_ASYNCH - if (twi_info->active) - { - return I2C_ERROR_BUS_BUSY; - } -#endif - twi_info->start_twi = true; - - return 0; -} - -int i2c_stop(i2c_t *obj) -{ - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - - // The current transfer may be suspended (if it is RX), so it must be - // resumed before the STOP task is triggered. - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP); - uint32_t remaining_time = TIMEOUT_VALUE; - - do - { - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_STOPPED)) - { - return 0; - } - } - while (--remaining_time); - - return 1; -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - twi_info_t *twi_info = TWI_INFO(obj); - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - - if (hz < 250000) - { - twi_info->frequency = NRF_TWI_FREQ_100K; - } - else if (hz < 400000) - { - twi_info->frequency = NRF_TWI_FREQ_250K; - } - else - { - twi_info->frequency = NRF_TWI_FREQ_400K; - } - nrf_twi_frequency_set(twi, twi_info->frequency); -} - -static uint8_t twi_address(int i2c_address) -{ - // The TWI peripheral requires 7-bit slave address (without R/W bit). - return (i2c_address >> 1); -} - -static void start_twi_read(NRF_TWI_Type *twi, int address) -{ - nrf_twi_event_clear(twi, NRF_TWI_EVENT_STOPPED); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - (void)nrf_twi_errorsrc_get_and_clear(twi); - - nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_SUSPEND_MASK); - - nrf_twi_address_set(twi, twi_address(address)); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTRX); -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - // Zero-length RX transfers are not supported. Such transfers cannot - // be easily achieved with TWI peripheral (some dirty tricks would be - // required for this), and they are actually useless (TX can be used - // to check if the address is acknowledged by a slave). - MBED_ASSERT(length > 0); - - twi_info_t *twi_info = TWI_INFO(obj); -#if DEVICE_I2C_ASYNCH - if (twi_info->active) - { - return I2C_ERROR_BUS_BUSY; - } -#endif - twi_info->start_twi = false; - - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - start_twi_read(twi, address); - - int result = length; - - while (length > 0) - { - int byte_read_result = i2c_byte_read(obj, (stop && length == 1)); - if (byte_read_result < 0) - { - // When an error occurs, return the number of bytes that have been - // received successfully. - result -= length; - // Force STOP condition. - stop = 1; - break; - } - *data++ = (uint8_t)byte_read_result; - --length; - } - - if (stop) - { - (void)i2c_stop(obj); - } - - return result; -} - -static uint8_t twi_byte_write(NRF_TWI_Type *twi, uint8_t data) -{ - nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - - nrf_twi_txd_set(twi, data); - uint32_t remaining_time = TIMEOUT_VALUE; - - do - { - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_TXDSENT)) - { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT); - return 1; // ACK received - } - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR)) - { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - return 0; // some error occurred - } - } - while (--remaining_time); - - return 2; // timeout; -} - -static void start_twi_write(NRF_TWI_Type *twi, int address) -{ - nrf_twi_event_clear(twi, NRF_TWI_EVENT_STOPPED); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - (void)nrf_twi_errorsrc_get_and_clear(twi); - - nrf_twi_shorts_set(twi, 0); - - nrf_twi_address_set(twi, twi_address(address)); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTTX); -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - twi_info_t *twi_info = TWI_INFO(obj); -#if DEVICE_I2C_ASYNCH - if (twi_info->active) - { - return I2C_ERROR_BUS_BUSY; - } -#endif - twi_info->start_twi = false; - - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - start_twi_write(twi, address); - - // Special case - transaction with no data. - // It can be used to check if a slave acknowledges the address. - if (length == 0) - { - nrf_twi_event_t event; - if (stop) - { - event = NRF_TWI_EVENT_STOPPED; - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP); - } - else - { - event = NRF_TWI_EVENT_SUSPENDED; - nrf_twi_event_clear(twi, event); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND); - } - uint32_t remaining_time = TIMEOUT_VALUE; - - do - { - if (nrf_twi_event_check(twi, event)) - { - break; - } - } - while (--remaining_time); - - uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi); - if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) - { - if (!stop) - { - i2c_stop(obj); - } - return I2C_ERROR_NO_SLAVE; - } - - return (remaining_time ? 0 : I2C_ERROR_BUS_BUSY); - } - - int result = length; - - do - { - uint8_t byte_write_result = twi_byte_write(twi, (uint8_t)*data++); - if (byte_write_result != 1) - { - if (byte_write_result == 0) - { - // Check what kind of error has been signaled by TWI. - uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi); - if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) - { - result = I2C_ERROR_NO_SLAVE; - } - else - { - // Some other error - return the number of bytes that - // have been sent successfully. - result -= length; - } - } - else - { - result = I2C_ERROR_BUS_BUSY; - } - // Force STOP condition. - stop = 1; - break; - } - --length; - } - while (length > 0); - - if (stop) - { - (void)i2c_stop(obj); - } - - return result; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - - if (last) - { - nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK); - } - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - - uint32_t remaining_time = TIMEOUT_VALUE; - - do - { - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_RXDREADY)) - { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY); - return nrf_twi_rxd_get(twi); - } - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR)) - { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - return I2C_ERROR_NO_SLAVE; - } - } - while (--remaining_time); - - return I2C_ERROR_BUS_BUSY; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - twi_info_t *twi_info = TWI_INFO(obj); - if (twi_info->start_twi) - { - twi_info->start_twi = false; - - if (data & 1) - { - start_twi_read(twi, data); - } - else - { - start_twi_write(twi, data); - } - return 1; - } - else - { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - // 0 - TWI signaled error (NAK is the only possibility here) - // 1 - ACK received - // 2 - timeout (clock stretched for too long?) - return twi_byte_write(twi, (uint8_t)data); - } -} - - -#if DEVICE_I2C_ASYNCH -void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, - void *rx, size_t rx_length, uint32_t address, - uint32_t stop, uint32_t handler, - uint32_t event, DMAUsage hint) -{ - (void)hint; - - twi_info_t *twi_info = TWI_INFO(obj); - if (twi_info->active) - { - return; - } - twi_info->active = true; - twi_info->events = 0; - twi_info->handler = (void (*)(void))handler; - twi_info->evt_mask = event; - twi_info->tx_length = tx_length; - twi_info->tx = tx; - twi_info->rx_length = rx_length; - twi_info->rx = rx; - twi_info->stop = stop; - - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - - nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_STOPPED); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_SUSPENDED); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - (void)nrf_twi_errorsrc_get_and_clear(twi); - - nrf_twi_address_set(twi, twi_address(address)); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - // TX only, or TX + RX (after a repeated start). - if (tx_length > 0) - { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTTX); - nrf_twi_txd_set(twi, *(twi_info->tx)); - ++(twi_info->tx); - // RX only. - } - else if (rx_length > 0) - { - start_asynch_rx(twi_info, twi); - // Both 'tx_length' and 'rx_length' are 0 - this case may be used - // to test if the slave is presentand ready for transfer (by just - // sending the address and checking if it is acknowledged). - } - else - { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTTX); - if (stop) - { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP); - } - else - { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND); - nrf_twi_int_enable(twi, NRF_TWI_INT_SUSPENDED_MASK); - } - twi_info->events |= I2C_EVENT_TRANSFER_COMPLETE; - } - - nrf_twi_int_enable(twi, NRF_TWI_INT_TXDSENT_MASK | - NRF_TWI_INT_RXDREADY_MASK | - NRF_TWI_INT_STOPPED_MASK | - NRF_TWI_INT_ERROR_MASK); -} - -uint32_t i2c_irq_handler_asynch(i2c_t *obj) -{ - twi_info_t *twi_info = TWI_INFO(obj); - return (twi_info->events & twi_info->evt_mask); -} - -uint8_t i2c_active(i2c_t *obj) -{ - twi_info_t *twi_info = TWI_INFO(obj); - return twi_info->active; -} - -void i2c_abort_asynch(i2c_t *obj) -{ - i2c_reset(obj); -} -#endif // DEVICE_I2C_ASYNCH - -#endif // DEVICE_I2C diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/irq_handlers_hw.h b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/irq_handlers_hw.h deleted file mode 100644 index 7eba37ad998..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/irq_handlers_hw.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2016 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/** - * @file irq_handlers_hw.h - * @brief Heleper file for wiring irq handlers to theirs vectors. - */ - -#ifndef IRQ_HANDLERS_HW_H__ -#define IRQ_HANDLERS_HW_H__ - - -typedef struct -{ - IRQn_Type IRQn; - uint32_t vector; -} peripheral_handler_desc_t; - -#endif // IRQ_HANDLERS_HW_H__ - diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/lp_ticker.c b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/lp_ticker.c deleted file mode 100644 index ae63c2a1e1a..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/lp_ticker.c +++ /dev/null @@ -1,48 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "lp_ticker_api.h" - -#if DEVICE_LOWPOWERTIMER - -#include "common_rtc.h" - -void lp_ticker_init(void) -{ - common_rtc_init(); -} - -uint32_t lp_ticker_read() -{ - return (uint32_t)common_rtc_64bit_us_get(); -} - -void lp_ticker_set_interrupt(timestamp_t timestamp) -{ - common_rtc_set_interrupt(timestamp, - LP_TICKER_CC_CHANNEL, LP_TICKER_INT_MASK); -} - -void lp_ticker_disable_interrupt(void) -{ - nrf_rtc_event_disable(COMMON_RTC_INSTANCE, LP_TICKER_INT_MASK); -} - -void lp_ticker_clear_interrupt(void) -{ - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT); -} - -#endif // DEVICE_LOWPOWERTIMER diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/nordic_critical.c b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/nordic_critical.c deleted file mode 100644 index 3bcd4c9501a..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/nordic_critical.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include // uint32_t, UINT32_MAX -#include // uint32_t, UINT32_MAX -#include "cmsis.h" -#include "nrf_soc.h" -#include "nrf_sdm.h" -#include "nrf_nvic.h" - -static uint8_t _sd_state = 0; -static volatile uint32_t _entry_count = 0; - -void core_util_critical_section_enter() -{ - // if a critical section has already been entered, just update the counter - if (_entry_count) - { - ++_entry_count; - return; - } - - // in this path, a critical section has never been entered - // routine of SD V11 work even if the softdevice is not active - sd_nvic_critical_region_enter(&_sd_state); - - assert(_entry_count == 0); // entry count should always be equal to 0 at this point - ++_entry_count; -} - -void core_util_critical_section_exit() -{ - assert(_entry_count > 0); - --_entry_count; - - // If their is other segments which have entered the critical section, just leave - if (_entry_count) - { - return; - } - - // This is the last segment of the critical section, state should be restored as before entering - // the critical section - sd_nvic_critical_region_exit(_sd_state); -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/nrf5x_lf_clk_helper.h b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/nrf5x_lf_clk_helper.h deleted file mode 100644 index 08744be767f..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/nrf5x_lf_clk_helper.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2016 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __NRF5X_LF_CLK_HELPER_H_ - -#ifndef MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC - #define MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC (NRF_LF_SRC_XTAL) - #warning No configuration for LF clock source. Xtal source will be used as a default configuration. -#endif - - - -#define NRF_LF_SRC_XTAL 2 -#define NRF_LF_SRC_SYNTH 3 -#define NRF_LF_SRC_RC 4 - -#if MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_SYNTH - #define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_Synth) -#elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_XTAL - #define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_Xtal) -#elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_RC - #define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_RC) -#else - #error Bad LFCLK configuration. Declare proper source through mbed configuration. -#endif - -#undef NRF_LF_SRC_XTAL -#undef NRF_LF_SRC_SYNTH -#undef NRF_LF_SRC_RC - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/objects.h b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/objects.h deleted file mode 100644 index 104ff648348..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/objects.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct serial_s -{ - uint32_t placeholder; // struct is unused by nRF5x API implementation -}; // but it must be not empty (required by strict compiler - IAR) - -struct spi_s -{ - uint8_t spi_idx; -}; - -struct port_s -{ - PortName port; - uint32_t mask; -}; - -struct pwmout_s -{ - PWMName pwm_name; - PinName pin; - uint8_t pwm_channel; - void * pwm_struct; -}; - -struct i2c_s -{ - uint8_t twi_idx; -}; - -struct analogin_s -{ - ADCName adc; - uint8_t adc_pin; -}; - -struct gpio_irq_s -{ - uint32_t ch; -}; - - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/pinmap.c b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/pinmap.c deleted file mode 100644 index 26fa761c1db..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/pinmap.c +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "mbed_error.h" -#include "pinmap.h" - -void pin_function(PinName pin, int function) -{ - /* Avoid compiler warnings */ - (void) pin; - (void) function; -} - -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - - uint32_t pin_number = (uint32_t)pin; - - NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number); - - reg->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_PULL_Msk; - reg->PIN_CNF[pin_number] |= (mode << GPIO_PIN_CNF_PULL_Pos); -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/port_api.c b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/port_api.c deleted file mode 100644 index faecdc9de53..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/port_api.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "port_api.h" -#include "pinmap.h" - -static NRF_GPIO_Type * const m_ports[] = GPIO_REG_LIST; - -#if defined(TARGET_MCU_NRF51822) - static const uint32_t m_gpio_pin_count[] = {31}; -#elif defined(TARGET_MCU_NRF52832) - static const uint32_t m_gpio_pin_count[] = {32}; -#elif defined(TARGET_MCU_NRF52840) - static const uint32_t m_gpio_pin_count[] = {32, 16}; -#else - #error not recognized gpio count for mcu -#endif - -#define GPIO_PORT_COUNT (sizeof(m_gpio_pin_count)/sizeof(uint32_t)) - - -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)NRF_GPIO_PIN_MAP(port, pin_n); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - MBED_ASSERT((uint32_t)port < GPIO_PORT_COUNT); - - obj->port = port; - obj->mask = mask; - - port_dir(obj, dir); -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - // The mode is set per pin: reuse pinmap logic - for (i = 0; i < m_gpio_pin_count[obj->port]; i++) - { - if (obj->mask & (1 << i)) - { - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - uint32_t i; - - volatile uint32_t *reg_cnf = (volatile uint32_t*) m_ports[obj->port]->PIN_CNF; - - switch (dir) - { - case PIN_INPUT: - - for (i = 0; i < m_gpio_pin_count[obj->port]; i++) - { - if (obj->mask & (1 << i)) - { - reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); - } - } - break; - - case PIN_OUTPUT: - - for (i = 0; i < m_gpio_pin_count[obj->port]; i++) - { - if (obj->mask & (1 << i)) - { - reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - } - } - break; - } -} - -void port_write(port_t *obj, int value) -{ - m_ports[obj->port]->OUTSET = value & obj->mask; - m_ports[obj->port]->OUTCLR = (~value) & obj->mask; -} - -int port_read(port_t *obj) -{ - return ((m_ports[obj->port]->IN) & obj->mask); -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/reloc_vector_table.c b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/reloc_vector_table.c deleted file mode 100644 index bf9577331ab..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/reloc_vector_table.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2016 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "nrf.h" -#include "cmsis_nvic.h" -#include "stdint.h" -#include "nrf_sdm.h" -#include "section_vars.h" - -#if defined(__CC_ARM) - __attribute__ ((section("noinit"),zero_init)) - uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS]; -#elif defined(__GNUC__) - __attribute__ ((section(".noinit"))) - uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS]; -#elif defined(__ICCARM__) - uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS] @ ".noinit"; -#endif - - -typedef void (*generic_irq_handler_t)(void); - - -extern uint32_t __Vectors[]; -#define VECTORS_FLASH_START __Vectors - -/** - * @brief Function for relocation of the vector to RAM on nRF5x devices. - * This function is intended to be called during startup. - */ -void nrf_reloc_vector_table(void) -{ - // Copy and switch to dynamic vectors - uint32_t *old_vectors = (uint32_t*)VECTORS_FLASH_START; - uint32_t i; - - for (i = 0; i< NVIC_NUM_VECTORS; i++) - { - nrf_dispatch_vector[i] = old_vectors[i]; - } - - sd_softdevice_vector_table_base_set((uint32_t) nrf_dispatch_vector); -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/rtc_api.c b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/rtc_api.c deleted file mode 100644 index 589b85cd596..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/rtc_api.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "rtc_api.h" - -#if DEVICE_RTC - -#include "common_rtc.h" -#include "nrf_drv_clock.h" -#include "app_util_platform.h" - -static time_t m_time_base; - -void rtc_init(void) -{ - common_rtc_init(); -} - -void rtc_free(void) -{ - // A common counter is used for RTC, lp_ticker and us_ticker, so it can't be - // disabled here, but this does not cause any extra cost. Besides, currently - // this function is not used by RTC API in mbed-drivers. -} - -int rtc_isenabled(void) -{ - return m_common_rtc_enabled; -} - -static uint32_t rtc_seconds_get(void) -{ - // Convert current counter value to seconds. - uint32_t seconds = nrf_rtc_counter_get(COMMON_RTC_INSTANCE) / RTC_INPUT_FREQ; - // Add proper amount of seconds for each registered overflow of the counter. - uint32_t seconds_per_overflow = (1uL << RTC_COUNTER_BITS) / RTC_INPUT_FREQ; - return (seconds + (m_common_rtc_overflows * seconds_per_overflow)); -} - -time_t rtc_read(void) -{ - return m_time_base + rtc_seconds_get(); -} - -void rtc_write(time_t t) -{ - uint32_t seconds; - - do - { - seconds = rtc_seconds_get(); - m_time_base = t - seconds; - // If the number of seconds indicated by the counter changed during the - // update of the time base, just repeat the update, now using the new - // number of seconds. - } while (seconds != rtc_seconds_get()); -} - -#endif // DEVICE_RTC diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/serial_api.c b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/serial_api.c deleted file mode 100644 index e0b91656c8e..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/serial_api.c +++ /dev/null @@ -1,723 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include -#include "mbed_assert.h" -#include "mbed_error.h" -#include "nrf_uart.h" -#include "nrf_drv_common.h" -#include "app_util_platform.h" -#include "nrf_gpio.h" - -#define UART_INSTANCE_COUNT 1 -#define UART_INSTANCE NRF_UART0 -#define UART_IRQn UART0_IRQn -#define UART_IRQ_HANDLER UART0_IRQHandler -#define UART_INSTANCE_ID 0 -#define UART_CB uart_cb[UART_INSTANCE_ID] - -#define UART_DEFAULT_BAUDRATE UART_DEFAULT_CONFIG_BAUDRATE -#define UART_DEFAULT_PARITY UART_DEFAULT_CONFIG_PARITY - -// expected the macro from mbed configuration system -#ifndef MBED_CONF_NORDIC_UART_HWFC - #define MBED_CONF_NORDIC_UART_HWFC 1 - #warning None of UART flow control configuration (expected macro MBED_CONF_NORDIC_UART_HWFC). The RTSCTS flow control is used by default . -#endif - -#if MBED_CONF_NORDIC_UART_HWFC == 1 - #define UART_DEFAULT_HWFC UART_DEFAULT_CONFIG_HWFC -#else - #define UART_DEFAULT_HWFC NRF_UART_HWFC_DISABLED -#endif - -#define UART_DEFAULT_CTS CTS_PIN_NUMBER -#define UART_DEFAULT_RTS RTS_PIN_NUMBER - -#ifdef NRF51 - #define NRFx_MBED_UART_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#elif defined(NRF52) || defined(NRF52840_XXAA) - #define NRFx_MBED_UART_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST -#endif - -// Required by "retarget.cpp". -int stdio_uart_inited = 0; -serial_t stdio_uart; - -typedef struct -{ - bool initialized; - uint32_t irq_context; - uart_irq_handler irq_handler; - - uint32_t pselrxd; - uint32_t pseltxd; - uint32_t pselcts; - uint32_t pselrts; - nrf_uart_hwfc_t hwfc; - nrf_uart_parity_t parity; - nrf_uart_baudrate_t baudrate; - -#if DEVICE_SERIAL_ASYNCH - bool volatile rx_active; - uint8_t *rx_buffer; - size_t rx_length; - size_t rx_pos; - void (*rx_asynch_handler)(); - uint8_t char_match; - - bool volatile tx_active; - const uint8_t *tx_buffer; - size_t tx_length; - size_t tx_pos; - void (*tx_asynch_handler)(); - - uint32_t events_wanted; - uint32_t events_occured; - -#define UART_IRQ_TX 1 -#define UART_IRQ_RX 2 - uint8_t irq_enabled; -#endif // DEVICE_SERIAL_ASYNCH -} uart_ctlblock_t; - -static uart_ctlblock_t uart_cb[UART_INSTANCE_COUNT]; - -static void internal_set_hwfc(FlowControl type, - PinName rxflow, PinName txflow); - - -#if DEVICE_SERIAL_ASYNCH -static void end_asynch_rx(void) -{ - // If RX interrupt is activated for synchronous operations, - // don't disable it, just stop handling it here. - if (!(UART_CB.irq_enabled & UART_IRQ_RX)) - { - nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY); - } - UART_CB.rx_active = false; -} -static void end_asynch_tx(void) -{ - // If TX interrupt is activated for synchronous operations, - // don't disable it, just stop handling it here. - if (!(UART_CB.irq_enabled & UART_IRQ_TX)) - { - nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY); - } - UART_CB.tx_active = false; -} -#endif // DEVICE_SERIAL_ASYNCH - -void UART_IRQ_HANDLER(void) -{ - if (nrf_uart_int_enable_check(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY) && - nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_RXDRDY)) - { - -#if DEVICE_SERIAL_ASYNCH - if (UART_CB.rx_active) - { - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY); - - uint8_t rx_data = nrf_uart_rxd_get(UART_INSTANCE); - UART_CB.rx_buffer[UART_CB.rx_pos] = rx_data; - - bool end_rx = false; - // If character matching should be performed, check if the current - // data matches the given one. - if (UART_CB.char_match != SERIAL_RESERVED_CHAR_MATCH && - rx_data == UART_CB.char_match) - { - // If it does, report the match and abort further receiving. - UART_CB.events_occured |= SERIAL_EVENT_RX_CHARACTER_MATCH; - if (UART_CB.events_wanted & SERIAL_EVENT_RX_CHARACTER_MATCH) - { - end_rx = true; - } - } - if (++UART_CB.rx_pos >= UART_CB.rx_length) - { - UART_CB.events_occured |= SERIAL_EVENT_RX_COMPLETE; - end_rx = true; - } - if (end_rx) - { - end_asynch_rx(); - - if (UART_CB.rx_asynch_handler) - { - // Use local variable to make it possible to start a next - // transfer from callback routine. - void (*handler)() = UART_CB.rx_asynch_handler; - UART_CB.rx_asynch_handler = NULL; - handler(); - } - } - } - else -#endif - - if (UART_CB.irq_handler) - { - UART_CB.irq_handler(UART_CB.irq_context, RxIrq); - } - } - - if (nrf_uart_int_enable_check(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY) && - nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY)) - { - -#if DEVICE_SERIAL_ASYNCH - if (UART_CB.tx_active) - { - if (++UART_CB.tx_pos <= UART_CB.tx_length) - { - // When there is still something to send, clear the TXDRDY event - // and put next byte to transmitter. - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY); - nrf_uart_txd_set(UART_INSTANCE, - UART_CB.tx_buffer[UART_CB.tx_pos]); - } - else - { - // When the TXDRDY event is set after the last byte to be sent - // has been passed to the transmitter, the job is done and TX - // complete can be indicated. - // Don't clear the TXDRDY event, it needs to remain set for the - // 'serial_writable' function to work properly. - end_asynch_tx(); - - UART_CB.events_occured |= SERIAL_EVENT_TX_COMPLETE; - if (UART_CB.tx_asynch_handler) - { - // Use local variable to make it possible to start a next - // transfer from callback routine. - void (*handler)() = UART_CB.tx_asynch_handler; - UART_CB.tx_asynch_handler = NULL; - handler(); - } - } - } - else -#endif - - if (UART_CB.irq_handler) - { - UART_CB.irq_handler(UART_CB.irq_context, TxIrq); - } - } - -#if DEVICE_SERIAL_ASYNCH - if (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_ERROR)) - { - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_ERROR); - - uint8_t errorsrc = nrf_uart_errorsrc_get_and_clear(UART_INSTANCE); - if (UART_CB.rx_asynch_handler) - { - UART_CB.events_occured |= SERIAL_EVENT_ERROR; - if (errorsrc & NRF_UART_ERROR_PARITY_MASK) - { - UART_CB.events_occured |= SERIAL_EVENT_RX_PARITY_ERROR; - } - if (errorsrc & NRF_UART_ERROR_FRAMING_MASK) - { - UART_CB.events_occured |= SERIAL_EVENT_RX_FRAMING_ERROR; - } - if (errorsrc & NRF_UART_ERROR_OVERRUN_MASK) - { - UART_CB.events_occured |= SERIAL_EVENT_RX_OVERRUN_ERROR; - } - UART_CB.rx_asynch_handler(); - } - } -#endif // DEVICE_SERIAL_ASYNCH -} - - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - - NVIC_SetVector(UART0_IRQn, (uint32_t) UART0_IRQHandler); - - - UART_CB.pseltxd = - (tx == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)tx; - UART_CB.pselrxd = - (rx == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)rx; - if (UART_CB.pseltxd != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_pin_set(UART_CB.pseltxd); - nrf_gpio_cfg_output(UART_CB.pseltxd); - } - if (UART_CB.pselrxd != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_input(UART_CB.pselrxd, NRF_GPIO_PIN_NOPULL); - } - - if (UART_CB.initialized) - { - // For already initialized peripheral it is sufficient to reconfigure - // RX/TX pins only. - - // Ensure that there is no unfinished TX transfer. - while (!serial_writable(obj)) - { - } - // UART pins can be configured only when the peripheral is disabled. - nrf_uart_disable(UART_INSTANCE); - nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd); - nrf_uart_enable(UART_INSTANCE); - } - else - { - UART_CB.baudrate = (nrf_uart_baudrate_t)UART_DEFAULT_BAUDRATE; - UART_CB.parity = (nrf_uart_parity_t)UART_DEFAULT_PARITY; - UART_CB.hwfc = (nrf_uart_hwfc_t)UART_DEFAULT_HWFC; - UART_CB.pselcts = UART_DEFAULT_CTS; - UART_CB.pselrts = UART_DEFAULT_RTS; - - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY); - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY); - nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTRX); - nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTTX); - - nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY | - NRF_UART_INT_MASK_TXDRDY); -#if DEVICE_SERIAL_ASYNCH - nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_ERROR); -#endif - nrf_drv_common_irq_enable(UART_IRQn, NRFx_MBED_UART_IRQ_PRIORITY); - - // TX interrupt needs to be signaled when transmitter buffer is empty, - // so a dummy transmission is needed to get the TXDRDY event initially - // set. - nrf_uart_configure(UART_INSTANCE, - NRF_UART_PARITY_EXCLUDED, NRF_UART_HWFC_DISABLED); - // Use maximum baud rate, so this dummy transmission takes as little - // time as possible. - nrf_uart_baudrate_set(UART_INSTANCE, NRF_UART_BAUDRATE_1000000); - // Perform it with disconnected TX pin, so nothing actually comes out - // of the device. - nrf_uart_txrx_pins_disconnect(UART_INSTANCE); - nrf_uart_hwfc_pins_disconnect(UART_INSTANCE); - nrf_uart_enable(UART_INSTANCE); - nrf_uart_txd_set(UART_INSTANCE, 0); - - while (!nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY)) - { - } - nrf_uart_disable(UART_INSTANCE); - - // Now everything is prepared to set the default configuration and - // connect the peripheral to actual pins. - nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd); - nrf_uart_baudrate_set(UART_INSTANCE, UART_CB.baudrate); - nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc); - if (UART_CB.hwfc == NRF_UART_HWFC_ENABLED) - { - internal_set_hwfc(FlowControlRTSCTS, - (PinName) UART_CB.pselrts, (PinName) UART_CB.pselcts); - } - - nrf_uart_enable(UART_INSTANCE); - - UART_CB.initialized = true; - } - - if (tx == STDIO_UART_TX && rx == STDIO_UART_RX) - { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } - else - { - stdio_uart_inited = 0; - } -} - -void serial_free(serial_t *obj) -{ - (void)obj; - - if (UART_CB.initialized) - { - nrf_uart_disable(UART_INSTANCE); - nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY | - NRF_UART_INT_MASK_TXDRDY | - NRF_UART_INT_MASK_ERROR); - nrf_drv_common_irq_disable(UART_IRQn); - UART_CB.initialized = false; - - // There is only one UART instance, thus at this point the stdio UART - // can no longer be initialized. - stdio_uart_inited = 0; - } -} - -void serial_baud(serial_t *obj, int baudrate) -{ - // nrf_uart_baudrate_set() is not used here (registers are accessed - // directly) to make it possible to set special baud rates like 56000 - // or 31250. - - static uint32_t const acceptedSpeeds[][2] = { - { 1200, UART_BAUDRATE_BAUDRATE_Baud1200 }, - { 2400, UART_BAUDRATE_BAUDRATE_Baud2400 }, - { 4800, UART_BAUDRATE_BAUDRATE_Baud4800 }, - { 9600, UART_BAUDRATE_BAUDRATE_Baud9600 }, - { 14400, UART_BAUDRATE_BAUDRATE_Baud14400 }, - { 19200, UART_BAUDRATE_BAUDRATE_Baud19200 }, - { 28800, UART_BAUDRATE_BAUDRATE_Baud28800 }, - { 31250, (0x00800000UL) /* 31250 baud */ }, - { 38400, UART_BAUDRATE_BAUDRATE_Baud38400 }, - { 56000, (0x00E51000UL) /* 56000 baud */ }, - { 57600, UART_BAUDRATE_BAUDRATE_Baud57600 }, - { 76800, UART_BAUDRATE_BAUDRATE_Baud76800 }, - { 115200, UART_BAUDRATE_BAUDRATE_Baud115200 }, - { 230400, UART_BAUDRATE_BAUDRATE_Baud230400 }, - { 250000, UART_BAUDRATE_BAUDRATE_Baud250000 }, - { 460800, UART_BAUDRATE_BAUDRATE_Baud460800 }, - { 921600, UART_BAUDRATE_BAUDRATE_Baud921600 }, - { 1000000, UART_BAUDRATE_BAUDRATE_Baud1M } - }; - - if (baudrate <= 1200) - { - UART_INSTANCE->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1200; - return; - } - - int const item_cnt = sizeof(acceptedSpeeds)/sizeof(acceptedSpeeds[0]); - - for (int i = 1; i < item_cnt; i++) - { - if ((uint32_t)baudrate < acceptedSpeeds[i][0]) - { - UART_INSTANCE->BAUDRATE = acceptedSpeeds[i - 1][1]; - return; - } - } - - UART_INSTANCE->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1M; -} - -void serial_format(serial_t *obj, - int data_bits, SerialParity parity, int stop_bits) -{ - (void)obj; - - if (data_bits != 8) - { - error("UART supports only 8 data bits.\r\n"); - } - if (stop_bits != 1) - { - error("UART supports only 1 stop bits.\r\n"); - } - if (parity == ParityNone) - { - UART_CB.parity = NRF_UART_PARITY_EXCLUDED; - } - else if (parity == ParityEven) - { - UART_CB.parity = NRF_UART_PARITY_INCLUDED; - } - else - { - error("UART supports only even parity.\r\n"); - } - - // Reconfigure UART peripheral. - nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - (void)obj; - UART_CB.irq_handler = handler; - UART_CB.irq_context = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - (void)obj; - if (enable) - { - switch (irq) - { - case RxIrq: -#if DEVICE_SERIAL_ASYNCH - UART_CB.irq_enabled |= UART_IRQ_RX; -#endif - nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY); - break; - - case TxIrq: -#if DEVICE_SERIAL_ASYNCH - UART_CB.irq_enabled |= UART_IRQ_TX; -#endif - nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY); - break; - } - } - else - { - switch (irq) - { - case RxIrq: -#if DEVICE_SERIAL_ASYNCH - UART_CB.irq_enabled &= ~UART_IRQ_RX; - if (!UART_CB.rx_active) -#endif - { - nrf_uart_int_disable(UART_INSTANCE, - NRF_UART_INT_MASK_RXDRDY); - } - break; - - case TxIrq: -#if DEVICE_SERIAL_ASYNCH - UART_CB.irq_enabled &= ~UART_IRQ_TX; - if (!UART_CB.tx_active) -#endif - { - nrf_uart_int_disable(UART_INSTANCE, - NRF_UART_INT_MASK_TXDRDY); - } - break; - } - } -} - -int serial_getc(serial_t *obj) -{ - while (!serial_readable(obj)) - { - } - - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY); - return nrf_uart_rxd_get(UART_INSTANCE); -} - -void serial_putc(serial_t *obj, int c) -{ - while (!serial_writable(obj)) - { - } - - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY); - nrf_uart_txd_set(UART_INSTANCE, (uint8_t)c); -} - -int serial_readable(serial_t *obj) -{ - (void)obj; -#if DEVICE_SERIAL_ASYNCH - if (UART_CB.rx_active) - { - return 0; - } -#endif - return (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_RXDRDY)); -} - -int serial_writable(serial_t *obj) -{ - (void)obj; -#if DEVICE_SERIAL_ASYNCH - if (UART_CB.tx_active) - { - return 0; - } -#endif - return (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY)); -} - -void serial_break_set(serial_t *obj) -{ - (void)obj; - nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_SUSPEND); - nrf_uart_txrx_pins_disconnect(UART_INSTANCE); - nrf_gpio_pin_clear(UART_CB.pseltxd); -} - -void serial_break_clear(serial_t *obj) -{ - (void)obj; - nrf_gpio_pin_set(UART_CB.pseltxd); - nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd); - nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTRX); - nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTTX); -} - - -static void internal_set_hwfc(FlowControl type, - PinName rxflow, PinName txflow) -{ - UART_CB.pselrts = - ((rxflow == NC) || (type == FlowControlCTS)) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)rxflow; - UART_CB.pselcts = - ((txflow == NC) || (type == FlowControlRTS)) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)txflow; - - if (UART_CB.pselrts != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_pin_set(UART_CB.pselrts); - nrf_gpio_cfg_output(UART_CB.pselrts); - } - if (UART_CB.pselcts != NRF_UART_PSEL_DISCONNECTED) - { - nrf_gpio_cfg_input(UART_CB.pselcts, NRF_GPIO_PIN_NOPULL); - } - - UART_CB.hwfc = (nrf_uart_hwfc_t)((type == FlowControlNone)? NRF_UART_HWFC_DISABLED : UART_DEFAULT_CONFIG_HWFC); - - nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc); - nrf_uart_hwfc_pins_set(UART_INSTANCE, UART_CB.pselrts, UART_CB.pselcts); -} - -void serial_set_flow_control(serial_t *obj, FlowControl type, - PinName rxflow, PinName txflow) -{ - (void)obj; - - nrf_uart_disable(UART_INSTANCE); - internal_set_hwfc(type, rxflow, txflow); - nrf_uart_enable(UART_INSTANCE); -} - - -void serial_clear(serial_t *obj) -{ - (void)obj; -} - -#if DEVICE_SERIAL_ASYNCH - -int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, - uint8_t tx_width, uint32_t handler, uint32_t event, - DMAUsage hint) -{ - (void)obj; - (void)tx_width; - (void)hint; - if (UART_CB.tx_active || !tx_length) - { - return 0; - } - - UART_CB.tx_buffer = tx; - UART_CB.tx_length = tx_length; - UART_CB.tx_pos = 0; - UART_CB.tx_asynch_handler = (void(*)())handler; - UART_CB.events_wanted &= ~SERIAL_EVENT_TX_ALL; - UART_CB.events_wanted |= event; - - UART_CB.tx_active = true; - nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY); - - return 0; -} - -void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, - uint8_t rx_width, uint32_t handler, uint32_t event, - uint8_t char_match, DMAUsage hint) -{ - (void)obj; - (void)rx_width; - (void)hint; - if (UART_CB.rx_active || !rx_length) - { - return; - } - - UART_CB.rx_buffer = rx; - UART_CB.rx_length = rx_length; - UART_CB.rx_pos = 0; - UART_CB.rx_asynch_handler = (void(*)())handler; - UART_CB.events_wanted &= ~SERIAL_EVENT_RX_ALL; - UART_CB.events_wanted |= event; - UART_CB.char_match = char_match; - - UART_CB.rx_active = true; - nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY); -} - -uint8_t serial_tx_active(serial_t *obj) -{ - (void)obj; - return UART_CB.tx_active; -} - -uint8_t serial_rx_active(serial_t *obj) -{ - (void)obj; - return UART_CB.rx_active; -} - -int serial_irq_handler_asynch(serial_t *obj) -{ - (void)obj; - uint32_t events_to_report = UART_CB.events_wanted & UART_CB.events_occured; - UART_CB.events_occured &= (~events_to_report); - return events_to_report; -} - -void serial_tx_abort_asynch(serial_t *obj) -{ - (void)obj; - end_asynch_tx(); - UART_CB.tx_asynch_handler = NULL; -} - -void serial_rx_abort_asynch(serial_t *obj) -{ - (void)obj; - end_asynch_rx(); - UART_CB.rx_asynch_handler = NULL; -} - -#endif // DEVICE_SERIAL_ASYNCH - -#endif // DEVICE_SERIAL diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sleep.c b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sleep.c deleted file mode 100644 index cc73962fccb..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/sleep.c +++ /dev/null @@ -1,85 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "cmsis.h" -#include "mbed_interface.h" -#include "softdevice_handler.h" -#include "nrf_soc.h" - -// Mask of reserved bits of the register ICSR in the System Control Block peripheral -// In this case, bits which are equal to 0 are the bits reserved in this register -#define SCB_ICSR_RESERVED_BITS_MASK 0x9E43F03F - -#define FPU_EXCEPTION_MASK 0x0000009F - -void hal_sleep(void) -{ - // ensure debug is disconnected if semihost is enabled.... - - // Trigger an event when an interrupt is pending. This allows to wake up - // the processor from disabled interrupts. - SCB->SCR |= SCB_SCR_SEVONPEND_Msk; - -#if defined(NRF52) || defined(NRF52840_XXAA) - /* Clear exceptions and PendingIRQ from the FPU unit */ - __set_FPSCR(__get_FPSCR() & ~(FPU_EXCEPTION_MASK)); - (void) __get_FPSCR(); - NVIC_ClearPendingIRQ(FPU_IRQn); -#endif - - // If the SoftDevice is enabled, its API must be used to go to sleep. - if (softdevice_handler_is_enabled()) - { - sd_power_mode_set(NRF_POWER_MODE_LOWPWR); - sd_app_evt_wait(); - } - else - { - NRF_POWER->TASKS_LOWPWR = 1; - - // Note: it is not sufficient to just use WFE here, since the internal - // event register may be already set from an event that occurred in the - // past (like an SVC call to the SoftDevice) and in such case WFE will - // just clear the register and continue execution. - // Therefore, the strategy here is to first clear the event register - // by using SEV/WFE pair, and then execute WFE again, unless there is - // a pending interrupt. - - // Set an event and wake up whatsoever, this will clear the event - // register from all previous events set (SVC call included) - __SEV(); - __WFE(); - - // Test if there is an interrupt pending (mask reserved regions) - if (SCB->ICSR & (SCB_ICSR_RESERVED_BITS_MASK)) - { - // Ok, there is an interrut pending, no need to go to sleep - return; - } - else - { - // next event will wakeup the CPU - // If an interrupt occured between the test of SCB->ICSR and this - // instruction, WFE will just not put the CPU to sleep - __WFE(); - } - } -} - -void hal_deepsleep(void) -{ - hal_sleep(); -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/spi_api.c b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/spi_api.c deleted file mode 100644 index da757720990..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/spi_api.c +++ /dev/null @@ -1,600 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#include "spi_api.h" - -#if DEVICE_SPI - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_assert.h" -#include "mbed_error.h" -#include "nrf_drv_spi.h" -#include "nrf_drv_spis.h" -#include "app_util_platform.h" - -#if DEVICE_SPI_ASYNCH - #define SPI_IDX(obj) ((obj)->spi.spi_idx) -#else - #define SPI_IDX(obj) ((obj)->spi_idx) -#endif -#define SPI_INFO(obj) (&m_spi_info[SPI_IDX(obj)]) -#define MASTER_INST(obj) (&m_instances[SPI_IDX(obj)].master) -#define SLAVE_INST(obj) (&m_instances[SPI_IDX(obj)].slave) - -typedef struct -{ - bool initialized; - bool master; - uint8_t sck_pin; - uint8_t mosi_pin; - uint8_t miso_pin; - uint8_t ss_pin; - uint8_t spi_mode; - nrf_drv_spi_frequency_t frequency; - volatile union - { - bool busy; // master - bool readable; // slave - } flag; - volatile uint8_t tx_buf; - volatile uint8_t rx_buf; - -#if DEVICE_SPI_ASYNCH - uint32_t handler; - uint32_t event; -#endif -} spi_info_t; -static spi_info_t m_spi_info[SPI_COUNT]; - -typedef struct -{ - nrf_drv_spi_t master; - nrf_drv_spis_t slave; -} sdk_driver_instances_t; - -void SPI0_TWI0_IRQHandler(void); -void SPI1_TWI1_IRQHandler(void); -void SPIM2_SPIS2_SPI2_IRQHandler(void); - -static const peripheral_handler_desc_t spi_handler_desc[SPI_COUNT] = { -#if SPI0_ENABLED - { - SPI0_IRQ, - (uint32_t) SPI0_TWI0_IRQHandler - }, -#endif -#if SPI1_ENABLED - { - SPI1_IRQ, - (uint32_t) SPI1_TWI1_IRQHandler - }, -#endif -#if SPI2_ENABLED - { - SPI2_IRQ, - (uint32_t) SPIM2_SPIS2_SPI2_IRQHandler - }, -#endif -}; - - -static sdk_driver_instances_t m_instances[SPI_COUNT] = { -#if SPI0_ENABLED - { - NRF_DRV_SPI_INSTANCE(0), - NRF_DRV_SPIS_INSTANCE(0) - }, -#endif -#if SPI1_ENABLED - { - NRF_DRV_SPI_INSTANCE(1), - NRF_DRV_SPIS_INSTANCE(1) - }, -#endif -#if SPI2_ENABLED - { - NRF_DRV_SPI_INSTANCE(2), - NRF_DRV_SPIS_INSTANCE(2) - }, -#endif -}; - -static void master_event_handler(uint8_t spi_idx, - nrf_drv_spi_evt_t const *p_event) -{ - spi_info_t *p_spi_info = &m_spi_info[spi_idx]; - - if (p_event->type == NRF_DRV_SPI_EVENT_DONE) - { - p_spi_info->flag.busy = false; - if (p_spi_info->handler) - { - void (*handler)(void) = (void (*)(void))p_spi_info->handler; - p_spi_info->handler = 0; - handler(); - } - } -} -#define MASTER_EVENT_HANDLER(idx) \ - static void master_event_handler_##idx(nrf_drv_spi_evt_t const *p_event) { \ - master_event_handler(SPI##idx##_INSTANCE_INDEX, p_event); \ - } -#if SPI0_ENABLED - MASTER_EVENT_HANDLER(0) -#endif -#if SPI1_ENABLED - MASTER_EVENT_HANDLER(1) -#endif -#if SPI2_ENABLED - MASTER_EVENT_HANDLER(2) -#endif - -static nrf_drv_spi_handler_t const m_master_event_handlers[SPI_COUNT] = { -#if SPI0_ENABLED - master_event_handler_0, -#endif -#if SPI1_ENABLED - master_event_handler_1, -#endif -#if SPI2_ENABLED - master_event_handler_2, -#endif -}; - - -static void slave_event_handler(uint8_t spi_idx, - nrf_drv_spis_event_t event) -{ - spi_info_t *p_spi_info = &m_spi_info[spi_idx]; - - if (event.evt_type == NRF_DRV_SPIS_XFER_DONE) - { - // Signal that there is some data received that could be read. - p_spi_info->flag.readable = true; - - // And prepare for the next transfer. - // Previous data set in 'spi_slave_write' (if any) has been transmitted, - // now use the default one, until some new is set by 'spi_slave_write'. - p_spi_info->tx_buf = SPIS_DEFAULT_ORC; - nrf_drv_spis_buffers_set(&m_instances[spi_idx].slave, - (uint8_t const *)&p_spi_info->tx_buf, 1, - (uint8_t *)&p_spi_info->rx_buf, 1); - } -} -#define SLAVE_EVENT_HANDLER(idx) \ - static void slave_event_handler_##idx(nrf_drv_spis_event_t event) { \ - slave_event_handler(SPIS##idx##_INSTANCE_INDEX, event); \ - } -#if SPIS0_ENABLED - SLAVE_EVENT_HANDLER(0) -#endif -#if SPIS1_ENABLED - SLAVE_EVENT_HANDLER(1) -#endif -#if SPIS2_ENABLED - SLAVE_EVENT_HANDLER(2) -#endif - -static nrf_drv_spis_event_handler_t const m_slave_event_handlers[SPIS_COUNT] = { -#if SPIS0_ENABLED - slave_event_handler_0, -#endif -#if SPIS1_ENABLED - slave_event_handler_1, -#endif -#if SPIS2_ENABLED - slave_event_handler_2, -#endif -}; - -static void prepare_master_config(nrf_drv_spi_config_t *p_config, - spi_info_t const *p_spi_info) -{ - p_config->sck_pin = p_spi_info->sck_pin; - p_config->mosi_pin = p_spi_info->mosi_pin; - p_config->miso_pin = p_spi_info->miso_pin; - p_config->ss_pin = p_spi_info->ss_pin; - p_config->frequency = p_spi_info->frequency; - p_config->mode = (nrf_drv_spi_mode_t)p_spi_info->spi_mode; - - p_config->irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY; - p_config->orc = 0xFF; - p_config->bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST; -} - -static void prepare_slave_config(nrf_drv_spis_config_t *p_config, - spi_info_t const *p_spi_info) -{ - p_config->sck_pin = p_spi_info->sck_pin; - p_config->mosi_pin = p_spi_info->mosi_pin; - p_config->miso_pin = p_spi_info->miso_pin; - p_config->csn_pin = p_spi_info->ss_pin; - p_config->mode = (nrf_drv_spis_mode_t)p_spi_info->spi_mode; - - p_config->irq_priority = SPIS_DEFAULT_CONFIG_IRQ_PRIORITY; - p_config->orc = SPIS_DEFAULT_ORC; - p_config->def = SPIS_DEFAULT_DEF; - p_config->bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST; - p_config->csn_pullup = NRF_DRV_SPIS_DEFAULT_CSN_PULLUP; - p_config->miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE; -} - -void spi_init(spi_t *obj, - PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - int i; - - // This block is only a workaround that allows to create SPI object several - // times, what would be otherwise impossible in the current implementation - // of mbed driver that does not call spi_free() from SPI destructor. - // Once this mbed's imperfection is corrected, this block should be removed. - for (i = 0; i < SPI_COUNT; ++i) - { - spi_info_t *p_spi_info = &m_spi_info[i]; - - if (p_spi_info->initialized && - p_spi_info->mosi_pin == (uint8_t)mosi && - p_spi_info->miso_pin == (uint8_t)miso && - p_spi_info->sck_pin == (uint8_t)sclk && - p_spi_info->ss_pin == (uint8_t)ssel) - { - // Reuse the already allocated SPI instance (instead of allocating - // a new one), if it appears to be initialized with exactly the same - // pin assignments. - SPI_IDX(obj) = i; - return; - } - } - - for (i = 0; i < SPI_COUNT; ++i) - { - spi_info_t *p_spi_info = &m_spi_info[i]; - - if (!p_spi_info->initialized) - { - p_spi_info->sck_pin = (uint8_t)sclk; - p_spi_info->mosi_pin = (mosi != NC) ? - (uint8_t)mosi : NRF_DRV_SPI_PIN_NOT_USED; - p_spi_info->miso_pin = (miso != NC) ? - (uint8_t)miso : NRF_DRV_SPI_PIN_NOT_USED; - p_spi_info->ss_pin = (ssel != NC) ? - (uint8_t)ssel : NRF_DRV_SPI_PIN_NOT_USED; - p_spi_info->spi_mode = (uint8_t)NRF_DRV_SPI_MODE_0; - p_spi_info->frequency = NRF_DRV_SPI_FREQ_1M; - - NVIC_SetVector(spi_handler_desc[i].IRQn, spi_handler_desc[i].vector); - - // By default each SPI instance is initialized to work as a master. - // Should the slave mode be used, the instance will be reconfigured - // appropriately in 'spi_format'. - nrf_drv_spi_config_t config; - prepare_master_config(&config, p_spi_info); - - nrf_drv_spi_t const *p_spi = &m_instances[i].master; - ret_code_t ret_code = nrf_drv_spi_init(p_spi, - &config, m_master_event_handlers[i]); - if (ret_code == NRF_SUCCESS) - { - p_spi_info->initialized = true; - p_spi_info->master = true; - p_spi_info->flag.busy = false; -#if DEVICE_SPI_ASYNCH - p_spi_info->handler = 0; -#endif - SPI_IDX(obj) = i; - - return; - } - } - } - - // No available peripheral - error("No available SPI peripheral\r\n"); -} - -void spi_free(spi_t *obj) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - - if (p_spi_info->master) - { - nrf_drv_spi_uninit(MASTER_INST(obj)); - } - else - { - nrf_drv_spis_uninit(SLAVE_INST(obj)); - } - p_spi_info->initialized = false; -} - -int spi_busy(spi_t *obj) -{ - return (int)(SPI_INFO(obj)->flag.busy); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - if (bits != 8) - { - error("Only 8-bits SPI is supported\r\n"); - } - if (mode > 3) - { - error("SPI format error\r\n"); - } - - spi_info_t *p_spi_info = SPI_INFO(obj); - - if (slave) - { - nrf_drv_spis_mode_t spi_modes[4] = { - NRF_DRV_SPIS_MODE_0, - NRF_DRV_SPIS_MODE_1, - NRF_DRV_SPIS_MODE_2, - NRF_DRV_SPIS_MODE_3, - }; - nrf_drv_spis_mode_t new_mode = spi_modes[mode]; - - // If the peripheral is currently working as a master, the SDK driver - // it uses needs to be switched from SPI to SPIS. - if (p_spi_info->master) - { - nrf_drv_spi_uninit(MASTER_INST(obj)); - } - // I the SPI mode has to be changed, the SDK's SPIS driver needs to be - // re-initialized (there is no other way to change its configuration). - else if (p_spi_info->spi_mode != (uint8_t)new_mode) - { - nrf_drv_spis_uninit(SLAVE_INST(obj)); - } - else - { - return; - } - - p_spi_info->spi_mode = (uint8_t)new_mode; - p_spi_info->master = false; - p_spi_info->flag.readable = false; - - // Initialize SDK's SPIS driver with the new configuration. - nrf_drv_spis_config_t config; - prepare_slave_config(&config, p_spi_info); - (void)nrf_drv_spis_init(SLAVE_INST(obj), &config, - m_slave_event_handlers[SPI_IDX(obj)]); - - // Prepare the slave for transfer. - p_spi_info->tx_buf = SPIS_DEFAULT_ORC; - nrf_drv_spis_buffers_set(SLAVE_INST(obj), - (uint8_t const *)&p_spi_info->tx_buf, 1, - (uint8_t *)&p_spi_info->rx_buf, 1); - } - else // master - { - nrf_drv_spi_mode_t spi_modes[4] = { - NRF_DRV_SPI_MODE_0, - NRF_DRV_SPI_MODE_1, - NRF_DRV_SPI_MODE_2, - NRF_DRV_SPI_MODE_3, - }; - nrf_drv_spi_mode_t new_mode = spi_modes[mode]; - - // If the peripheral is currently working as a slave, the SDK driver - // it uses needs to be switched from SPIS to SPI. - if (!p_spi_info->master) - { - nrf_drv_spis_uninit(SLAVE_INST(obj)); - } - // I the SPI mode has to be changed, the SDK's SPI driver needs to be - // re-initialized (there is no other way to change its configuration). - else if (p_spi_info->spi_mode != (uint8_t)new_mode) - { - nrf_drv_spi_uninit(MASTER_INST(obj)); - } - else - { - return; - } - - p_spi_info->spi_mode = (uint8_t)new_mode; - p_spi_info->master = true; - p_spi_info->flag.busy = false; - - // Initialize SDK's SPI driver with the new configuration. - nrf_drv_spi_config_t config; - prepare_master_config(&config, p_spi_info); - (void)nrf_drv_spi_init(MASTER_INST(obj), &config, - m_master_event_handlers[SPI_IDX(obj)]); - } -} - -static nrf_drv_spi_frequency_t freq_translate(int hz) -{ - nrf_drv_spi_frequency_t frequency; - - if (hz<250000) //125Kbps - { - frequency = NRF_DRV_SPI_FREQ_125K; - } - else if (hz<500000) //250Kbps - { - frequency = NRF_DRV_SPI_FREQ_250K; - } - else if (hz<1000000) //500Kbps - { - frequency = NRF_DRV_SPI_FREQ_500K; - } - else if (hz<2000000) //1Mbps - { - frequency = NRF_DRV_SPI_FREQ_1M; - } - else if (hz<4000000) //2Mbps - { - frequency = NRF_DRV_SPI_FREQ_2M; - } - else if (hz<8000000) //4Mbps - { - frequency = NRF_DRV_SPI_FREQ_4M; - } - else //8Mbps - { - frequency = NRF_DRV_SPI_FREQ_8M; - } - return frequency; -} - -void spi_frequency(spi_t *obj, int hz) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - nrf_drv_spi_frequency_t new_frequency = freq_translate(hz); - - if (p_spi_info->master) - { - if (p_spi_info->frequency != new_frequency) - { - p_spi_info->frequency = new_frequency; - - nrf_drv_spi_config_t config; - prepare_master_config(&config, p_spi_info); - - nrf_drv_spi_t const *p_spi = MASTER_INST(obj); - nrf_drv_spi_uninit(p_spi); - (void)nrf_drv_spi_init(p_spi, &config, - m_master_event_handlers[SPI_IDX(obj)]); - } - } - // There is no need to set anything in slaves when it comes to frequency, - // since slaves just synchronize with the clock provided by a master. -} - -int spi_master_write(spi_t *obj, int value) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - -#if DEVICE_SPI_ASYNCH - - while (p_spi_info->flag.busy) - { - } -#endif - - p_spi_info->tx_buf = value; - p_spi_info->flag.busy = true; - (void)nrf_drv_spi_transfer(MASTER_INST(obj), - (uint8_t const *)&p_spi_info->tx_buf, 1, - (uint8_t *)&p_spi_info->rx_buf, 1); - - while (p_spi_info->flag.busy) - { - } - - return p_spi_info->rx_buf; -} - -int spi_slave_receive(spi_t *obj) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - MBED_ASSERT(!p_spi_info->master); - return p_spi_info->flag.readable; -} - -int spi_slave_read(spi_t *obj) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - MBED_ASSERT(!p_spi_info->master); - - while (!p_spi_info->flag.readable) - { - } - p_spi_info->flag.readable = false; - return p_spi_info->rx_buf; -} - -void spi_slave_write(spi_t *obj, int value) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - MBED_ASSERT(!p_spi_info->master); - - p_spi_info->tx_buf = (uint8_t)value; -} - -#if DEVICE_SPI_ASYNCH - -void spi_master_transfer(spi_t *obj, - const void *tx, size_t tx_length, - void *rx, size_t rx_length, uint8_t bit_width, - uint32_t handler, uint32_t event, DMAUsage hint) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - MBED_ASSERT(p_spi_info->master); - (void)hint; - (void)bit_width; - - p_spi_info->handler = handler; - p_spi_info->event = event; - - p_spi_info->flag.busy = true; - (void)nrf_drv_spi_transfer(MASTER_INST(obj), - (uint8_t const *)tx, tx_length, - (uint8_t *)rx, rx_length); -} - -uint32_t spi_irq_handler_asynch(spi_t *obj) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - MBED_ASSERT(p_spi_info->master); - return p_spi_info->event & SPI_EVENT_COMPLETE; -} - -uint8_t spi_active(spi_t *obj) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - MBED_ASSERT(p_spi_info->master); - return p_spi_info->flag.busy; -} - -void spi_abort_asynch(spi_t *obj) -{ - MBED_ASSERT(SPI_INFO(obj)->master); - nrf_drv_spi_abort(MASTER_INST(obj)); -} - -#endif // DEVICE_SPI_ASYNCH - -#endif // DEVICE_SPI diff --git a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/us_ticker.c b/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/us_ticker.c deleted file mode 100644 index f716e235bb4..00000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5_SDK13/us_ticker.c +++ /dev/null @@ -1,636 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "us_ticker_api.h" -#include "common_rtc.h" -#include "app_util.h" -#include "nrf_drv_common.h" -#include "lp_ticker_api.h" -#include "mbed_critical.h" - -#if defined(NRF52_ERRATA_20) - #include "softdevice_handler.h" -#endif - -//------------------------------------------------------------------------------ -// Common stuff used also by lp_ticker and rtc_api (see "common_rtc.h"). -// -#include "app_util_platform.h" - -bool m_common_rtc_enabled = false; -uint32_t volatile m_common_rtc_overflows = 0; - -__STATIC_INLINE void rtc_ovf_event_check(void) -{ - if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) { - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW); - // Don't disable this event. It shall occur periodically. - - ++m_common_rtc_overflows; - } -} - -#if defined(TARGET_MCU_NRF51822) -void common_rtc_irq_handler(void) -#else -void COMMON_RTC_IRQ_HANDLER(void) -#endif -{ - - rtc_ovf_event_check(); - - if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT)) { - us_ticker_irq_handler(); - } - -#if DEVICE_LOWPOWERTIMER - if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT)) { - - lp_ticker_irq_handler(); - } -#endif - -} - -// Function for fix errata 20: RTC Register values are invalid -__STATIC_INLINE void errata_20(void) -{ -#if defined(NRF52_ERRATA_20) - if (!softdevice_handler_is_enabled()) - { - NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; - NRF_CLOCK->TASKS_LFCLKSTART = 1; - - while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) - { - } - } - NRF_RTC1->TASKS_STOP = 0; -#endif -} - -#if (defined (__ICCARM__)) && defined(TARGET_MCU_NRF51822)//IAR -__stackless __task -#endif -void RTC1_IRQHandler(void); - -void common_rtc_init(void) -{ - if (m_common_rtc_enabled) { - return; - } - - errata_20(); - - NVIC_SetVector(RTC1_IRQn, (uint32_t)RTC1_IRQHandler); - - // RTC is driven by the low frequency (32.768 kHz) clock, a proper request - // must be made to have it running. - // Currently this clock is started in 'SystemInit' (see "system_nrf51.c" - // or "system_nrf52.c", respectively). - - nrf_rtc_prescaler_set(COMMON_RTC_INSTANCE, 0); - - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT); -#if defined(TARGET_MCU_NRF51822) - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT); -#endif -#if DEVICE_LOWPOWERTIMER - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT); -#endif - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW); - - // Interrupts on all related events are enabled permanently. Particular - // events will be enabled or disabled as needed (such approach is more - // energy efficient). - nrf_rtc_int_enable(COMMON_RTC_INSTANCE, -#if DEVICE_LOWPOWERTIMER - LP_TICKER_INT_MASK | -#endif - US_TICKER_INT_MASK | - NRF_RTC_INT_OVERFLOW_MASK); - - // This event is enabled permanently, since overflow indications are needed - // continuously. - nrf_rtc_event_enable(COMMON_RTC_INSTANCE, NRF_RTC_INT_OVERFLOW_MASK); - // All other relevant events are initially disabled. - nrf_rtc_event_disable(COMMON_RTC_INSTANCE, -#if defined(TARGET_MCU_NRF51822) - OS_TICK_INT_MASK | -#endif -#if DEVICE_LOWPOWERTIMER - LP_TICKER_INT_MASK | -#endif - US_TICKER_INT_MASK); - - nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE), -#ifdef NRF51 - APP_IRQ_PRIORITY_LOW -#elif defined(NRF52) || defined(NRF52840_XXAA) - APP_IRQ_PRIORITY_LOWEST -#endif - ); - - nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_START); - - m_common_rtc_enabled = true; -} - -__STATIC_INLINE void rtc_ovf_event_safe_check(void) -{ - core_util_critical_section_enter(); - - rtc_ovf_event_check(); - - core_util_critical_section_exit(); -} - - -uint32_t common_rtc_32bit_ticks_get(void) -{ - uint32_t ticks; - uint32_t prev_overflows; - - do { - prev_overflows = m_common_rtc_overflows; - - ticks = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); - // The counter used for time measurements is less than 32 bit wide, - // so its value is complemented with the number of registered overflows - // of the counter. - ticks += (m_common_rtc_overflows << RTC_COUNTER_BITS); - - // Check in case that OVF occurred during execution of a RTC handler (apply if call was from RTC handler) - // m_common_rtc_overflows might been updated in this call. - rtc_ovf_event_safe_check(); - - // If call was made from a low priority level m_common_rtc_overflows might have been updated in RTC handler. - } while (m_common_rtc_overflows != prev_overflows); - - return ticks; -} - -uint64_t common_rtc_64bit_us_get(void) -{ - uint32_t ticks = common_rtc_32bit_ticks_get(); - // [ticks -> microseconds] - return ROUNDED_DIV(((uint64_t)ticks) * 1000000, RTC_INPUT_FREQ); -} - -void common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel, - uint32_t int_mask) -{ - // The internal counter is clocked with a frequency that cannot be easily - // multiplied to 1 MHz, therefore besides the translation of values - // (microsecond <-> ticks) a special care of overflows handling must be - // taken. Here the 32-bit timestamp value is complemented with information - // about current the system up time of (ticks + number of overflows of tick - // counter on upper bits, converted to microseconds), and such 64-bit value - // is then translated to counter ticks. Finally, the lower 24 bits of thus - // calculated value is written to the counter compare register to prepare - // the interrupt generation. - uint64_t current_time64 = common_rtc_64bit_us_get(); - // [add upper 32 bits from the current time to the timestamp value] - uint64_t timestamp64 = us_timestamp + - (current_time64 & ~(uint64_t)0xFFFFFFFF); - // [if the original timestamp value happens to be after the 32 bit counter - // of microsends overflows, correct the upper 32 bits accordingly] - if (us_timestamp < (uint32_t)(current_time64 & 0xFFFFFFFF)) { - timestamp64 += ((uint64_t)1 << 32); - } - // [microseconds -> ticks, always round the result up to avoid too early - // interrupt generation] - uint32_t compare_value = - (uint32_t)CEIL_DIV((timestamp64) * RTC_INPUT_FREQ, 1000000); - - core_util_critical_section_enter(); - // The COMPARE event occurs when the value in compare register is N and - // the counter value changes from N-1 to N. Therefore, the minimal safe - // difference between the compare value to be set and the current counter - // value is 2 ticks. This guarantees that the compare trigger is properly - // setup before the compare condition occurs. - uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2; - if ((int)(compare_value - closest_safe_compare) <= 0) { - compare_value = closest_safe_compare; - } - - nrf_rtc_cc_set(COMMON_RTC_INSTANCE, cc_channel, RTC_WRAP(compare_value)); - nrf_rtc_event_enable(COMMON_RTC_INSTANCE, int_mask); - core_util_critical_section_exit(); -} -//------------------------------------------------------------------------------ - - -void us_ticker_init(void) -{ - common_rtc_init(); -} - -uint32_t us_ticker_read() -{ - us_ticker_init(); - return (uint32_t)common_rtc_64bit_us_get(); -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - common_rtc_set_interrupt(timestamp, - US_TICKER_CC_CHANNEL, US_TICKER_INT_MASK); -} - -void us_ticker_disable_interrupt(void) -{ - nrf_rtc_event_disable(COMMON_RTC_INSTANCE, US_TICKER_INT_MASK); -} - -void us_ticker_clear_interrupt(void) -{ - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT); -} - - -// Since there is no SysTick on NRF51, the RTC1 channel 1 is used as an -// alternative source of RTOS ticks. -#if defined(TARGET_MCU_NRF51822) - -#include "mbed_toolchain.h" - - -#define MAX_RTC_COUNTER_VAL ((1uL << RTC_COUNTER_BITS) - 1) - -/** - * The value previously set in the capture compare register of channel 1 - */ -static uint32_t previous_tick_cc_value = 0; - -/* - RTX provide the following definitions which are used by the tick code: - * os_trv: The number (minus 1) of clock cycle between two tick. - * os_clockrate: Time duration between two ticks (in us). - * OS_Tick_Handler: The function which handle a tick event. - This function is special because it never returns. - Those definitions are used by the code which handle the os tick. - To allow compilation of us_ticker programs without RTOS, those symbols are - exported from this module as weak ones. - */ -MBED_WEAK uint32_t const os_trv; -MBED_WEAK uint32_t const os_clockrate; -MBED_WEAK void OS_Tick_Handler(void) -{ -} - - -#if defined (__CC_ARM) /* ARMCC Compiler */ - -__asm void COMMON_RTC_IRQ_HANDLER(void) -{ - IMPORT OS_Tick_Handler - IMPORT common_rtc_irq_handler - - /** - * Chanel 1 of RTC1 is used by RTX as a systick. - * If the compare event on channel 1 is set, then branch to OS_Tick_Handler. - * Otherwise, just execute common_rtc_irq_handler. - * This function has to be written in assembly and tagged as naked because OS_Tick_Handler - * will never return. - * A c function would put lr on the stack before calling OS_Tick_Handler and this value - * would never been dequeued. - * - * \code - * void COMMON_RTC_IRQ_HANDLER(void) { - if(NRF_RTC1->EVENTS_COMPARE[1]) { - // never return... - OS_Tick_Handler(); - } else { - common_rtc_irq_handler(); - } - } - * \endcode - */ - ldr r0,=0x40011144 - ldr r1, [r0, #0] - cmp r1, #0 - beq US_TICKER_HANDLER - bl OS_Tick_Handler -US_TICKER_HANDLER - push {r3, lr} - bl common_rtc_irq_handler - pop {r3, pc} - ; ALIGN ; -} - -#elif defined (__GNUC__) /* GNU Compiler */ - -__attribute__((naked)) void COMMON_RTC_IRQ_HANDLER(void) -{ - /** - * Chanel 1 of RTC1 is used by RTX as a systick. - * If the compare event on channel 1 is set, then branch to OS_Tick_Handler. - * Otherwise, just execute common_rtc_irq_handler. - * This function has to be written in assembly and tagged as naked because OS_Tick_Handler - * will never return. - * A c function would put lr on the stack before calling OS_Tick_Handler and this value - * would never been dequeued. - * - * \code - * void COMMON_RTC_IRQ_HANDLER(void) { - if(NRF_RTC1->EVENTS_COMPARE[1]) { - // never return... - OS_Tick_Handler(); - } else { - common_rtc_irq_handler(); - } - } - * \endcode - */ - __asm__ ( - "ldr r0,=0x40011144\n" - "ldr r1, [r0, #0]\n" - "cmp r1, #0\n" - "beq US_TICKER_HANDLER\n" - "bl OS_Tick_Handler\n" - "US_TICKER_HANDLER:\n" - "push {r3, lr}\n" - "bl common_rtc_irq_handler\n" - "pop {r3, pc}\n" - "nop" - ); -} - -#elif defined (__ICCARM__)//IAR -void common_rtc_irq_handler(void); - -__stackless __task void COMMON_RTC_IRQ_HANDLER(void) -{ - uint32_t temp; - - __asm volatile( - " ldr %[temp], [%[reg2check]] \n" - " cmp %[temp], #0 \n" - " beq 1f \n" - " bl.w OS_Tick_Handler \n" - "1: \n" - " push {r3, lr}\n" - " blx %[rtc_irq] \n" - " pop {r3, pc}\n" - - : /* Outputs */ - [temp] "=&r"(temp) - : /* Inputs */ - [reg2check] "r"(0x40011144), - [rtc_irq] "r"(common_rtc_irq_handler) - : /* Clobbers */ - "cc" - ); - (void)temp; -} - - -#else - -#error Compiler not supported. -#error Provide a definition of COMMON_RTC_IRQ_HANDLER. - -/* - * Chanel 1 of RTC1 is used by RTX as a systick. - * If the compare event on channel 1 is set, then branch to OS_Tick_Handler. - * Otherwise, just execute common_rtc_irq_handler. - * This function has to be written in assembly and tagged as naked because OS_Tick_Handler - * will never return. - * A c function would put lr on the stack before calling OS_Tick_Handler and this value - * will never been dequeued. After a certain time a stack overflow will happen. - * - * \code - * void COMMON_RTC_IRQ_HANDLER(void) { - if(NRF_RTC1->EVENTS_COMPARE[1]) { - // never return... - OS_Tick_Handler(); - } else { - common_rtc_irq_handler(); - } - } - * \endcode - */ - -#endif - -/** - * Return the next number of clock cycle needed for the next tick. - * @note This function has been carrefuly optimized for a systick occuring every 1000us. - */ -static uint32_t get_next_tick_cc_delta() -{ - uint32_t delta = 0; - - if (os_clockrate != 1000) { - // In RTX, by default SYSTICK is is used. - // A tick event is generated every os_trv + 1 clock cycles of the system timer. - delta = os_trv + 1; - } else { - // If the clockrate is set to 1000us then 1000 tick should happen every second. - // Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31. - // If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be - // generated in 32000 clock cycle instead of 32768 clock cycles. - // As a result, if a user schedule an OS timer to start in 100s, the timer will start - // instead after 97.656s - // The code below fix this issue, a clock rate of 1000s will generate 1000 ticks in 32768 - // clock cycles. - // The strategy is simple, for 1000 ticks: - // * 768 ticks will occur 33 clock cycles after the previous tick - // * 232 ticks will occur 32 clock cycles after the previous tick - // By default every delta is equal to 33. - // Every five ticks (20%, 200 delta in one second), the delta is equal to 32 - // The remaining (32) deltas equal to 32 are distributed using primes numbers. - static uint32_t counter = 0; - if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) { - delta = 32; - } else { - delta = 33; - } - ++counter; - if (counter == 1000) { - counter = 0; - } - } - return delta; -} - -static inline void clear_tick_interrupt() -{ - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT); - nrf_rtc_event_disable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK); -} - -/** - * Indicate if a value is included in a range which can be wrapped. - * @param begin start of the range - * @param end end of the range - * @param val value to check - * @return true if the value is included in the range and false otherwise. - */ -static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val) -{ - // regular case, begin < end - // return true if begin <= val < end - if (begin < end) { - if (begin <= val && val < end) { - return true; - } else { - return false; - } - } else { - // In this case end < begin because it has wrap around the limits - // return false if end < val < begin - if (end < val && val < begin) { - return false; - } else { - return true; - } - } - -} - -/** - * Register the next tick. - */ -static void register_next_tick() -{ - previous_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL); - uint32_t delta = get_next_tick_cc_delta(); - uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL; - - // Disable irq directly for few cycles, - // Validation of the new CC value against the COUNTER, - // Setting the new CC value and enabling CC IRQ should be an atomic operation - // Otherwise, there is a possibility to set an invalid CC value because - // the RTC1 keeps running. - // This code is very short 20-38 cycles in the worst case, it shouldn't - // disturb softdevice. - core_util_critical_section_enter(); - uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); - - // If an overflow occur, set the next tick in COUNTER + delta clock cycles - if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter + 1) == false) { - new_compare_value = current_counter + delta; - } - nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, new_compare_value); - // Enable generation of the compare event for the value set above (this - // event will trigger the interrupt). - nrf_rtc_event_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK); - core_util_critical_section_exit(); -} - -/** - * Initialize alternative hardware timer as RTX kernel timer - * This function is directly called by RTX. - * @note this function shouldn't be called directly. - * @return IRQ number of the alternative hardware timer - */ -int os_tick_init (void) -{ - common_rtc_init(); - nrf_rtc_int_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK); - - nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, 0); - register_next_tick(); - - return nrf_drv_get_IRQn(COMMON_RTC_INSTANCE); -} - -/** - * Acknowledge the tick interrupt. - * This function is called by the function OS_Tick_Handler of RTX. - * @note this function shouldn't be called directly. - */ -void os_tick_irqack(void) -{ - clear_tick_interrupt(); - register_next_tick(); -} - -/** - * Returns the overflow flag of the alternative hardware timer. - * @note This function is exposed by RTX kernel. - * @return 1 if the timer has overflowed and 0 otherwise. - */ -uint32_t os_tick_ovf(void) -{ - uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); - uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL); - - return is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter) ? 0 : 1; -} - -/** - * Return the value of the alternative hardware timer. - * @note The documentation is not very clear about what is expected as a result, - * is it an ascending counter, a descending one ? - * None of this is specified. - * The default systick is a descending counter and this function return values in - * descending order, even if the internal counter used is an ascending one. - * @return the value of the alternative hardware timer. - */ -uint32_t os_tick_val(void) -{ - uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); - uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL); - - // do not use os_tick_ovf because its counter value can be different - if(is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter)) { - if (next_tick_cc_value > previous_tick_cc_value) { - return next_tick_cc_value - current_counter; - } else if(current_counter <= next_tick_cc_value) { - return next_tick_cc_value - current_counter; - } else { - return next_tick_cc_value + (MAX_RTC_COUNTER_VAL - current_counter); - } - } else { - // use (os_trv + 1) has the base step, can be totally inacurate ... - uint32_t clock_cycles_by_tick = os_trv + 1; - - // if current counter has wrap arround, add the limit to it. - if (current_counter < next_tick_cc_value) { - current_counter = current_counter + MAX_RTC_COUNTER_VAL; - } - - return clock_cycles_by_tick - ((current_counter - next_tick_cc_value) % clock_cycles_by_tick); - } - -} - -#endif // defined(TARGET_MCU_NRF51822) diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h index 7191422fa09..6744a32ce9a 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h @@ -61,6 +61,7 @@ struct serial_s { void (*vec)(void); uint32_t irq_handler; uint32_t irq_id; + uint32_t irq_en; uint32_t inten_msk; // Async transfer related fields diff --git a/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c b/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c index 0bfc53f4855..ab7fdff47d2 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/dma_api.c @@ -23,6 +23,10 @@ #include "nu_bitutil.h" #include "dma.h" +#define NU_PDMA_CH_MAX PDMA_CH_MAX /* Specify maximum channels of PDMA */ +#define NU_PDMA_CH_Pos 0 /* Specify first channel number of PDMA */ +#define NU_PDMA_CH_Msk (((1 << NU_PDMA_CH_MAX) - 1) << NU_PDMA_CH_Pos) + struct nu_dma_chn_s { void (*handler)(uint32_t, uint32_t); uint32_t id; @@ -31,7 +35,7 @@ struct nu_dma_chn_s { static int dma_inited = 0; static uint32_t dma_chn_mask = 0; -static struct nu_dma_chn_s dma_chn_arr[PDMA_CH_MAX]; +static struct nu_dma_chn_s dma_chn_arr[NU_PDMA_CH_MAX]; static void pdma_vec(void); static const struct nu_modinit_s dma_modinit = {DMA_0, PDMA_MODULE, 0, 0, PDMA_RST, PDMA_IRQn, (void *) pdma_vec}; @@ -44,7 +48,7 @@ void dma_init(void) } dma_inited = 1; - dma_chn_mask = 0; + dma_chn_mask = ~NU_PDMA_CH_Msk; memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr)); // Reset this module @@ -65,25 +69,12 @@ int dma_channel_allocate(uint32_t capabilities) dma_init(); } -#if 1 int i = nu_cto(dma_chn_mask); if (i != 32) { dma_chn_mask |= 1 << i; - memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s)); + memset(dma_chn_arr + i - NU_PDMA_CH_Pos, 0x00, sizeof (struct nu_dma_chn_s)); return i; } -#else - int i; - - for (i = 0; i < PDMA_CH_MAX; i ++) { - if ((dma_chn_mask & (1 << i)) == 0) { - // Channel available - dma_chn_mask |= 1 << i; - memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s)); - return i; - } - } -#endif // No channel available return DMA_ERROR_OUT_OF_CHANNELS; @@ -102,9 +93,9 @@ void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t even { MBED_ASSERT(dma_chn_mask & (1 << channelid)); - dma_chn_arr[channelid].handler = (void (*)(uint32_t, uint32_t)) handler; - dma_chn_arr[channelid].id = id; - dma_chn_arr[channelid].event = event; + dma_chn_arr[channelid - NU_PDMA_CH_Pos].handler = (void (*)(uint32_t, uint32_t)) handler; + dma_chn_arr[channelid - NU_PDMA_CH_Pos].id = id; + dma_chn_arr[channelid - NU_PDMA_CH_Pos].event = event; // Set interrupt vector if someone has removed it. NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var); @@ -127,14 +118,14 @@ static void pdma_vec(void) PDMA_CLR_ABORT_FLAG(abtsts); while (abtsts) { - int chn_id = nu_ctz(abtsts); + int chn_id = nu_ctz(abtsts) - PDMA_ABTSTS_ABTIFn_Pos + NU_PDMA_CH_Pos; if (dma_chn_mask & (1 << chn_id)) { - struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) { dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT); } } - abtsts &= ~(1 << chn_id); + abtsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_ABTSTS_ABTIFn_Pos)); } } @@ -145,14 +136,14 @@ static void pdma_vec(void) PDMA_CLR_TD_FLAG(tdsts); while (tdsts) { - int chn_id = nu_ctz(tdsts); + int chn_id = nu_ctz(tdsts) - PDMA_TDSTS_TDIFn_Pos + NU_PDMA_CH_Pos; if (dma_chn_mask & (1 << chn_id)) { - struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) { dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE); } } - tdsts &= ~(1 << chn_id); + tdsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_TDSTS_TDIFn_Pos)); } } @@ -170,14 +161,14 @@ static void pdma_vec(void) PDMA->INTSTS = reqto; while (reqto) { - int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOFn_Pos; + int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOFn_Pos + NU_PDMA_CH_Pos; if (dma_chn_mask & (1 << chn_id)) { - struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) { dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT); } } - reqto &= ~(1 << (chn_id + PDMA_INTSTS_REQTOFn_Pos)); + reqto &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_INTSTS_REQTOFn_Pos)); } } } diff --git a/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c index f04d1b8b057..f89dc4f6a00 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c @@ -99,11 +99,9 @@ void pwmout_init(pwmout_t* obj, PinName pin) ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn; - if (((struct nu_pwm_var *) modinit->var)->en_msk) { - // Mark this module to be inited. - int i = modinit - pwm_modinit_tab; - pwm_modinit_mask |= 1 << i; - } + // Mark this module to be inited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask |= 1 << i; } void pwmout_free(pwmout_t* obj) @@ -122,11 +120,9 @@ void pwmout_free(pwmout_t* obj) CLK_DisableModuleClock(modinit->clkidx); } - if (((struct nu_pwm_var *) modinit->var)->en_msk == 0) { - // Mark this module to be deinited. - int i = modinit - pwm_modinit_tab; - pwm_modinit_mask &= ~(1 << i); - } + // Mark this module to be deinited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask &= ~(1 << i); } void pwmout_write(pwmout_t* obj, float value) diff --git a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c index 30eb950285f..4fa7e7a47ac 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c @@ -24,6 +24,7 @@ #include "PeripheralPins.h" #include "nu_modutil.h" #include "nu_bitutil.h" +#include #if DEVICE_SERIAL_ASYNCH #include "dma_api.h" @@ -61,6 +62,8 @@ static void uart_dma_handler_rx(uint32_t id, uint32_t event); static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable); static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable); +static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable); +static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq); static int serial_write_async(serial_t *obj); static int serial_read_async(serial_t *obj); @@ -159,7 +162,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; @@ -186,6 +189,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) serial_format(obj, 8, ParityNone, 1); obj->serial.vec = var->vec; + obj->serial.irq_en = 0; #if DEVICE_SERIAL_ASYNCH obj->serial.dma_usage_tx = DMA_USAGE_NEVER; @@ -212,7 +216,7 @@ void serial_free(serial_t *obj) { const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; @@ -329,7 +333,7 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); obj->serial.irq_handler = (uint32_t) handler; obj->serial.irq_id = id; @@ -340,51 +344,18 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - if (enable) { - const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); - MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); - - NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec); - NVIC_EnableIRQ(modinit->irq_n); - - struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; - // Multiple serial S/W objects for single UART H/W module possibly. - // Bind serial S/W object to UART H/W module as interrupt is enabled. - var->obj = obj; - - switch (irq) { - // NOTE: Setting inten_msk first to avoid race condition - case RxIrq: - obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); - UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); - break; - case TxIrq: - obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk; - UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); - break; - } - } else { // disable - switch (irq) { - case RxIrq: - UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); - obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); - break; - case TxIrq: - UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); - obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk; - break; - } - } + obj->serial.irq_en = enable; + serial_enable_interrupt(obj, irq, enable); } int serial_getc(serial_t *obj) { - // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much. + // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation. while (! serial_readable(obj)); int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); - // Simulate clear of the interrupt flag + // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq. + // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively. if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); } @@ -394,11 +365,12 @@ int serial_getc(serial_t *obj) void serial_putc(serial_t *obj, int c) { - // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much. + // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation. while (! serial_writable(obj)); UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c); - // Simulate clear of the interrupt flag + // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq. + // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively. if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); } @@ -500,7 +472,7 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx // DMA way const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); PDMA_T *pdma_base = dma_modbase(); @@ -563,7 +535,7 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt // DMA way const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); PDMA_T *pdma_base = dma_modbase(); @@ -612,10 +584,8 @@ void serial_tx_abort_asynch(serial_t *obj) } // Necessary for both interrupt way and DMA way - serial_irq_set(obj, TxIrq, 0); - // FIXME: more complete abort operation - //UART_HAL_DisableTransmitter(obj->serial.serial.address); - //UART_HAL_FlushTxFifo(obj->serial.serial.address); + serial_enable_interrupt(obj, TxIrq, 0); + serial_rollback_interrupt(obj, TxIrq); } void serial_rx_abort_asynch(serial_t *obj) @@ -633,20 +603,30 @@ void serial_rx_abort_asynch(serial_t *obj) } // Necessary for both interrupt way and DMA way - serial_irq_set(obj, RxIrq, 0); - // FIXME: more complete abort operation - //UART_HAL_DisableReceiver(obj->serial.serial.address); - //UART_HAL_FlushRxFifo(obj->serial.serial.address); + serial_enable_interrupt(obj, RxIrq, 0); + serial_rollback_interrupt(obj, RxIrq); } uint8_t serial_tx_active(serial_t *obj) { - return serial_is_irq_en(obj, TxIrq); + // NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag. + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + return (obj->serial.vec == var->vec_async); } uint8_t serial_rx_active(serial_t *obj) { - return serial_is_irq_en(obj, RxIrq); + // NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag. + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + return (obj->serial.vec == var->vec_async); } int serial_irq_handler_asynch(serial_t *obj) @@ -886,7 +866,7 @@ static int serial_write_async(serial_t *obj) { const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); @@ -938,7 +918,7 @@ static int serial_read_async(serial_t *obj) { const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos; //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy; @@ -1013,28 +993,81 @@ static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t { const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); // Necessary for both interrupt way and DMA way struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; // With our own async vector, tx/rx handlers can be different. obj->serial.vec = var->vec_async; obj->serial.irq_handler_tx_async = (void (*)(void)) handler; - serial_irq_set(obj, TxIrq, enable); + serial_enable_interrupt(obj, TxIrq, enable); } static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable) { const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); // Necessary for both interrupt way and DMA way struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; // With our own async vector, tx/rx handlers can be different. obj->serial.vec = var->vec_async; obj->serial.irq_handler_rx_async = (void (*) (void)) handler; - serial_irq_set(obj, RxIrq, enable); + serial_enable_interrupt(obj, RxIrq, enable); +} + +static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + if (enable) { + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec); + NVIC_EnableIRQ(modinit->irq_n); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + // Multiple serial S/W objects for single UART H/W module possibly. + // Bind serial S/W object to UART H/W module as interrupt is enabled. + var->obj = obj; + + switch (irq) { + // NOTE: Setting inten_msk first to avoid race condition + case RxIrq: + obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + break; + case TxIrq: + obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk; + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + break; + } + } + else { // disable + switch (irq) { + case RxIrq: + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + break; + case TxIrq: + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk; + break; + } + } +} + +static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + + obj->serial.vec = var->vec; + serial_enable_interrupt(obj, irq, obj->serial.irq_en); } static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch) diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h index 2f0596770b3..2e62f15efc7 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h @@ -61,6 +61,7 @@ struct serial_s { void (*vec)(void); uint32_t irq_handler; uint32_t irq_id; + uint32_t irq_en; uint32_t inten_msk; // Async transfer related fields diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/dma_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/dma_api.c index 1b789090f3c..257fe019ae5 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/dma_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/dma_api.c @@ -23,6 +23,10 @@ #include "nu_bitutil.h" #include "dma.h" +#define NU_PDMA_CH_MAX PDMA_CH_MAX /* Specify maximum channels of PDMA */ +#define NU_PDMA_CH_Pos 0 /* Specify first channel number of PDMA */ +#define NU_PDMA_CH_Msk (((1 << NU_PDMA_CH_MAX) - 1) << NU_PDMA_CH_Pos) + struct nu_dma_chn_s { void (*handler)(uint32_t, uint32_t); uint32_t id; @@ -31,7 +35,7 @@ struct nu_dma_chn_s { static int dma_inited = 0; static uint32_t dma_chn_mask = 0; -static struct nu_dma_chn_s dma_chn_arr[PDMA_CH_MAX]; +static struct nu_dma_chn_s dma_chn_arr[NU_PDMA_CH_MAX]; static void pdma_vec(void); static const struct nu_modinit_s dma_modinit = {DMA_0, PDMA_MODULE, 0, 0, PDMA_RST, PDMA_IRQn, (void *) pdma_vec}; @@ -44,7 +48,7 @@ void dma_init(void) } dma_inited = 1; - dma_chn_mask = 0; + dma_chn_mask = ~NU_PDMA_CH_Msk; memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr)); // Reset this module @@ -65,25 +69,12 @@ int dma_channel_allocate(uint32_t capabilities) dma_init(); } -#if 1 int i = nu_cto(dma_chn_mask); if (i != 32) { dma_chn_mask |= 1 << i; - memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s)); + memset(dma_chn_arr + i - NU_PDMA_CH_Pos, 0x00, sizeof (struct nu_dma_chn_s)); return i; } -#else - int i; - - for (i = 0; i < PDMA_CH_MAX; i ++) { - if ((dma_chn_mask & (1 << i)) == 0) { - // Channel available - dma_chn_mask |= 1 << i; - memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s)); - return i; - } - } -#endif // No channel available return DMA_ERROR_OUT_OF_CHANNELS; @@ -102,9 +93,9 @@ void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t even { MBED_ASSERT(dma_chn_mask & (1 << channelid)); - dma_chn_arr[channelid].handler = (void (*)(uint32_t, uint32_t)) handler; - dma_chn_arr[channelid].id = id; - dma_chn_arr[channelid].event = event; + dma_chn_arr[channelid - NU_PDMA_CH_Pos].handler = (void (*)(uint32_t, uint32_t)) handler; + dma_chn_arr[channelid - NU_PDMA_CH_Pos].id = id; + dma_chn_arr[channelid - NU_PDMA_CH_Pos].event = event; // Set interrupt vector if someone has removed it. NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var); @@ -127,14 +118,14 @@ static void pdma_vec(void) PDMA_CLR_ABORT_FLAG(abtsts); while (abtsts) { - int chn_id = nu_ctz(abtsts); + int chn_id = nu_ctz(abtsts) - PDMA_ABTSTS_ABTIF_Pos + NU_PDMA_CH_Pos; if (dma_chn_mask & (1 << chn_id)) { - struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) { dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT); } } - abtsts &= ~(1 << chn_id); + abtsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_ABTSTS_ABTIF_Pos)); } } @@ -145,14 +136,14 @@ static void pdma_vec(void) PDMA_CLR_TD_FLAG(tdsts); while (tdsts) { - int chn_id = nu_ctz(tdsts); + int chn_id = nu_ctz(tdsts) - PDMA_TDSTS_TDIF_Pos + NU_PDMA_CH_Pos; if (dma_chn_mask & (1 << chn_id)) { - struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) { dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE); } } - tdsts &= ~(1 << chn_id); + tdsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_TDSTS_TDIF_Pos)); } } @@ -170,14 +161,14 @@ static void pdma_vec(void) PDMA->INTSTS = reqto; while (reqto) { - int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOFX_Pos; + int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOFX_Pos + NU_PDMA_CH_Pos; if (dma_chn_mask & (1 << chn_id)) { - struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) { dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT); } } - reqto &= ~(1 << (chn_id + PDMA_INTSTS_REQTOFX_Pos)); + reqto &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_INTSTS_REQTOFX_Pos)); } } } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c index 2ca1cd49cd3..90165697c63 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c @@ -105,11 +105,9 @@ void pwmout_init(pwmout_t* obj, PinName pin) ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn; - if (((struct nu_pwm_var *) modinit->var)->en_msk) { - // Mark this module to be inited. - int i = modinit - pwm_modinit_tab; - pwm_modinit_mask |= 1 << i; - } + // Mark this module to be inited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask |= 1 << i; } void pwmout_free(pwmout_t* obj) @@ -145,11 +143,9 @@ void pwmout_free(pwmout_t* obj) } } - if (((struct nu_pwm_var *) modinit->var)->en_msk == 0) { - // Mark this module to be deinited. - int i = modinit - pwm_modinit_tab; - pwm_modinit_mask &= ~(1 << i); - } + // Mark this module to be deinited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask &= ~(1 << i); } void pwmout_write(pwmout_t* obj, float value) diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c index 13bae2a9665..a67684d8d4e 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c @@ -24,6 +24,7 @@ #include "PeripheralPins.h" #include "nu_modutil.h" #include "nu_bitutil.h" +#include #if DEVICE_SERIAL_ASYNCH #include "dma_api.h" @@ -65,6 +66,8 @@ static void uart_dma_handler_rx(uint32_t id, uint32_t event); static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable); static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable); +static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable); +static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq); static int serial_write_async(serial_t *obj); static int serial_read_async(serial_t *obj); @@ -189,7 +192,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; @@ -216,6 +219,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) serial_format(obj, 8, ParityNone, 1); obj->serial.vec = var->vec; + obj->serial.irq_en = 0; #if DEVICE_SERIAL_ASYNCH obj->serial.dma_usage_tx = DMA_USAGE_NEVER; @@ -242,7 +246,7 @@ void serial_free(serial_t *obj) { const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; @@ -361,7 +365,7 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); obj->serial.irq_handler = (uint32_t) handler; obj->serial.irq_id = id; @@ -372,51 +376,18 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - if (enable) { - const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); - MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); - - NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec); - NVIC_EnableIRQ(modinit->irq_n); - - struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; - // Multiple serial S/W objects for single UART H/W module possibly. - // Bind serial S/W object to UART H/W module as interrupt is enabled. - var->obj = obj; - - switch (irq) { - // NOTE: Setting inten_msk first to avoid race condition - case RxIrq: - obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); - UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); - break; - case TxIrq: - obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk; - UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); - break; - } - } else { // disable - switch (irq) { - case RxIrq: - UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); - obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); - break; - case TxIrq: - UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); - obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk; - break; - } - } + obj->serial.irq_en = enable; + serial_enable_interrupt(obj, irq, enable); } int serial_getc(serial_t *obj) { - // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much. + // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation. while (! serial_readable(obj)); int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); - // Simulate clear of the interrupt flag + // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq. + // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively. if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); } @@ -426,11 +397,12 @@ int serial_getc(serial_t *obj) void serial_putc(serial_t *obj, int c) { - // TODO: Fix every byte access requires accompaniness of one interrupt. This degrades performance much. + // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation. while (! serial_writable(obj)); UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c); - // Simulate clear of the interrupt flag + // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq. + // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively. if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); } @@ -542,7 +514,7 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx // DMA way const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); PDMA_T *pdma_base = dma_modbase(); @@ -603,7 +575,7 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt // DMA way const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); PDMA_T *pdma_base = dma_modbase(); @@ -650,10 +622,8 @@ void serial_tx_abort_asynch(serial_t *obj) } // Necessary for both interrupt way and DMA way - serial_irq_set(obj, TxIrq, 0); - // FIXME: more complete abort operation - //UART_HAL_DisableTransmitter(obj->serial.serial.address); - //UART_HAL_FlushTxFifo(obj->serial.serial.address); + serial_enable_interrupt(obj, TxIrq, 0); + serial_rollback_interrupt(obj, TxIrq); } void serial_rx_abort_asynch(serial_t *obj) @@ -671,20 +641,30 @@ void serial_rx_abort_asynch(serial_t *obj) } // Necessary for both interrupt way and DMA way - serial_irq_set(obj, RxIrq, 0); - // FIXME: more complete abort operation - //UART_HAL_DisableReceiver(obj->serial.serial.address); - //UART_HAL_FlushRxFifo(obj->serial.serial.address); + serial_enable_interrupt(obj, RxIrq, 0); + serial_rollback_interrupt(obj, RxIrq); } uint8_t serial_tx_active(serial_t *obj) { - return serial_is_irq_en(obj, TxIrq); + // NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag. + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + return (obj->serial.vec == var->vec_async); } uint8_t serial_rx_active(serial_t *obj) { - return serial_is_irq_en(obj, RxIrq); + // NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag. + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + return (obj->serial.vec == var->vec_async); } int serial_irq_handler_asynch(serial_t *obj) @@ -934,7 +914,7 @@ static int serial_write_async(serial_t *obj) { const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); @@ -986,7 +966,7 @@ static int serial_read_async(serial_t *obj) { const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos; //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy; @@ -1061,28 +1041,81 @@ static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t { const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); // Necessary for both interrupt way and DMA way struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; // With our own async vector, tx/rx handlers can be different. obj->serial.vec = var->vec_async; obj->serial.irq_handler_tx_async = (void (*)(void)) handler; - serial_irq_set(obj, TxIrq, enable); + serial_enable_interrupt(obj, TxIrq, enable); } static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable) { const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); MBED_ASSERT(modinit != NULL); - MBED_ASSERT(modinit->modname == obj->serial.uart); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); // Necessary for both interrupt way and DMA way struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; // With our own async vector, tx/rx handlers can be different. obj->serial.vec = var->vec_async; obj->serial.irq_handler_rx_async = (void (*) (void)) handler; - serial_irq_set(obj, RxIrq, enable); + serial_enable_interrupt(obj, RxIrq, enable); +} + +static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + if (enable) { + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec); + NVIC_EnableIRQ(modinit->irq_n); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + // Multiple serial S/W objects for single UART H/W module possibly. + // Bind serial S/W object to UART H/W module as interrupt is enabled. + var->obj = obj; + + switch (irq) { + // NOTE: Setting inten_msk first to avoid race condition + case RxIrq: + obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + break; + case TxIrq: + obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk; + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + break; + } + } + else { // disable + switch (irq) { + case RxIrq: + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + break; + case TxIrq: + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk; + break; + } + } +} + +static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + + obj->serial.vec = var->vec; + serial_enable_interrupt(obj, irq, obj->serial.irq_en); } static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch) diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/NCS36510.sct b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/NCS36510.sct index 04b039fe115..56b1e6bf94a 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/NCS36510.sct +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/NCS36510.sct @@ -9,7 +9,7 @@ LR_IROM1 0x00003000 0x0004F000 { ; load region size_region ; no uvisor support at this time - RW_IRAM1 0x3FFF4000 { + RW_IRAM1 0x3FFF4000 + 0x90 { ; 8_byte_aligned(35 vectors * 4 bytes each) = 0x90 .ANY(+RW +ZI) } ARM_LIB_HEAP AlignExpr(+0, 8) ALIGN 8 EMPTY (0x3FFF4000 + 0xC000 - AlignExpr(ImageLimit(RW_IRAM1),8) ) {} diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld index 6076d11859d..1d87e639626 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/NCS36510.ld @@ -5,7 +5,7 @@ MEMORY { VECTORS (rx) : ORIGIN = 0x00003000, LENGTH = 0x00000090 FLASH (rx) : ORIGIN = 0x00003090, LENGTH = 320K - 4K - 0x90 - RAM (rwx) : ORIGIN = 0x3FFF4000, LENGTH = 48K + RAM (rwx) : ORIGIN = 0x3FFF4090, LENGTH = 48K - 0x90 /* 8_byte_aligned(35 vectors * 4 bytes each) = 0x90 */ } /* Linker script to place sections and symbol values. Should be used together diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf index e5ba72e9491..572cdcd2bec 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/NCS36510.icf @@ -8,8 +8,8 @@ define region FLASHB = Mem:[from 0x00100000 size 0x50000]; define region RAMA = Mem:[from 0x3FFFC000 size 0x4000]; define region RAMB = Mem:[from 0x3FFF8000 size 0x4000]; /* G2H ZPRO requires RAMC to be enabled */ -define region RAMC = Mem:[from 0x3FFF4000 size 0x4000]; -define region RAM_ALL = Mem:[from 0x3FFF4000 size 0xC000]; +define region RAMC = Mem:[from 0x3FFF4000 + 0x90 size 0x4000 - 0x90]; /* 8_byte_aligned(35 vectors * 4 bytes each) = 0x90 */ +define region RAM_ALL = Mem:[from 0x3FFF4000 + 0x90 size 0xC000 - 0x90]; /* 8_byte_aligned(35 vectors * 4 bytes each) = 0x90 */ /* Create a stack */ define block CSTACK with size = 0x200, alignment = 8 { }; diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.c index 06bbcd6759c..76ed0fd68d8 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/cmsis_nvic.c @@ -31,7 +31,7 @@ #include -#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_RAM_VECTOR_ADDRESS (0x3FFF4000) // Vectors positioned at start of RAM #define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash diff --git a/targets/TARGET_STM/TARGET_STM32F0/analogout_api.c b/targets/TARGET_STM/TARGET_STM32F0/analogout_api.c index 25319b3fef8..f9f907b9f2f 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/analogout_api.c +++ b/targets/TARGET_STM/TARGET_STM32F0/analogout_api.c @@ -59,7 +59,7 @@ void analogout_init(dac_t *obj, PinName pin) { obj->pin = pin; // Enable DAC clock - __DAC1_CLK_ENABLE(); + __HAL_RCC_DAC1_CLK_ENABLE(); // Configure DAC DacHandle.Instance = (DAC_TypeDef *)(obj->dac); @@ -78,9 +78,9 @@ void analogout_init(dac_t *obj, PinName pin) { void analogout_free(dac_t *obj) { // Reset DAC and disable clock - __DAC1_FORCE_RESET(); - __DAC1_RELEASE_RESET(); - __DAC1_CLK_DISABLE(); + __HAL_RCC_DAC1_FORCE_RESET(); + __HAL_RCC_DAC1_RELEASE_RESET(); + __HAL_RCC_DAC1_CLK_DISABLE(); // Configure GPIO pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h index 608a14ff991..5872d57f7ae 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h @@ -44,10 +44,10 @@ #define TIM_MST TIM4 #define TIM_MST_IRQ TIM4_IRQn -#define TIM_MST_RCC __TIM4_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM4_CLK_ENABLE() -#define TIM_MST_RESET_ON __TIM4_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM4_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM4_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM4_RELEASE_RESET() #define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/stm32f103xb.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/stm32f103xb.h index 140567a9a2a..9ff8ad63859 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/stm32f103xb.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/stm32f103xb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f103xb.h * @author MCD Application Team - * @version V4.1.0 - * @date 29-April-2016 + * @version V4.2.0 + * @date 31-March-2017 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F1xx devices. @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -65,10 +65,10 @@ /** * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ - #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ -#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ + #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ /** * @} @@ -143,7 +143,6 @@ typedef enum USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ } IRQn_Type; - /** * @} */ @@ -617,72 +616,72 @@ typedef struct */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */ +#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */ -#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ - - - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) +#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) +#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) +#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) + +#define SDIO_BASE (PERIPH_BASE + 0x00018000U) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ +#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */ + + + +#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */ /* USB device FS */ -#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ /** @@ -693,48 +692,48 @@ typedef struct * @{ */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define USB ((USB_TypeDef *) USB_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define USB ((USB_TypeDef *)USB_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) /** @@ -805,14 +804,24 @@ typedef struct #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ -#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */ -#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */ -#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */ -#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */ -#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */ -#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */ -#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */ -#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */ +#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ +#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ +#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ +#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ +#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ +#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ +#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ +#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ + +/* Legacy defines */ +#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 +#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 +#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 +#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 +#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 +#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 +#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 +#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 #define PWR_CR_DBP_Pos (8U) #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ @@ -977,9 +986,9 @@ typedef struct #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ +#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ /*!< SWS configuration */ #define RCC_CFGR_SWS_Pos (2U) @@ -988,9 +997,9 @@ typedef struct #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ +#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (4U) @@ -1001,15 +1010,15 @@ typedef struct #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ +#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ #define RCC_CFGR_PPRE1_Pos (8U) @@ -1019,11 +1028,11 @@ typedef struct #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ #define RCC_CFGR_PPRE2_Pos (11U) @@ -1033,11 +1042,11 @@ typedef struct #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ /*!< ADCPPRE configuration */ #define RCC_CFGR_ADCPRE_Pos (14U) @@ -1046,10 +1055,10 @@ typedef struct #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ #define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ -#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ +#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ #define RCC_CFGR_PLLSRC_Pos (16U) #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ @@ -1068,10 +1077,10 @@ typedef struct #define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ #define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ -#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ -#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ +#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */ +#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */ -#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ +#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ #define RCC_CFGR_PLLMULL3_Pos (18U) #define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ @@ -1126,11 +1135,11 @@ typedef struct #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ -#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ -#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ -#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ -#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ +#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ +#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ /* Reference defines */ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO @@ -1416,10 +1425,10 @@ typedef struct #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ /*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ +#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ #define RCC_BDCR_RTCEN_Pos (15U) #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ @@ -1989,7 +1998,7 @@ typedef struct #define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ /*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ #define AFIO_EVCR_PIN_PX1_Pos (0U) #define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ @@ -2044,7 +2053,7 @@ typedef struct #define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ /*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ #define AFIO_EVCR_PORT_PB_Pos (4U) #define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ @@ -2083,7 +2092,7 @@ typedef struct #define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ /* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ @@ -2098,7 +2107,7 @@ typedef struct #define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ /*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ @@ -2113,7 +2122,7 @@ typedef struct #define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ /*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ @@ -2131,7 +2140,7 @@ typedef struct #define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ /*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ @@ -2150,7 +2159,7 @@ typedef struct #define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ /*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ @@ -2170,7 +2179,7 @@ typedef struct #define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ #define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ -#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ @@ -2197,7 +2206,7 @@ typedef struct #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ /*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ @@ -2218,7 +2227,7 @@ typedef struct #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ /*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ @@ -2239,7 +2248,7 @@ typedef struct #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ /*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ @@ -2260,7 +2269,7 @@ typedef struct #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ /*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ @@ -2295,7 +2304,7 @@ typedef struct #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ /*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ @@ -2316,7 +2325,7 @@ typedef struct #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ /* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ @@ -2337,7 +2346,7 @@ typedef struct #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ /*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ @@ -2358,7 +2367,7 @@ typedef struct #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ /*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ @@ -2393,7 +2402,7 @@ typedef struct #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ /*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ @@ -2414,7 +2423,7 @@ typedef struct #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ /*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ @@ -2435,7 +2444,7 @@ typedef struct #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ /*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ @@ -2456,7 +2465,7 @@ typedef struct #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ /*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ @@ -2491,7 +2500,7 @@ typedef struct #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ /* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ @@ -2512,7 +2521,7 @@ typedef struct #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ /* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ @@ -2533,7 +2542,7 @@ typedef struct #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ /*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ @@ -2554,7 +2563,7 @@ typedef struct #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ /*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ @@ -2578,440 +2587,6 @@ typedef struct -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (0U) -#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (1U) -#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (3U) -#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (4U) -#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (7U) -#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (8U) -#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (9U) -#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (10U) -#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (11U) -#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (12U) -#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (15U) -#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (16U) -#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (17U) -#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (18U) -#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (19U) -#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (24U) -#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (25U) -#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ - /******************************************************************************/ /* */ /* External Interrupt/Event Controller */ @@ -3076,9 +2651,6 @@ typedef struct #define EXTI_IMR_MR18_Pos (18U) #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19_Pos (19U) -#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ -#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ /* References Defines */ #define EXTI_IMR_IM0 EXTI_IMR_MR0 @@ -3100,8 +2672,8 @@ typedef struct #define EXTI_IMR_IM16 EXTI_IMR_MR16 #define EXTI_IMR_IM17 EXTI_IMR_MR17 #define EXTI_IMR_IM18 EXTI_IMR_MR18 -#define EXTI_IMR_IM19 EXTI_IMR_MR19 - +#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */ + /******************* Bit definition for EXTI_EMR register *******************/ #define EXTI_EMR_MR0_Pos (0U) #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ @@ -3160,9 +2732,6 @@ typedef struct #define EXTI_EMR_MR18_Pos (18U) #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19_Pos (19U) -#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ -#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ /* References Defines */ #define EXTI_EMR_EM0 EXTI_EMR_MR0 @@ -3184,7 +2753,6 @@ typedef struct #define EXTI_EMR_EM16 EXTI_EMR_MR16 #define EXTI_EMR_EM17 EXTI_EMR_MR17 #define EXTI_EMR_EM18 EXTI_EMR_MR18 -#define EXTI_EMR_EM19 EXTI_EMR_MR19 /****************** Bit definition for EXTI_RTSR register *******************/ #define EXTI_RTSR_TR0_Pos (0U) @@ -3244,9 +2812,6 @@ typedef struct #define EXTI_RTSR_TR18_Pos (18U) #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19_Pos (19U) -#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ -#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ /* References Defines */ #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 @@ -3268,7 +2833,6 @@ typedef struct #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 -#define EXTI_RTSR_RT19 EXTI_RTSR_TR19 /****************** Bit definition for EXTI_FTSR register *******************/ #define EXTI_FTSR_TR0_Pos (0U) @@ -3328,9 +2892,6 @@ typedef struct #define EXTI_FTSR_TR18_Pos (18U) #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19_Pos (19U) -#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ -#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ /* References Defines */ #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 @@ -3352,7 +2913,6 @@ typedef struct #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 -#define EXTI_FTSR_FT19 EXTI_FTSR_TR19 /****************** Bit definition for EXTI_SWIER register ******************/ #define EXTI_SWIER_SWIER0_Pos (0U) @@ -3412,9 +2972,6 @@ typedef struct #define EXTI_SWIER_SWIER18_Pos (18U) #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19_Pos (19U) -#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ -#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ /* References Defines */ #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 @@ -3436,7 +2993,6 @@ typedef struct #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 -#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 /******************* Bit definition for EXTI_PR register ********************/ #define EXTI_PR_PR0_Pos (0U) @@ -3496,9 +3052,6 @@ typedef struct #define EXTI_PR_PR18_Pos (18U) #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19_Pos (19U) -#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ -#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ /* References Defines */ #define EXTI_PR_PIF0 EXTI_PR_PR0 @@ -3520,7 +3073,6 @@ typedef struct #define EXTI_PR_PIF16 EXTI_PR_PR16 #define EXTI_PR_PIF17 EXTI_PR_PR17 #define EXTI_PR_PIF18 EXTI_PR_PR18 -#define EXTI_PR_PIF19 EXTI_PR_PR19 /******************************************************************************/ /* */ @@ -4381,10 +3933,6 @@ typedef struct #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ -#define TIM_SMCR_OCCS_Pos (3U) -#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ -#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ - #define TIM_SMCR_TS_Pos (4U) #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -108,10 +108,10 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V4.0.0 + * @brief CMSIS Device version number V4.2.0 */ -#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ -#define __STM32F1_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ +#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.c index 4e27fcd17cd..717c3cddfbd 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.c +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f1xx.c * @author MCD Application Team - * @version V4.1.0 - * @date 29-April-2016 + * @version V4.2.0 + * @date 31-March-2017 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from @@ -52,7 +52,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -111,12 +111,12 @@ */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ @@ -128,7 +128,7 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ @@ -156,13 +156,13 @@ * Clock Definitions *******************************************************************************/ #if defined(STM32F100xB) ||defined(STM32F100xE) - uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */ + uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */ #else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */ + uint32_t SystemCoreClock = 72000000U; /*!< System Clock Frequency (Core Clock) */ #endif -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} @@ -204,42 +204,42 @@ void SystemInit (void) { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; + RCC->CR |= 0x00000001U; /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #if !defined(STM32F105xC) && !defined(STM32F107xC) - RCC->CFGR &= (uint32_t)0xF8FF0000; + RCC->CFGR &= 0xF8FF0000U; #else - RCC->CFGR &= (uint32_t)0xF0FF0000; + RCC->CFGR &= 0xF0FF0000U; #endif /* STM32F105xC */ /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; + RCC->CR &= 0xFEF6FFFFU; /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + RCC->CR &= 0xFFFBFFFFU; /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; + RCC->CFGR &= 0xFF80FFFFU; #if defined(STM32F105xC) || defined(STM32F107xC) /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; + RCC->CR &= 0xEBFFFFFFU; /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; + RCC->CIR = 0x00FF0000U; /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; + RCC->CFGR2 = 0x00000000U; #elif defined(STM32F100xB) || defined(STM32F100xE) /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; + RCC->CIR = 0x009F0000U; /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; + RCC->CFGR2 = 0x00000000U; #else /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; + RCC->CIR = 0x009F0000U; #endif /* STM32F105xC */ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) @@ -304,14 +304,14 @@ void SystemInit (void) */ void SystemCoreClockUpdate (void) { - uint32_t tmp = 0, pllmull = 0, pllsource = 0; + uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; #if defined(STM32F105xC) || defined(STM32F107xC) - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; + uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; #endif /* STM32F105xC */ #if defined(STM32F100xB) || defined(STM32F100xE) - uint32_t prediv1factor = 0; + uint32_t prediv1factor = 0U; #endif /* STM32F100xB or STM32F100xE */ /* Get SYSCLK source -------------------------------------------------------*/ @@ -319,37 +319,37 @@ void SystemCoreClockUpdate (void) switch (tmp) { - case 0x00: /* HSI used as system clock */ + case 0x00U: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; - case 0x04: /* HSE used as system clock */ + case 0x04U: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; - case 0x08: /* PLL used as system clock */ + case 0x08U: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; #if !defined(STM32F105xC) && !defined(STM32F107xC) - pllmull = ( pllmull >> 18) + 2; + pllmull = ( pllmull >> 18U) + 2U; - if (pllsource == 0x00) + if (pllsource == 0x00U) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; } else { #if defined(STM32F100xB) || defined(STM32F100xE) - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; #else /* HSE selected as PLL clock entry */ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) {/* HSE oscillator clock divided by 2 */ - SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; } else { @@ -358,30 +358,30 @@ void SystemCoreClockUpdate (void) #endif } #else - pllmull = pllmull >> 18; + pllmull = pllmull >> 18U; - if (pllmull != 0x0D) + if (pllmull != 0x0DU) { - pllmull += 2; + pllmull += 2U; } else { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; + pllmull = 13U / 2U; } - if (pllsource == 0x00) + if (pllsource == 0x00U) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; } else {/* PREDIV1 selected as PLL clock entry */ /* Get PREDIV1 clock source and division factor */ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; - if (prediv1source == 0) + if (prediv1source == 0U) { /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; @@ -390,8 +390,8 @@ void SystemCoreClockUpdate (void) {/* PLL2 clock selected as PREDIV1 clock entry */ /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } @@ -405,7 +405,7 @@ void SystemCoreClockUpdate (void) /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } @@ -434,13 +434,13 @@ void SystemInit_ExtMemCtl(void) required, then adjust the Register Addresses */ /* Enable FSMC clock */ - RCC->AHBENR = 0x00000114; + RCC->AHBENR = 0x00000114U; /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ - RCC->APB2ENR = 0x000001E0; + RCC->APB2ENR = 0x000001E0U; /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); @@ -453,23 +453,23 @@ void SystemInit_ExtMemCtl(void) /*---------------- NE3 configuration ----------------------------------------*/ /*---------------- NBL0, NBL1 configuration ---------------------------------*/ - GPIOD->CRL = 0x44BB44BB; - GPIOD->CRH = 0xBBBBBBBB; + GPIOD->CRL = 0x44BB44BBU; + GPIOD->CRH = 0xBBBBBBBBU; - GPIOE->CRL = 0xB44444BB; - GPIOE->CRH = 0xBBBBBBBB; + GPIOE->CRL = 0xB44444BBU; + GPIOE->CRH = 0xBBBBBBBBU; - GPIOF->CRL = 0x44BBBBBB; - GPIOF->CRH = 0xBBBB4444; + GPIOF->CRL = 0x44BBBBBBU; + GPIOF->CRH = 0xBBBB4444U; - GPIOG->CRL = 0x44BBBBBB; - GPIOG->CRH = 0x444B4B44; + GPIOG->CRL = 0x44BBBBBBU; + GPIOG->CRH = 0x444B4B44U; /*---------------- FSMC Configuration ---------------------------------------*/ /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ - FSMC_Bank1->BTCR[4] = 0x00001091; - FSMC_Bank1->BTCR[5] = 0x00110212; + FSMC_Bank1->BTCR[4U] = 0x00001091U; + FSMC_Bank1->BTCR[5U] = 0x00110212U; } #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.h index 8efeb9aadbc..f2557fa9579 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_stm32f1xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f10x.h * @author MCD Application Team - * @version V4.1.0 - * @date 29-April-2016 + * @version V4.2.0 + * @date 31-March-2017 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -67,8 +67,8 @@ */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h index 608a14ff991..5872d57f7ae 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h @@ -44,10 +44,10 @@ #define TIM_MST TIM4 #define TIM_MST_IRQ TIM4_IRQn -#define TIM_MST_RCC __TIM4_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM4_CLK_ENABLE() -#define TIM_MST_RESET_ON __TIM4_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM4_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM4_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM4_RELEASE_RESET() #define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/stm32f100xb.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/stm32f100xb.h index bebed071dd4..fecc192071d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/stm32f100xb.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/stm32f100xb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f100xb.h * @author MCD Application Team - * @version V4.1.0 - * @date 29-April-2016 + * @version V4.2.0 + * @date 31-March-2017 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F1xx devices. @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -65,10 +65,10 @@ /** * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ - #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ -#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ + #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ /** * @} @@ -141,7 +141,6 @@ typedef enum TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ } IRQn_Type; - /** * @} */ @@ -555,73 +554,73 @@ typedef struct */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */ +#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define CEC_BASE (APB1PERIPH_BASE + 0x7800) -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */ -#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ - - - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ +#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x00007400U) +#define CEC_BASE (APB1PERIPH_BASE + 0x00007800U) +#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) +#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000U) +#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400U) +#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800U) + +#define SDIO_BASE (PERIPH_BASE + 0x00018000U) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ +#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */ + + + +#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */ @@ -633,52 +632,53 @@ typedef struct * @{ */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define CEC ((CEC_TypeDef *) CEC_BASE) -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define TIM6 ((TIM_TypeDef *)TIM6_BASE) +#define TIM7 ((TIM_TypeDef *)TIM7_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define DAC1 ((DAC_TypeDef *)DAC_BASE) +#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */ +#define CEC ((CEC_TypeDef *)CEC_BASE) +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define TIM15 ((TIM_TypeDef *)TIM15_BASE) +#define TIM16 ((TIM_TypeDef *)TIM16_BASE) +#define TIM17 ((TIM_TypeDef *)TIM17_BASE) +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) /** @@ -749,14 +749,24 @@ typedef struct #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ -#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */ -#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */ -#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */ -#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */ -#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */ -#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */ -#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */ -#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */ +#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ +#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ +#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ +#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ +#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ +#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ +#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ +#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ + +/* Legacy defines */ +#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 +#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 +#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 +#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 +#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 +#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 +#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 +#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 #define PWR_CR_DBP_Pos (8U) #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ @@ -921,9 +931,9 @@ typedef struct #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ +#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ /*!< SWS configuration */ #define RCC_CFGR_SWS_Pos (2U) @@ -932,9 +942,9 @@ typedef struct #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ +#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (4U) @@ -945,15 +955,15 @@ typedef struct #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ +#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ #define RCC_CFGR_PPRE1_Pos (8U) @@ -963,11 +973,11 @@ typedef struct #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ #define RCC_CFGR_PPRE2_Pos (11U) @@ -977,11 +987,11 @@ typedef struct #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ /*!< ADCPPRE configuration */ #define RCC_CFGR_ADCPRE_Pos (14U) @@ -990,10 +1000,10 @@ typedef struct #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ #define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ -#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ +#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ #define RCC_CFGR_PLLSRC_Pos (16U) #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ @@ -1012,10 +1022,10 @@ typedef struct #define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ #define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ -#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ -#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ +#define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */ +#define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */ -#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ +#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ #define RCC_CFGR_PLLMULL3_Pos (18U) #define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ @@ -1067,22 +1077,22 @@ typedef struct #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ -#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ -#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ -#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ -#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ +#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ +#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ /* Reference defines */ - #define RCC_CFGR_MCOSEL RCC_CFGR_MCO - #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 - #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 - #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 - #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK - #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK - #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI - #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE - #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 + #define RCC_CFGR_MCOSEL RCC_CFGR_MCO + #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 + #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 + #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 + #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK + #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK + #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI + #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE + #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!<****************** Bit definition for RCC_CIR register ********************/ #define RCC_CIR_LSIRDYF_Pos (0U) @@ -1381,10 +1391,10 @@ typedef struct #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ /*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ +#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ #define RCC_BDCR_RTCEN_Pos (15U) #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ @@ -1433,7 +1443,7 @@ typedef struct #define RCC_CFGR2_PREDIV1_2 (0x4U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */ #define RCC_CFGR2_PREDIV1_3 (0x8U << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */ -#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ +#define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */ #define RCC_CFGR2_PREDIV1_DIV2_Pos (0U) #define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1U << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */ #define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */ @@ -2010,7 +2020,7 @@ typedef struct #define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ /*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ #define AFIO_EVCR_PIN_PX1_Pos (0U) #define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ @@ -2065,7 +2075,7 @@ typedef struct #define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ /*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ #define AFIO_EVCR_PORT_PB_Pos (4U) #define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ @@ -2104,7 +2114,7 @@ typedef struct #define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ /* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ @@ -2119,7 +2129,7 @@ typedef struct #define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ /*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ @@ -2134,7 +2144,7 @@ typedef struct #define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ /*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ @@ -2152,7 +2162,7 @@ typedef struct #define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ /*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ @@ -2177,7 +2187,7 @@ typedef struct #define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ #define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ -#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ @@ -2204,7 +2214,7 @@ typedef struct #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ /*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ @@ -2225,7 +2235,7 @@ typedef struct #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ /*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ @@ -2246,7 +2256,7 @@ typedef struct #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ /*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ @@ -2267,7 +2277,7 @@ typedef struct #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ /*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ @@ -2302,7 +2312,7 @@ typedef struct #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ /*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ @@ -2323,7 +2333,7 @@ typedef struct #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ /* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ @@ -2344,7 +2354,7 @@ typedef struct #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ /*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ @@ -2365,7 +2375,7 @@ typedef struct #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ /*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ @@ -2400,7 +2410,7 @@ typedef struct #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ /*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ @@ -2421,7 +2431,7 @@ typedef struct #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ /*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ @@ -2442,7 +2452,7 @@ typedef struct #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ /*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ @@ -2463,7 +2473,7 @@ typedef struct #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ /*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ @@ -2498,7 +2508,7 @@ typedef struct #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ /* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ @@ -2519,7 +2529,7 @@ typedef struct #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ /* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ @@ -2540,7 +2550,7 @@ typedef struct #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ /*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ @@ -2561,7 +2571,7 @@ typedef struct #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ /*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ @@ -2603,440 +2613,6 @@ typedef struct #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP AFIO_MAPR2_TIM67_DAC_DMA_REMAP_Msk /*!< TIM6/TIM7 and DAC DMA remapping */ -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (0U) -#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (1U) -#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (3U) -#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (4U) -#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (7U) -#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (8U) -#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (9U) -#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (10U) -#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (11U) -#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (12U) -#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (15U) -#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (16U) -#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (17U) -#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (18U) -#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (19U) -#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (24U) -#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (25U) -#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ - /******************************************************************************/ /* */ /* External Interrupt/Event Controller */ @@ -3098,12 +2674,6 @@ typedef struct #define EXTI_IMR_MR17_Pos (17U) #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18_Pos (18U) -#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ -#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19_Pos (19U) -#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ -#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ /* References Defines */ #define EXTI_IMR_IM0 EXTI_IMR_MR0 @@ -3124,9 +2694,8 @@ typedef struct #define EXTI_IMR_IM15 EXTI_IMR_MR15 #define EXTI_IMR_IM16 EXTI_IMR_MR16 #define EXTI_IMR_IM17 EXTI_IMR_MR17 -#define EXTI_IMR_IM18 EXTI_IMR_MR18 -#define EXTI_IMR_IM19 EXTI_IMR_MR19 - +#define EXTI_IMR_IM 0x0003FFFFU /*!< Interrupt Mask All */ + /******************* Bit definition for EXTI_EMR register *******************/ #define EXTI_EMR_MR0_Pos (0U) #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ @@ -3182,12 +2751,6 @@ typedef struct #define EXTI_EMR_MR17_Pos (17U) #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18_Pos (18U) -#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ -#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19_Pos (19U) -#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ -#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ /* References Defines */ #define EXTI_EMR_EM0 EXTI_EMR_MR0 @@ -3208,8 +2771,6 @@ typedef struct #define EXTI_EMR_EM15 EXTI_EMR_MR15 #define EXTI_EMR_EM16 EXTI_EMR_MR16 #define EXTI_EMR_EM17 EXTI_EMR_MR17 -#define EXTI_EMR_EM18 EXTI_EMR_MR18 -#define EXTI_EMR_EM19 EXTI_EMR_MR19 /****************** Bit definition for EXTI_RTSR register *******************/ #define EXTI_RTSR_TR0_Pos (0U) @@ -3266,12 +2827,6 @@ typedef struct #define EXTI_RTSR_TR17_Pos (17U) #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18_Pos (18U) -#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ -#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19_Pos (19U) -#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ -#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ /* References Defines */ #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 @@ -3292,8 +2847,6 @@ typedef struct #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 -#define EXTI_RTSR_RT18 EXTI_RTSR_TR18 -#define EXTI_RTSR_RT19 EXTI_RTSR_TR19 /****************** Bit definition for EXTI_FTSR register *******************/ #define EXTI_FTSR_TR0_Pos (0U) @@ -3350,12 +2903,6 @@ typedef struct #define EXTI_FTSR_TR17_Pos (17U) #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18_Pos (18U) -#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ -#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19_Pos (19U) -#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ -#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ /* References Defines */ #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 @@ -3376,8 +2923,6 @@ typedef struct #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 -#define EXTI_FTSR_FT18 EXTI_FTSR_TR18 -#define EXTI_FTSR_FT19 EXTI_FTSR_TR19 /****************** Bit definition for EXTI_SWIER register ******************/ #define EXTI_SWIER_SWIER0_Pos (0U) @@ -3434,12 +2979,6 @@ typedef struct #define EXTI_SWIER_SWIER17_Pos (17U) #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18_Pos (18U) -#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ -#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19_Pos (19U) -#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ -#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ /* References Defines */ #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 @@ -3460,8 +2999,6 @@ typedef struct #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 -#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 -#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 /******************* Bit definition for EXTI_PR register ********************/ #define EXTI_PR_PR0_Pos (0U) @@ -3518,12 +3055,6 @@ typedef struct #define EXTI_PR_PR17_Pos (17U) #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18_Pos (18U) -#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ -#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19_Pos (19U) -#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ -#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ /* References Defines */ #define EXTI_PR_PIF0 EXTI_PR_PR0 @@ -3544,8 +3075,6 @@ typedef struct #define EXTI_PR_PIF15 EXTI_PR_PR15 #define EXTI_PR_PIF16 EXTI_PR_PR16 #define EXTI_PR_PIF17 EXTI_PR_PR17 -#define EXTI_PR_PIF18 EXTI_PR_PR18 -#define EXTI_PR_PIF19 EXTI_PR_PR19 /******************************************************************************/ /* */ @@ -4648,10 +4177,6 @@ typedef struct #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ -#define TIM_SMCR_OCCS_Pos (3U) -#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ -#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ - #define TIM_SMCR_TS_Pos (4U) #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!
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+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -108,10 +108,10 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V4.0.0 + * @brief CMSIS Device version number V4.2.0 */ -#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ -#define __STM32F1_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ +#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_stm32f1xx.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_stm32f1xx.c index 0c2e24fd702..a2efc1a6e18 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_stm32f1xx.c +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_stm32f1xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f1xx.c * @author MCD Application Team - * @version V4.1.0 - * @date 29-April-2016 + * @version V4.2.0 + * @date 31-March-2017 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from @@ -50,7 +50,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -109,12 +109,12 @@ */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ @@ -126,7 +126,7 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ @@ -154,13 +154,13 @@ * Clock Definitions *******************************************************************************/ #if defined(STM32F100xB) ||defined(STM32F100xE) - uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */ + uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */ #else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */ + uint32_t SystemCoreClock = 72000000U; /*!< System Clock Frequency (Core Clock) */ #endif -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} @@ -202,42 +202,42 @@ void SystemInit (void) { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; + RCC->CR |= 0x00000001U; /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #if !defined(STM32F105xC) && !defined(STM32F107xC) - RCC->CFGR &= (uint32_t)0xF8FF0000; + RCC->CFGR &= 0xF8FF0000U; #else - RCC->CFGR &= (uint32_t)0xF0FF0000; + RCC->CFGR &= 0xF0FF0000U; #endif /* STM32F105xC */ /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; + RCC->CR &= 0xFEF6FFFFU; /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + RCC->CR &= 0xFFFBFFFFU; /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; + RCC->CFGR &= 0xFF80FFFFU; #if defined(STM32F105xC) || defined(STM32F107xC) /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; + RCC->CR &= 0xEBFFFFFFU; /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; + RCC->CIR = 0x00FF0000U; /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; + RCC->CFGR2 = 0x00000000U; #elif defined(STM32F100xB) || defined(STM32F100xE) /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; + RCC->CIR = 0x009F0000U; /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; + RCC->CFGR2 = 0x00000000U; #else /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; + RCC->CIR = 0x009F0000U; #endif /* STM32F105xC */ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) @@ -302,14 +302,14 @@ void SystemInit (void) */ void SystemCoreClockUpdate (void) { - uint32_t tmp = 0, pllmull = 0, pllsource = 0; + uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; #if defined(STM32F105xC) || defined(STM32F107xC) - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; + uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; #endif /* STM32F105xC */ #if defined(STM32F100xB) || defined(STM32F100xE) - uint32_t prediv1factor = 0; + uint32_t prediv1factor = 0U; #endif /* STM32F100xB or STM32F100xE */ /* Get SYSCLK source -------------------------------------------------------*/ @@ -317,37 +317,37 @@ void SystemCoreClockUpdate (void) switch (tmp) { - case 0x00: /* HSI used as system clock */ + case 0x00U: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; - case 0x04: /* HSE used as system clock */ + case 0x04U: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; - case 0x08: /* PLL used as system clock */ + case 0x08U: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; #if !defined(STM32F105xC) && !defined(STM32F107xC) - pllmull = ( pllmull >> 18) + 2; + pllmull = ( pllmull >> 18U) + 2U; - if (pllsource == 0x00) + if (pllsource == 0x00U) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; } else { #if defined(STM32F100xB) || defined(STM32F100xE) - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; #else /* HSE selected as PLL clock entry */ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) {/* HSE oscillator clock divided by 2 */ - SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; } else { @@ -356,30 +356,30 @@ void SystemCoreClockUpdate (void) #endif } #else - pllmull = pllmull >> 18; + pllmull = pllmull >> 18U; - if (pllmull != 0x0D) + if (pllmull != 0x0DU) { - pllmull += 2; + pllmull += 2U; } else { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; + pllmull = 13U / 2U; } - if (pllsource == 0x00) + if (pllsource == 0x00U) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; } else {/* PREDIV1 selected as PLL clock entry */ /* Get PREDIV1 clock source and division factor */ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; - if (prediv1source == 0) + if (prediv1source == 0U) { /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; @@ -388,8 +388,8 @@ void SystemCoreClockUpdate (void) {/* PLL2 clock selected as PREDIV1 clock entry */ /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } @@ -403,7 +403,7 @@ void SystemCoreClockUpdate (void) /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } @@ -432,13 +432,13 @@ void SystemInit_ExtMemCtl(void) required, then adjust the Register Addresses */ /* Enable FSMC clock */ - RCC->AHBENR = 0x00000114; + RCC->AHBENR = 0x00000114U; /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ - RCC->APB2ENR = 0x000001E0; + RCC->APB2ENR = 0x000001E0U; /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); @@ -451,23 +451,23 @@ void SystemInit_ExtMemCtl(void) /*---------------- NE3 configuration ----------------------------------------*/ /*---------------- NBL0, NBL1 configuration ---------------------------------*/ - GPIOD->CRL = 0x44BB44BB; - GPIOD->CRH = 0xBBBBBBBB; + GPIOD->CRL = 0x44BB44BBU; + GPIOD->CRH = 0xBBBBBBBBU; - GPIOE->CRL = 0xB44444BB; - GPIOE->CRH = 0xBBBBBBBB; + GPIOE->CRL = 0xB44444BBU; + GPIOE->CRH = 0xBBBBBBBBU; - GPIOF->CRL = 0x44BBBBBB; - GPIOF->CRH = 0xBBBB4444; + GPIOF->CRL = 0x44BBBBBBU; + GPIOF->CRH = 0xBBBB4444U; - GPIOG->CRL = 0x44BBBBBB; - GPIOG->CRH = 0x444B4B44; + GPIOG->CRL = 0x44BBBBBBU; + GPIOG->CRH = 0x444B4B44U; /*---------------- FSMC Configuration ---------------------------------------*/ /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ - FSMC_Bank1->BTCR[4] = 0x00001091; - FSMC_Bank1->BTCR[5] = 0x00110212; + FSMC_Bank1->BTCR[4U] = 0x00001091U; + FSMC_Bank1->BTCR[5U] = 0x00110212U; } #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_stm32f1xx.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_stm32f1xx.h index 8efeb9aadbc..f2557fa9579 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_stm32f1xx.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_stm32f1xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f10x.h * @author MCD Application Team - * @version V4.1.0 - * @date 29-April-2016 + * @version V4.2.0 + * @date 31-March-2017 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -67,8 +67,8 @@ */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h index 608a14ff991..5872d57f7ae 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h @@ -44,10 +44,10 @@ #define TIM_MST TIM4 #define TIM_MST_IRQ TIM4_IRQn -#define TIM_MST_RCC __TIM4_CLK_ENABLE() +#define TIM_MST_RCC __HAL_RCC_TIM4_CLK_ENABLE() -#define TIM_MST_RESET_ON __TIM4_FORCE_RESET() -#define TIM_MST_RESET_OFF __TIM4_RELEASE_RESET() +#define TIM_MST_RESET_ON __HAL_RCC_TIM4_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM4_RELEASE_RESET() #define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/stm32f103xb.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/stm32f103xb.h index 140567a9a2a..9ff8ad63859 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/stm32f103xb.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/stm32f103xb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f103xb.h * @author MCD Application Team - * @version V4.1.0 - * @date 29-April-2016 + * @version V4.2.0 + * @date 31-March-2017 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F1xx devices. @@ -16,7 +16,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -65,10 +65,10 @@ /** * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ - #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ -#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ + #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ /** * @} @@ -143,7 +143,6 @@ typedef enum USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ } IRQn_Type; - /** * @} */ @@ -617,72 +616,72 @@ typedef struct */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ +#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */ +#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */ +#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */ +#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ +#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U) +#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U) +#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ -#define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */ -#define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ - - - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ +#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U) +#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U) +#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U) +#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U) +#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U) +#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U) +#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U) +#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U) + +#define SDIO_BASE (PERIPH_BASE + 0x00018000U) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */ +#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ +#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */ + + + +#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */ /* USB device FS */ -#define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */ +#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */ /** @@ -693,48 +692,48 @@ typedef struct * @{ */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define USB ((USB_TypeDef *) USB_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define USB ((USB_TypeDef *)USB_BASE) +#define CAN1 ((CAN_TypeDef *)CAN1_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define SDIO ((SDIO_TypeDef *)SDIO_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) /** @@ -805,14 +804,24 @@ typedef struct #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ -#define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */ -#define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */ -#define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */ -#define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */ -#define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */ -#define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */ -#define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */ -#define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */ +#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ +#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ +#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ +#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ +#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ +#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ +#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ +#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ + +/* Legacy defines */ +#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 +#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 +#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 +#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 +#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 +#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 +#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 +#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 #define PWR_CR_DBP_Pos (8U) #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ @@ -977,9 +986,9 @@ typedef struct #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ +#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ /*!< SWS configuration */ #define RCC_CFGR_SWS_Pos (2U) @@ -988,9 +997,9 @@ typedef struct #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ +#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (4U) @@ -1001,15 +1010,15 @@ typedef struct #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ +#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ #define RCC_CFGR_PPRE1_Pos (8U) @@ -1019,11 +1028,11 @@ typedef struct #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ #define RCC_CFGR_PPRE2_Pos (11U) @@ -1033,11 +1042,11 @@ typedef struct #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ +#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ /*!< ADCPPRE configuration */ #define RCC_CFGR_ADCPRE_Pos (14U) @@ -1046,10 +1055,10 @@ typedef struct #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ #define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ -#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ +#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ #define RCC_CFGR_PLLSRC_Pos (16U) #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ @@ -1068,10 +1077,10 @@ typedef struct #define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ #define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ -#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ -#define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ +#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */ +#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */ -#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ +#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */ #define RCC_CFGR_PLLMULL3_Pos (18U) #define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ @@ -1126,11 +1135,11 @@ typedef struct #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ -#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ -#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ -#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ -#define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ +#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ +#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ +#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ /* Reference defines */ #define RCC_CFGR_MCOSEL RCC_CFGR_MCO @@ -1416,10 +1425,10 @@ typedef struct #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ /*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ +#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ #define RCC_BDCR_RTCEN_Pos (15U) #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ @@ -1989,7 +1998,7 @@ typedef struct #define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ /*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ #define AFIO_EVCR_PIN_PX1_Pos (0U) #define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ @@ -2044,7 +2053,7 @@ typedef struct #define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ /*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ #define AFIO_EVCR_PORT_PB_Pos (4U) #define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ @@ -2083,7 +2092,7 @@ typedef struct #define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ /* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ @@ -2098,7 +2107,7 @@ typedef struct #define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ /*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ @@ -2113,7 +2122,7 @@ typedef struct #define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ /*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ @@ -2131,7 +2140,7 @@ typedef struct #define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ /*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ @@ -2150,7 +2159,7 @@ typedef struct #define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ /*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ @@ -2170,7 +2179,7 @@ typedef struct #define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ #define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ -#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ @@ -2197,7 +2206,7 @@ typedef struct #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ /*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ @@ -2218,7 +2227,7 @@ typedef struct #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ /*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ @@ -2239,7 +2248,7 @@ typedef struct #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ /*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ @@ -2260,7 +2269,7 @@ typedef struct #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ /*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ @@ -2295,7 +2304,7 @@ typedef struct #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ /*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ @@ -2316,7 +2325,7 @@ typedef struct #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ /* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ @@ -2337,7 +2346,7 @@ typedef struct #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ /*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ @@ -2358,7 +2367,7 @@ typedef struct #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ /*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ @@ -2393,7 +2402,7 @@ typedef struct #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ /*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ @@ -2414,7 +2423,7 @@ typedef struct #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ /*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ @@ -2435,7 +2444,7 @@ typedef struct #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ /*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ @@ -2456,7 +2465,7 @@ typedef struct #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ /*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ @@ -2491,7 +2500,7 @@ typedef struct #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ /* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ @@ -2512,7 +2521,7 @@ typedef struct #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ /* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ @@ -2533,7 +2542,7 @@ typedef struct #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ /*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ @@ -2554,7 +2563,7 @@ typedef struct #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ /*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ @@ -2578,440 +2587,6 @@ typedef struct -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA_Pos (0U) -#define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */ -#define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */ -#define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */ -#define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */ -#define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */ -#define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */ -#define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */ -#define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */ -#define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */ -#define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */ -#define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */ -#define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */ -#define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */ -#define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */ -#define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */ -#define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */ -#define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */ -#define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */ -#define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */ -#define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */ -#define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */ -#define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */ -#define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */ -#define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */ -#define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */ -#define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */ -#define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */ -#define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */ -#define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */ -#define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */ -#define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */ -#define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA_Pos (0U) -#define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */ -#define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */ -#define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */ -#define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */ -#define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */ -#define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */ -#define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */ -#define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */ -#define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */ -#define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */ -#define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */ -#define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */ -#define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */ -#define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */ -#define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */ -#define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */ -#define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */ -#define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */ -#define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */ -#define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */ -#define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */ -#define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */ -#define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */ -#define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */ -#define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */ -#define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */ -#define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */ -#define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */ -#define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */ -#define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */ -#define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */ -#define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND_Pos (0U) -#define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND_Pos (0U) -#define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */ -#define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */ -#define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */ -#define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */ -#define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */ -#define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */ -#define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */ -#define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */ -#define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */ -#define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */ -#define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */ -#define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */ -#define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */ -#define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */ -#define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */ -#define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */ -#define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */ -#define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */ -#define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */ -#define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */ -#define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */ -#define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */ -#define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */ -#define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */ -#define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */ -#define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */ -#define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */ -#define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */ -#define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */ -#define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */ -#define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */ -#define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE_Pos (0U) -#define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */ -#define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */ -#define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */ -#define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */ -#define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */ -#define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */ -#define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */ -#define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */ -#define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */ -#define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */ -#define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */ -#define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */ -#define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */ -#define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */ -#define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */ -#define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */ -#define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */ -#define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */ -#define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */ -#define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */ -#define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */ -#define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */ -#define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */ -#define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */ -#define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */ -#define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */ -#define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */ -#define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */ -#define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */ -#define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */ -#define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */ -#define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */ -#define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N_Pos (0U) -#define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */ -#define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1_Pos (8U) -#define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */ -#define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2_Pos (16U) -#define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */ -#define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3_Pos (24U) -#define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */ -#define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL_Pos (0U) -#define SCB_CFSR_IACCVIOL_Msk (0x1U << SCB_CFSR_IACCVIOL_Pos) /*!< 0x00000001 */ -#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL_Pos (1U) -#define SCB_CFSR_DACCVIOL_Msk (0x1U << SCB_CFSR_DACCVIOL_Pos) /*!< 0x00000002 */ -#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR_Pos (3U) -#define SCB_CFSR_MUNSTKERR_Msk (0x1U << SCB_CFSR_MUNSTKERR_Pos) /*!< 0x00000008 */ -#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR_Pos (4U) -#define SCB_CFSR_MSTKERR_Msk (0x1U << SCB_CFSR_MSTKERR_Pos) /*!< 0x00000010 */ -#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_MMARVALID_Pos (7U) -#define SCB_CFSR_MMARVALID_Msk (0x1U << SCB_CFSR_MMARVALID_Pos) /*!< 0x00000080 */ -#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR_Pos (8U) -#define SCB_CFSR_IBUSERR_Msk (0x1U << SCB_CFSR_IBUSERR_Pos) /*!< 0x00000100 */ -#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR_Pos (9U) -#define SCB_CFSR_PRECISERR_Msk (0x1U << SCB_CFSR_PRECISERR_Pos) /*!< 0x00000200 */ -#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR_Pos (10U) -#define SCB_CFSR_IMPRECISERR_Msk (0x1U << SCB_CFSR_IMPRECISERR_Pos) /*!< 0x00000400 */ -#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR_Pos (11U) -#define SCB_CFSR_UNSTKERR_Msk (0x1U << SCB_CFSR_UNSTKERR_Pos) /*!< 0x00000800 */ -#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */ -#define SCB_CFSR_STKERR_Pos (12U) -#define SCB_CFSR_STKERR_Msk (0x1U << SCB_CFSR_STKERR_Pos) /*!< 0x00001000 */ -#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */ -#define SCB_CFSR_BFARVALID_Pos (15U) -#define SCB_CFSR_BFARVALID_Msk (0x1U << SCB_CFSR_BFARVALID_Pos) /*!< 0x00008000 */ -#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR_Pos (16U) -#define SCB_CFSR_UNDEFINSTR_Msk (0x1U << SCB_CFSR_UNDEFINSTR_Pos) /*!< 0x00010000 */ -#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to execute an undefined instruction */ -#define SCB_CFSR_INVSTATE_Pos (17U) -#define SCB_CFSR_INVSTATE_Msk (0x1U << SCB_CFSR_INVSTATE_Pos) /*!< 0x00020000 */ -#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC_Pos (18U) -#define SCB_CFSR_INVPC_Msk (0x1U << SCB_CFSR_INVPC_Pos) /*!< 0x00040000 */ -#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP_Pos (19U) -#define SCB_CFSR_NOCP_Msk (0x1U << SCB_CFSR_NOCP_Pos) /*!< 0x00080000 */ -#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED_Pos (24U) -#define SCB_CFSR_UNALIGNED_Msk (0x1U << SCB_CFSR_UNALIGNED_Pos) /*!< 0x01000000 */ -#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO_Pos (25U) -#define SCB_CFSR_DIVBYZERO_Msk (0x1U << SCB_CFSR_DIVBYZERO_Pos) /*!< 0x02000000 */ -#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occurs because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS_Pos (0U) -#define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS_Pos (0U) -#define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ -#define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF_Pos (0U) -#define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */ -#define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */ - /******************************************************************************/ /* */ /* External Interrupt/Event Controller */ @@ -3076,9 +2651,6 @@ typedef struct #define EXTI_IMR_MR18_Pos (18U) #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19_Pos (19U) -#define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ -#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ /* References Defines */ #define EXTI_IMR_IM0 EXTI_IMR_MR0 @@ -3100,8 +2672,8 @@ typedef struct #define EXTI_IMR_IM16 EXTI_IMR_MR16 #define EXTI_IMR_IM17 EXTI_IMR_MR17 #define EXTI_IMR_IM18 EXTI_IMR_MR18 -#define EXTI_IMR_IM19 EXTI_IMR_MR19 - +#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */ + /******************* Bit definition for EXTI_EMR register *******************/ #define EXTI_EMR_MR0_Pos (0U) #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ @@ -3160,9 +2732,6 @@ typedef struct #define EXTI_EMR_MR18_Pos (18U) #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19_Pos (19U) -#define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ -#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ /* References Defines */ #define EXTI_EMR_EM0 EXTI_EMR_MR0 @@ -3184,7 +2753,6 @@ typedef struct #define EXTI_EMR_EM16 EXTI_EMR_MR16 #define EXTI_EMR_EM17 EXTI_EMR_MR17 #define EXTI_EMR_EM18 EXTI_EMR_MR18 -#define EXTI_EMR_EM19 EXTI_EMR_MR19 /****************** Bit definition for EXTI_RTSR register *******************/ #define EXTI_RTSR_TR0_Pos (0U) @@ -3244,9 +2812,6 @@ typedef struct #define EXTI_RTSR_TR18_Pos (18U) #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19_Pos (19U) -#define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ -#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ /* References Defines */ #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 @@ -3268,7 +2833,6 @@ typedef struct #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 -#define EXTI_RTSR_RT19 EXTI_RTSR_TR19 /****************** Bit definition for EXTI_FTSR register *******************/ #define EXTI_FTSR_TR0_Pos (0U) @@ -3328,9 +2892,6 @@ typedef struct #define EXTI_FTSR_TR18_Pos (18U) #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19_Pos (19U) -#define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ -#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ /* References Defines */ #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 @@ -3352,7 +2913,6 @@ typedef struct #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 -#define EXTI_FTSR_FT19 EXTI_FTSR_TR19 /****************** Bit definition for EXTI_SWIER register ******************/ #define EXTI_SWIER_SWIER0_Pos (0U) @@ -3412,9 +2972,6 @@ typedef struct #define EXTI_SWIER_SWIER18_Pos (18U) #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19_Pos (19U) -#define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ -#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ /* References Defines */ #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 @@ -3436,7 +2993,6 @@ typedef struct #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 -#define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 /******************* Bit definition for EXTI_PR register ********************/ #define EXTI_PR_PR0_Pos (0U) @@ -3496,9 +3052,6 @@ typedef struct #define EXTI_PR_PR18_Pos (18U) #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19_Pos (19U) -#define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ -#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ /* References Defines */ #define EXTI_PR_PIF0 EXTI_PR_PR0 @@ -3520,7 +3073,6 @@ typedef struct #define EXTI_PR_PIF16 EXTI_PR_PR16 #define EXTI_PR_PIF17 EXTI_PR_PR17 #define EXTI_PR_PIF18 EXTI_PR_PR18 -#define EXTI_PR_PIF19 EXTI_PR_PR19 /******************************************************************************/ /* */ @@ -4381,10 +3933,6 @@ typedef struct #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ -#define TIM_SMCR_OCCS_Pos (3U) -#define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ -#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ - #define TIM_SMCR_TS_Pos (4U) #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!
© COPYRIGHT(c) 2016 STMicroelectronics
+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -108,10 +108,10 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V4.0.0 + * @brief CMSIS Device version number V4.2.0 */ -#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ -#define __STM32F1_CMSIS_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */ +#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_stm32f1xx.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_stm32f1xx.c index 4e27fcd17cd..717c3cddfbd 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_stm32f1xx.c +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_stm32f1xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f1xx.c * @author MCD Application Team - * @version V4.1.0 - * @date 29-April-2016 + * @version V4.2.0 + * @date 31-March-2017 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. * * 1. This file provides two functions and one global variable to be called from @@ -52,7 +52,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -111,12 +111,12 @@ */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz. This value can be provided and adapted by the user application. */ #endif /* HSI_VALUE */ @@ -128,7 +128,7 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ @@ -156,13 +156,13 @@ * Clock Definitions *******************************************************************************/ #if defined(STM32F100xB) ||defined(STM32F100xE) - uint32_t SystemCoreClock = 24000000; /*!< System Clock Frequency (Core Clock) */ + uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */ #else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = 72000000; /*!< System Clock Frequency (Core Clock) */ + uint32_t SystemCoreClock = 72000000U; /*!< System Clock Frequency (Core Clock) */ #endif -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} @@ -204,42 +204,42 @@ void SystemInit (void) { /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; + RCC->CR |= 0x00000001U; /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #if !defined(STM32F105xC) && !defined(STM32F107xC) - RCC->CFGR &= (uint32_t)0xF8FF0000; + RCC->CFGR &= 0xF8FF0000U; #else - RCC->CFGR &= (uint32_t)0xF0FF0000; + RCC->CFGR &= 0xF0FF0000U; #endif /* STM32F105xC */ /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; + RCC->CR &= 0xFEF6FFFFU; /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; + RCC->CR &= 0xFFFBFFFFU; /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; + RCC->CFGR &= 0xFF80FFFFU; #if defined(STM32F105xC) || defined(STM32F107xC) /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; + RCC->CR &= 0xEBFFFFFFU; /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; + RCC->CIR = 0x00FF0000U; /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; + RCC->CFGR2 = 0x00000000U; #elif defined(STM32F100xB) || defined(STM32F100xE) /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; + RCC->CIR = 0x009F0000U; /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; + RCC->CFGR2 = 0x00000000U; #else /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; + RCC->CIR = 0x009F0000U; #endif /* STM32F105xC */ #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) @@ -304,14 +304,14 @@ void SystemInit (void) */ void SystemCoreClockUpdate (void) { - uint32_t tmp = 0, pllmull = 0, pllsource = 0; + uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U; #if defined(STM32F105xC) || defined(STM32F107xC) - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; + uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U; #endif /* STM32F105xC */ #if defined(STM32F100xB) || defined(STM32F100xE) - uint32_t prediv1factor = 0; + uint32_t prediv1factor = 0U; #endif /* STM32F100xB or STM32F100xE */ /* Get SYSCLK source -------------------------------------------------------*/ @@ -319,37 +319,37 @@ void SystemCoreClockUpdate (void) switch (tmp) { - case 0x00: /* HSI used as system clock */ + case 0x00U: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; break; - case 0x04: /* HSE used as system clock */ + case 0x04U: /* HSE used as system clock */ SystemCoreClock = HSE_VALUE; break; - case 0x08: /* PLL used as system clock */ + case 0x08U: /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; #if !defined(STM32F105xC) && !defined(STM32F107xC) - pllmull = ( pllmull >> 18) + 2; + pllmull = ( pllmull >> 18U) + 2U; - if (pllsource == 0x00) + if (pllsource == 0x00U) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; } else { #if defined(STM32F100xB) || defined(STM32F100xE) - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; #else /* HSE selected as PLL clock entry */ if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) {/* HSE oscillator clock divided by 2 */ - SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + SystemCoreClock = (HSE_VALUE >> 1U) * pllmull; } else { @@ -358,30 +358,30 @@ void SystemCoreClockUpdate (void) #endif } #else - pllmull = pllmull >> 18; + pllmull = pllmull >> 18U; - if (pllmull != 0x0D) + if (pllmull != 0x0DU) { - pllmull += 2; + pllmull += 2U; } else { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; + pllmull = 13U / 2U; } - if (pllsource == 0x00) + if (pllsource == 0x00U) { /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + SystemCoreClock = (HSI_VALUE >> 1U) * pllmull; } else {/* PREDIV1 selected as PLL clock entry */ /* Get PREDIV1 clock source and division factor */ prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U; - if (prediv1source == 0) + if (prediv1source == 0U) { /* HSE oscillator clock selected as PREDIV1 clock entry */ SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; @@ -390,8 +390,8 @@ void SystemCoreClockUpdate (void) {/* PLL2 clock selected as PREDIV1 clock entry */ /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; } } @@ -405,7 +405,7 @@ void SystemCoreClockUpdate (void) /* Compute HCLK clock frequency ----------------*/ /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; /* HCLK clock frequency */ SystemCoreClock >>= tmp; } @@ -434,13 +434,13 @@ void SystemInit_ExtMemCtl(void) required, then adjust the Register Addresses */ /* Enable FSMC clock */ - RCC->AHBENR = 0x00000114; + RCC->AHBENR = 0x00000114U; /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ - RCC->APB2ENR = 0x000001E0; + RCC->APB2ENR = 0x000001E0U; /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN); @@ -453,23 +453,23 @@ void SystemInit_ExtMemCtl(void) /*---------------- NE3 configuration ----------------------------------------*/ /*---------------- NBL0, NBL1 configuration ---------------------------------*/ - GPIOD->CRL = 0x44BB44BB; - GPIOD->CRH = 0xBBBBBBBB; + GPIOD->CRL = 0x44BB44BBU; + GPIOD->CRH = 0xBBBBBBBBU; - GPIOE->CRL = 0xB44444BB; - GPIOE->CRH = 0xBBBBBBBB; + GPIOE->CRL = 0xB44444BBU; + GPIOE->CRH = 0xBBBBBBBBU; - GPIOF->CRL = 0x44BBBBBB; - GPIOF->CRH = 0xBBBB4444; + GPIOF->CRL = 0x44BBBBBBU; + GPIOF->CRH = 0xBBBB4444U; - GPIOG->CRL = 0x44BBBBBB; - GPIOG->CRH = 0x444B4B44; + GPIOG->CRL = 0x44BBBBBBU; + GPIOG->CRH = 0x444B4B44U; /*---------------- FSMC Configuration ---------------------------------------*/ /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ - FSMC_Bank1->BTCR[4] = 0x00001091; - FSMC_Bank1->BTCR[5] = 0x00110212; + FSMC_Bank1->BTCR[4U] = 0x00001091U; + FSMC_Bank1->BTCR[5U] = 0x00110212U; } #endif /* DATA_IN_ExtSRAM */ #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_stm32f1xx.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_stm32f1xx.h index 8efeb9aadbc..f2557fa9579 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_stm32f1xx.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/system_stm32f1xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32f10x.h * @author MCD Application Team - * @version V4.1.0 - * @date 29-April-2016 + * @version V4.2.0 + * @date 31-March-2017 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -67,8 +67,8 @@ */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32f1xx_hal.html b/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32f1xx_hal.html index 9339962394e..c026d296fc5 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32f1xx_hal.html +++ b/targets/TARGET_STM/TARGET_STM32F1/device/Release_Notes_stm32f1xx_hal.html @@ -920,7 +920,91 @@

Update History

-

V1.0.5 / 06-December-2016

+

V1.1.0 / 14-April-2017

  • Add Low Layer drivers allowing performance and footprint optimization
    • Low +Layer drivers APIs provide register level programming: require deep +knowledge of peripherals described in STM32F1xx Reference Manuals
    • Low +Layer drivers are available for: ADC, Cortex, CRC, DAC, DMA, EXTI, GPIO, I2C, IWDG, PWR, RCC, RTC, SPI, TIM, +USART, WWDG peripherals and additionnal Low Level Bus, System and +Utilities APIs.
    • Low Layer drivers APIs are implemented as static inline function in new Inc/stm32f1xx_ll_ppp.h files for PPP peripherals, there is no configuration file and each stm32f1xx_ll_ppp.h file must be included in user code.
  • Add new HAL MMC driver
  • General updates to fix known defects and enhancements implementation
  • + +Enhance HAL delay and time base implementation:
    • Add +new drivers stm32f1xx_hal_timebase_rtc_alarm_template.c and +stm32f1xx_hal_timebase_tim_template.c which override the native +HAL time base functions (defined as weak) to either use the RTC/TIM as time +base tick source. For more details about the usage of these drivers, +please refer to HAL\HAL_TimeBase_RTC  and HAL\HAL_TimeBase_TIM examples and FreeRTOS-based applications
  • Fix extra warnings with GCC compiler
  • HAL drivers clean up: update 'uint32_t' cast with 'U'
  • Update to used the new defined Bit_Pos CMSIS defines insetad of POSITION_VAL() macro
  • Update HAL +weak empty callbacks to prevent unused argument compilation warnings with some +compilers by calling the following line: +
    • UNUSED(hppp);
  • STM32Fxxx_User_Manual.chm files regenerated for HAL V1.1.0
  • The following changes done on the HAL drivers require an update on the application code based on older HAL versions
    • HAL UART, USART, IRDA, SMARTCARD, SPI, I2C (referenced as PPP here below) drivers
      • Add PPP error management during DMA process. This requires the following updates on user application:
        • Configure and enable the PPP IRQ in HAL_PPP_MspInit() function
        • In stm32f1xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function
        • Add customize the Error Callback API: HAL_PPP_ErrorCallback()
    • HAL SD driver:
      • Overall rework of the driver for a more efficient implementation
        • Modify initialization API and structures
        • Modify Read / Write sequences: separate transfer process and SD Cards state management 
        • Adding interrupt mode for Read / Write operations
        • Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors
      • Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application
    • HAL NAND driver:
      • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
      • Add new HAL_NAND_ConfigDevice API
    • HAL CEC driver:  Overall driver rework with compatibility break versus previous HAL version
      • Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()
      • Remove +HAL CEC receive interrupt process function HAL_CEC_Receive_IT() +and enable the "receive"  mode during the Init phase
      • Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' +field from the CEC_InitTypeDef structure and manage +it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
    • HAL IWDG driver: rework overall driver for better implementation
      • Remove HAL_IWDG_Start(), HAL_IWDG_MspInit() and HAL_IWDG_GetState() APIs
    • HAL WWDG driver: rework overall driver for better implementation
      • Remove HAL_WWDG_Start(), HAL_WWDG_Start_IT(), HAL_WWDG_MspDeInit() and HAL_WWDG_GetState() APIs 
      • Update the HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t counter)  function and API  by removing the  "counter" parameter
  • HAL GENERIC update
    • Modifiy default HAL_Delay implementation to guarantee minimum delay 
    • stm32f1xx_hal_conf_template.h
      • Add new define LSI_VALUE
      • Add new define USE_SPI_CRC for code cleanup when the CRC calculation is disabled.
  • HAL CORTEX update
    • Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f4xx_hal_cortex.h to stm32f4xx_hal_cortex.c
    • Clear the whole MPU control register in HAL_MPU_Disable() API
  • HAL FLASH update
    • HAL_FLASH_OB_Launch(): fix static code analyzer warning: The removed code will not execute under any circumstances
  • HAL GPIO update
    • Update IS_GPIO_PIN() macro implementation to be more safe
    • Update remap macros implementation to use CLEAR_BIT()/SET_BIT() macros instead of  MODIFY_REG() macro.
  • HAL RCC update
    • Update LSI workaround delay to use CPU cycles instead of systick
    • Move LSI_VALUE define from RCC HAL driver to stm32f1xx_hal_conf.h file
    • Adjust defined PLL MUL values in aPLLMULFactorTable[]
  • HAL ADC update
    • HAL_ADCEx_MultiModeStart_DMA()  and HAL_ADCEx_MultiModeStop_DMA() API's update to fix code static analyzer warning: Redundant Condition / Unreachable Computation
  • HAL DMA update
    • HAL_DMA_Init(): update to check compatibility between FIFO threshold level and size of the memory burst 
    • Global driver code optimization to reduce memory footprint 
    • New APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() to register/unregister the different possible callbacks identified by enum typedef HAL_DMA_CallbackIDTypeDef
    • Add new Error Codes: HAL_DMA_ERROR_NO_XFER and HAL_DMA_ERROR_NOT_SUPPORTED
  • HAL USART update
    • Add Transfer abort functions and callbacks

    • DMA Receive process; the code +has been updated to clear the USART OVR flag before enabling DMA receive request.

    • Update HAL_USART_IRQHandler() to add a check on interrupt source before managing the error 
  • + +HAL UART update +
    • Several update on HAL UART driver to implement the new UART state machine: 
      • Add new field in UART_HandleTypeDef structure: "rxState", UART state information related to Rx Operations
      • Rename "state" field in UART_HandleTypeDef structure by "gstate": UART state information related to global Handle management and Tx Operations
      • Update UART process to manage the new UART states.
      • Update __HAL_UART_RESET_HANDLE_STATE() macro +to handle the new UART state parameters (gState, rxState)
    • Add Transfer abort functions and callbacks
    • Update HAL_UART_IRQHandler() to add a check on interrupt source before managing the error 

    • DMA Receive process; the code +has been updated to clear the USART OVR flag before enabling DMA receive request.

+ + + + +
  • + +HAL IRDA update +
    • Several update on HAL IRDA driver to implement the new UART state machine: 
      • Add new field in IRDA_HandleTypeDef structure: "rxState", IRDA state information related to Rx Operations
      • Rename "state" field in UART_HandleTypeDef structure by "gstate": IRDA state information related to global Handle management and Tx Operations
      • Update IRDA process to manage the new UART states.
      • Update __HAL_IRDA_RESET_HANDLE_STATE() macro +to handle the new IRDA state parameters (gState, rxState)
    • Removal of IRDA_TIMEOUT_VALUE define
    • Add Transfer abort functions and callbacks
    • Update HAL_IRDA_IRQHandler() to add a check on interrupt source before managing the error 

    • DMA Receive process; the code +has been updated to clear the USART OVR flag before enabling DMA receive request.

  • + +HAL SMARTCARD update +
    • Several update on HAL SMARTCARD driver to implement the new UART state machine: 
      • Add new field in SMARTCARD_HandleTypeDef structure: "rxState", SMARTCARDstate information related to Rx Operations
      • Rename "state" field in UART_HandleTypeDef structure by "gstate": SMARTCARDstate information related to global Handle management and Tx Operations
      • Update SMARTCARD process to manage the new UART states.
      • Update __HAL_SMARTCARD_RESET_HANDLE_STATE() macro +to handle the new SMARTCARD state parameters (gState, rxState)
    • Add Transfer abort functions and callbacks
    • Update HAL_SMARTCARD_IRQHandler() to add a check on interrupt source before managing the error 

    • DMA Receive process; the code +has been updated to clear the USART OVR flag before enabling DMA receive request.

  • HAL CAN update
    • Add + management of overrun error. 
    • Allow + possibility to receive messages from the 2 RX FIFOs in parallel via + interrupt.
    • Fix message + lost issue with specific sequence of transmit requests.
    • Handle + transmission failure with error callback, when NART is enabled.
    • Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when + timeout is reached
  • HAL TIM update
    • Add __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() macro to disable Master output without check on TIM channel state. 
    • Update HAL_TIMEx_ConfigBreakDeadTime() to fix TIM BDTR register corruption.
    • Update Input Capture polarity by removing non-supported "TIM_INPUTCHANNELPOLARITY_BOTHEDGE" define.
    • Update HAL_TIM_ConfigOCrefClear() API by removing the usage of non-existant SMCR OCCS bit.
    • Add +"AutoReloadPreload" field to TIM_Base_InitTypeDef structure and +corresponding macros __HAL_TIM_ENABLE_OCxPRELOAD() and +__HAL_TIM_DISABLE_OCxPRELOAD() .
    • Update TIM_Base_SetConfig() API to set the auto-reload preload.
  • HAL I2C update
    • Update +HAL_I2C_Master_Transmit() and HAL_I2C_Slave_Transmit() to avoid sending +extra bytes at the end of the transmit processes
    • Update + HAL_I2C_Mem_Read() API to fix wrong check on misused parameter “Size”
    • Update + I2C_MasterReceive_RXNE() and I2C_MasterReceive_BTF() static APIs to + enhance Master sequential reception process.
  • HAL SPI update
    • Major Update to improve performance in + polling/interrupt mode to reach max frequency:
      • Polling mode :
        • Replace use of + SPI_WaitOnFlagUnitTimeout() funnction by "if" statement to + check on RXNE/TXE flage while transferring data.
        • Use API data pointer instead of SPI + handle data pointer.
      • Use a Goto implementation instead of + "if..else" statements
      • Interrupt mode
        • Minimize access on SPI registers.
        • Split the SPI modes into dedicated + static functions to minimize checking statements under + HAL_IRQHandler():
          • 1lines/2lines modes
          • 8 bit/ 16 bits data formats
          • CRC calculation enabled/disabled.
      • Remove waiting loop under ISR when + closing  the communication.
      • All modes:  
        • Adding switch USE_SPI_CRC to minimize + number of statements when CRC calculation is disabled.
        • Update Timeout management to check on + global process.
        • Update Error code management in all + processes.
    • Add note to the max frequencies reached in + all modes.
    • Add note about Master Receive mode + restrictions :
    • Master Receive mode restriction:
      +       (#) In Master unidirectional receive-only + mode (MSTR =1, BIDIMODE=0, RXONLY=0) or
      +           bidirectional + receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
      +           does not initiate + a new transfer the following procedure has to be respected:
      +           (##) + HAL_SPI_DeInit()
      +           (##) + HAL_SPI_Init()
    • Add transfer abort APIs and + associated callbacks in interrupt mode
      • HAL_SPI_Abort()
      • HAL_SPI_Abort_IT()
      • HAL_SPI_AbortCpltCallback()
  • + +HAL CEC update
    • Overall driver rework with break of compatibility with HAL V1.0.5
      • Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()
      • Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase
      • Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function
      • Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()
      • Remove the 'InitiatorAddress' +field from the CEC_InitTypeDef structure and manage +it as a parameter in the HAL_CEC_Transmit_IT() function
      • Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function
      • Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure
    • Update driver to implement the new CEC state machine:
      • Add new "rxState" field in CEC_HandleTypeDef structure to provide the CEC state information related to Rx Operations
      • Rename "state" field in CEC_HandleTypeDef structure to "gstate": CEC state information related to global Handle management and Tx Operations
      • Update CEC process to manage the new CEC states.
      • Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)
+
  • HAL I2S update
    • Update I2S Transmit/Receive polling process to manage Overrun and Underrun errors
    • HAL I2S driver ovall clean-up and optimization
    • HAL_I2S_Init() API updated to
      • Fix wrong I2S clock calculation when PCM mode is used.
      • Return state HAL_I2S_ERROR_PRESCALER when the I2S clock is wrongly configured
  • HAL NAND update
    • Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields
    • Add new HAL_NAND_ConfigDevice API
+
  • HAL USB PCD update
    • Flush all TX FIFOs on USB Reset
    • Remove Lock mechanism from HAL_PCD_EP_Transmit() and HAL_PCD_EP_Receive() API's
  • LL USB update
    • Enable DMA Burst mode for USB OTG HS
    • Fix SD card detection issue
  • LL SDMMC update
    • Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions

V1.0.5 / 06-December-2016

diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32_hal_legacy.h index 932527387a6..6cc1ce6c2b8 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32_hal_legacy.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32_hal_legacy.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief This file contains aliases definition for the STM32Cube HAL constants * macros and functions maintained for legacy purpose. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -138,6 +138,7 @@ #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */ #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 @@ -150,6 +151,9 @@ #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT @@ -160,8 +164,16 @@ #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 @@ -229,9 +241,9 @@ #define DAC1_CHANNEL_1 DAC_CHANNEL_1 #define DAC1_CHANNEL_2 DAC_CHANNEL_2 #define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE ((uint32_t)0x00000000U) -#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE @@ -344,6 +356,7 @@ #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 + /** * @} */ @@ -369,7 +382,7 @@ /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ -#if defined(STM32L4) || defined(STM32F7) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 @@ -444,6 +457,25 @@ * @} */ +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) + #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE + #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE + #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET + #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET + #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE + #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + + +/** + * @} + */ + + /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose * @{ */ @@ -841,6 +873,8 @@ #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 +#define __DIV_LPUART UART_DIV_LPUART + #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK @@ -881,9 +915,9 @@ #define CAN_IT_RQCP2 CAN_IT_TME #define INAK_TIMEOUT CAN_TIMEOUT_VALUE #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) -#define CAN_TXSTATUS_OK ((uint8_t)0x01U) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) +#define CAN_TXSTATUS_OK ((uint8_t)0x01) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) /** * @} @@ -902,48 +936,45 @@ #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK -#define ETH_MMCCR ((uint32_t)0x00000100U) -#define ETH_MMCRIR ((uint32_t)0x00000104U) -#define ETH_MMCTIR ((uint32_t)0x00000108U) -#define ETH_MMCRIMR ((uint32_t)0x0000010CU) -#define ETH_MMCTIMR ((uint32_t)0x00000110U) -#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU) -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U) -#define ETH_MMCTGFCR ((uint32_t)0x00000168U) -#define ETH_MMCRFCECR ((uint32_t)0x00000194U) -#define ETH_MMCRFAECR ((uint32_t)0x00000198U) -#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U) +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U -#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */ -#if defined(STM32F1) -#else -#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#endif -#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */ +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ /** * @} @@ -965,7 +996,7 @@ * @} */ -#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\ defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose * @{ @@ -990,7 +1021,7 @@ /** * @} */ -#endif /* STM32L4xx || STM32F7*/ +#endif /* STM32L4 || STM32F7*/ /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ @@ -1175,6 +1206,9 @@ * @{ */ #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig /** * @} */ @@ -1216,6 +1250,7 @@ #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 @@ -1610,7 +1645,11 @@ #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ #define __HAL_I2C_RISE_TIME I2C_RISE_TIME #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST @@ -2216,26 +2255,26 @@ #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET @@ -2619,6 +2658,30 @@ #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE #endif +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + #if defined(STM32F7) #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK @@ -2637,10 +2700,22 @@ #define RCC_IT_HSI14 RCC_IT_HSI14RDY -#if defined(STM32L0) -#define RCC_IT_LSECSS RCC_IT_CSSLSE -#define RCC_IT_CSS RCC_IT_CSSHSE -#endif +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG @@ -2757,10 +2832,22 @@ #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED #define DfsdmClockSelection Dfsdm1ClockSelection #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 /** * @} @@ -2840,7 +2927,7 @@ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS -#if defined(STM32F4) +#if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED @@ -2891,6 +2978,14 @@ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler #endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + /** * @} */ @@ -3079,6 +3174,7 @@ * @{ */ #define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.c index 7cbec5a20b1..59a58207708 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -70,20 +70,19 @@ /** @defgroup HAL_Private_Constants HAL Private Constants * @{ */ - /** - * @brief STM32F1xx HAL Driver version number + * @brief STM32F1xx HAL Driver version number V1.1.0 */ -#define __STM32F1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F1xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32F1xx_HAL_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ -#define __STM32F1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32F1xx_HAL_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */ +#define __STM32F1xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32F1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F1xx_HAL_VERSION ((__STM32F1xx_HAL_VERSION_MAIN << 24)\ |(__STM32F1xx_HAL_VERSION_SUB1 << 16)\ |(__STM32F1xx_HAL_VERSION_SUB2 << 8 )\ |(__STM32F1xx_HAL_VERSION_RC)) -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +#define IDCODE_DEVID_MASK 0x00000FFFU /** * @} @@ -95,13 +94,10 @@ /** @defgroup HAL_Private_Variables HAL Private Variables * @{ */ - -static __IO uint32_t uwTick; - +__IO uint32_t uwTick; /** * @} */ - /* Private function prototypes -----------------------------------------------*/ /* Exported functions ---------------------------------------------------------*/ @@ -136,22 +132,27 @@ static __IO uint32_t uwTick; peripheral ISR process, the Tick interrupt line must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - (++) functions affecting time base configurations are declared as __Weak + (++) functions affecting time base configurations are declared as __weak to make override possible in case of other implementations in user file. - @endverbatim * @{ */ /** - * @brief This function configures the Flash prefetch, - * Configures time base source, NVIC and Low level hardware - * @note This function is called at the beginning of program after reset and before - * the clock configuration - * @note The time base configuration is based on MSI clock when exiting from Reset. - * Once done, time base tick start incrementing. - * In the default implementation,Systick is used as source of time base. - * The tick variable is incremented each 1ms in its ISR. + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configure the Flash prefetch. + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32f1xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) @@ -241,7 +242,7 @@ __weak void HAL_MspDeInit(void) * Care must be taken if HAL_Delay() is called from a peripheral ISR process, * The the SysTick interrupt must have higher priority (numerically lower) * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __Weak to be overwritten in case of other + * The function is declared as __weak to be overwritten in case of other * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status @@ -249,12 +250,12 @@ __weak void HAL_MspDeInit(void) __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { /*Configure the SysTick to have interrupt in 1ms time basis*/ - HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); + HAL_SYSTICK_Config(SystemCoreClock/1000U); /*Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U); - /* Return function status */ + /* Return function status */ return HAL_OK; } @@ -263,8 +264,8 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) */ /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * + * @brief HAL Control functions + * @verbatim =============================================================================== ##### HAL Control functions ##### @@ -277,10 +278,10 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) (+) Get the HAL API driver version (+) Get the device identifier (+) Get the device revision identifier - (+) Enable/Disable Debug module during Sleep mode + (+) Enable/Disable Debug module during SLEEP mode (+) Enable/Disable Debug module during STOP mode (+) Enable/Disable Debug module during STANDBY mode - + @endverbatim * @{ */ @@ -301,7 +302,7 @@ __weak void HAL_IncTick(void) /** * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ @@ -311,21 +312,28 @@ __weak uint32_t HAL_GetTick(void) } /** - * @brief This function provides accurate delay (in milliseconds) based + * @brief This function provides minimum delay (in milliseconds) based * on variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick * is incremented. - * @note ThiS function is declared as __weak to be overwritten in case of other + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @param Delay: specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(__IO uint32_t Delay) { - uint32_t tickstart = 0; - tickstart = HAL_GetTick(); - while((HAL_GetTick() - tickstart) < Delay) + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a period to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait++; + } + + while((HAL_GetTick() - tickstart) < wait) { } } @@ -334,7 +342,7 @@ __weak void HAL_Delay(__IO uint32_t Delay) * @brief Suspend Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the the SysTick interrupt will be disabled and so Tick increment + * is called, the SysTick interrupt will be disabled and so Tick increment * is suspended. * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. @@ -350,9 +358,9 @@ __weak void HAL_SuspendTick(void) * @brief Resume Tick increment. * @note In the default implementation , SysTick timer is the source of time base. It is * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the the SysTick interrupt will be enabled and so Tick increment + * is called, the SysTick interrupt will be enabled and so Tick increment * is resumed. - * @note This function is declared as __weak to be overwritten in case of other + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ @@ -363,8 +371,8 @@ __weak void HAL_ResumeTick(void) } /** - * @brief This method returns the HAL revision - * @retval version: 0xXYZR (8bits for each decimal, R for RC) + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) */ uint32_t HAL_GetHalVersion(void) { @@ -384,7 +392,7 @@ uint32_t HAL_GetHalVersion(void) */ uint32_t HAL_GetREVID(void) { - return((DBGMCU->IDCODE) >> POSITION_VAL(DBGMCU_IDCODE_REV_ID)); + return((DBGMCU->IDCODE) >> DBGMCU_IDCODE_REV_ID_Pos); } /** @@ -506,6 +514,18 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void) CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } +/** + * @brief Return the unique device identifier (UID based on 96 bits) + * @param UID: pointer to 3 words array. + * @retval Device identifier + */ +void HAL_GetUID(uint32_t *UID) +{ + UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE))); + UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); + UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.h index 31b4e16395d..d48fb278a03 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f1xx_hal.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,7 +59,6 @@ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ - /** @defgroup HAL_Exported_Macros HAL Exported Macros * @{ */ @@ -262,22 +261,18 @@ */ /* Exported functions --------------------------------------------------------*/ - /** @addtogroup HAL_Exported_Functions * @{ */ - /** @addtogroup HAL_Exported_Functions_Group1 * @{ */ - /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); - /** * @} */ @@ -285,23 +280,22 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); /** @addtogroup HAL_Exported_Functions_Group2 * @{ */ - /* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(__IO uint32_t Delay); -uint32_t HAL_GetTick(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -void HAL_DBGMCU_EnableDBGSleepMode(void); -void HAL_DBGMCU_DisableDBGSleepMode(void); -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); - +void HAL_IncTick(void); +void HAL_Delay(__IO uint32_t Delay); +uint32_t HAL_GetTick(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +void HAL_GetUID(uint32_t *UID); /** * @} */ @@ -309,11 +303,26 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void); /** * @} */ - - +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ /** * @} - */ + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.c index 452186190eb..ddc0776f94b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_adc.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -300,18 +300,18 @@ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ /* Unit: ms */ - #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) - #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) + #define ADC_ENABLE_TIMEOUT 2U + #define ADC_DISABLE_TIMEOUT 2U /* Delay for ADC stabilization time. */ /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ /* Unit: us */ - #define ADC_STAB_DELAY_US ((uint32_t) 1) + #define ADC_STAB_DELAY_US 1U /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ - #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) + #define ADC_TEMPSENSOR_DELAY_US 10U /** * @} @@ -374,9 +374,9 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmp_cr1 = 0; - uint32_t tmp_cr2 = 0; - uint32_t tmp_sqr1 = 0; + uint32_t tmp_cr1 = 0U; + uint32_t tmp_cr2 = 0U; + uint32_t tmp_sqr1 = 0U; /* Check ADC handle */ if(hadc == NULL) @@ -924,12 +924,12 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ - __IO uint32_t Conversion_Timeout_CPU_cycles = 0; - uint32_t Conversion_Timeout_CPU_cycles_max = 0; + __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; + uint32_t Conversion_Timeout_CPU_cycles_max = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -974,7 +974,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1002,7 +1002,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1055,7 +1055,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1070,7 +1070,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -1702,7 +1702,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1716,14 +1716,14 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Regular sequence configuration */ /* For Rank 1 to 6 */ - if (sConfig->Rank < 7) + if (sConfig->Rank < 7U) { MODIFY_REG(hadc->Instance->SQR3 , ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank) , ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) ); } /* For Rank 7 to 12 */ - else if (sConfig->Rank < 13) + else if (sConfig->Rank < 13U) { MODIFY_REG(hadc->Instance->SQR2 , ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank) , @@ -1771,8 +1771,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); - while(wait_loop_index != 0) + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -1933,8 +1933,8 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) */ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { - uint32_t tickstart = 0; - __IO uint32_t wait_loop_index = 0; + uint32_t tickstart = 0U; + __IO uint32_t wait_loop_index = 0U; /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ @@ -1947,8 +1947,8 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(wait_loop_index != 0) + wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -1988,7 +1988,7 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) */ HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Verification if ADC is not already disabled */ if (ADC_IS_ENABLE(hadc) != RESET) diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.h index 0b88d548357..4d2ed413587 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_adc.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention @@ -154,36 +154,36 @@ typedef struct * @brief HAL ADC state machine: ADC states definition (bitfields) */ /* States of ADC global scope */ -#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */ -#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ +#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ /* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ +#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ /* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, - external trigger, low power auto power-on, multimode ADC master control) */ -#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Not available on STM32F1 device: Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32F1 device: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, + external trigger, low power auto power-on, multimode ADC master control) */ +#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */ /* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, - external trigger, low power auto power-on, multimode ADC master control) */ -#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ +#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, + external trigger, low power auto power-on, multimode ADC master control) */ +#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */ /* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */ +#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */ /* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master ( */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */ /** @@ -218,11 +218,11 @@ typedef struct /** @defgroup ADC_Error_Code ADC Error Code * @{ */ -#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, - enable/disable, erroneous state */ -#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ +#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, + enable/disable, erroneous state */ +#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ /** * @} @@ -232,7 +232,7 @@ typedef struct /** @defgroup ADC_Data_align ADC data alignment * @{ */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) +#define ADC_DATAALIGN_RIGHT 0x00000000U #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) /** * @} @@ -244,7 +244,7 @@ typedef struct /* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */ /* compatibility with other STM32 devices having a sequencer with */ /* additional options. */ -#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) +#define ADC_SCAN_DISABLE 0x00000000U #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN) /** * @} @@ -253,7 +253,7 @@ typedef struct /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group * @{ */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG) /** * @} @@ -264,7 +264,7 @@ typedef struct */ /* Note: Depending on devices, some channels may not be available on package */ /* pins. Refer to device datasheet for channels availability. */ -#define ADC_CHANNEL_0 ((uint32_t)0x00000000) +#define ADC_CHANNEL_0 0x00000000U #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0)) #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 )) #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0)) @@ -292,7 +292,7 @@ typedef struct /** @defgroup ADC_sampling_times ADC sampling times * @{ */ -#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */ #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */ #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */ @@ -307,22 +307,22 @@ typedef struct /** @defgroup ADC_regular_rank ADC rank into regular group * @{ */ -#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) -#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) -#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) -#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) -#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) -#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) -#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) -#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) -#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) -#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) -#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) -#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) -#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) -#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) -#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) -#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) +#define ADC_REGULAR_RANK_1 0x00000001U +#define ADC_REGULAR_RANK_2 0x00000002U +#define ADC_REGULAR_RANK_3 0x00000003U +#define ADC_REGULAR_RANK_4 0x00000004U +#define ADC_REGULAR_RANK_5 0x00000005U +#define ADC_REGULAR_RANK_6 0x00000006U +#define ADC_REGULAR_RANK_7 0x00000007U +#define ADC_REGULAR_RANK_8 0x00000008U +#define ADC_REGULAR_RANK_9 0x00000009U +#define ADC_REGULAR_RANK_10 0x0000000AU +#define ADC_REGULAR_RANK_11 0x0000000BU +#define ADC_REGULAR_RANK_12 0x0000000CU +#define ADC_REGULAR_RANK_13 0x0000000DU +#define ADC_REGULAR_RANK_14 0x0000000EU +#define ADC_REGULAR_RANK_15 0x0000000FU +#define ADC_REGULAR_RANK_16 0x00000010U /** * @} */ @@ -330,12 +330,12 @@ typedef struct /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode * @{ */ -#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) +#define ADC_ANALOGWATCHDOG_NONE 0x00000000U #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) -#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN) -#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN) +#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) +#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) /** * @} @@ -400,14 +400,14 @@ typedef struct /* ADC conversion cycles (unit: ADC clock cycles) */ /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */ /* resolution 12 bits) */ -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14) -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20) -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26) -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41) -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54) -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68) -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84) -#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252) +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U +#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U /** * @} */ @@ -439,7 +439,7 @@ typedef struct (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \ ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 ) -#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS ((uint32_t)0x00000000) +#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) @@ -448,7 +448,7 @@ typedef struct #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0) -#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS ((uint32_t)0x00000000) +#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) @@ -629,7 +629,7 @@ typedef struct * @retval None */ #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \ - (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L)) + (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos) /** * @brief Set the ADC's sample time for channel numbers between 10 and 18. @@ -638,7 +638,7 @@ typedef struct * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \ - ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR1_SMP11) * ((_CHANNELNB_) - 10))) + ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10))) /** * @brief Set the ADC's sample time for channel numbers between 0 and 9. @@ -647,7 +647,7 @@ typedef struct * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \ - ((_SAMPLETIME_) << (POSITION_VAL(ADC_SMPR2_SMP1) * (_CHANNELNB_))) + ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_))) /** * @brief Set the selected regular channel rank for rank between 1 and 6. @@ -656,7 +656,7 @@ typedef struct * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \ - ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR3_SQ2) * ((_RANKNB_) - 1))) + ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1))) /** * @brief Set the selected regular channel rank for rank between 7 and 12. @@ -665,7 +665,7 @@ typedef struct * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \ - ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR2_SQ8) * ((_RANKNB_) - 7))) + ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7))) /** * @brief Set the selected regular channel rank for rank between 13 and 16. @@ -674,7 +674,7 @@ typedef struct * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \ - ((_CHANNELNB_) << (POSITION_VAL(ADC_SQR1_SQ14) * ((_RANKNB_) - 13))) + ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13))) /** * @brief Set the injected sequence length. @@ -682,7 +682,7 @@ typedef struct * @retval None */ #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \ - (((_JSQR_JL_) -1) << POSITION_VAL(ADC_JSQR_JL)) + (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos) /** * @brief Set the selected injected channel rank @@ -695,7 +695,7 @@ typedef struct * @retval None */ #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \ - ((_CHANNELNB_) << (POSITION_VAL(ADC_JSQR_JSQ2) * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) + ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1))) /** * @brief Enable ADC continuous conversion mode. @@ -703,7 +703,7 @@ typedef struct * @retval None */ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \ - ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT)) + ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos) /** * @brief Configures the number of discontinuous conversions for the regular group channels. @@ -711,7 +711,7 @@ typedef struct * @retval None */ #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \ - (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) + (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos) /** * @brief Enable ADC scan mode to convert multiple ranks with sequencer. @@ -825,7 +825,7 @@ typedef struct * For a unique ADC resolution: 12 bits * @{ */ -#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF)) +#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU) /** * @} */ @@ -833,7 +833,7 @@ typedef struct /** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification * @{ */ -#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16))) +#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) /** * @} */ @@ -841,7 +841,7 @@ typedef struct /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification * @{ */ -#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) +#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.c index b1c050f157e..df0cacf3fa8 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -77,7 +77,7 @@ /* Hardware prerequisite before starting a calibration: the ADC must have */ /* been in power-on state for at least two ADC clock cycles. */ /* Unit: ADC clock cycles */ - #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ((uint32_t) 2) + #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U /* Timeout value for ADC calibration */ /* Value defined to be higher than worst cases: low clocks freq, */ @@ -85,12 +85,12 @@ /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */ /* Unit: ms */ - #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10) + #define ADC_CALIBRATION_TIMEOUT 10U /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ - #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) + #define ADC_TEMPSENSOR_DELAY_US 10U /** * @} @@ -145,7 +145,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tickstart; - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -175,7 +175,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); - while(wait_loop_index != 0) + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -405,8 +405,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ - __IO uint32_t Conversion_Timeout_CPU_cycles = 0; - uint32_t Conversion_Timeout_CPU_cycles_max = 0; + __IO uint32_t Conversion_Timeout_CPU_cycles = 0U; + uint32_t Conversion_Timeout_CPU_cycles_max = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -438,7 +438,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); @@ -666,7 +666,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) return tmp_hal_status; } -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /** * @brief Enables ADC, starts conversion of regular group and transfers result * through DMA. @@ -704,8 +704,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* conversion trigger ADC_SOFTWARE_START. */ /* Note: External trigger of ADC slave must be enabled, it is already done */ /* into function "HAL_ADC_Init()". */ - if ((tmphadcSlave.Instance == NULL) || - (! ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) ) + if(!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); @@ -829,39 +828,26 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) + if(tmp_hal_status == HAL_OK) { /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - if (tmphadcSlave.Instance == NULL) + /* Disable ADC slave peripheral */ + tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave); + + /* Check if ADC is effectively disabled */ + if(tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } - else - { - /* Disable ADC slave peripheral */ - tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status != HAL_OK) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - + /* Disable ADC DMA mode */ CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); @@ -871,21 +857,11 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - - /* Check if DMA channel effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Change ADC state (ADC master) */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - } + + /* Change ADC state (ADC master) */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); } /* Process unlocked */ @@ -894,7 +870,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) /* Return function status */ return tmp_hal_status; } -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Get ADC injected group conversion result. @@ -926,7 +902,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) { - uint32_t tmp_jdr = 0; + uint32_t tmp_jdr = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -954,7 +930,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa return tmp_jdr; } -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /** * @brief Returns the last ADC Master&Slave regular conversions results data * in the selected multi mode. @@ -963,7 +939,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa */ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) { - uint32_t tmpDR = 0; + uint32_t tmpDR = 0U; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); @@ -980,13 +956,13 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA)) { - tmpDR |= (ADC2->DR << 16); + tmpDR |= (ADC2->DR << 16U); } /* Return ADC converted value */ return tmpDR; } -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Injected conversion complete callback in non blocking mode @@ -1038,7 +1014,7 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0U; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -1080,7 +1056,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I ADC_JSQR_JSQ1 , ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1, - 0x01) ); + 0x01U)); } /* If another injected rank than rank1 was intended to be set, and could */ /* not due to ScanConvMode disabled, error is reported. */ @@ -1123,7 +1099,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) , - 0x00000000 ); + 0x00000000U); } } @@ -1255,8 +1231,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ - wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); - while(wait_loop_index != 0) + wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + while(wait_loop_index != 0U) { wait_loop_index--; } @@ -1279,7 +1255,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I return tmp_hal_status; } -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /** * @brief Enable ADC multimode and configure multimode parameters * @note Possibility to update parameters on the fly: @@ -1344,7 +1320,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /* Return function status */ return tmp_hal_status; } -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.h index 2337bf61f5b..eba417077a0 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of ADC HAL extension module. ****************************************************************************** * @attention @@ -125,7 +125,7 @@ typedef struct configure a channel on injected group can impact the configuration of other channels previously set. */ }ADC_InjectionConfTypeDef; -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /** * @brief Structure definition of ADC multimode * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group). @@ -145,7 +145,7 @@ typedef struct }ADC_MultiModeTypeDef; -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} @@ -161,10 +161,10 @@ typedef struct /** @defgroup ADCEx_injected_rank ADCEx rank into injected group * @{ */ -#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) -#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) -#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) -#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) +#define ADC_INJECTED_RANK_1 0x00000001U +#define ADC_INJECTED_RANK_2 0x00000002U +#define ADC_INJECTED_RANK_3 0x00000003U +#define ADC_INJECTED_RANK_4 0x00000004U /** * @} */ @@ -172,7 +172,7 @@ typedef struct /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group * @{ */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG) /** * @} @@ -204,7 +204,7 @@ typedef struct /*!< External triggers of regular group for all ADC instances */ #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3 -#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) +#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) /*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ /* To use it on ADC or ADC2, a remap of trigger must be done from */ @@ -216,7 +216,7 @@ typedef struct /* its definition is set to value for ADC1&ADC2 by default and changed to */ /* value for ADC3 by HAL ADC driver if ADC3 is selected. */ #define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO -#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #define ADC_SOFTWARE_START ADC1_2_3_SWSTART /** @@ -248,7 +248,7 @@ typedef struct #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO -#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) +#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) /*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ /* To use it on ADC1 or ADC2, a remap of trigger must be done from */ @@ -260,18 +260,18 @@ typedef struct /* its definition is set to value for ADC1&ADC2 by default and changed to */ /* value for ADC3 by HAL ADC driver if ADC3 is selected. */ #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4 -#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART /** * @} */ -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode * @{ */ -#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< ADC dual mode disabled (ADC independent mode) */ +#define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */ #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */ #define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */ @@ -284,7 +284,7 @@ typedef struct /** * @} */ -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} @@ -305,13 +305,13 @@ typedef struct /* (used internally by HAL driver. To not use into HAL structure parameters) */ /* External triggers of regular group for ADC1&ADC2 (if ADCx available) */ -#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t) 0x00000000) +#define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 )) #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 )) -#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ #define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11 @@ -347,7 +347,7 @@ typedef struct #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 )) #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 )) -#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) /* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */ /* XL-density devices. */ #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 @@ -363,7 +363,7 @@ typedef struct #endif /* STM32F103xE || defined STM32F103xG */ /* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */ -#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t) 0x00000000) +#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U #define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0)) #define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) /** @@ -448,7 +448,7 @@ typedef struct * @param __HANDLE__: ADC handle * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled */ -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \ )? \ @@ -459,14 +459,14 @@ typedef struct #else #define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \ (RESET) -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs) * @param __HANDLE__: ADC handle * @retval None */ -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ (( (((__HANDLE__)->Instance) == ADC2) \ )? \ @@ -477,14 +477,14 @@ typedef struct #else #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ (!RESET) -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs) * @param __HANDLE__: ADC handle * @retval None */ -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \ )? \ @@ -495,9 +495,9 @@ typedef struct #else #define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \ (RESET) -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /** * @brief Set handle of the other ADC sharing the common multimode settings * @param __HANDLE__: ADC handle @@ -518,21 +518,20 @@ typedef struct #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ((__HANDLE_SLAVE__)->Instance = ADC2) -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ ((CHANNEL) == ADC_INJECTED_RANK_2) || \ ((CHANNEL) == ADC_INJECTED_RANK_3) || \ - ((CHANNEL) == ADC_INJECTED_RANK_4) ) + ((CHANNEL) == ADC_INJECTED_RANK_4)) #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ - ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) ) + ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)) /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification * @{ */ -#define IS_ADC_INJECTED_NB_CONV(LENGTH) \ - (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4))) +#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U)) /** * @} */ @@ -544,10 +543,9 @@ typedef struct ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ - \ - ((REGTRIG) == ADC_SOFTWARE_START) ) + ((REGTRIG) == ADC_SOFTWARE_START)) #endif -#if defined (STM32F101xE) || defined (STM32F101xG) +#if defined (STM32F101xE) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ @@ -555,8 +553,16 @@ typedef struct ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ - \ - ((REGTRIG) == ADC_SOFTWARE_START) ) + ((REGTRIG) == ADC_SOFTWARE_START)) +#endif +#if defined (STM32F101xG) +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ + ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined (STM32F103xE) || defined (STM32F103xG) #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ @@ -565,16 +571,14 @@ typedef struct ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ - \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ - \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ - ((REGTRIG) == ADC_SOFTWARE_START) ) + ((REGTRIG) == ADC_SOFTWARE_START)) #endif #if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) @@ -583,24 +587,30 @@ typedef struct ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ - \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ - \ - ((REGTRIG) == ADC_INJECTED_SOFTWARE_START) ) + ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif -#if defined (STM32F101xE) || defined (STM32F101xG) +#if defined (STM32F101xE) #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ - \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ - \ - ((REGTRIG) == ADC_INJECTED_SOFTWARE_START) ) + ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) +#endif +#if defined (STM32F101xG) +#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ + ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif #if defined (STM32F103xE) || defined (STM32F103xG) #define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ @@ -609,20 +619,17 @@ typedef struct ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \ - \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ - \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ - \ - ((REGTRIG) == ADC_INJECTED_SOFTWARE_START) ) + ((REGTRIG) == ADC_INJECTED_SOFTWARE_START)) #endif -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ @@ -632,8 +639,8 @@ typedef struct ((MODE) == ADC_DUALMODE_REGSIMULT) || \ ((MODE) == ADC_DUALMODE_INTERLFAST) || \ ((MODE) == ADC_DUALMODE_INTERLSLOW) || \ - ((MODE) == ADC_DUALMODE_ALTERTRIG) ) -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ + ((MODE) == ADC_DUALMODE_ALTERTRIG) ) +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} @@ -666,17 +673,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* h HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /* ADC retrieve conversion value intended to be used with polling or interruption */ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); @@ -690,9 +697,9 @@ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* ha * @{ */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); -#if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) +#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); -#endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ +#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.c index df438113ad5..9eccce65384 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_can.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief CAN HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Controller Area Network (CAN) peripheral: @@ -27,12 +27,16 @@ (++) Connect and configure the involved CAN pins using the following function HAL_GPIO_Init(); - (#) Initialise and configure the CAN using HAL_CAN_Init() function. + (#) Initialize and configure the CAN using HAL_CAN_Init() function. (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function. + + (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function. (#) Receive a CAN frame using HAL_CAN_Receive() function. + (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function. + *** Polling mode IO operation *** ================================= [..] @@ -73,7 +77,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -102,12 +106,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" - -#ifdef HAL_CAN_MODULE_ENABLED - -#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \ - defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) - + /** @addtogroup STM32F1xx_HAL_Driver * @{ */ @@ -117,31 +116,34 @@ * @{ */ +#ifdef HAL_CAN_MODULE_ENABLED + +#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \ + defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) + + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup CAN_Private_Constants CAN Private Constants * @{ */ -#define CAN_TIMEOUT_VALUE 10 - -#define CAN_TI0R_STID_BIT_POSITION ((uint32_t)21) /* Position of LSB bits STID in register CAN_TI0R */ -#define CAN_TI0R_EXID_BIT_POSITION ((uint32_t) 3) /* Position of LSB bits EXID in register CAN_TI0R */ -#define CAN_TDL0R_DATA0_BIT_POSITION ((uint32_t) 0) /* Position of LSB bits DATA0 in register CAN_TDL0R */ -#define CAN_TDL0R_DATA1_BIT_POSITION ((uint32_t) 8) /* Position of LSB bits DATA1 in register CAN_TDL0R */ -#define CAN_TDL0R_DATA2_BIT_POSITION ((uint32_t)16) /* Position of LSB bits DATA2 in register CAN_TDL0R */ -#define CAN_TDL0R_DATA3_BIT_POSITION ((uint32_t)24) /* Position of LSB bits DATA3 in register CAN_TDL0R */ - +#define CAN_TIMEOUT_VALUE 10U /** * @} */ - /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @defgroup CAN_Private_Functions CAN Private Functions + * @{ + */ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber); static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); -/* Exported functions ---------------------------------------------------------*/ +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ /** @defgroup CAN_Exported_Functions CAN Exported Functions * @{ */ @@ -171,8 +173,8 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan); HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) { uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ - uint32_t tickstart = 0; - uint32_t tmp_mcr = 0; + uint32_t tickstart = 0U; + uint32_t tmp_mcr = 0U; /* Check CAN handle */ if(hcan == NULL) @@ -220,10 +222,8 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; } } @@ -236,36 +236,58 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) { SET_BIT(tmp_mcr, CAN_MCR_TTCM); } + else + { + CLEAR_BIT(tmp_mcr, CAN_MCR_TTCM); + } /* Set the automatic bus-off management */ if (hcan->Init.ABOM == ENABLE) { SET_BIT(tmp_mcr, CAN_MCR_ABOM); } + else + { + CLEAR_BIT(tmp_mcr, CAN_MCR_ABOM); + } /* Set the automatic wake-up mode */ if (hcan->Init.AWUM == ENABLE) { SET_BIT(tmp_mcr, CAN_MCR_AWUM); } - + else + { + CLEAR_BIT(tmp_mcr, CAN_MCR_AWUM); + } /* Set the no automatic retransmission */ if (hcan->Init.NART == ENABLE) { SET_BIT(tmp_mcr, CAN_MCR_NART); } + else + { + CLEAR_BIT(tmp_mcr, CAN_MCR_NART); + } /* Set the receive FIFO locked mode */ if (hcan->Init.RFLM == ENABLE) { SET_BIT(tmp_mcr, CAN_MCR_RFLM); } - + else + { + CLEAR_BIT(tmp_mcr, CAN_MCR_RFLM); + } /* Set the transmit FIFO priority */ if (hcan->Init.TXFP == ENABLE) { SET_BIT(tmp_mcr, CAN_MCR_TXFP); } + else + { + CLEAR_BIT(tmp_mcr, CAN_MCR_TXFP); + } /* Update register MCR */ MODIFY_REG(hcan->Instance->MCR, @@ -282,7 +304,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) hcan->Init.SJW | hcan->Init.BS1 | hcan->Init.BS2 | - (hcan->Init.Prescaler - 1) )); + (hcan->Init.Prescaler - 1U))); /* Request leave initialisation */ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); @@ -291,7 +313,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) tickstart = HAL_GetTick(); /* Wait the acknowledge */ - while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK)) + while(HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)) { if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) { @@ -305,7 +327,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) } /* Check acknowledged */ - if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)) + if(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK)) { status = CAN_INITSTATUS_SUCCESS; } @@ -326,7 +348,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) { /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_ERROR; - + /* Return function status */ return HAL_ERROR; } @@ -343,8 +365,11 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) { - uint32_t filternbrbitpos = 0; + uint32_t filternbrbitpos = 0U; + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + /* Check the parameters */ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); @@ -353,18 +378,18 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); - filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; + filternbrbitpos = (1U) << sFilterConfig->FilterNumber; /* Initialisation mode for the filter */ /* Select the start slave bank */ MODIFY_REG(hcan->Instance->FMR , CAN_FMR_CAN2SB , CAN_FMR_FINIT | - (uint32_t)(sFilterConfig->BankNumber << 8) ); - + (uint32_t)(sFilterConfig->BankNumber << 8U) ); + /* Filter Deactivation */ CLEAR_BIT(hcan->Instance->FA1R, filternbrbitpos); - + /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) { @@ -374,14 +399,14 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) @@ -390,12 +415,12 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy SET_BIT(hcan->Instance->FS1R, filternbrbitpos); /* 32-bit identifier or First 32-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); /* 32-bit mask or Second 32-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); } /* Filter Mode */ @@ -503,8 +528,8 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) */ /** @defgroup CAN_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions - * + * @brief I/O operation functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -529,7 +554,7 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) { uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX; - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); @@ -539,33 +564,39 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) - { + { /* Process locked */ __HAL_LOCK(hcan); - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; } /* Select one empty transmit mailbox */ if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) { - transmitmailbox = 0; + transmitmailbox = CAN_TXMAILBOX_0; } else if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) { - transmitmailbox = 1; + transmitmailbox = CAN_TXMAILBOX_1; } else { - transmitmailbox = 2; + transmitmailbox = CAN_TXMAILBOX_2; } /* Set up the Id */ @@ -573,35 +604,35 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) if (hcan->pTxMsg->IDE == CAN_ID_STD) { assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_BIT_POSITION) | + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | hcan->pTxMsg->RTR); } else { assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_BIT_POSITION) | + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | hcan->pTxMsg->IDE | hcan->pTxMsg->RTR); } /* Set up the DLC */ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U; hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_BIT_POSITION) ); - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_BIT_POSITION) ); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_Pos)); /* Request transmission */ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); - /* Get tick */ + /* Get tick */ tickstart = HAL_GetTick(); /* Check End of transmission flag */ @@ -610,24 +641,34 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hcan->State = HAL_CAN_STATE_TIMEOUT; + + /* Cancel transmission */ + __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox); + /* Process unlocked */ __HAL_UNLOCK(hcan); return HAL_TIMEOUT; } } } - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - else + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; } /* Process unlocked */ @@ -671,57 +712,63 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) /* Select one empty transmit mailbox */ if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0)) { - transmitmailbox = 0; + transmitmailbox = CAN_TXMAILBOX_0; } else if(HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1)) { - transmitmailbox = 1; + transmitmailbox = CAN_TXMAILBOX_1; } else { - transmitmailbox = 2; + transmitmailbox = CAN_TXMAILBOX_2; } /* Set up the Id */ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; - if (hcan->pTxMsg->IDE == CAN_ID_STD) + if(hcan->pTxMsg->IDE == CAN_ID_STD) { assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_BIT_POSITION) | + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << CAN_TI0R_STID_Pos) | \ hcan->pTxMsg->RTR); } else { assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_BIT_POSITION) | + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << CAN_TI0R_EXID_Pos) | \ hcan->pTxMsg->IDE | hcan->pTxMsg->RTR); } /* Set up the DLC */ - hcan->pTxMsg->DLC &= (uint8_t)0x0000000F; - hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0; + hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; + hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U; hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3] << CAN_TDL0R_DATA3_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[2] << CAN_TDL0R_DATA2_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[1] << CAN_TDL0R_DATA1_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[0] << CAN_TDL0R_DATA0_BIT_POSITION) ); - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7] << CAN_TDL0R_DATA3_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[6] << CAN_TDL0R_DATA2_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[5] << CAN_TDL0R_DATA1_BIT_POSITION) | - ((uint32_t)hcan->pTxMsg->Data[4] << CAN_TDL0R_DATA0_BIT_POSITION) ); - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, ((uint32_t)hcan->pTxMsg->Data[3U] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[2U] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[1U] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[0U] << CAN_TDL0R_DATA0_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, ((uint32_t)hcan->pTxMsg->Data[7U] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)hcan->pTxMsg->Data[6U] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)hcan->pTxMsg->Data[5U] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)hcan->pTxMsg->Data[4U] << CAN_TDL0R_DATA0_Pos)); + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; } /* Set CAN error code to none */ @@ -730,6 +777,9 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) /* Process Unlocked */ __HAL_UNLOCK(hcan); + /* Request transmission */ + hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; + /* Enable interrupts: */ /* - Enable Error warning Interrupt */ /* - Enable Error passive Interrupt */ @@ -743,9 +793,6 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) CAN_IT_LEC | CAN_IT_ERR | CAN_IT_TME ); - - /* Request transmission */ - hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; } else { @@ -766,75 +813,129 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan) * @param FIFONumber: FIFO Number value * @param Timeout: Specify Timeout value * @retval HAL status - * @retval None */ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + CanRxMsgTypeDef* pRxMsg = NULL; + /* Check the parameters */ assert_param(IS_CAN_FIFO(FIFONumber)); - + + /* Check if CAN state is not busy for RX FIFO0 */ + if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + + /* Check if CAN state is not busy for RX FIFO1 */ + if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } + /* Process locked */ __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + } } - else + else /* FIFONumber == CAN_FIFO1 */ { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + } } - /* Get tick */ tickstart = HAL_GetTick(); /* Check pending message */ - while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0) + while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { hcan->State = HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; } } } - + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) + { + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) + pRxMsg->IDE = (uint8_t)CAN_ID_EXT & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) { - hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); } else { - hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); } - hcan->pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + pRxMsg->RTR = (uint8_t)CAN_RTR_REMOTE & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); + pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); - hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); - hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); - hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); - hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); - hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); + pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); + pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); + pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); + pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); + pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); + pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); /* Release the FIFO */ if(FIFONumber == CAN_FIFO0) @@ -848,17 +949,44 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); } - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } - else + else /* FIFONumber == CAN_FIFO1 */ { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } - + /* Process unlocked */ __HAL_UNLOCK(hcan); @@ -872,66 +1000,102 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u * the configuration information for the specified CAN. * @param FIFONumber: Specify the FIFO number * @retval HAL status - * @retval None */ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) { /* Check the parameters */ assert_param(IS_CAN_FIFO(FIFONumber)); - if((hcan->State == HAL_CAN_STATE_READY) || (hcan->State == HAL_CAN_STATE_BUSY_TX)) + /* Check if CAN state is not busy for RX FIFO0 */ + if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) { - /* Process locked */ - __HAL_LOCK(hcan); - - if(hcan->State == HAL_CAN_STATE_BUSY_TX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX_RX; - } - else - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; - } - - /* Set CAN error code to none */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Enable interrupts: */ - /* - Enable Error warning Interrupt */ - /* - Enable Error passive Interrupt */ - /* - Enable Bus-off Interrupt */ - /* - Enable Last error code Interrupt */ - /* - Enable Error Interrupt */ - /* - Enable Transmit mailbox empty Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | - CAN_IT_EPV | - CAN_IT_BOF | - CAN_IT_LEC | - CAN_IT_ERR | - CAN_IT_TME ); + return HAL_BUSY; + } - /* Process unlocked */ - __HAL_UNLOCK(hcan); + /* Check if CAN state is not busy for RX FIFO1 */ + if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \ + (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1))) + { + return HAL_BUSY; + } - if(FIFONumber == CAN_FIFO0) + /* Process locked */ + __HAL_LOCK(hcan); + + /* Change CAN state */ + if(FIFONumber == CAN_FIFO0) + { + switch(hcan->State) { - /* Enable FIFO 0 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP0); + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + case(HAL_CAN_STATE_BUSY_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; } - else + } + else /* FIFONumber == CAN_FIFO1 */ + { + switch(hcan->State) { - /* Enable FIFO 1 message pending Interrupt */ - __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FMP1); + case(HAL_CAN_STATE_BUSY_TX): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + case(HAL_CAN_STATE_BUSY_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1; + break; + default: /* HAL_CAN_STATE_READY */ + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; } - + } + /* Set CAN error code to none */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + + /* Enable interrupts: */ + /* - Enable Error warning Interrupt */ + /* - Enable Error passive Interrupt */ + /* - Enable Bus-off Interrupt */ + /* - Enable Last error code Interrupt */ + /* - Enable Error Interrupt */ + /* - Enable Transmit mailbox empty Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_TME ); + + /* Process unlocked */ + __HAL_UNLOCK(hcan); + + if(FIFONumber == CAN_FIFO0) + { + /* Enable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); } else { - return HAL_BUSY; + /* Enable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); } - + /* Return function status */ return HAL_OK; } @@ -944,7 +1108,7 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber */ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Process locked */ __HAL_LOCK(hcan); @@ -956,7 +1120,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) MODIFY_REG(hcan->Instance->MCR, CAN_MCR_INRQ , CAN_MCR_SLEEP ); - + /* Sleep mode status */ if (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) || HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) ) @@ -968,20 +1132,20 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) return HAL_ERROR; } - /* Get tick */ + /* Get tick */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ while (HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_SLAK) || - HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK) ) + HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK)) { if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) { hcan->State = HAL_CAN_STATE_TIMEOUT; - + /* Process unlocked */ __HAL_UNLOCK(hcan); - + return HAL_TIMEOUT; } } @@ -1005,7 +1169,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan) */ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Process locked */ __HAL_LOCK(hcan); @@ -1025,10 +1189,8 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; - /* Process unlocked */ __HAL_UNLOCK(hcan); - return HAL_TIMEOUT; } } @@ -1059,70 +1221,125 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan) */ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) { + uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U; + uint32_t errorcode = HAL_CAN_ERROR_NONE; + + /* Check Overrun flag for FIFO0 */ + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0); + if((tmp1 != 0U) && tmp2) + { + /* Set CAN error code to FOV0 error */ + errorcode |= HAL_CAN_ERROR_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + + /* Check Overrun flag for FIFO1 */ + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1); + if((tmp1 != 0U) && tmp2) + { + /* Set CAN error code to FOV1 error */ + errorcode |= HAL_CAN_ERROR_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + /* Check End of transmission flag */ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME)) { - if((__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0)) || - (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1)) || - (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))) + /* Check Transmit request completion status */ + tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0); + tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1); + tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2); + if(tmp1 || tmp2 || tmp3) { - /* Call transmit function */ - CAN_Transmit_IT(hcan); + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0); + tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1); + tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2); + /* Check Transmit success */ + if((tmp1) || (tmp2) || (tmp3)) + { + /* Call transmit function */ + CAN_Transmit_IT(hcan); + } + else /* Transmit failure */ + { + /* Set CAN error code to TXFAIL error */ + errorcode |= HAL_CAN_ERROR_TXFAIL; + } + + /* Clear transmission status flags (RQCPx and TXOKx) */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \ + CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2); } } + tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0); /* Check End of reception flag for FIFO0 */ - if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0) != 0)) + if((tmp1 != 0U) && tmp2) { /* Call receive function */ CAN_Receive_IT(hcan, CAN_FIFO0); } + tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1); /* Check End of reception flag for FIFO1 */ - if((__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1)) && - (__HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1) != 0)) + if((tmp1 != 0U) && tmp2) { /* Call receive function */ CAN_Receive_IT(hcan, CAN_FIFO1); } - + + /* Set error code in handle */ + hcan->ErrorCode |= errorcode; + + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); /* Check Error Warning Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + if(tmp1 && tmp2 && tmp3) { /* Set CAN error code to EWG error */ hcan->ErrorCode |= HAL_CAN_ERROR_EWG; /* No need for clear of Error Warning Flag as read-only */ } + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); /* Check Error Passive Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + if(tmp1 && tmp2 && tmp3) { /* Set CAN error code to EPV error */ hcan->ErrorCode |= HAL_CAN_ERROR_EPV; /* No need for clear of Error Passive Flag as read-only */ } + tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); /* Check Bus-Off Flag */ - if((__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + if(tmp1 && tmp2 && tmp3) { /* Set CAN error code to BOF error */ hcan->ErrorCode |= HAL_CAN_ERROR_BOF; /* No need for clear of Bus-Off Flag as read-only */ } + tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC); + tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC); + tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR); /* Check Last error code Flag */ - if((!HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC)) && - (__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR))) + if((!tmp1) && tmp2 && tmp3) { - switch(hcan->Instance->ESR & CAN_ESR_LEC) + tmp1 = (hcan->Instance->ESR & CAN_ESR_LEC); + switch(tmp1) { case(CAN_ESR_LEC_0): /* Set CAN error code to STF error */ @@ -1155,15 +1372,37 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan) /* Clear Last error code Flag */ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); } - + /* Call the Error call Back in case of Errors */ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE) { /* Clear ERRI Flag */ - hcan->Instance->MSR |= CAN_MSR_ERRI; + hcan->Instance->MSR = CAN_MSR_ERRI; /* Set the CAN state ready to be able to start again the process */ hcan->State = HAL_CAN_STATE_READY; - + + /* Disable interrupts: */ + /* - Disable Error warning Interrupt */ + /* - Disable Error passive Interrupt */ + /* - Disable Bus-off Interrupt */ + /* - Disable Last error code Interrupt */ + /* - Disable Error Interrupt */ + /* - Disable FIFO 0 message pending Interrupt */ + /* - Disable FIFO 0 Overrun Interrupt */ + /* - Disable FIFO 1 message pending Interrupt */ + /* - Disable FIFO 1 Overrun Interrupt */ + /* - Disable Transmit mailbox empty Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG | + CAN_IT_EPV | + CAN_IT_BOF | + CAN_IT_LEC | + CAN_IT_ERR | + CAN_IT_FMP0| + CAN_IT_FOV0| + CAN_IT_FMP1| + CAN_IT_FOV1| + CAN_IT_TME ); + /* Call Error callback function */ HAL_CAN_ErrorCallback(hcan); } @@ -1219,8 +1458,8 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) */ /** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * + * @brief CAN Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -1265,9 +1504,9 @@ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) * @} */ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ +/** @addtogroup CAN_Private_Functions + * @{ + */ /** * @brief Initiates and transmits a CAN frame message. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains @@ -1291,20 +1530,26 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) CAN_IT_EPV | CAN_IT_BOF | CAN_IT_LEC | - CAN_IT_ERR ); - } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) - { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_RX; + CAN_IT_ERR); } - else + + /* Change CAN state */ + switch(hcan->State) { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_TX */ + hcan->State = HAL_CAN_STATE_READY; + break; } - + /* Transmission complete callback */ HAL_CAN_TxCpltCallback(hcan); @@ -1321,50 +1566,66 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan) */ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber) { + uint32_t tmp1 = 0U; + CanRxMsgTypeDef* pRxMsg = NULL; + + /* Set RxMsg pointer */ + if(FIFONumber == CAN_FIFO0) + { + pRxMsg = hcan->pRxMsg; + } + else /* FIFONumber == CAN_FIFO1 */ + { + pRxMsg = hcan->pRx1Msg; + } + /* Get the Id */ - hcan->pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; - if (hcan->pRxMsg->IDE == CAN_ID_STD) + pRxMsg->IDE = (uint8_t)0x04U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + if (pRxMsg->IDE == CAN_ID_STD) { - hcan->pRxMsg->StdId = (uint32_t)0x000007FF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21); + pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U); } else { - hcan->pRxMsg->ExtId = (uint32_t)0x1FFFFFFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3); + pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U); } - hcan->pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; + pRxMsg->RTR = (uint8_t)0x02U & hcan->Instance->sFIFOMailBox[FIFONumber].RIR; /* Get the DLC */ - hcan->pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + pRxMsg->DLC = (uint8_t)0x0FU & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FIFONumber */ + pRxMsg->FIFONumber = FIFONumber; /* Get the FMI */ - hcan->pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8); + pRxMsg->FMI = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U); /* Get the data field */ - hcan->pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; - hcan->pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8); - hcan->pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16); - hcan->pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24); - hcan->pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; - hcan->pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8); - hcan->pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16); - hcan->pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24); + pRxMsg->Data[0] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR; + pRxMsg->Data[1] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U); + pRxMsg->Data[2] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U); + pRxMsg->Data[3] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U); + pRxMsg->Data[4] = (uint8_t)0xFFU & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR; + pRxMsg->Data[5] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U); + pRxMsg->Data[6] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U); + pRxMsg->Data[7] = (uint8_t)0xFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U); /* Release the FIFO */ /* Release FIFO0 */ if (FIFONumber == CAN_FIFO0) { __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0); - /* Disable FIFO 0 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP0); + /* Disable FIFO 0 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0); } /* Release FIFO1 */ else /* FIFONumber == CAN_FIFO1 */ { __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1); - /* Disable FIFO 1 message pending Interrupt */ - __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FMP1); + /* Disable FIFO 1 overrun and message pending Interrupt */ + __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1); } - - if(hcan->State == HAL_CAN_STATE_BUSY_RX) + + tmp1 = hcan->State; + if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1)) { /* Disable interrupts: */ /* - Disable Error warning Interrupt */ @@ -1376,18 +1637,45 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum CAN_IT_EPV | CAN_IT_BOF | CAN_IT_LEC | - CAN_IT_ERR ); + CAN_IT_ERR); } - - if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) + + /* Change CAN state */ + if (FIFONumber == CAN_FIFO0) { - /* Disable CAN state */ - hcan->State = HAL_CAN_STATE_BUSY_TX; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX0): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX1; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX1; + break; + default: /* HAL_CAN_STATE_BUSY_RX0 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } - else + else /* FIFONumber == CAN_FIFO1 */ { - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_READY; + switch(hcan->State) + { + case(HAL_CAN_STATE_BUSY_TX_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX; + break; + case(HAL_CAN_STATE_BUSY_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_RX0; + break; + case(HAL_CAN_STATE_BUSY_TX_RX0_RX1): + hcan->State = HAL_CAN_STATE_BUSY_TX_RX0; + break; + default: /* HAL_CAN_STATE_BUSY_RX1 */ + hcan->State = HAL_CAN_STATE_READY; + break; + } } /* Receive complete callback */ @@ -1397,18 +1685,15 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum return HAL_OK; } -/** - * @} - */ - /** * @} */ - -#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */ - /* STM32F103xG) || STM32F105xC || STM32F107xC */ +#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */ #endif /* HAL_CAN_MODULE_ENABLED */ +/** + * @} + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.h index 79d3b330a2f..9be1de209ad 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_hal_can.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -36,13 +36,13 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __stm32f1xx_CAN_H -#define __stm32f1xx_CAN_H +#ifndef __STM32F1xx_HAL_CAN_H +#define __STM32F1xx_HAL_CAN_H #ifdef __cplusplus extern "C" { #endif - + #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \ defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) @@ -60,37 +60,41 @@ /* Exported types ------------------------------------------------------------*/ /** @defgroup CAN_Exported_Types CAN Exported Types * @{ - */ -/** - * @brief HAL State structures definition - */ + */ + +/** + * @brief HAL State structures definition + */ typedef enum { - HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */ - HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */ - HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */ - HAL_CAN_STATE_TIMEOUT = 0x03, /*!< CAN in Timeout state */ - HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ + HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ + HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ }HAL_CAN_StateTypeDef; - -/** +/** * @brief CAN init structure definition */ typedef struct { - uint32_t Prescaler; /*!< Specifies the length of a time quantum. - This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ - + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ + uint32_t Mode; /*!< Specifies the CAN operating mode. This parameter can be a value of @ref CAN_operating_mode */ - uint32_t SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or + uint32_t SJW; /*!< Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter can be a value of @ref CAN_synchronisation_jump_width */ @@ -99,24 +103,24 @@ typedef struct uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - + uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. This parameter can be set to ENABLE or DISABLE. */ - + uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set to ENABLE or DISABLE. */ + This parameter can be set to ENABLE or DISABLE */ - uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set to ENABLE or DISABLE. */ + uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE */ uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set to ENABLE or DISABLE. */ + This parameter can be set to ENABLE or DISABLE */ - uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set to ENABLE or DISABLE. */ + uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE */ uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set to ENABLE or DISABLE. */ + This parameter can be set to ENABLE or DISABLE */ }CAN_InitTypeDef; /** @@ -125,81 +129,84 @@ typedef struct typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ + uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. - This parameter can be a value of @ref CAN_identifier_type */ + This parameter can be a value of @ref CAN_Identifier_Type */ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref CAN_remote_transmission_request */ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ - uint8_t Data[8]; /*!< Contains the data to be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ - }CanTxMsgTypeDef; -/** - * @brief CAN Rx message structure definition +/** + * @brief CAN Rx message structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. - This parameter can be a value of @ref CAN_identifier_type */ + This parameter can be a value of @ref CAN_Identifier_Type */ uint32_t RTR; /*!< Specifies the type of frame for the received message. This parameter can be a value of @ref CAN_remote_transmission_request */ uint32_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ - uint8_t Data[8]; /*!< Contains the data to be received. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + uint8_t Data[8]; /*!< Contains the data to be received. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ - uint32_t FIFONumber; /*!< Specifies the receive FIFO number. - This parameter can be a value of @ref CAN_receive_FIFO_number_constants */ + uint32_t FIFONumber; /*!< Specifies the receive FIFO number. + This parameter can be CAN_FIFO0 or CAN_FIFO1 */ }CanRxMsgTypeDef; -/** - * @brief CAN handle Structure definition - */ +/** + * @brief CAN handle Structure definition + */ typedef struct { CAN_TypeDef *Instance; /*!< Register base address */ - + CAN_InitTypeDef Init; /*!< CAN required parameters */ - + CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ - CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */ - - HAL_LockTypeDef Lock; /*!< CAN locking object */ - + CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ + + CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - + + HAL_LockTypeDef Lock; /*!< CAN locking object */ + __IO uint32_t ErrorCode; /*!< CAN Error code */ - + }CAN_HandleTypeDef; + /** * @} */ -/* Exported constants --------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ /** @defgroup CAN_Exported_Constants CAN Exported Constants * @{ */ @@ -207,30 +214,28 @@ typedef struct /** @defgroup CAN_Error_Code CAN Error Code * @{ */ - - -#define HAL_CAN_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_CAN_ERROR_EWG ((uint32_t)0x01) /*!< EWG error */ -#define HAL_CAN_ERROR_EPV ((uint32_t)0x02) /*!< EPV error */ -#define HAL_CAN_ERROR_BOF ((uint32_t)0x04) /*!< BOF error */ -#define HAL_CAN_ERROR_STF ((uint32_t)0x08) /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR ((uint32_t)0x10) /*!< Form error */ -#define HAL_CAN_ERROR_ACK ((uint32_t)0x20) /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR ((uint32_t)0x40) /*!< Bit recessive */ -#define HAL_CAN_ERROR_BD ((uint32_t)0x80) /*!< LEC dominant */ -#define HAL_CAN_ERROR_CRC ((uint32_t)0x100) /*!< LEC transfer error */ - - +#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ +#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ +#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ +#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ +#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ +#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ +#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ +#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ +#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ +#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ /** * @} */ - /** @defgroup CAN_InitStatus CAN initialization Status * @{ */ -#define CAN_INITSTATUS_FAILED ((uint32_t)0x00000000) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS ((uint32_t)0x00000001) /*!< CAN initialization OK */ +#define CAN_INITSTATUS_FAILED 0x00000000U /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS 0x00000001U /*!< CAN initialization OK */ /** * @} */ @@ -238,24 +243,21 @@ typedef struct /** @defgroup CAN_operating_mode CAN Operating Mode * @{ */ -#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ +#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ - /** * @} */ - /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width * @{ */ -#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */ #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ - /** * @} */ @@ -263,7 +265,7 @@ typedef struct /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 * @{ */ -#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */ #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ @@ -279,15 +281,14 @@ typedef struct #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ - /** * @} */ -/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 * @{ */ -#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */ +#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */ #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ @@ -295,17 +296,15 @@ typedef struct #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ - /** * @} */ -/** @defgroup CAN_filter_mode CAN Filter Mode +/** @defgroup CAN_filter_mode CAN Filter Mode * @{ */ #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ - /** * @} */ @@ -315,7 +314,6 @@ typedef struct */ #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ - /** * @} */ @@ -325,18 +323,15 @@ typedef struct */ #define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ #define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ - - /** * @} */ -/** @defgroup CAN_identifier_type CAN Identifier Type +/** @defgroup CAN_Identifier_Type CAN Identifier Type * @{ */ -#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ - +#define CAN_ID_STD 0x00000000U /*!< Standard Id */ +#define CAN_ID_EXT 0x00000004U /*!< Extended Id */ /** * @} */ @@ -344,9 +339,8 @@ typedef struct /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request * @{ */ -#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ - +#define CAN_RTR_DATA 0x00000000U /*!< Data frame */ +#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */ /** * @} */ @@ -355,7 +349,6 @@ typedef struct * @{ */ #define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ - /** * @} */ @@ -365,7 +358,6 @@ typedef struct */ #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ - /** * @} */ @@ -375,7 +367,7 @@ typedef struct */ /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with +/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ /* Transmit Flags */ @@ -400,6 +392,7 @@ typedef struct #define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */ #define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */ #define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */ + /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. In this case the SLAK bit can be polled.*/ @@ -412,10 +405,9 @@ typedef struct * @} */ - -/** @defgroup CAN_interrupts CAN Interrupts +/** @defgroup CAN_Interrupts CAN Interrupts * @{ - */ + */ #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ /* Receive Interrupts */ @@ -436,14 +428,10 @@ typedef struct #define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ - - /** * @} */ - - /** * @} */ @@ -453,57 +441,54 @@ typedef struct */ /* CAN intermediate shift values used for CAN flags */ -#define TSR_REGISTER_INDEX ((uint32_t)0x5) -#define RF0R_REGISTER_INDEX ((uint32_t)0x2) -#define RF1R_REGISTER_INDEX ((uint32_t)0x4) -#define MSR_REGISTER_INDEX ((uint32_t)0x1) -#define ESR_REGISTER_INDEX ((uint32_t)0x3) +#define TSR_REGISTER_INDEX 0x5U +#define RF0R_REGISTER_INDEX 0x2U +#define RF1R_REGISTER_INDEX 0x4U +#define MSR_REGISTER_INDEX 0x1U +#define ESR_REGISTER_INDEX 0x3U /* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */ /* Transmit Flags */ -#define CAN_TSR_RQCP0_BIT_POSITION ((uint32_t)0x00000000) -#define CAN_TSR_RQCP1_BIT_POSITION ((uint32_t)0x00000008) -#define CAN_TSR_RQCP2_BIT_POSITION ((uint32_t)0x00000010) -#define CAN_TSR_TXOK0_BIT_POSITION ((uint32_t)0x00000001) -#define CAN_TSR_TXOK1_BIT_POSITION ((uint32_t)0x00000009) -#define CAN_TSR_TXOK2_BIT_POSITION ((uint32_t)0x00000011) -#define CAN_TSR_TME0_BIT_POSITION ((uint32_t)0x0000001A) -#define CAN_TSR_TME1_BIT_POSITION ((uint32_t)0x0000001B) -#define CAN_TSR_TME2_BIT_POSITION ((uint32_t)0x0000001C) +#define CAN_TSR_RQCP0_BIT_POSITION 0x00000000U +#define CAN_TSR_RQCP1_BIT_POSITION 0x00000008U +#define CAN_TSR_RQCP2_BIT_POSITION 0x00000010U +#define CAN_TSR_TXOK0_BIT_POSITION 0x00000001U +#define CAN_TSR_TXOK1_BIT_POSITION 0x00000009U +#define CAN_TSR_TXOK2_BIT_POSITION 0x00000011U +#define CAN_TSR_TME0_BIT_POSITION 0x0000001AU +#define CAN_TSR_TME1_BIT_POSITION 0x0000001BU +#define CAN_TSR_TME2_BIT_POSITION 0x0000001CU /* Receive Flags */ -#define CAN_RF0R_FF0_BIT_POSITION ((uint32_t)0x00000003) -#define CAN_RF0R_FOV0_BIT_POSITION ((uint32_t)0x00000004) +#define CAN_RF0R_FF0_BIT_POSITION 0x00000003U +#define CAN_RF0R_FOV0_BIT_POSITION 0x00000004U -#define CAN_RF1R_FF1_BIT_POSITION ((uint32_t)0x00000003) -#define CAN_RF1R_FOV1_BIT_POSITION ((uint32_t)0x00000004) +#define CAN_RF1R_FF1_BIT_POSITION 0x00000003U +#define CAN_RF1R_FOV1_BIT_POSITION 0x00000004U /* Operating Mode Flags */ -#define CAN_MSR_WKU_BIT_POSITION ((uint32_t)0x00000003) -#define CAN_MSR_SLAK_BIT_POSITION ((uint32_t)0x00000001) -#define CAN_MSR_SLAKI_BIT_POSITION ((uint32_t)0x00000004) +#define CAN_MSR_WKU_BIT_POSITION 0x00000003U +#define CAN_MSR_SLAK_BIT_POSITION 0x00000001U +#define CAN_MSR_SLAKI_BIT_POSITION 0x00000004U /* Error Flags */ -#define CAN_ESR_EWG_BIT_POSITION ((uint32_t)0x00000000) -#define CAN_ESR_EPV_BIT_POSITION ((uint32_t)0x00000001) -#define CAN_ESR_BOF_BIT_POSITION ((uint32_t)0x00000002) +#define CAN_ESR_EWG_BIT_POSITION 0x00000000U +#define CAN_ESR_EPV_BIT_POSITION 0x00000001U +#define CAN_ESR_BOF_BIT_POSITION 0x00000002U /* Mask used by macro to get/clear CAN flags*/ -#define CAN_FLAG_MASK ((uint32_t)0x000000FF) +#define CAN_FLAG_MASK 0x000000FFU /* Mailboxes definition */ #define CAN_TXMAILBOX_0 ((uint8_t)0x00) #define CAN_TXMAILBOX_1 ((uint8_t)0x01) #define CAN_TXMAILBOX_2 ((uint8_t)0x02) - - /** * @} */ - /* Exported macros -----------------------------------------------------------*/ -/** @defgroup CAN_Exported_Macro CAN Exported Macros +/** @defgroup CAN_Exported_Macros CAN Exported Macros * @{ */ @@ -566,7 +551,7 @@ typedef struct * @retval The number of pending message. */ #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03))) +((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U))) /** @brief Check whether the specified CAN flag is set or not. * @param __HANDLE__: specifies the CAN Handle. @@ -596,10 +581,10 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ +((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) /** @brief Clear the specified CAN pending flag. @@ -629,8 +614,7 @@ typedef struct ((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0) - + (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) /** @brief Check if the specified CAN interrupt source is enabled or disabled. * @param __HANDLE__: specifies the CAN Handle. @@ -661,9 +645,9 @@ typedef struct * @retval The new status of transmission (TRUE or FALSE). */ #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ - ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\ + ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2))) /** * @brief Release the specified receive FIFO. @@ -672,7 +656,7 @@ typedef struct * @retval None. */ #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) +((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) /** * @brief Cancel a transmit request. @@ -681,68 +665,21 @@ typedef struct * @retval None. */ #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\ - ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2)) +(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ + ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ + ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) /** * @brief Enable or disables the DBG Freeze for CAN. * @param __HANDLE__: specifies the CAN Handle. - * @param __NEWSTATE__: new state of the CAN peripheral. + * @param __NEWSTATE__: new state of the CAN peripheral. * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) + * during debug. Reception FIFOs can still be accessed/controlled normally) * or DISABLE (CAN is working during debug). * @retval None */ #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ -((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup CAN_Private_Macros CAN Private Macros - * @{ - */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ - ((MODE) == CAN_MODE_LOOPBACK)|| \ - ((MODE) == CAN_MODE_SILENT) || \ - ((MODE) == CAN_MODE_SILENT_LOOPBACK)) - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ - ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ - ((MODE) == CAN_FILTERMODE_IDLIST)) - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ - ((SCALE) == CAN_FILTERSCALE_32BIT)) - - -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ - ((FIFO) == CAN_FILTER_FIFO1)) - -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ - ((IDTYPE) == CAN_ID_EXT)) - -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) - -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28) - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) +((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) /** * @} @@ -751,30 +688,30 @@ typedef struct /* Include CAN HAL Extension module */ #include "stm32f1xx_hal_can_ex.h" -/* Exported functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup CAN_Exported_Functions * @{ */ - + /** @addtogroup CAN_Exported_Functions_Group1 - * @brief Initialization and Configuration functions - * @{ - */ -/* Initialization and de-initialization functions *****************************/ + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); /** - * @} - */ - + * @} + */ + /** @addtogroup CAN_Exported_Functions_Group2 - * @brief I/O operation functions - * @{ - */ -/* IO operation functions *****************************************************/ + * @brief I/O operation functions + * @{ + */ +/* I/O operation functions *****************************************************/ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); @@ -786,24 +723,61 @@ void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); /** - * @} - */ - + * @} + */ + /** @addtogroup CAN_Exported_Functions_Group3 - * @brief CAN Peripheral State functions - * @{ - */ + * @brief CAN Peripheral State functions + * @{ + */ /* Peripheral State and Error functions ***************************************/ uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); /** - * @} - */ - + * @} + */ + /** - * @} - */ - + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) +#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + /** * @} */ @@ -812,14 +786,13 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); * @} */ -#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */ - /* STM32F103xG) || STM32F105xC || STM32F107xC */ +#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */ #ifdef __cplusplus } #endif -#endif /* __stm32f1xx_CAN_H */ +#endif /* __STM32F1xx_HAL_CAN_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can_ex.h index d7ea278000e..69995b52d0d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_can_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_can_ex.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of CAN HAL Extension module. ****************************************************************************** * @attention @@ -58,7 +58,7 @@ */ /* Exported types ------------------------------------------------------------*/ - + /** * @brief CAN filter configuration structure definition */ @@ -117,9 +117,9 @@ typedef struct * @{ */ #if defined(STM32F105xC) || defined(STM32F107xC) -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) #else -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) +#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13U) #endif /* STM32F105xC || STM32F107xC */ /** @@ -135,8 +135,7 @@ typedef struct * @} */ -#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || */ - /* STM32F103xG) || STM32F105xC || STM32F107xC */ +#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.c index dc3ce1fd2c3..96c61ac39ad 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.c @@ -2,39 +2,46 @@ ****************************************************************************** * @file stm32f1xx_hal_cec.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief CEC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface * Consumer Electronics Control Peripheral (CEC). - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * - * @verbatim - ============================================================================== + * + Initialization and de-initialization function + * + IO operation function + * + Peripheral Control function + * + * + @verbatim + =============================================================================== ##### How to use this driver ##### - ============================================================================== - [..] - The CEC HAL driver can be used as follows: + =============================================================================== + [..] + The CEC HAL driver can be used as follow: + (#) Declare a CEC_HandleTypeDef handle structure. (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API: (##) Enable the CEC interface clock. - (##) Enable the clock for the CEC GPIOs. - (##) Configure these CEC pins as alternate function pull-up. + (##) CEC pins configuration: + (+++) Enable the clock for the CEC GPIOs. + (+++) Configure these CEC pins as alternate function pull-up. (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT() and HAL_CEC_Receive_IT() APIs): - (##) Configure the CEC interrupt priority. - (##) Enable the NVIC CEC IRQ handle. - (##) The CEC interrupt is activated/deactivated by the HAL driver + (+++) Configure the CEC interrupt priority. + (+++) Enable the NVIC CEC IRQ handle. + (+++) The specific CEC interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit + and receive process. (#) Program the Bit Timing Error Mode and the Bit Period Error Mode in the hcec Init structure. (#) Initialize the CEC registers by calling the HAL_CEC_Init() API. - - (#) This API (HAL_CEC_Init()) configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized HAL_CEC_MspInit() API. + + [..] + (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc) + by calling the customed HAL_CEC_MspInit() API. @endverbatim ****************************************************************************** @@ -82,7 +89,7 @@ * @brief HAL CEC module driver * @{ */ - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup CEC_Private_Constants CEC Private Constants @@ -94,8 +101,8 @@ #define CEC_ESR_ALL_ERROR (CEC_ESR_BTE|CEC_ESR_BPE|CEC_ESR_RBTFE|CEC_ESR_SBE|CEC_ESR_ACKE|CEC_ESR_LINE|CEC_ESR_TBTFE) #define CEC_RXXFERSIZE_INITIALIZE 0xFFFF /*!< Value used to initialise the RxXferSize of the handle */ /** - * @} - */ + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -106,9 +113,9 @@ static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec); static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec); /** - * @} - */ - + * @} + */ + /* Exported functions ---------------------------------------------------------*/ /** @defgroup CEC_Exported_Functions CEC Exported Functions @@ -118,7 +125,7 @@ static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec); /** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== @@ -142,7 +149,7 @@ static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec); HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) { /* Check the CEC handle allocation */ - if(hcec == NULL) + if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL)) { return HAL_ERROR; } @@ -151,40 +158,42 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(hcec->Init.TimingErrorFree)); assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(hcec->Init.PeriodErrorFree)); - assert_param(IS_CEC_ADDRESS(hcec->Init.InitiatorAddress)); + assert_param(IS_CEC_ADDRESS(hcec->Init.OwnAddress)); - if(hcec->State == HAL_CEC_STATE_RESET) + if(hcec->gState == HAL_CEC_STATE_RESET) { /* Allocate lock resource and initialize it */ hcec->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK */ HAL_CEC_MspInit(hcec); } - - hcec->State = HAL_CEC_STATE_BUSY; + hcec->gState = HAL_CEC_STATE_BUSY; /* Disable the Peripheral */ __HAL_CEC_DISABLE(hcec); /* Write to CEC Control Register */ - MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, hcec->Init.TimingErrorFree|hcec->Init.PeriodErrorFree); + MODIFY_REG(hcec->Instance->CFGR, CEC_CFGR_FIELDS, hcec->Init.TimingErrorFree | hcec->Init.PeriodErrorFree); /* Write to CEC Own Address Register */ - MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.InitiatorAddress); + MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress); /* Configure the prescaler to generate the required 50 microseconds time base.*/ - MODIFY_REG(hcec->Instance->PRES, CEC_PRES_PRES, 50*(HAL_RCC_GetPCLK1Freq()/1000000)-1); + MODIFY_REG(hcec->Instance->PRES, CEC_PRES_PRES, 50U * (HAL_RCC_GetPCLK1Freq()/1000000U) - 1U); - /* Enable the Peripheral */ - __HAL_CEC_ENABLE(hcec); + /* Enable the following CEC Interrupt */ + __HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE); - hcec->State = HAL_CEC_STATE_READY; + /* Enable the CEC Peripheral */ + __HAL_CEC_ENABLE(hcec); + + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + hcec->gState = HAL_CEC_STATE_READY; + hcec->RxState = HAL_CEC_STATE_READY; return HAL_OK; } - - /** * @brief DeInitializes the CEC peripheral * @param hcec: CEC handle @@ -201,26 +210,17 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) /* Check the parameters */ assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); - hcec->State = HAL_CEC_STATE_BUSY; - - /* Set peripheral to reset state */ - hcec->Instance->CFGR = 0x0; - hcec->Instance->OAR = 0x0; - hcec->Instance->PRES = 0x0; - hcec->Instance->CFGR = 0x0; - hcec->Instance->ESR = 0x0; - hcec->Instance->CSR = 0x0; - hcec->Instance->TXD = 0x0; - hcec->Instance->RXD = 0x0; - - /* Disable the Peripheral */ - __HAL_CEC_DISABLE(hcec); - + hcec->gState = HAL_CEC_STATE_BUSY; + /* DeInit the low level hardware */ HAL_CEC_MspDeInit(hcec); + __HAL_RCC_CEC_FORCE_RESET(); + __HAL_RCC_CEC_RELEASE_RESET(); + hcec->ErrorCode = HAL_CEC_ERROR_NONE; - hcec->State = HAL_CEC_STATE_RESET; + hcec->gState = HAL_CEC_STATE_RESET; + hcec->RxState = HAL_CEC_STATE_RESET; /* Process Unlock */ __HAL_UNLOCK(hcec); @@ -228,6 +228,53 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) return HAL_OK; } +/** + * @brief Initializes the Own Address of the CEC device + * @param hcec: CEC handle + * @param CEC_OwnAddress: The CEC own address. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) +{ + /* Check the parameters */ + assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress)); + + if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY)) + { + /* Process Locked */ + __HAL_LOCK(hcec); + + hcec->gState = HAL_CEC_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_CEC_DISABLE(hcec); + + if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE) + { + MODIFY_REG(hcec->Instance->OAR, CEC_OAR_OA, hcec->Init.OwnAddress); + } + else + { + CLEAR_BIT(hcec->Instance->OAR, CEC_OAR_OA); + } + + hcec->gState = HAL_CEC_STATE_READY; + hcec->ErrorCode = HAL_CEC_ERROR_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hcec); + + /* Enable the Peripheral */ + __HAL_CEC_ENABLE(hcec); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + /** * @brief CEC MSP Init * @param hcec: CEC handle @@ -269,318 +316,36 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) =============================================================================== [..] This subsection provides a set of functions allowing to manage the CEC data transfers. - - (#) There are two modes of transfer: - (##) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (##) No-Blocking mode: The communication is performed using Interrupts. + + (#) The CEC handle must contain the initiator (TX side) and the destination (RX side) + logical addresses (4-bit long addresses, 0xF for broadcast messages destination) + + (#) The communication is performed using Interrupts. These API's return the HAL status. The end of the data processing will be indicated through the dedicated CEC IRQ when using Interrupt mode. The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the Transmit or Receive process. - The HAL_CEC_ErrorCallback()user callback will be executed when a communication + will be executed respectively at the end of the transmit or Receive process + The HAL_CEC_ErrorCallback() user callback will be executed when a communication error is detected - (#) Blocking mode API's are : - (##) HAL_CEC_Transmit() - (##) HAL_CEC_Receive() - (#) Non-Blocking mode API's with Interrupt are : - (##) HAL_CEC_Transmit_IT() - (##) HAL_CEC_Receive_IT() - (##) HAL_CEC_IRQHandler() - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: - (##) HAL_CEC_TxCpltCallback() - (##) HAL_CEC_RxCpltCallback() - (##) HAL_CEC_ErrorCallback() + + (#) API's with Interrupt are : + (+) HAL_CEC_Transmit_IT() + (+) HAL_CEC_IRQHandler() + + (#) A set of User Callbacks are provided: + (+) HAL_CEC_TxCpltCallback() + (+) HAL_CEC_RxCpltCallback() + (+) HAL_CEC_ErrorCallback() @endverbatim * @{ */ -/** - * @brief Send data in blocking mode - * @param hcec: CEC handle - * @param DestinationAddress: destination logical address - * @param pData: pointer to input byte data buffer - * @param Size: amount of data to be sent in bytes (without counting the header). - * 0 means only the header is sent (ping operation). - * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). - * @param Timeout: Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout) -{ - uint8_t temp = 0; - uint32_t tickstart = 0; - - /* If the IP is ready */ - if((hcec->State == HAL_CEC_STATE_READY) - && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) - { - /* Basic check on pData pointer */ - if(((pData == NULL) && (Size > 0)) || (! IS_CEC_MSGSIZE(Size))) - { - return HAL_ERROR; - } - - assert_param(IS_CEC_ADDRESS(DestinationAddress)); - - /* Process Locked */ - __HAL_LOCK(hcec); - - /* Enter the transmit mode */ - hcec->State = HAL_CEC_STATE_BUSY_TX; - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - - /* Initialize the number of bytes to send, - * 0 means only one header is sent (ping operation) */ - hcec->TxXferCount = Size; - - /* Send header block */ - temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress; - hcec->Instance->TXD = temp; - - /* In case no data to be sent, sender is only pinging the system */ - if (Size != 0) - { - /* Set TX Start of Message (TXSOM) bit */ - hcec->Instance->CSR = CEC_FLAG_TSOM; - } - else - { - /* Send a ping command */ - hcec->Instance->CSR = CEC_FLAG_TEOM|CEC_FLAG_TSOM; - } - - /* Polling TBTRF bit with timeout handling*/ - while (hcec->TxXferCount > 0) - { - /* Decreasing of the number of remaining data to receive */ - hcec->TxXferCount--; - - /* Timeout handling */ - tickstart = HAL_GetTick(); - - /* Waiting for the next data transmission */ - while(HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_TBTRF)) - { - /* Timeout handling */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hcec->State = HAL_CEC_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - return HAL_TIMEOUT; - } - } - - /* Check if an error occured */ - if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR)) - { - /* Copy ESR for error handling purposes */ - hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); - - /* Acknowledgement of the error */ - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR); - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); - - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - return HAL_ERROR; - } - } - - /* Write the next data to TX buffer */ - hcec->Instance->TXD = *pData++; - - /* If this is the last byte of the ongoing transmission */ - if (hcec->TxXferCount == 0) - { - /* Acknowledge byte request and signal end of message */ - MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM); - } - else - { - /* Acknowledge byte request by writing 0x00 */ - MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00); - } - } - - /* Timeout handling */ - tickstart = HAL_GetTick(); - - /* Wait for message transmission completion (TBTRF is set) */ - while (HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_TBTRF)) - { - /* Timeout handling */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - return HAL_TIMEOUT; - } - } - - /* Check of error during transmission of the last byte */ - if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR)) - { - /* Copy ESR for error handling purposes */ - hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); - - /* Acknowledgement of the error */ - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR); - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); - - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - return HAL_ERROR; - } - } - - /* Check of error after the last byte transmission */ - if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR)) - { - /* Copy ESR for error handling purposes */ - hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); - - /* Acknowledgement of the error */ - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR); - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); - - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - return HAL_ERROR; - } - - /* Acknowledge successful completion by writing 0x00 */ - MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00); - - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive data in blocking mode. - * @param hcec: CEC handle - * @param pData: pointer to received data buffer. - * @param Timeout: Timeout duration. - * @note The received data size is not known beforehand, the latter is known - * when the reception is complete and is stored in hcec->RxXferSize. - * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). - * If only a header is received, hcec->RxXferSize = 0 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout) -{ - uint32_t temp = 0; - uint32_t tickstart = 0; - - if(hcec->State == HAL_CEC_STATE_READY) - { - if(pData == NULL) - { - return HAL_ERROR; - } - - /* When a ping is received, RxXferSize is 0*/ - /* When a message is received, RxXferSize contains the number of received bytes */ - hcec->RxXferSize = CEC_RXXFERSIZE_INITIALIZE; - - /* Process Locked */ - __HAL_LOCK(hcec); - - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - - /* Continue the reception until the End Of Message is received (CEC_FLAG_REOM) */ - do - { - /* Timeout handling */ - tickstart = HAL_GetTick(); - - /* Wait for next byte to be received */ - while (HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_RBTF)) - { - /* Timeout handling */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - return HAL_TIMEOUT; - } - } - - /* Check if an error occured during the reception */ - if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR)) - { - /* Copy ESR for error handling purposes */ - hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); - - /* Acknowledgement of the error */ - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); - - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - return HAL_ERROR; - } - } - - /* Keep the value of CSR register as the register is cleared during reception process */ - temp = hcec->Instance->CSR; - - /* Read received data */ - *pData++ = hcec->Instance->RXD; - - /* Acknowledge received byte by writing 0x00 */ - CLEAR_BIT(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK); - - /* Increment the number of received data */ - if(hcec->RxXferSize == CEC_RXXFERSIZE_INITIALIZE) - { - hcec->RxXferSize = 0; - } - else - { - hcec->RxXferSize++; - } - - }while (HAL_IS_BIT_CLR(temp, CEC_FLAG_REOM)); - - hcec->State = HAL_CEC_STATE_READY; - __HAL_UNLOCK(hcec); - - if(IS_CEC_MSGSIZE(hcec->RxXferSize)) - { - return HAL_OK; - } - else - { - return HAL_ERROR; - } - } - else - { - return HAL_BUSY; - } -} - - /** * @brief Send data in interrupt mode * @param hcec: CEC handle + * @param InitiatorAddress: Initiator address * @param DestinationAddress: destination logical address * @param pData: pointer to input byte data buffer * @param Size: amount of data to be sent in bytes (without counting the header). @@ -588,52 +353,33 @@ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint3 * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @retval HAL status */ -HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size) { - uint8_t temp = 0; - uint32_t tmp_state = 0; - - tmp_state = hcec->State; - if(((tmp_state == HAL_CEC_STATE_READY) || (tmp_state == HAL_CEC_STATE_BUSY_RX)) - && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) - { - - /* Basic check on pData pointer */ - if(((pData == NULL) && (Size > 0)) || (! IS_CEC_MSGSIZE(Size))) + /* if the IP isn't already busy and if there is no previous transmission + already pending due to arbitration lost */ + if(hcec->gState == HAL_CEC_STATE_READY) + { + if((pData == NULL ) && (Size > 0U)) { return HAL_ERROR; } assert_param(IS_CEC_ADDRESS(DestinationAddress)); + assert_param(IS_CEC_ADDRESS(InitiatorAddress)); + assert_param(IS_CEC_MSGSIZE(Size)); /* Process Locked */ __HAL_LOCK(hcec); hcec->pTxBuffPtr = pData; - - /* Check if a receive process is ongoing or not */ - if(hcec->State == HAL_CEC_STATE_BUSY_RX) - { - hcec->State = HAL_CEC_STATE_BUSY_TX_RX; - - /* Interrupt are not enabled here because they are already enabled in the Reception process */ - } - else - { - hcec->State = HAL_CEC_STATE_BUSY_TX; - - /* Enable the CEC interrupt */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE); - } - + hcec->gState = HAL_CEC_STATE_BUSY_TX; hcec->ErrorCode = HAL_CEC_ERROR_NONE; - + /* initialize the number of bytes to send, * 0 means only one header is sent (ping operation) */ hcec->TxXferCount = Size; /* send header block */ - temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress; - hcec->Instance->TXD = temp; + hcec->Instance->TXD = (uint8_t)((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress; /* Process Unlocked */ __HAL_UNLOCK(hcec); @@ -650,6 +396,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Destinati MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM|CEC_FLAG_TSOM); } return HAL_OK; + } else { @@ -657,70 +404,26 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Destinati } } - /** - * @brief Receive data in interrupt mode. + * @brief Get size of the received frame. * @param hcec: CEC handle - * @param pData: pointer to received data buffer. - * @note The received data size is not known beforehand, the latter is known - * when the reception is complete and is stored in hcec->RxXferSize. - * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). - * If only a header is received, hcec->RxXferSize = 0 - * @retval HAL status + * @retval Frame size */ -HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData) +uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) { - uint32_t tmp_state = 0; - tmp_state = hcec->State; - if((tmp_state == HAL_CEC_STATE_READY) || (tmp_state == HAL_CEC_STATE_BUSY_TX)) - { - if(pData == NULL) - { - return HAL_ERROR; - } - - /* When a ping is received, RxXferSize is 0 */ - /* When a message is received, RxXferSize contains the number of received bytes */ - hcec->RxXferSize = CEC_RXXFERSIZE_INITIALIZE; - - /* Process Locked */ - __HAL_LOCK(hcec); - - hcec->pRxBuffPtr = pData; - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - - /* Check if a transmit process is ongoing or not */ - if(hcec->State == HAL_CEC_STATE_BUSY_TX) - { - hcec->State = HAL_CEC_STATE_BUSY_TX_RX; - } - else - { - hcec->State = HAL_CEC_STATE_BUSY_RX; - - /* Enable CEC interrupt */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IT_IE); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } + return hcec->RxXferSize; } /** - * @brief Get size of the received frame. + * @brief Change Rx Buffer. * @param hcec: CEC handle + * @param Rxbuffer: Rx Buffer + * @note This function can be called only inside the HAL_CEC_RxCpltCallback() * @retval Frame size */ -uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec) +void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer) { - return hcec->RxXferSize; + hcec->Init.RxBuffer = Rxbuffer; } /** @@ -734,63 +437,44 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); /* Transmit error */ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TERR) != RESET)) + if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TERR) != RESET) { /* Acknowledgement of the error */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR); - /* Check if a receive process is ongoing or not */ - if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX) - { - /* Interrupts are not disabled due to reception still ongoing */ - - hcec->State = HAL_CEC_STATE_BUSY_RX; - } - else - { - /* Disable the CEC Transmission Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE); - - hcec->State = HAL_CEC_STATE_READY; - } + hcec->gState = HAL_CEC_STATE_READY; } /* Receive error */ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RERR) != RESET)) + if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RERR) != RESET) { /* Acknowledgement of the error */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); - - /* Check if a transmit process is ongoing or not */ - if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX) - { - /* Interrupts are not disabled due to reception still ongoing */ - - hcec->State = HAL_CEC_STATE_BUSY_TX; - } - else - { - /* Disable the CEC Transmission Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE); - - hcec->State = HAL_CEC_STATE_READY; - } - } + hcec->Init.RxBuffer-=hcec->RxXferSize; + hcec->RxXferSize = 0U; + hcec->RxState = HAL_CEC_STATE_READY; + } - if ((hcec->ErrorCode & CEC_ESR_ALL_ERROR) != 0) + if((hcec->ErrorCode & CEC_ESR_ALL_ERROR) != 0U) { + /* Error Call Back */ HAL_CEC_ErrorCallback(hcec); } /* Transmit byte request or block transfer finished */ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TBTRF) != RESET)) + if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TBTRF) != RESET) { CEC_Transmit_IT(hcec); - } + } /* Receive byte or block transfer finished */ - if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RBTF) != RESET)) + if(__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RBTF) != RESET) { + if(hcec->RxXferSize == 0U) + { + /* reception is starting */ + hcec->RxState = HAL_CEC_STATE_BUSY_RX; + } CEC_Receive_IT(hcec); } } @@ -813,12 +497,14 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /** * @brief Rx Transfer completed callback * @param hcec: CEC handle + * @param RxFrameSize: Size of frame * @retval None */ -__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec) +__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) { /* Prevent unused argument(s) compilation warning */ UNUSED(hcec); + UNUSED(RxFrameSize); /* NOTE : This function should not be modified, when the callback is needed, the HAL_CEC_RxCpltCallback can be implemented in the user file */ @@ -837,7 +523,6 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec) the HAL_CEC_ErrorCallback can be implemented in the user file */ } - /** * @} */ @@ -847,24 +532,28 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec) * @verbatim =============================================================================== - ##### Peripheral Control functions ##### + ##### Peripheral Control function ##### =============================================================================== [..] This subsection provides a set of functions allowing to control the CEC. (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. - (+) HAL_CEC_GetError() API can be helpful to get the error code of a failed transmission or reception. + (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral. @endverbatim * @{ */ - /** * @brief return the CEC state - * @param hcec: CEC handle + * @param hcec: pointer to a CEC_HandleTypeDef structure that contains + * the configuration information for the specified CEC module. * @retval HAL state */ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) { - return hcec->State; + uint32_t temp1= 0x00U, temp2 = 0x00U; + temp1 = hcec->gState; + temp2 = hcec->RxState; + + return (HAL_CEC_StateTypeDef)(temp1 | temp2); } /** @@ -899,34 +588,17 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) */ static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec) { - uint32_t tmp_state = 0; - - tmp_state = hcec->State; /* if the IP is already busy or if there is a previous transmission already pending due to arbitration loss */ - if(((tmp_state == HAL_CEC_STATE_BUSY_TX) || (tmp_state == HAL_CEC_STATE_BUSY_TX_RX)) - || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) + if((hcec->gState == HAL_CEC_STATE_BUSY_TX) || (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) != RESET)) { /* if all data have been sent */ - if(hcec->TxXferCount == 0) + if(hcec->TxXferCount == 0U) { /* Acknowledge successful completion by writing 0x00 */ - MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00); + MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00U); - /* Check if a receive process is ongoing or not */ - if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX) - { - /* Interrupts are not disabled due to reception still ongoing */ - - hcec->State = HAL_CEC_STATE_BUSY_RX; - } - else - { - /* Disable the CEC Transmission Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE); - - hcec->State = HAL_CEC_STATE_READY; - } + hcec->gState = HAL_CEC_STATE_READY; HAL_CEC_TxCpltCallback(hcec); @@ -941,7 +613,7 @@ static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec) hcec->Instance->TXD = *hcec->pTxBuffPtr++; /* If this is the last byte of the ongoing transmission */ - if (hcec->TxXferCount == 0) + if(hcec->TxXferCount == 0U) { /* Acknowledge byte request and signal end of message */ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM); @@ -949,7 +621,7 @@ static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec) else { /* Acknowledge byte request by writing 0x00 */ - MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00); + MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00U); } return HAL_OK; @@ -971,50 +643,28 @@ static HAL_StatusTypeDef CEC_Transmit_IT(CEC_HandleTypeDef *hcec) static HAL_StatusTypeDef CEC_Receive_IT(CEC_HandleTypeDef *hcec) { static uint32_t temp; - uint32_t tmp_state = 0; - - tmp_state = hcec->State; - if((tmp_state == HAL_CEC_STATE_BUSY_RX) || (tmp_state == HAL_CEC_STATE_BUSY_TX_RX)) + + if(hcec->RxState == HAL_CEC_STATE_BUSY_RX) { temp = hcec->Instance->CSR; /* Store received data */ - *hcec->pRxBuffPtr++ = hcec->Instance->RXD; + hcec->RxXferSize++; + *hcec->Init.RxBuffer++ = hcec->Instance->RXD; /* Acknowledge received byte by writing 0x00 */ - MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK, 0x00); - - /* Increment the number of received data */ - if(hcec->RxXferSize == CEC_RXXFERSIZE_INITIALIZE) - { - hcec->RxXferSize = 0; - } - else - { - hcec->RxXferSize++; - } + MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK, 0x00U); /* If the End Of Message is reached */ if(HAL_IS_BIT_SET(temp, CEC_FLAG_REOM)) { - if(hcec->State == HAL_CEC_STATE_BUSY_TX_RX) - { - /* Interrupts are not disabled due to transmission still ongoing */ - - hcec->State = HAL_CEC_STATE_BUSY_TX; - } - else - { - /* Disable the CEC Transmission Interrupts */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IT_IE); - - hcec->State = HAL_CEC_STATE_READY; - } - - HAL_CEC_RxCpltCallback(hcec); - + /* Interrupts are not disabled due to transmission still ongoing */ + hcec->RxState = HAL_CEC_STATE_READY; + + HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize); + return HAL_OK; - } + } else { return HAL_BUSY; diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.h index f0af5fcb0c0..eb1fd35d359 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cec.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_hal_cec.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of CEC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -53,89 +53,82 @@ /** @addtogroup CEC * @{ - */ - -/** @addtogroup CEC_Private_Constants - * @{ - */ -#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \ - ((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE)) -#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \ - ((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE)) - -/** @brief Check CEC device Own Address Register (OAR) setting. - * @param __ADDRESS__: CEC own address. - * @retval Test result (TRUE or FALSE). - */ -#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) - -/** @brief Check CEC initiator or destination logical address setting. - * Initiator and destination addresses are coded over 4 bits. - * @param __ADDRESS__: CEC initiator or logical address. - * @retval Test result (TRUE or FALSE). */ -#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) - -/** @brief Check CEC message size. - * The message size is the payload size: without counting the header, - * it varies from 0 byte (ping operation, one header only, no payload) to - * 15 bytes (1 opcode and up to 14 operands following the header). - * @param __SIZE__: CEC message size. - * @retval Test result (TRUE or FALSE). - */ -#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF) - -/** - * @} - */ /* Exported types ------------------------------------------------------------*/ /** @defgroup CEC_Exported_Types CEC Exported Types * @{ - */ + */ /** * @brief CEC Init Structure definition */ typedef struct -{ +{ uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode. This parameter can be a value of @ref CEC_BitTimingErrorMode */ uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode. This parameter can be a value of @ref CEC_BitPeriodErrorMode */ - uint8_t InitiatorAddress; /*!< Initiator address (source logical address, sent in each header) - This parameter can be a value <= 0xF */ + uint16_t OwnAddress; /*!< Own addresses configuration + This parameter can be a value of @ref CEC_OWN_ADDRESS */ + uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */ }CEC_InitTypeDef; /** - * @brief HAL CEC State structures definition + * @brief HAL CEC State structures definition + * @note HAL CEC State value is a combination of 2 different substates: gState and RxState. + * - gState contains CEC state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7 (not used) + * x : Should be set to 0 + * b6 Error information + * 0 : No Error + * 1 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP initialized. HAL CEC Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef enum { - HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */ - HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_CEC_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */ - HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */ - HAL_CEC_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */ - HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */ - HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */ + HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */ }HAL_CEC_StateTypeDef; -/** - * @brief HAL Error structures definition - */ -typedef enum -{ - HAL_CEC_ERROR_NONE = (uint32_t) 0x0, /*!< no error */ - HAL_CEC_ERROR_BTE = CEC_ESR_BTE, /*!< Bit Timing Error */ - HAL_CEC_ERROR_BPE = CEC_ESR_BPE, /*!< Bit Period Error */ - HAL_CEC_ERROR_RBTFE = CEC_ESR_RBTFE, /*!< Rx Block Transfer Finished Error */ - HAL_CEC_ERROR_SBE = CEC_ESR_SBE, /*!< Start Bit Error */ - HAL_CEC_ERROR_ACKE = CEC_ESR_ACKE, /*!< Block Acknowledge Error */ - HAL_CEC_ERROR_LINE = CEC_ESR_LINE, /*!< Line Error */ - HAL_CEC_ERROR_TBTFE = CEC_ESR_TBTFE, /*!< Tx Block Transfer Finished Error */ -}HAL_CEC_ErrorTypeDef; - /** * @brief CEC handle Structure definition */ @@ -149,31 +142,48 @@ typedef struct uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /*!< Pointer to CEC Rx transfer Buffer */ - uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ - uint32_t ErrorCode; /*!< For errors handling purposes, copy of ESR register in case error is reported */ - HAL_LockTypeDef Lock; /*!< Locking object */ + + HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_CEC_StateTypeDef */ + + HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. + This parameter can be a value of @ref HAL_CEC_StateTypeDef */ - HAL_CEC_StateTypeDef State; /*!< CEC communication state */ - + uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register + in case error is reported */ }CEC_HandleTypeDef; - /** - * @} - */ + * @} + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup CEC_Exported_Constants CEC Exported Constants * @{ */ - + +/** @defgroup CEC_Error_Code CEC Error Code + * @{ + */ +#define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */ +#define HAL_CEC_ERROR_BTE CEC_ESR_BTE /*!< Bit Timing Error */ +#define HAL_CEC_ERROR_BPE CEC_ESR_BPE /*!< Bit Period Error */ +#define HAL_CEC_ERROR_RBTFE CEC_ESR_RBTFE /*!< Rx Block Transfer Finished Error */ +#define HAL_CEC_ERROR_SBE CEC_ESR_SBE /*!< Start Bit Error */ +#define HAL_CEC_ERROR_ACKE CEC_ESR_ACKE /*!< Block Acknowledge Error */ +#define HAL_CEC_ERROR_LINE CEC_ESR_LINE /*!< Line Error */ +#define HAL_CEC_ERROR_TBTFE CEC_ESR_TBTFE /*!< Tx Block Transfer Finished Error */ +/** + * @} + */ + /** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode * @{ */ -#define CEC_BIT_TIMING_ERROR_MODE_STANDARD ((uint32_t)0x00) /*!< Bit timing error Standard Mode */ +#define CEC_BIT_TIMING_ERROR_MODE_STANDARD 0x00000000U /*!< Bit timing error Standard Mode */ #define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ /** * @} @@ -182,19 +192,44 @@ typedef struct /** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode * @{ */ -#define CEC_BIT_PERIOD_ERROR_MODE_STANDARD ((uint32_t)0x00) /*!< Bit period error Standard Mode */ +#define CEC_BIT_PERIOD_ERROR_MODE_STANDARD 0x00000000U /*!< Bit period error Standard Mode */ #define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ /** * @} */ -/** @defgroup CEC_Initiator_Position Initiator logical address position in message header +/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header + * @{ + */ +#define CEC_INITIATOR_LSB_POS 4U +/** + * @} + */ + +/** @defgroup CEC_OWN_ADDRESS CEC Own Address * @{ */ -#define CEC_INITIATOR_LSB_POS ((uint32_t) 4) +#define CEC_OWN_ADDRESS_NONE CEC_OWN_ADDRESS_0 /* Reset value */ +#define CEC_OWN_ADDRESS_0 ((uint16_t)0x0000U) /* Logical Address 0 */ +#define CEC_OWN_ADDRESS_1 ((uint16_t)0x0001U) /* Logical Address 1 */ +#define CEC_OWN_ADDRESS_2 ((uint16_t)0x0002U) /* Logical Address 2 */ +#define CEC_OWN_ADDRESS_3 ((uint16_t)0x0003U) /* Logical Address 3 */ +#define CEC_OWN_ADDRESS_4 ((uint16_t)0x0004U) /* Logical Address 4 */ +#define CEC_OWN_ADDRESS_5 ((uint16_t)0x0005U) /* Logical Address 5 */ +#define CEC_OWN_ADDRESS_6 ((uint16_t)0x0006U) /* Logical Address 6 */ +#define CEC_OWN_ADDRESS_7 ((uint16_t)0x0007U) /* Logical Address 7 */ +#define CEC_OWN_ADDRESS_8 ((uint16_t)0x0008U) /* Logical Address 8 */ +#define CEC_OWN_ADDRESS_9 ((uint16_t)0x0009U) /* Logical Address 9 */ +#define CEC_OWN_ADDRESS_10 ((uint16_t)0x000AU) /* Logical Address 10 */ +#define CEC_OWN_ADDRESS_11 ((uint16_t)0x000BU) /* Logical Address 11 */ +#define CEC_OWN_ADDRESS_12 ((uint16_t)0x000CU) /* Logical Address 12 */ +#define CEC_OWN_ADDRESS_13 ((uint16_t)0x000DU) /* Logical Address 13 */ +#define CEC_OWN_ADDRESS_14 ((uint16_t)0x000EU) /* Logical Address 14 */ +#define CEC_OWN_ADDRESS_15 ((uint16_t)0x000FU) /* Logical Address 15 */ /** * @} */ + /** @defgroup CEC_Interrupts_Definitions Interrupts definition * @{ */ @@ -227,63 +262,66 @@ typedef struct * @{ */ -/** @brief Reset CEC handle state +/** @brief Reset CEC handle gstate & RxState * @param __HANDLE__: CEC handle. * @retval None */ -#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET) +#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ + } while(0U) /** @brief Checks whether or not the specified CEC interrupt flag is set. * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: specifies the interrupt to check. + * @param __FLAG__: specifies the flag to check. * @arg CEC_FLAG_TERR: Tx Error - * @arg CEC_FLAG_TBTF: Tx Block Transfer Finished + * @arg CEC_FLAG_TBTRF:Tx Block Transfer Finished * @arg CEC_FLAG_RERR: Rx Error * @arg CEC_FLAG_RBTF: Rx Block Transfer Finished * @retval ITStatus */ -#define __HAL_CEC_GET_FLAG(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CSR,(__INTERRUPT__)) +#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) READ_BIT((__HANDLE__)->Instance->CSR,(__FLAG__)) /** @brief Clears the CEC's pending flags. * @param __HANDLE__: specifies the CEC Handle. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg CEC_CSR_TERR: Tx Error - * @arg CEC_CSR_TBTF: Tx Block Transfer Finished + * @arg CEC_FLAG_TBTRF: Tx Block Transfer Finished * @arg CEC_CSR_RERR: Rx Error * @arg CEC_CSR_RBTF: Rx Block Transfer Finished * @retval none */ -#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ - do { \ - uint32_t tmp = 0x0; \ - tmp = (__HANDLE__)->Instance->CSR & 0x2; \ - (__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFC) | tmp);\ - } while(0) - +#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + do { \ + uint32_t tmp = 0x0U; \ + tmp = (__HANDLE__)->Instance->CSR & 0x00000002U; \ + (__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFCU) | tmp);\ + } while(0U) + /** @brief Enables the specified CEC interrupt. * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: The CEC interrupt to enable. + * @param __INTERRUPT__: specifies the CEC interrupt to enable. * This parameter can be: - * @arg CEC_IT_IE : Interrupt Enable + * @arg CEC_IT_IE : Interrupt Enable. * @retval none */ #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__)) /** @brief Disables the specified CEC interrupt. * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: The CEC interrupt to enable. + * @param __INTERRUPT__: specifies the CEC interrupt to disable. * This parameter can be: - * @arg CEC_IT_IE : Interrupt Enable + * @arg CEC_IT_IE : Interrupt Enable * @retval none */ #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__)) /** @brief Checks whether or not the specified CEC interrupt is enabled. * @param __HANDLE__: specifies the CEC Handle. - * @param __INTERRUPT__: The CEC interrupt to enable. + * @param __INTERRUPT__: specifies the CEC interrupt to check. * This parameter can be: - * @arg CEC_IT_IE : Interrupt Enable + * @arg CEC_IT_IE : Interrupt Enable * @retval FlagStatus */ #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__)) @@ -308,7 +346,7 @@ typedef struct /** @brief Set Transmission End flag * @param __HANDLE__: specifies the CEC Handle. - * @retval none + * @retval none */ #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM) @@ -345,7 +383,7 @@ typedef struct /** @addtogroup CEC_Exported_Functions CEC Exported Functions * @{ */ - + /** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @{ @@ -353,6 +391,7 @@ typedef struct /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); +HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress); void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); /** @@ -363,15 +402,13 @@ void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); * @brief CEC Transmit/Receive functions * @{ */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); -HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData); -uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec); +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); +uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec); +void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer); void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); -void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec); +void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); /** * @} @@ -392,16 +429,86 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); * @} */ +/* Private types -------------------------------------------------------------*/ +/** @defgroup CEC_Private_Types CEC Private Types + * @{ + */ + /** * @} */ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CEC_Private_Variables CEC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CEC_Private_Constants CEC Private Constants + * @{ + */ + /** * @} */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CEC_Private_Macros CEC Private Macros + * @{ + */ +#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \ + ((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE)) + +#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \ + ((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE)) + +/** @brief Check CEC message size. + * The message size is the payload size: without counting the header, + * it varies from 0 byte (ping operation, one header only, no payload) to + * 15 bytes (1 opcode and up to 14 operands following the header). + * @param __SIZE__: CEC message size. + * @retval Test result (TRUE or FALSE). + */ +#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) +/** @brief Check CEC device Own Address Register (OAR) setting. + * @param __ADDRESS__: CEC own address. + * @retval Test result (TRUE or FALSE). + */ +#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU) + +/** @brief Check CEC initiator or destination logical address setting. + * Initiator and destination addresses are coded over 4 bits. + * @param __ADDRESS__: CEC initiator or logical address. + * @retval Test result (TRUE or FALSE). + */ +#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU) + + + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CEC_Private_Functions CEC Private Functions + * @{ + */ -#endif /* defined(STM32F100xB) || defined(STM32F100xE) */ +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ +#endif /* defined(STM32F100xB) || defined(STM32F100xE) */ #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h index 89cd6356a8f..31178c3fc11 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h @@ -2,15 +2,15 @@ ****************************************************************************** * @file stm32f1xx_hal_conf.h * @author MCD Application Team - * @version V1.0.4 - * @date 29-April-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32f1xx_hal_conf.h. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -83,6 +83,7 @@ #define HAL_UART_MODULE_ENABLED #define HAL_USART_MODULE_ENABLED #define HAL_WWDG_MODULE_ENABLED +#define HAL_MMC_MODULE_ENABLED /* ########################## Oscillator Values adaptation ####################*/ /** @@ -92,14 +93,14 @@ */ #if !defined (HSE_VALUE) #if defined(USE_STM3210C_EVAL) - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ #else - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ #endif #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -108,23 +109,29 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ + #define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */ #endif /* HSI_VALUE */ +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ /** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency */ #if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ + #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ #endif /* LSE_VALUE */ - #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ + #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ - /* Tip: To avoid modifying this file each time you need to use different HSE, === you can define the HSE value in your toolchain compiler preprocessor. */ @@ -132,53 +139,52 @@ /** * @brief This is the HAL system configuration section */ -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0x000F) /*!< tick interrupt priority */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 1 +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U /* ########################## Assert Selection ############################## */ /** * @brief Uncomment the line below to expanse the "assert_param" macro in the * HAL drivers code */ -/*#define USE_FULL_ASSERT 1*/ - +/* #define USE_FULL_ASSERT 1U */ /* ################## Ethernet peripheral configuration ##################### */ /* Section 1 : Ethernet peripheral configuration */ /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2 -#define MAC_ADDR1 0 -#define MAC_ADDR2 0 -#define MAC_ADDR3 0 -#define MAC_ADDR4 0 -#define MAC_ADDR5 0 +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U /* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ -#define ETH_RXBUFNB ((uint32_t)8) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ +#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ /* Section 2: PHY configuration section */ /* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01 +#define DP83848_PHY_ADDRESS 0x01U /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY ((uint32_t)0x000000FF) +#define PHY_RESET_DELAY 0x000000FFU /* PHY Configuration delay */ -#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) +#define PHY_CONFIG_DELAY 0x00000FFFU -#define PHY_READ_TO ((uint32_t)0x0000FFFF) -#define PHY_WRITE_TO ((uint32_t)0x0000FFFF) +#define PHY_READ_TO 0x0000FFFFU +#define PHY_WRITE_TO 0x0000FFFFU /* Section 3: Common PHY Registers */ -#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ +#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ @@ -197,9 +203,9 @@ /* Section 4: Extended PHY Registers */ -#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */ +#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ @@ -211,7 +217,14 @@ #define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ #define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ +/* ################## SPI peripheral configuration ########################## */ +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 1U /* Includes ------------------------------------------------------------------*/ /** @@ -334,11 +347,13 @@ #include "stm32f1xx_hal_pcd.h" #endif /* HAL_PCD_MODULE_ENABLED */ - #ifdef HAL_HCD_MODULE_ENABLED #include "stm32f1xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f1xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT @@ -353,9 +368,10 @@ #include "mbed_assert.h" #define assert_param(expr) MBED_ASSERT(expr) #else - #define assert_param(expr) ((void)0) + #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.c index 29dd4f36016..eaa8c73cf2a 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.c @@ -2,81 +2,59 @@ ****************************************************************************** * @file stm32f1xx_hal_cortex.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief CORTEX HAL module driver. - * - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the CORTEX: * + Initialization and de-initialization functions - * + Peripheral Control functions - * - * @verbatim + * + Peripheral Control functions + * + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - *** How to configure Interrupts using Cortex HAL driver *** + *** How to configure Interrupts using CORTEX HAL driver *** =========================================================== [..] - This section provide functions allowing to configure the NVIC interrupts (IRQ). + This section provides functions allowing to configure the NVIC interrupts (IRQ). The Cortex-M3 exceptions are managed by CMSIS functions. (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function according to the following table. - - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. - ========================================================================================================================== - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ========================================================================================================================== - NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ========================================================================================================================== - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() - - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. The pending IRQ priority will be managed only by the sub priority. -@- IRQ priority order (sorted by highest to lowest priority): - (+@) Lowest pre-emption priority + (+@) Lowest preemption priority (+@) Lowest sub priority (+@) Lowest hardware priority (IRQ number) [..] - *** How to configure Systick using Cortex HAL driver *** + *** How to configure Systick using CORTEX HAL driver *** ======================================================== [..] - Setup SysTick Timer for 1 msec interrupts. + Setup SysTick Timer for time base. (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which is a CMSIS function that: (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Configures the SysTick IRQ priority to the lowest value 0x0F. (++) Resets the SysTick Counter register. (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). (++) Enables the SysTick Interrupt. (++) Starts the SysTick Counter. - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the function - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32f1xx_hal_cortex.h file. (+) You can change the SysTick IRQ priority by calling the HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function @@ -92,7 +70,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -133,12 +111,12 @@ #ifdef HAL_CORTEX_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions * @{ @@ -146,14 +124,14 @@ /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] - This section provide the Cortex HAL driver functions allowing to configure Interrupts + This section provides the CORTEX HAL driver functions allowing to configure Interrupts Systick functionalities @endverbatim @@ -162,21 +140,21 @@ /** - * @brief Sets the priority grouping field (pre-emption priority and subpriority) + * @brief Sets the priority grouping field (preemption priority and subpriority) * using the required unlock sequence. * @param PriorityGroup: The priority grouping bits length. * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ @@ -191,10 +169,10 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) /** * @brief Sets the priority of an interrupt. - * @param IRQn: External interrupt number + * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) - * @param PreemptPriority: The pre-emption priority for the IRQn channel. + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xx.h)) + * @param PreemptPriority: The preemption priority for the IRQn channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority * @param SubPriority: the subpriority level for the IRQ channel. @@ -203,8 +181,8 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t prioritygroup = 0x00; +{ + uint32_t prioritygroup = 0x00U; /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); @@ -219,7 +197,7 @@ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t Sub * @brief Enables a device specific interrupt in the NVIC interrupt controller. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() * function should be called before. - * @param IRQn External interrupt number + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None @@ -235,7 +213,7 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) /** * @brief Disables a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None @@ -245,7 +223,6 @@ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - /* Disable interrupt */ NVIC_DisableIRQ(IRQn); } @@ -276,8 +253,8 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) */ /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * + * @brief Cortex control functions + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -291,7 +268,47 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) * @{ */ -#if (__MPU_PRESENT == 1) +#if (__MPU_PRESENT == 1U) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0U; +} + +/** + * @brief Enable the MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + /** * @brief Initializes and configures the Region and the memory to be protected. * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains @@ -332,8 +349,8 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) } else { - MPU->RBAR = 0x00; - MPU->RASR = 0x00; + MPU->RBAR = 0x00U; + MPU->RASR = 0x00U; } } #endif /* __MPU_PRESENT */ @@ -350,26 +367,26 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) /** * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number + * @param IRQn: External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @param PriorityGroup: the priority grouping bits length. * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * 0 bits for subpriority * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). * @param pSubPriority: Pointer on the Subpriority value (starting from 0). * @retval None */ -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); @@ -385,35 +402,44 @@ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPre * @retval None */ void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Set interrupt pending */ NVIC_SetPendingIRQ(IRQn); } /** - * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * @brief Gets Pending Interrupt (reads the pending register in the NVIC * and returns the pending bit for the specified interrupt). - * @param IRQn External interrupt number + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval status: - 0 Interrupt status is not pending. * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Return 1 if pending else 0 */ return NVIC_GetPendingIRQ(IRQn); } /** - * @brief Clears the pending bit of an external interrupt. - * @param IRQn External interrupt number + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h)) * @retval None */ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Clear pending interrupt */ NVIC_ClearPendingIRQ(IRQn); } @@ -427,7 +453,10 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) * - 1 Interrupt status is pending. */ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) -{ +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Return 1 if active else 0 */ return NVIC_GetActive(IRQn); } diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.h index a74f74d82a1..f7fedadf0b5 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_cortex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_hal_cortex.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -58,7 +58,7 @@ * @{ */ -#if (__MPU_PRESENT == 1) +#if (__MPU_PRESENT == 1U) /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition * @brief MPU Region initialization structure * @{ @@ -97,34 +97,33 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants * @{ */ - -/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group * @{ */ - -#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ /** * @} */ -/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source * @{ */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U /** * @} @@ -134,10 +133,11 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) -#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) -#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) -#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) +#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U +#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk +#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk +#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) + /** * @} */ @@ -202,44 +202,44 @@ typedef struct */ #define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_64B ((uint8_t)0x05) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) -/** +/** * @} */ /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05) +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05) #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) /** * @} @@ -248,11 +248,11 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number * @{ */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04) +#define MPU_REGION_NUMBER0 ((uint8_t)0x00) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04) #define MPU_REGION_NUMBER5 ((uint8_t)0x05) #define MPU_REGION_NUMBER6 ((uint8_t)0x06) #define MPU_REGION_NUMBER7 ((uint8_t)0x07) @@ -264,14 +264,61 @@ typedef struct /** * @} */ + + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ -/* Private macro -------------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Macros CORTEX Private Macros +/** @addtogroup CORTEX_Exported_Functions_Group2 * @{ - */ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1U) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ -/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros * @{ */ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ @@ -280,25 +327,16 @@ typedef struct ((GROUP) == NVIC_PRIORITYGROUP_3) || \ ((GROUP) == NVIC_PRIORITYGROUP_4)) -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) -#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) -/** - * @} - */ +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) -/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source - * @{ - */ #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) -/** - * @} - */ -#if (__MPU_PRESENT == 1) + +#if (__MPU_PRESENT == 1U) #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ ((STATE) == MPU_REGION_DISABLE)) @@ -366,97 +404,11 @@ typedef struct #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) #endif /* __MPU_PRESENT */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CORTEX_Exported_Functions - * @{ - */ - -/** @addtogroup CORTEX_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); -void HAL_NVIC_SystemReset(void); -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -/** - * @} - */ - -/** @addtogroup CORTEX_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -#if (__MPU_PRESENT == 1) -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); -#endif /* __MPU_PRESENT */ -uint32_t HAL_NVIC_GetPriorityGrouping(void); -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); -void HAL_SYSTICK_IRQHandler(void); -void HAL_SYSTICK_Callback(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Functions CORTEX Private Functions - * @brief CORTEX private functions - * @{ +/** + * @} */ -#if (__MPU_PRESENT == 1) -/** - * @brief Disables the MPU - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Disable(void) -{ - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU */ - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; -} - -/** - * @brief Enables the MPU - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged accessto the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -} -#endif /* __MPU_PRESENT */ - -/** - * @} - */ +/* Private functions ---------------------------------------------------------*/ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.c index fe8195b06ee..ab491e39b2e 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_crc.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -162,6 +162,9 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /* Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF */ __HAL_CRC_DR_RESET(hcrc); + /* Reset IDR register content */ + CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_RESET; @@ -234,7 +237,7 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) */ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { - uint32_t index = 0; + uint32_t index = 0U; /* Process Locked */ __HAL_LOCK(hcrc); @@ -243,7 +246,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ hcrc->State = HAL_CRC_STATE_BUSY; /* Enter Data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) + for(index = 0U; index < BufferLength; index++) { hcrc->Instance->DR = pBuffer[index]; } @@ -269,7 +272,7 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_ */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) { - uint32_t index = 0; + uint32_t index = 0U; /* Process Locked */ __HAL_LOCK(hcrc); @@ -281,7 +284,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t __HAL_CRC_DR_RESET(hcrc); /* Enter Data to the CRC calculator */ - for(index = 0; index < BufferLength; index++) + for(index = 0U; index < BufferLength; index++) { hcrc->Instance->DR = pBuffer[index]; } diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.h index 83d0e078a14..155f387eeae 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_crc.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -65,11 +65,11 @@ */ typedef enum { - HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */ - HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */ - HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */ - HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */ - HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */ + HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ }HAL_CRC_StateTypeDef; diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.c index f380eae018b..1c84042343d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_dac.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -471,7 +471,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The destination peripheral Buffer address. + * @param pData: The Source memory Buffer address. * @param Length: The length of data to be transferred from memory to DAC peripheral * @param Alignment: Specifies the data alignment for DAC channel. * This parameter can be one of the following values: @@ -482,7 +482,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) */ __weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -740,7 +740,7 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) { - uint32_t tmpreg1 = 0; + uint32_t tmpreg1 = 0U; /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); @@ -795,7 +795,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { - __IO uint32_t tmp = 0; + __IO uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.h index 6e095cfce5f..9487a1ef7e6 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_dac.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention @@ -67,11 +67,11 @@ */ typedef enum { - HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */ - HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */ - HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */ - HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */ - HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */ + HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ + HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ }HAL_DAC_StateTypeDef; @@ -121,10 +121,10 @@ typedef struct /** @defgroup DAC_Error_Code DAC Error Code * @{ */ -#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */ -#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ +#define HAL_DAC_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x00000001U /*!< DAC channel1 DMA underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x00000002U /*!< DAC channel2 DMA underrun error */ +#define HAL_DAC_ERROR_DMA 0x00000004U /*!< DMA error */ /** * @} */ @@ -132,7 +132,7 @@ typedef struct /** @defgroup DAC_output_buffer DAC output buffer * @{ */ -#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) +#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U #define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) /** @@ -142,8 +142,8 @@ typedef struct /** @defgroup DAC_Channel_selection DAC Channel selection * @{ */ -#define DAC_CHANNEL_1 ((uint32_t)0x00000000) -#define DAC_CHANNEL_2 ((uint32_t)0x00000010) +#define DAC_CHANNEL_1 0x00000000U +#define DAC_CHANNEL_2 0x00000010U /** * @} @@ -152,9 +152,9 @@ typedef struct /** @defgroup DAC_data_alignement DAC data alignement * @{ */ -#define DAC_ALIGN_12B_R ((uint32_t)0x00000000) -#define DAC_ALIGN_12B_L ((uint32_t)0x00000004) -#define DAC_ALIGN_8B_R ((uint32_t)0x00000008) +#define DAC_ALIGN_12B_R 0x00000000U +#define DAC_ALIGN_12B_L 0x00000004U +#define DAC_ALIGN_8B_R 0x00000008U /** * @} @@ -212,13 +212,13 @@ typedef struct ((ALIGN) == DAC_ALIGN_12B_L) || \ ((ALIGN) == DAC_ALIGN_8B_R)) -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) -#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__)) +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__)) -#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__)) +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__)) -#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__)) +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__)) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.c index 38ebcecbd47..188cefb7d78 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: @@ -106,11 +106,11 @@ */ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) { - uint32_t tmp = 0; + uint32_t tmp = 0U; tmp |= hdac->Instance->DOR1; - tmp |= hdac->Instance->DOR2 << 16; + tmp |= hdac->Instance->DOR2 << 16U; /* Returns the DAC channel data output register value */ return tmp; @@ -229,7 +229,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t */ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) { - uint32_t data = 0, tmp = 0; + uint32_t data = 0U, tmp = 0U; /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); @@ -239,11 +239,11 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align /* Calculate and set dual DAC data holding register value */ if (Alignment == DAC_ALIGN_8B_R) { - data = ((uint32_t)Data2 << 8) | Data1; + data = ((uint32_t)Data2 << 8U) | Data1; } else { - data = ((uint32_t)Data2 << 16) | Data1; + data = ((uint32_t)Data2 << 16U) | Data1; } tmp = (uint32_t)hdac->Instance; @@ -366,7 +366,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.h index 5f5c9c856a5..1fc977ee4d1 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dac_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention @@ -67,7 +67,7 @@ /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude * @{ */ -#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ @@ -79,7 +79,7 @@ #define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */ #define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ #define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ #define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ @@ -99,7 +99,7 @@ /** @defgroup DACEx_trigger_selection DAC trigger selection * @{ */ -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register +#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_TRIGGER_T7_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_def.h index a3dbb87c30d..be4adf42f4f 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_def.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32f1xx_hal_def.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -46,7 +46,9 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx.h" +#if defined(USE_HAL_LEGACY) #include "stm32_hal_legacy.h" +#endif #include /* Exported types ------------------------------------------------------------*/ @@ -56,10 +58,10 @@ */ typedef enum { - HAL_OK = 0x00, - HAL_ERROR = 0x01, - HAL_BUSY = 0x02, - HAL_TIMEOUT = 0x03 + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U } HAL_StatusTypeDef; /** @@ -67,22 +69,21 @@ typedef enum */ typedef enum { - HAL_UNLOCKED = 0x00, - HAL_LOCKED = 0x01 + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ - -#define HAL_MAX_DELAY 0xFFFFFFFF +#define HAL_MAX_DELAY 0xFFFFFFFFU #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ - (__DMA_HANDLE_).Parent = (__HANDLE__); \ - } while(0) +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0U) #define UNUSED(x) ((void)(x)) @@ -101,14 +102,15 @@ typedef enum * HAL_PPP_MspInit() which will reconfigure the low level hardware. * @retval None */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) -#if (USE_RTOS == 1) - #error " USE_RTOS should be 0 in the current HAL release " +#if (USE_RTOS == 1U) + /* Reserved for future use */ + #error "USE_RTOS should be 0 in the current HAL release" #else #define __HAL_LOCK(__HANDLE__) \ do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ { \ return HAL_BUSY; \ } \ @@ -116,12 +118,12 @@ typedef enum { \ (__HANDLE__)->Lock = HAL_LOCKED; \ } \ - }while (0) + }while (0U) #define __HAL_UNLOCK(__HANDLE__) \ do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) #endif /* USE_RTOS */ #if defined ( __GNUC__ ) && !defined ( __CC_ARM ) @@ -148,13 +150,14 @@ typedef enum #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) + #define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN #endif /* __CC_ARM */ #endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ + /** * @brief __RAM_FUNC definition */ @@ -194,7 +197,7 @@ typedef enum /* ARM & GNUCompiler ---------------- */ -#define __NOINLINE __attribute__ ( (noinline) ) +#define __NOINLINE __attribute__ ( (noinline) ) #elif defined ( __ICCARM__ ) /* ICCARM Compiler @@ -204,7 +207,6 @@ typedef enum #endif - #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.c index 76167bb4d8a..2b271fccf2b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.c @@ -2,28 +2,27 @@ ****************************************************************************** * @file stm32f1xx_hal_dma.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief DMA HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and errors functions - @verbatim - ============================================================================== + @verbatim + ============================================================================== ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] (#) Enable and configure the peripheral to be connected to the DMA Channel (except for internal SRAM / FLASH memories: no initialization is - necessary) please refer to Reference manual for connection between peripherals + necessary). Please refer to the Reference manual for connection between peripherals and DMA requests. - (#) For a given Channel, program the required configuration through the following parameters: - Transfer Direction, Source and Destination data formats, - Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, + (#) For a given Channel, program the required configuration through the following parameters: + Channel request, Transfer Direction, Source and Destination data formats, + Circular or Normal mode, Channel Priority level, Source and Destination Increment mode using HAL_DMA_Init() function. (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error @@ -33,29 +32,29 @@ -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. - - *** Interrupt mode IO operation *** - =================================== + ================================= [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. - In this case the DMA interrupt is configured - (+) Use HAL_DMAy_Channelx_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e a member of DMA handle structure). + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. + In this case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e. a member of DMA handle structure). *** DMA HAL driver macros list *** ============================================= - [..] + [..] Below the list of most used macros in DMA HAL driver. (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. @@ -73,7 +72,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -98,7 +97,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -116,14 +115,6 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup DMA_Private_Constants DMA Private Constants - * @{ - */ -#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ -/** - * @} - */ - /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -142,12 +133,12 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t */ /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim + * @brief Initialization and de-initialization functions + * +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to initialize the DMA Channel source and destination addresses, incrementation and data sizes, transfer direction, @@ -159,24 +150,24 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t @endverbatim * @{ */ - + /** - * @brief Initializes the DMA according to the specified - * parameters in the DMA_InitTypeDef and create the associated handle. + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp = 0; - +{ + uint32_t tmp = 0U; + /* Check the DMA handle allocation */ if(hdma == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); @@ -186,24 +177,38 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - - if(hdma->State == HAL_DMA_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hdma->Lock = HAL_UNLOCKED; + +#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; } - + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; + hdma->DmaBaseAddress = DMA2; + } +#else + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; +#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */ + /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Get the CR register value */ tmp = hdma->Instance->CCR; - - /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR)); - + /* Prepare the DMA Channel configuration */ tmp |= hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | @@ -211,21 +216,30 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) hdma->Init.Mode | hdma->Init.Priority; /* Write to DMA Channel CR register */ - hdma->Instance->CCR = tmp; - + hdma->Instance->CCR = tmp; + + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + /* Initialise the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; + /* Allocate lock resource and initialize it */ + hdma->Lock = HAL_UNLOCKED; return HAL_OK; } /** - * @brief DeInitializes the DMA peripheral + * @brief DeInitialize the DMA peripheral. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) @@ -235,36 +249,48 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - /* Check the DMA peripheral state */ - if(hdma->State == HAL_DMA_STATE_BUSY) - { - return HAL_ERROR; - } - /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); - + /* Reset DMA Channel control register */ - hdma->Instance->CCR = 0; - + hdma->Instance->CCR = 0U; + /* Reset DMA Channel Number of Data to Transfer register */ - hdma->Instance->CNDTR = 0; - + hdma->Instance->CNDTR = 0U; + /* Reset DMA Channel peripheral address register */ - hdma->Instance->CPAR = 0; - + hdma->Instance->CPAR = 0U; + /* Reset DMA Channel memory address register */ - hdma->Instance->CMAR = 0; + hdma->Instance->CMAR = 0U; + +#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC) + /* calculation of the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; + hdma->DmaBaseAddress = DMA2; + } +#else + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; + hdma->DmaBaseAddress = DMA1; +#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */ /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); + /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; @@ -281,29 +307,29 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) * @} */ -/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions - * @brief I/O operation functions - * -@verbatim +/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + * @brief Input and Output operation functions + * +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and + (+) Configure the source, destination address and data length and Start DMA transfer with interrupt (+) Abort DMA transfer (+) Poll for transfer complete - (+) Handle DMA interrupt request + (+) Handle DMA interrupt request @endverbatim * @{ */ /** - * @brief Starts the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * @brief Start the DMA Transfer. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination @@ -311,31 +337,42 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) */ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { - /* Process locked */ - __HAL_LOCK(hdma); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; + HAL_StatusTypeDef status = HAL_OK; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); + /* Process locked */ + __HAL_LOCK(hdma); - return HAL_OK; + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + status = HAL_BUSY; + } + return status; } /** * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination @@ -343,89 +380,84 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { - /* Process locked */ - __HAL_LOCK(hdma); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; + HAL_StatusTypeDef status = HAL_OK; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC); - - /* Enable the Half transfer complete interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); - /* Enable the transfer Error interrupt */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE); - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); + /* Process locked */ + __HAL_LOCK(hdma); - return HAL_OK; -} + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if(NULL != hdma->XferHalfCpltCallback) + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + } + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Remain BUSY */ + status = HAL_BUSY; + } + return status; +} /** - * @brief Aborts the DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * - * @note After disabling a DMA Channel, a check for wait until the DMA Channel is - * effectively disabled is added. If a Channel is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Channel will be effectively disabled only after the transfer of - * this single data is finished. + * @brief Abort the DMA Transfer. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) { - uint32_t tickstart = 0x00; - + HAL_StatusTypeDef status = HAL_OK; + + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + /* Disable the channel */ __HAL_DMA_DISABLE(hdma); + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the DMA Channel is effectively disabled */ - while((hdma->Instance->CCR & DMA_CCR_EN) != 0) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_TIMEOUT; - } - } /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; - + /* Process Unlocked */ - __HAL_UNLOCK(hdma); + __HAL_UNLOCK(hdma); - return HAL_OK; + return status; } /** * @brief Aborts the DMA Transfer in Interrupt mode. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. + * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) @@ -436,11 +468,11 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - + status = HAL_ERROR; } else - { + { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); @@ -469,14 +501,29 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) * @brief Polling for transfer complete. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. - * @param CompleteLevel: Specifies the DMA level complete. + * @param CompleteLevel: Specifies the DMA level complete. * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) { uint32_t temp; - uint32_t tickstart = 0x00; + uint32_t tickstart = 0U; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode */ + if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) @@ -496,36 +543,38 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) { if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) - { - /* Clear the transfer error flags */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_ERROR; - + hdma->State= HAL_DMA_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hdma); - + return HAL_ERROR; } /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); - + /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; + hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); - - return HAL_TIMEOUT; + + return HAL_ERROR; } } } @@ -535,19 +584,14 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - /* The selected Channelx EN bit is cleared (DMA is disabled and + /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; - } else - { + { /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - - /* The selected Channelx EN bit is cleared (DMA is disabled and - all transfers of half buffer are complete) */ - hdma->State = HAL_DMA_STATE_READY_HALF; } /* Process unlocked */ @@ -564,101 +608,206 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { - /* Transfer Error Interrupt management ***************************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET) + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + uint32_t source_it = hdma->Instance->CCR; + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_HT) != RESET)) { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - /* Disable the transfer error interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE); - - /* Clear the transfer error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); - + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + } + /* Clear the half transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if (((flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex)) != RESET) && ((source_it & DMA_IT_TC) != RESET)) + { + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if (hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } + hdma->State = HAL_DMA_STATE_READY; + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); } } - /* Half Transfer Complete Interrupt management ******************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET) + /* Transfer Error Interrupt management **************************************/ + else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE))) { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) - { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable the half transfer interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - } - /* Clear the half transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF; + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); } } + return; +} + +/** + * @brief Register callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID: User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @param pCallback: pointer to private callbacsk function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; - /* Transfer Complete Interrupt management ***********************************/ - if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET) + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + switch (CallbackID) { - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - /* Disable the transfer complete interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC); - } - /* Clear the transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - - /* Update error code */ - SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE); + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; } } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; } +/** + * @brief UnRegister callbacks + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @param CallbackID: User Callback identifer + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + /** * @} */ -/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### State and Errors functions ##### +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== [..] This subsection provides functions allowing to (+) Check the DMA state @@ -669,18 +818,19 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) */ /** - * @brief Returns the DMA state. + * @brief Return the DMA hande state. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @retval HAL state */ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) { + /* Return DMA handle state */ return hdma->State; } /** - * @brief Return the DMA error code + * @brief Return the DMA error code. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval DMA Error Code @@ -698,14 +848,14 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) * @} */ -/** @addtogroup DMA_Private_Functions DMA Private Functions +/** @addtogroup DMA_Private_Functions * @{ */ /** * @brief Sets the DMA Transfer parameter. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. + * the configuration information for the specified DMA Channel. * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param DataLength: The length of data to be transferred from source to destination @@ -713,15 +863,18 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); + /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; - + /* Peripheral to Memory */ if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; - + /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; } @@ -730,7 +883,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t { /* Configure DMA Channel source address */ hdma->Instance->CPAR = SrcAddress; - + /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.h index 607a70b92ec..03521b9b3f8 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_hal_dma.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_DMA_H @@ -52,15 +52,15 @@ /** @addtogroup DMA * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DMA_Exported_Types DMA Exported Types * @{ */ - -/** + +/** * @brief DMA Configuration Structure definition */ typedef struct @@ -71,57 +71,58 @@ typedef struct uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. This parameter can be a value of @ref DMA_Memory_incremented_mode */ - + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_Peripheral_data_size */ uint32_t MemDataAlignment; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_Memory_data_size */ - + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_mode @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ + data transfer is configured on the selected Channel */ - uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_Priority_level */ + uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_Priority_level */ } DMA_InitTypeDef; -/** - * @brief DMA Configuration enumeration values definition - */ -typedef enum -{ - DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */ - DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */ - -} DMA_ControlTypeDef; - /** - * @brief HAL DMA State structures definition + * @brief HAL DMA State structures definition */ typedef enum { - HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */ - HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */ - HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ }HAL_DMA_StateTypeDef; -/** +/** * @brief HAL DMA Error Code structure definition */ typedef enum { - HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ }HAL_DMA_LevelCompleteTypeDef; +/** + * @brief HAL DMA Callback ID structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ + +}HAL_DMA_CallbackIDTypeDef; + /** * @brief DMA handle Structure definition */ @@ -146,6 +147,11 @@ typedef struct __DMA_HandleTypeDef void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ __IO uint32_t ErrorCode; /*!< DMA Error code */ + + DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ + + uint32_t ChannelIndex; /*!< DMA Channel Index */ + } DMA_HandleTypeDef; /** * @} @@ -160,19 +166,19 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Error_Code DMA Error Code * @{ */ -#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ -#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ -#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoing transfer */ -#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ - +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ /** * @} */ /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction * @{ - */ -#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ @@ -182,46 +188,46 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode * @{ - */ -#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ -#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */ + */ +#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ /** * @} - */ + */ /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode * @{ - */ -#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */ + */ +#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ /** * @} */ /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size * @{ - */ -#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */ -#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ -#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ /** * @} - */ + */ /** @defgroup DMA_Memory_data_size DMA Memory data size - * @{ + * @{ */ -#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */ -#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ -#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ /** * @} */ /** @defgroup DMA_mode DMA mode * @{ - */ -#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ /** * @} @@ -230,13 +236,13 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_Priority_level DMA Priority level * @{ */ -#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ -#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ -#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ -#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ +#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ +#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ /** * @} - */ + */ /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions @@ -251,35 +257,35 @@ typedef struct __DMA_HandleTypeDef /** @defgroup DMA_flag_definitions DMA flag definitions * @{ - */ -#define DMA_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA_FLAG_TE7 ((uint32_t)0x08000000) + */ +#define DMA_FLAG_GL1 0x00000001U +#define DMA_FLAG_TC1 0x00000002U +#define DMA_FLAG_HT1 0x00000004U +#define DMA_FLAG_TE1 0x00000008U +#define DMA_FLAG_GL2 0x00000010U +#define DMA_FLAG_TC2 0x00000020U +#define DMA_FLAG_HT2 0x00000040U +#define DMA_FLAG_TE2 0x00000080U +#define DMA_FLAG_GL3 0x00000100U +#define DMA_FLAG_TC3 0x00000200U +#define DMA_FLAG_HT3 0x00000400U +#define DMA_FLAG_TE3 0x00000800U +#define DMA_FLAG_GL4 0x00001000U +#define DMA_FLAG_TC4 0x00002000U +#define DMA_FLAG_HT4 0x00004000U +#define DMA_FLAG_TE4 0x00008000U +#define DMA_FLAG_GL5 0x00010000U +#define DMA_FLAG_TC5 0x00020000U +#define DMA_FLAG_HT5 0x00040000U +#define DMA_FLAG_TE5 0x00080000U +#define DMA_FLAG_GL6 0x00100000U +#define DMA_FLAG_TC6 0x00200000U +#define DMA_FLAG_HT6 0x00400000U +#define DMA_FLAG_TE6 0x00800000U +#define DMA_FLAG_GL7 0x01000000U +#define DMA_FLAG_TC7 0x02000000U +#define DMA_FLAG_HT7 0x04000000U +#define DMA_FLAG_TE7 0x08000000U /** * @} */ @@ -287,15 +293,15 @@ typedef struct __DMA_HandleTypeDef /** * @} */ - -/* Exported macro ------------------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ /** @defgroup DMA_Exported_Macros DMA Exported Macros * @{ */ -/** @brief Reset DMA handle state - * @param __HANDLE__: DMA handle. +/** @brief Reset DMA handle state. + * @param __HANDLE__: DMA handle * @retval None */ #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) @@ -303,14 +309,14 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enable the specified DMA Channel. * @param __HANDLE__: DMA handle - * @retval None. + * @retval None */ #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) /** * @brief Disable the specified DMA Channel. * @param __HANDLE__: DMA handle - * @retval None. + * @retval None */ #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) @@ -320,7 +326,7 @@ typedef struct __DMA_HandleTypeDef /** * @brief Enables the specified DMA Channel interrupts. * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -330,9 +336,9 @@ typedef struct __DMA_HandleTypeDef #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) /** - * @brief Disables the specified DMA Channel interrupts. + * @brief Disable the specified DMA Channel interrupts. * @param __HANDLE__: DMA handle - * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask @@ -342,7 +348,7 @@ typedef struct __DMA_HandleTypeDef #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) /** - * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled. + * @brief Check whether the specified DMA Channel interrupt is enabled or not. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt source to check. * This parameter can be one of the following values: @@ -354,9 +360,8 @@ typedef struct __DMA_HandleTypeDef #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** - * @brief Returns the number of remaining data units in the current DMAy Channelx transfer. + * @brief Return the number of remaining data units in the current DMA Channel transfer. * @param __HANDLE__: DMA handle - * * @retval The number of remaining data units in the current DMA Channel transfer. */ #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) @@ -369,11 +374,11 @@ typedef struct __DMA_HandleTypeDef #include "stm32f1xx_hal_dma_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA_Exported_Functions DMA Exported Functions +/** @addtogroup DMA_Exported_Functions * @{ */ -/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions +/** @addtogroup DMA_Exported_Functions_Group1 * @{ */ /* Initialization and de-initialization functions *****************************/ @@ -383,7 +388,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); * @} */ -/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions +/** @addtogroup DMA_Exported_Functions_Group2 * @{ */ /* IO operation functions *****************************************************/ @@ -392,17 +397,20 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + /** * @} */ -/** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions +/** @addtogroup DMA_Exported_Functions_Group3 * @{ */ /* Peripheral State and Error functions ***************************************/ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); /** * @} */ @@ -411,26 +419,16 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); * @} */ -/* Private Constants -------------------------------------------------------------*/ -/** @defgroup DMA_Private_Constants DMA Private Constants - * @brief DMA private defines and constants - * @{ - */ -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /** @defgroup DMA_Private_Macros DMA Private Macros - * @brief DMA private macros * @{ */ -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) - #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ ((STATE) == DMA_PINC_DISABLE)) @@ -447,29 +445,22 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); ((SIZE) == DMA_MDATAALIGN_WORD )) #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) + ((MODE) == DMA_CIRCULAR)) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) /** * @} */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions - * @brief DMA private functions - * @{ - */ -/** - * @} - */ /** * @} - */ + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma_ex.h index b28cdeada70..6f03958bd63 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_dma_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -52,7 +52,7 @@ /** @defgroup DMAEx DMAEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -197,10 +197,10 @@ DMA_FLAG_TC7) /** - * @brief Returns the current DMA Channel half transfer complete flag. + * @brief Return the current DMA Channel half transfer complete flag. * @param __HANDLE__: DMA handle * @retval The specified half transfer complete flag index. - */ + */ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ @@ -211,7 +211,7 @@ DMA_FLAG_HT7) /** - * @brief Returns the current DMA Channel transfer error flag. + * @brief Return the current DMA Channel transfer error flag. * @param __HANDLE__: DMA handle * @retval The specified transfer error flag index. */ @@ -246,6 +246,7 @@ * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GLx: Global interrupt flag * Where x can be 1_7 to select the DMA Channel flag. * @retval The state of FLAG (SET or RESET). */ @@ -253,13 +254,14 @@ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) /** - * @brief Clears the DMA Channel pending flags. + * @brief Clear the DMA Channel pending flags. * @param __HANDLE__: DMA handle * @param __FLAG__: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCx: Transfer complete flag * @arg DMA_FLAG_HTx: Half transfer complete flag * @arg DMA_FLAG_TEx: Transfer error flag + * @arg DMA_FLAG_GLx: Global interrupt flag * Where x can be 1_7 to select the DMA Channel flag. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.c index 439cb7012c7..0905aeb4286 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_eth.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief ETH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: @@ -118,13 +118,13 @@ /** @defgroup ETH_Private_Constants ETH Private Constants * @{ */ -#define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */ -#define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */ +#define ETH_TIMEOUT_SWRESET 500U +#define ETH_TIMEOUT_LINKED_STATE 5000U +#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U /** * @} */ - /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -142,6 +142,7 @@ static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth); static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth); static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth); static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); +static void ETH_Delay(uint32_t mdelay); /** * @} @@ -176,9 +177,9 @@ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); */ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) { - uint32_t tmpreg = 0, phyreg = 0; - uint32_t hclk = 60000000; - uint32_t tickstart = 0; + uint32_t tmpreg1 = 0U, phyreg = 0U; + uint32_t hclk = 60000000U; + uint32_t tickstart = 0U; uint32_t err = ETH_SUCCESS; /* Check the ETH peripheral state */ @@ -197,7 +198,6 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) { /* Allocate lock resource and initialize it */ heth->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspInit(heth); } @@ -211,39 +211,54 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) /* After reset all the registers holds their respective reset values */ (heth->Instance)->DMABMR |= ETH_DMABMR_SR; + /* Get tick */ + tickstart = HAL_GetTick(); + /* Wait for software reset */ while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET) + { + heth->State= HAL_ETH_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are + not available, please check your external PHY or the IO configuration */ + return HAL_TIMEOUT; + } } /*-------------------------------- MAC Initialization ----------------------*/ /* Get the ETHERNET MACMIIAR value */ - tmpreg = (heth->Instance)->MACMIIAR; + tmpreg1 = (heth->Instance)->MACMIIAR; /* Clear CSR Clock Range CR[2:0] bits */ - tmpreg &= ETH_MACMIIAR_CR_MASK; + tmpreg1 &= ETH_MACMIIAR_CR_MASK; /* Get hclk frequency value */ hclk = HAL_RCC_GetHCLKFreq(); /* Set CR bits depending on hclk value */ - if((hclk >= 20000000)&&(hclk < 35000000)) + if((hclk >= 20000000U)&&(hclk < 35000000U)) { /* CSR Clock Range between 20-35 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_DIV16; + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV16; } - else if((hclk >= 35000000)&&(hclk < 60000000)) + else if((hclk >= 35000000U)&&(hclk < 60000000U)) { /* CSR Clock Range between 35-60 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_DIV26; + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV26; } else { /* CSR Clock Range between 60-72 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_DIV42; + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV42; } /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ - (heth->Instance)->MACMIIAR = (uint32_t)tmpreg; + (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1; /*-------------------- PHY initialization and configuration ----------------*/ /* Put the PHY in reset mode */ @@ -276,7 +291,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE) { /* In case of write timeout */ err = ETH_ERROR; @@ -319,7 +334,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED) { /* In case of write timeout */ err = ETH_ERROR; @@ -383,8 +398,8 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); /* Set MAC Speed and Duplex Mode */ - if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) | - (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK) + if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) | + (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK) { /* In case of write timeout */ err = ETH_ERROR; @@ -448,7 +463,7 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) */ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) { - uint32_t i = 0; + uint32_t i = 0U; ETH_DMADescTypeDef *dmatxdesc; /* Process Locked */ @@ -461,7 +476,7 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc heth->TxDesc = DMATxDescTab; /* Fill each DMATxDesc descriptor with the right values */ - for(i=0; i < TxBuffCount; i++) + for(i=0U; i < TxBuffCount; i++) { /* Get the pointer on the ith member of the Tx Desc list */ dmatxdesc = DMATxDescTab + i; @@ -479,10 +494,10 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc } /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (TxBuffCount-1)) + if(i < (TxBuffCount-1U)) { /* Set next descriptor address register with next descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U); } else { @@ -515,7 +530,7 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc */ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) { - uint32_t i = 0; + uint32_t i = 0U; ETH_DMADescTypeDef *DMARxDesc; /* Process Locked */ @@ -528,7 +543,7 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc heth->RxDesc = DMARxDescTab; /* Fill each DMARxDesc descriptor with the right values */ - for(i=0; i < RxBuffCount; i++) + for(i=0U; i < RxBuffCount; i++) { /* Get the pointer on the ith member of the Rx Desc list */ DMARxDesc = DMARxDescTab+i; @@ -549,10 +564,10 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc } /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (RxBuffCount-1)) + if(i < (RxBuffCount-1U)) { /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U); } else { @@ -640,7 +655,7 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) */ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) { - uint32_t bufcount = 0, size = 0, i = 0; + uint32_t bufcount = 0U, size = 0U, i = 0U; /* Process Locked */ __HAL_LOCK(heth); @@ -648,7 +663,7 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL /* Set the ETH peripheral state to BUSY */ heth->State = HAL_ETH_STATE_BUSY; - if (FrameLength == 0) + if (FrameLength == 0U) { /* Set ETH HAL state to READY */ heth->State = HAL_ETH_STATE_READY; @@ -682,9 +697,9 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL } else { - bufcount = 1; + bufcount = 1U; } - if (bufcount == 1) + if (bufcount == 1U) { /* Set LAST and FIRST segment */ heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS; @@ -697,12 +712,12 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL } else { - for (i=0; i< bufcount; i++) + for (i=0U; i< bufcount; i++) { /* Clear FIRST and LAST segment bits */ heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); - if (i == 0) + if (i == 0U) { /* Setting the first segment bit */ heth->TxDesc->Status |= ETH_DMATXDESC_FS; @@ -711,11 +726,11 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL /* Program size */ heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); - if (i == (bufcount-1)) + if (i == (bufcount-1U)) { /* Setting the last segment bit */ heth->TxDesc->Status |= ETH_DMATXDESC_LS; - size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE; + size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE; heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); } @@ -732,7 +747,7 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL /* Clear TBUS ETHERNET DMA flag */ (heth->Instance)->DMASR = ETH_DMASR_TBUS; /* Resume DMA transmission*/ - (heth->Instance)->DMATPDR = 0; + (heth->Instance)->DMATPDR = 0U; } /* Set ETH HAL State to Ready */ @@ -753,7 +768,7 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL */ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) { - uint32_t framelength = 0; + uint32_t framelength = 0U; /* Process Locked */ __HAL_LOCK(heth); @@ -772,7 +787,7 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) (heth->RxFrameInfos).SegCount++; /* Check if last segment is first segment: one segment contains the frame */ - if ((heth->RxFrameInfos).SegCount == 1) + if ((heth->RxFrameInfos).SegCount == 1U) { (heth->RxFrameInfos).FSRxDesc =heth->RxDesc; } @@ -780,7 +795,7 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) heth->RxFrameInfos.LSRxDesc = heth->RxDesc; /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4; + framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; heth->RxFrameInfos.length = framelength; /* Get the address of the buffer start address */ @@ -802,7 +817,7 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) { (heth->RxFrameInfos).FSRxDesc = heth->RxDesc; (heth->RxFrameInfos).LSRxDesc = NULL; - (heth->RxFrameInfos).SegCount = 1; + (heth->RxFrameInfos).SegCount = 1U; /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); } @@ -833,7 +848,7 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) */ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) { - uint32_t descriptorscancounter = 0; + uint32_t descriptorscancounter = 0U; /* Process Locked */ __HAL_LOCK(heth); @@ -852,7 +867,7 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS) { heth->RxFrameInfos.FSRxDesc = heth->RxDesc; - heth->RxFrameInfos.SegCount = 1; + heth->RxFrameInfos.SegCount = 1U; /* Point to next descriptor */ heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); } @@ -875,13 +890,13 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) (heth->RxFrameInfos.SegCount)++; /* Check if last segment is first segment: one segment contains the frame */ - if ((heth->RxFrameInfos.SegCount) == 1) + if ((heth->RxFrameInfos.SegCount) == 1U) { heth->RxFrameInfos.FSRxDesc = heth->RxDesc; } /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4; + heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; /* Get the address of the buffer start address */ heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; @@ -1029,8 +1044,8 @@ __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) */ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) { - uint32_t tmpreg = 0; - uint32_t tickstart = 0; + uint32_t tmpreg1 = 0U; + uint32_t tickstart = 0U; /* Check parameters */ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); @@ -1044,25 +1059,25 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR heth->State = HAL_ETH_STATE_BUSY_RD; /* Get the ETHERNET MACMIIAR value */ - tmpreg = heth->Instance->MACMIIAR; + tmpreg1 = heth->Instance->MACMIIAR; /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~ETH_MACMIIAR_CR_MASK; + tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; /* Prepare the MII address register value */ - tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ - tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg; + heth->Instance->MACMIIAR = tmpreg1; /* Get tick */ tickstart = HAL_GetTick(); /* Check for the Busy flag */ - while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > PHY_READ_TO) @@ -1075,7 +1090,7 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR return HAL_TIMEOUT; } - tmpreg = heth->Instance->MACMIIAR; + tmpreg1 = heth->Instance->MACMIIAR; } /* Get MACMIIDR value */ @@ -1101,8 +1116,8 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYR */ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) { - uint32_t tmpreg = 0; - uint32_t tickstart = 0; + uint32_t tmpreg1 = 0U; + uint32_t tickstart = 0U; /* Check parameters */ assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); @@ -1116,28 +1131,28 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY heth->State = HAL_ETH_STATE_BUSY_WR; /* Get the ETHERNET MACMIIAR value */ - tmpreg = heth->Instance->MACMIIAR; + tmpreg1 = heth->Instance->MACMIIAR; /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~ETH_MACMIIAR_CR_MASK; + tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; /* Prepare the MII register address value */ - tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ - tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ /* Give the value to the MII data register */ heth->Instance->MACMIIDR = (uint16_t)RegValue; /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg; + heth->Instance->MACMIIAR = tmpreg1; /* Get tick */ tickstart = HAL_GetTick(); /* Check for the Busy flag */ - while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO) @@ -1150,7 +1165,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHY return HAL_TIMEOUT; } - tmpreg = heth->Instance->MACMIIAR; + tmpreg1 = heth->Instance->MACMIIAR; } /* Set ETH HAL State to READY */ @@ -1272,7 +1287,7 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) */ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) { - uint32_t tmpreg = 0; + uint32_t tmpreg1 = 0U; /* Process Locked */ __HAL_LOCK(heth); @@ -1316,11 +1331,11 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ - tmpreg = (heth->Instance)->MACCR; + tmpreg1 = (heth->Instance)->MACCR; /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg &= ETH_MACCR_CLEAR_MASK; + tmpreg1 &= ETH_MACCR_CLEAR_MASK; - tmpreg |= (uint32_t)(macconf->Watchdog | + tmpreg1 |= (uint32_t)(macconf->Watchdog | macconf->Jabber | macconf->InterFrameGap | macconf->CarrierSense | @@ -1335,13 +1350,13 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef macconf->DeferralCheck); /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg; + (heth->Instance)->MACCR = (uint32_t)tmpreg1; /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; + tmpreg1 = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; + (heth->Instance)->MACCR = tmpreg1; /*----------------------- ETHERNET MACFFR Configuration --------------------*/ /* Write to ETHERNET MACFFR */ @@ -1356,9 +1371,9 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACFFR; + tmpreg1 = (heth->Instance)->MACFFR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg; + (heth->Instance)->MACFFR = tmpreg1; /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ /* Write to ETHERNET MACHTHR */ @@ -1369,11 +1384,11 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef /*----------------------- ETHERNET MACFCR Configuration --------------------*/ /* Get the ETHERNET MACFCR value */ - tmpreg = (heth->Instance)->MACFCR; + tmpreg1 = (heth->Instance)->MACFCR; /* Clear xx bits */ - tmpreg &= ETH_MACFCR_CLEAR_MASK; + tmpreg1 &= ETH_MACFCR_CLEAR_MASK; - tmpreg |= (uint32_t)((macconf->PauseTime << 16) | + tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | macconf->ZeroQuantaPause | macconf->PauseLowThreshold | macconf->UnicastPauseFrameDetect | @@ -1381,13 +1396,13 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef macconf->TransmitFlowControl); /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg; + (heth->Instance)->MACFCR = (uint32_t)tmpreg1; /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACFCR; + tmpreg1 = (heth->Instance)->MACFCR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg; + (heth->Instance)->MACFCR = tmpreg1; /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | @@ -1395,29 +1410,29 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACVLANTR; + tmpreg1 = (heth->Instance)->MACVLANTR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg; + (heth->Instance)->MACVLANTR = tmpreg1; } else /* macconf == NULL : here we just configure Speed and Duplex mode */ { /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ - tmpreg = (heth->Instance)->MACCR; + tmpreg1 = (heth->Instance)->MACCR; /* Clear FES and DM bits */ - tmpreg &= ~((uint32_t)0x00004800); + tmpreg1 &= ~(0x00004800U); - tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); + tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg; + (heth->Instance)->MACCR = (uint32_t)tmpreg1; /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; + tmpreg1 = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; + (heth->Instance)->MACCR = tmpreg1; } /* Set the ETH state to Ready */ @@ -1439,7 +1454,7 @@ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef */ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) { - uint32_t tmpreg = 0; + uint32_t tmpreg1 = 0U; /* Process Locked */ __HAL_LOCK(heth); @@ -1466,11 +1481,11 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ /* Get the ETHERNET DMAOMR value */ - tmpreg = (heth->Instance)->DMAOMR; + tmpreg1 = (heth->Instance)->DMAOMR; /* Clear xx bits */ - tmpreg &= ETH_DMAOMR_CLEAR_MASK; + tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; - tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | + tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | dmaconf->ReceiveStoreForward | dmaconf->FlushReceivedFrame | dmaconf->TransmitStoreForward | @@ -1481,28 +1496,28 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef dmaconf->SecondFrameOperate); /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg; + (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMAOMR; + tmpreg1 = (heth->Instance)->DMAOMR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg; + (heth->Instance)->DMAOMR = tmpreg1; /*----------------------- ETHERNET DMABMR Configuration --------------------*/ (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | dmaconf->FixedBurst | dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ dmaconf->TxDMABurstLength | - (dmaconf->DescriptorSkipLength << 2) | + (dmaconf->DescriptorSkipLength << 2U) | dmaconf->DMAArbitration | ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMABMR; + tmpreg1 = (heth->Instance)->DMABMR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg; + (heth->Instance)->DMABMR = tmpreg1; /* Set the ETH state to Ready */ heth->State= HAL_ETH_STATE_READY; @@ -1571,7 +1586,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) { ETH_MACInitTypeDef macinit; ETH_DMAInitTypeDef dmainit; - uint32_t tmpreg = 0; + uint32_t tmpreg1 = 0U; if (err != ETH_SUCCESS) /* Auto-negotiation failed */ { @@ -1609,22 +1624,22 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; - macinit.HashTableHigh = 0x0; - macinit.HashTableLow = 0x0; - macinit.PauseTime = 0x0; + macinit.HashTableHigh = 0x0U; + macinit.HashTableLow = 0x0U; + macinit.PauseTime = 0x0U; macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; - macinit.VLANTagIdentifier = 0x0; + macinit.VLANTagIdentifier = 0x0U; /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ - tmpreg = (heth->Instance)->MACCR; + tmpreg1 = (heth->Instance)->MACCR; /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg &= ETH_MACCR_CLEAR_MASK; + tmpreg1 &= ETH_MACCR_CLEAR_MASK; /* Set the WD bit according to ETH Watchdog value */ /* Set the JD: bit according to ETH Jabber value */ /* Set the IFG bit according to ETH InterFrameGap value */ @@ -1638,7 +1653,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ /* Set the BL bit according to ETH BackOffLimit value */ /* Set the DC bit according to ETH DeferralCheck value */ - tmpreg |= (uint32_t)(macinit.Watchdog | + tmpreg1 |= (uint32_t)(macinit.Watchdog | macinit.Jabber | macinit.InterFrameGap | macinit.CarrierSense | @@ -1653,13 +1668,13 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) macinit.DeferralCheck); /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg; + (heth->Instance)->MACCR = (uint32_t)tmpreg1; /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; + tmpreg1 = (heth->Instance)->MACCR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; + (heth->Instance)->MACCR = tmpreg1; /*----------------------- ETHERNET MACFFR Configuration --------------------*/ /* Set the RA bit according to ETH ReceiveAll value */ @@ -1682,9 +1697,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACFFR; + tmpreg1 = (heth->Instance)->MACFFR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg; + (heth->Instance)->MACFFR = tmpreg1; /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ /* Write to ETHERNET MACHTHR */ @@ -1695,9 +1710,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /*----------------------- ETHERNET MACFCR Configuration -------------------*/ /* Get the ETHERNET MACFCR value */ - tmpreg = (heth->Instance)->MACFCR; + tmpreg1 = (heth->Instance)->MACFCR; /* Clear xx bits */ - tmpreg &= ETH_MACFCR_CLEAR_MASK; + tmpreg1 &= ETH_MACFCR_CLEAR_MASK; /* Set the PT bit according to ETH PauseTime value */ /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ @@ -1705,7 +1720,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ /* Set the RFE bit according to ETH ReceiveFlowControl value */ /* Set the TFE bit according to ETH TransmitFlowControl value */ - tmpreg |= (uint32_t)((macinit.PauseTime << 16) | + tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) | macinit.ZeroQuantaPause | macinit.PauseLowThreshold | macinit.UnicastPauseFrameDetect | @@ -1713,13 +1728,13 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) macinit.TransmitFlowControl); /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg; + (heth->Instance)->MACFCR = (uint32_t)tmpreg1; /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACFCR; + tmpreg1 = (heth->Instance)->MACFCR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg; + (heth->Instance)->MACFCR = tmpreg1; /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ /* Set the ETV bit according to ETH VLANTagComparison value */ @@ -1729,9 +1744,9 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACVLANTR; + tmpreg1 = (heth->Instance)->MACVLANTR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg; + (heth->Instance)->MACVLANTR = tmpreg1; /* Ethernet DMA default initialization ************************************/ dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; @@ -1747,13 +1762,13 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE; dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; - dmainit.DescriptorSkipLength = 0x0; + dmainit.DescriptorSkipLength = 0x0U; dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; /* Get the ETHERNET DMAOMR value */ - tmpreg = (heth->Instance)->DMAOMR; + tmpreg1 = (heth->Instance)->DMAOMR; /* Clear xx bits */ - tmpreg &= ETH_DMAOMR_CLEAR_MASK; + tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ /* Set the RSF bit according to ETH ReceiveStoreForward value */ @@ -1764,7 +1779,7 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ /* Set the RTC bit according to ETH ReceiveThresholdControl value */ /* Set the OSF bit according to ETH SecondFrameOperate value */ - tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | + tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | dmainit.ReceiveStoreForward | dmainit.FlushReceivedFrame | dmainit.TransmitStoreForward | @@ -1775,13 +1790,13 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) dmainit.SecondFrameOperate); /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg; + (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMAOMR; + tmpreg1 = (heth->Instance)->DMAOMR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg; + (heth->Instance)->DMAOMR = tmpreg1; /*----------------------- ETHERNET DMABMR Configuration ------------------*/ /* Set the AAL bit according to ETH AddressAlignedBeats value */ @@ -1794,15 +1809,15 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) dmainit.FixedBurst | dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ dmainit.TxDMABurstLength | - (dmainit.DescriptorSkipLength << 2) | + (dmainit.DescriptorSkipLength << 2U) | dmainit.DMAArbitration | ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMABMR; + tmpreg1 = (heth->Instance)->DMABMR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg; + (heth->Instance)->DMABMR = tmpreg1; if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) { @@ -1829,20 +1844,23 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) */ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) { - uint32_t tmpreg; + uint32_t tmpreg1; + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* Check the parameters */ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); /* Calculate the selected MAC address high register */ - tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; /* Load the selected MAC address high register */ - (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg; + (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; /* Calculate the selected MAC address low register */ - tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U]; /* Load the selected MAC address low register */ - (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg; + (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; } /** @@ -1853,16 +1871,16 @@ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint */ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) { - __IO uint32_t tmpreg = 0; + __IO uint32_t tmpreg1 = 0U; /* Enable the MAC transmission */ (heth->Instance)->MACCR |= ETH_MACCR_TE; /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; + tmpreg1 = (heth->Instance)->MACCR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; } /** @@ -1873,16 +1891,16 @@ static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) */ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) { - __IO uint32_t tmpreg = 0; + __IO uint32_t tmpreg1 = 0U; /* Disable the MAC transmission */ (heth->Instance)->MACCR &= ~ETH_MACCR_TE; /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; + tmpreg1 = (heth->Instance)->MACCR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; } /** @@ -1893,16 +1911,16 @@ static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) */ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) { - __IO uint32_t tmpreg = 0; + __IO uint32_t tmpreg1 = 0U; /* Enable the MAC reception */ (heth->Instance)->MACCR |= ETH_MACCR_RE; /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; + tmpreg1 = (heth->Instance)->MACCR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; } /** @@ -1913,16 +1931,16 @@ static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) */ static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) { - __IO uint32_t tmpreg = 0; + __IO uint32_t tmpreg1 = 0U; /* Disable the MAC reception */ (heth->Instance)->MACCR &= ~ETH_MACCR_RE; /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg; + tmpreg1 = (heth->Instance)->MACCR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; } /** @@ -1981,16 +1999,31 @@ static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) */ static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) { - __IO uint32_t tmpreg = 0; + __IO uint32_t tmpreg1 = 0U; /* Set the Flush Transmit FIFO bit */ (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg; + tmpreg1 = (heth->Instance)->DMAOMR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMAOMR = tmpreg1; +} + +/** + * @brief This function provides delay (in milliseconds) based on CPU cycles method. + * @param mdelay: specifies the delay time length, in milliseconds. + * @retval None + */ +static void ETH_Delay(uint32_t mdelay) +{ + __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); + do + { + __NOP(); + } + while (Delay --); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h index 8ec39a39ab4..cb2f3c85ba4 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_eth.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of ETH HAL module. ****************************************************************************** * @attention @@ -58,7 +58,7 @@ /** @addtogroup ETH_Private_Macros * @{ */ -#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ @@ -122,7 +122,7 @@ #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) -#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ @@ -137,7 +137,7 @@ ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) -#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ ((ADDRESS) == ETH_MAC_ADDRESS1) || \ ((ADDRESS) == ETH_MAC_ADDRESS2) || \ @@ -207,80 +207,157 @@ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) +#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) - +#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ + ((FLAG) == ETH_DMATXDESC_IC) || \ + ((FLAG) == ETH_DMATXDESC_LS) || \ + ((FLAG) == ETH_DMATXDESC_FS) || \ + ((FLAG) == ETH_DMATXDESC_DC) || \ + ((FLAG) == ETH_DMATXDESC_DP) || \ + ((FLAG) == ETH_DMATXDESC_TTSE) || \ + ((FLAG) == ETH_DMATXDESC_TER) || \ + ((FLAG) == ETH_DMATXDESC_TCH) || \ + ((FLAG) == ETH_DMATXDESC_TTSS) || \ + ((FLAG) == ETH_DMATXDESC_IHE) || \ + ((FLAG) == ETH_DMATXDESC_ES) || \ + ((FLAG) == ETH_DMATXDESC_JT) || \ + ((FLAG) == ETH_DMATXDESC_FF) || \ + ((FLAG) == ETH_DMATXDESC_PCE) || \ + ((FLAG) == ETH_DMATXDESC_LCA) || \ + ((FLAG) == ETH_DMATXDESC_NC) || \ + ((FLAG) == ETH_DMATXDESC_LCO) || \ + ((FLAG) == ETH_DMATXDESC_EC) || \ + ((FLAG) == ETH_DMATXDESC_VF) || \ + ((FLAG) == ETH_DMATXDESC_CC) || \ + ((FLAG) == ETH_DMATXDESC_ED) || \ + ((FLAG) == ETH_DMATXDESC_UF) || \ + ((FLAG) == ETH_DMATXDESC_DB)) #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) -#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) - +#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) +#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ + ((FLAG) == ETH_DMARXDESC_AFM) || \ + ((FLAG) == ETH_DMARXDESC_ES) || \ + ((FLAG) == ETH_DMARXDESC_DE) || \ + ((FLAG) == ETH_DMARXDESC_SAF) || \ + ((FLAG) == ETH_DMARXDESC_LE) || \ + ((FLAG) == ETH_DMARXDESC_OE) || \ + ((FLAG) == ETH_DMARXDESC_VLAN) || \ + ((FLAG) == ETH_DMARXDESC_FS) || \ + ((FLAG) == ETH_DMARXDESC_LS) || \ + ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ + ((FLAG) == ETH_DMARXDESC_LC) || \ + ((FLAG) == ETH_DMARXDESC_FT) || \ + ((FLAG) == ETH_DMARXDESC_RWT) || \ + ((FLAG) == ETH_DMARXDESC_RE) || \ + ((FLAG) == ETH_DMARXDESC_DBE) || \ + ((FLAG) == ETH_DMARXDESC_CE) || \ + ((FLAG) == ETH_DMARXDESC_MAMPCE)) #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ ((BUFFER) == ETH_DMARXDESC_BUFFER2)) - +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ + ((FLAG) == ETH_PMT_FLAG_MPR)) +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) +#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ + ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ + ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ + ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ + ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ + ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ + ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ + ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ + ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ + ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ + ((FLAG) == ETH_DMA_FLAG_T)) +#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) +#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ + ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ + ((IT) == ETH_MAC_IT_PMT)) +#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ + ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ + ((FLAG) == ETH_MAC_FLAG_PMT)) +#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) +#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ + ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ + ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ + ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ + ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ + ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ + ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ + ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ + ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) +#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ + ((IT) != 0x00U)) +#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ + ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ + ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) +#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ + ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) /** * @} */ -/** @addtogroup ETH_Private_Constants +/** @addtogroup ETH_Private_Defines * @{ */ /* Delay to wait when writing to some Ethernet registers */ -#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001) +#define ETH_REG_WRITE_DELAY 0x00000001U /* ETHERNET Errors */ -#define ETH_SUCCESS ((uint32_t)0) -#define ETH_ERROR ((uint32_t)1) +#define ETH_SUCCESS 0U +#define ETH_ERROR 1U /* ETHERNET DMA Tx descriptors Collision Count Shift */ -#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3) +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ -#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16) +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U /* ETHERNET DMA Rx descriptors Frame Length Shift */ -#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16) +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ -#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16) +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U /* ETHERNET DMA Rx descriptors Frame length Shift */ -#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16) +#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U /* ETHERNET MAC address offsets */ -#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */ +#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ /* ETHERNET MACMIIAR register Mask */ -#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) +#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U /* ETHERNET MACCR register Mask */ -#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) +#define ETH_MACCR_CLEAR_MASK 0xFF20810FU /* ETHERNET MACFCR register Mask */ -#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) +#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U /* ETHERNET DMAOMR register Mask */ -#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) +#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U /* ETHERNET Remote Wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8 +#define ETH_WAKEUP_REGISTER_LENGTH 8U /* ETHERNET Missed frames counter Shift */ -#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U /** * @} - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ETH_Exported_Types ETH Exported Types @@ -292,16 +369,16 @@ */ typedef enum { - HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */ - HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */ - HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */ - HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ + HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ + HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ + HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ + HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ + HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ }HAL_ETH_StateTypeDef; /** @@ -332,7 +409,7 @@ typedef struct uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. This parameter can be a value of @ref ETH_Checksum_Mode */ - uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface. + uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. This parameter can be a value of @ref ETH_Media_Interface */ } ETH_InitTypeDef; @@ -387,10 +464,10 @@ typedef struct uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). This parameter can be a value of @ref ETH_Receive_All */ - uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. - This parameter can be a value of @ref ETH_Source_Addr_Filter */ + uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. + This parameter can be a value of @ref ETH_Source_Addr_Filter */ - uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) This parameter can be a value of @ref ETH_Pass_Control_Frames */ uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. @@ -409,13 +486,13 @@ typedef struct This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */ uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ @@ -423,7 +500,7 @@ typedef struct uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame. This parameter can be a value of @ref ETH_Pause_Low_Threshold */ - + uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 unicast address and unique multicast address). This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ @@ -444,7 +521,6 @@ typedef struct } ETH_MACInitTypeDef; - /** * @brief ETH DMA Configuration Structure definition */ @@ -485,7 +561,7 @@ typedef struct uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. This parameter can be a value of @ref ETH_Fixed_Burst */ - + uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ @@ -493,7 +569,7 @@ typedef struct This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) - This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ + This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. This parameter can be a value of @ref ETH_DMA_Arbitration */ @@ -516,7 +592,6 @@ typedef struct } ETH_DMADescTypeDef; - /** * @brief Received Frame Informations structure definition */ @@ -534,7 +609,6 @@ typedef struct } ETH_DMARxFrameInfos; - /** * @brief ETH Handle Structure definition */ @@ -571,14 +645,14 @@ typedef struct /** @defgroup ETH_Buffers_setting ETH Buffers setting * @{ */ -#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */ -#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */ -#define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */ -#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */ -#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */ -#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */ +#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4U /*!< Ethernet CRC */ +#define ETH_EXTRA 2U /*!< Extra bytes in some cases */ +#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ +#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ +#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ /* Ethernet driver receive buffers are organized in a chained linked-list, when an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO @@ -603,7 +677,7 @@ typedef struct /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ #ifndef ETH_RXBUFNB - #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ + #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ #endif @@ -630,7 +704,7 @@ typedef struct /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ #ifndef ETH_TXBUFNB - #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ + #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ #endif /** @@ -642,7 +716,7 @@ typedef struct */ /* - DMA Tx Desciptor + DMA Tx Descriptor ----------------------------------------------------------------------------------------------- TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | ----------------------------------------------------------------------------------------------- @@ -657,56 +731,56 @@ typedef struct /** * @brief Bit definition of TDES0 register: DMA Tx descriptor status register */ -#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ -#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */ -#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */ -#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */ -#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */ -#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ -#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ -#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ -#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ -#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ -#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ -#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ -#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ -#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ -#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ -#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ -#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ -#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */ -#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */ -#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ -#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ -#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ -#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */ -#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ -#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ -#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ +#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ +#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ +#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ +#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ +#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ +#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ +#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ +#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ +#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ +#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ +#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ +#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ +#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ +#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ +#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ +#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ +#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ +#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ /** * @brief Bit definition of TDES1 register */ -#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ -#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ +#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ +#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ /** * @brief Bit definition of TDES2 register */ -#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ +#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ /** * @brief Bit definition of TDES3 register */ -#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ +#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ /** * @} */ -/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor +/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor * @{ */ @@ -726,44 +800,44 @@ typedef struct /** * @brief Bit definition of RDES0 register: DMA Rx descriptor status register */ -#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ -#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ -#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ -#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */ -#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ -#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ -#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ -#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ -#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ -#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ -#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ -#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ -#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ -#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ -#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ -#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ -#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */ -#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ +#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ +#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ +#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ +#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ +#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ +#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ +#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ +#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ +#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ +#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ /** * @brief Bit definition of RDES1 register */ -#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ -#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ -#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ -#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ -#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ +#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ +#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ +#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ +#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ +#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ /** * @brief Bit definition of RDES2 register */ -#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ +#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ /** * @brief Bit definition of RDES3 register */ -#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ +#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ /** * @} @@ -771,8 +845,8 @@ typedef struct /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation * @{ */ -#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001) -#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000) +#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U +#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U /** * @} @@ -780,25 +854,25 @@ typedef struct /** @defgroup ETH_Speed ETH Speed * @{ */ -#define ETH_SPEED_10M ((uint32_t)0x00000000) -#define ETH_SPEED_100M ((uint32_t)0x00004000) +#define ETH_SPEED_10M 0x00000000U +#define ETH_SPEED_100M 0x00004000U /** * @} */ -/** @defgroup ETH_Duplex_Mode ETH Duplex Mode +/** @defgroup ETH_Duplex_Mode ETH Duplex Mode * @{ */ -#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800) -#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000) +#define ETH_MODE_FULLDUPLEX 0x00000800U +#define ETH_MODE_HALFDUPLEX 0x00000000U /** * @} */ -/** @defgroup ETH_Rx_Mode ETH Rx Mode +/** @defgroup ETH_Rx_Mode ETH Rx Mode * @{ */ -#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000) -#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001) +#define ETH_RXPOLLING_MODE 0x00000000U +#define ETH_RXINTERRUPT_MODE 0x00000001U /** * @} */ @@ -806,8 +880,8 @@ typedef struct /** @defgroup ETH_Checksum_Mode ETH Checksum Mode * @{ */ -#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000) -#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001) +#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U +#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U /** * @} */ @@ -815,7 +889,7 @@ typedef struct /** @defgroup ETH_Media_Interface ETH Media Interface * @{ */ -#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000) +#define ETH_MEDIA_INTERFACE_MII 0x00000000U #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL) /** @@ -825,19 +899,17 @@ typedef struct /** @defgroup ETH_Watchdog ETH Watchdog * @{ */ -#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000) -#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000) - +#define ETH_WATCHDOG_ENABLE 0x00000000U +#define ETH_WATCHDOG_DISABLE 0x00800000U /** * @} */ -/** @defgroup ETH_Jabber ETH Jabber +/** @defgroup ETH_Jabber ETH Jabber * @{ */ -#define ETH_JABBER_ENABLE ((uint32_t)0x00000000) -#define ETH_JABBER_DISABLE ((uint32_t)0x00400000) - +#define ETH_JABBER_ENABLE 0x00000000U +#define ETH_JABBER_DISABLE 0x00400000U /** * @} */ @@ -845,15 +917,14 @@ typedef struct /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap * @{ */ -#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ -#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ -#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ -#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ -#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ -#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ -#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ -#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ - +#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ +#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ +#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ +#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ +#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ +#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ +#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ +#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ /** * @} */ @@ -861,9 +932,8 @@ typedef struct /** @defgroup ETH_Carrier_Sense ETH Carrier Sense * @{ */ -#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000) -#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000) - +#define ETH_CARRIERSENCE_ENABLE 0x00000000U +#define ETH_CARRIERSENCE_DISABLE 0x00010000U /** * @} */ @@ -871,19 +941,17 @@ typedef struct /** @defgroup ETH_Receive_Own ETH Receive Own * @{ */ -#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000) -#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000) - +#define ETH_RECEIVEOWN_ENABLE 0x00000000U +#define ETH_RECEIVEOWN_DISABLE 0x00002000U /** * @} */ -/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode +/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode * @{ */ -#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000) -#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000) - +#define ETH_LOOPBACKMODE_ENABLE 0x00001000U +#define ETH_LOOPBACKMODE_DISABLE 0x00000000U /** * @} */ @@ -891,9 +959,8 @@ typedef struct /** @defgroup ETH_Checksum_Offload ETH Checksum Offload * @{ */ -#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400) -#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000) - +#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U +#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U /** * @} */ @@ -901,9 +968,8 @@ typedef struct /** @defgroup ETH_Retry_Transmission ETH Retry Transmission * @{ */ -#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000) -#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200) - +#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U +#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U /** * @} */ @@ -911,9 +977,8 @@ typedef struct /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip * @{ */ -#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080) -#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000) - +#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U +#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U /** * @} */ @@ -921,11 +986,10 @@ typedef struct /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit * @{ */ -#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000) -#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020) -#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040) -#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060) - +#define ETH_BACKOFFLIMIT_10 0x00000000U +#define ETH_BACKOFFLIMIT_8 0x00000020U +#define ETH_BACKOFFLIMIT_4 0x00000040U +#define ETH_BACKOFFLIMIT_1 0x00000060U /** * @} */ @@ -933,9 +997,8 @@ typedef struct /** @defgroup ETH_Deferral_Check ETH Deferral Check * @{ */ -#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010) -#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000) - +#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U +#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U /** * @} */ @@ -943,9 +1006,8 @@ typedef struct /** @defgroup ETH_Receive_All ETH Receive All * @{ */ -#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000) -#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000) - +#define ETH_RECEIVEALL_ENABLE 0x80000000U +#define ETH_RECEIVEAll_DISABLE 0x00000000U /** * @} */ @@ -953,10 +1015,9 @@ typedef struct /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter * @{ */ -#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200) -#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300) -#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000) - +#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U +#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U +#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U /** * @} */ @@ -964,10 +1025,9 @@ typedef struct /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames * @{ */ -#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ -#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ -#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ - +#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ +#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ /** * @} */ @@ -975,9 +1035,8 @@ typedef struct /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception * @{ */ -#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000) -#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020) - +#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U +#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U /** * @} */ @@ -985,9 +1044,8 @@ typedef struct /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter * @{ */ -#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000) -#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008) - +#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U +#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U /** * @} */ @@ -995,9 +1053,8 @@ typedef struct /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode * @{ */ -#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001) -#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000) - +#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U +#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U /** * @} */ @@ -1005,11 +1062,10 @@ typedef struct /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter * @{ */ -#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404) -#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004) -#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000) -#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010) - +#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U +#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U +#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U +#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U /** * @} */ @@ -1017,20 +1073,18 @@ typedef struct /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter * @{ */ -#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402) -#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002) -#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000) - +#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U +#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U +#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U /** * @} */ -/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause +/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause * @{ */ -#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000) -#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080) - +#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U +#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U /** * @} */ @@ -1038,11 +1092,10 @@ typedef struct /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold * @{ */ -#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ - +#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ /** * @} */ @@ -1050,9 +1103,8 @@ typedef struct /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect * @{ */ -#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008) -#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000) - +#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U +#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U /** * @} */ @@ -1060,9 +1112,8 @@ typedef struct /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control * @{ */ -#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004) -#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000) - +#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U +#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U /** * @} */ @@ -1070,9 +1121,8 @@ typedef struct /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control * @{ */ -#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002) -#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000) - +#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U +#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U /** * @} */ @@ -1080,9 +1130,8 @@ typedef struct /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison * @{ */ -#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000) -#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000) - +#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U +#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U /** * @} */ @@ -1090,34 +1139,32 @@ typedef struct /** @defgroup ETH_MAC_addresses ETH MAC addresses * @{ */ -#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000) -#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008) -#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010) -#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018) - +#define ETH_MAC_ADDRESS0 0x00000000U +#define ETH_MAC_ADDRESS1 0x00000008U +#define ETH_MAC_ADDRESS2 0x00000010U +#define ETH_MAC_ADDRESS3 0x00000018U /** * @} */ -/** @defgroup ETH_MAC_Addresses_Filter_SA_DA ETH MAC Addresses Filter SA DA +/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA * @{ */ -#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000) -#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008) +#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U +#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U /** * @} */ -/** @defgroup ETH_MAC_Addresses_Filter_Mask_Bytes ETH_MAC Addresses Filter Mask Bytes +/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes * @{ */ -#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ -#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ -#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ -#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ - +#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ /** * @} */ @@ -1125,19 +1172,17 @@ typedef struct /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame * @{ */ -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000) -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000) - +#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U +#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U /** * @} */ -/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward +/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward * @{ */ -#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000) -#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000) - +#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U +#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U /** * @} */ @@ -1145,9 +1190,8 @@ typedef struct /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame * @{ */ -#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000) -#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000) - +#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U +#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U /** * @} */ @@ -1155,9 +1199,8 @@ typedef struct /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward * @{ */ -#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000) -#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000) - +#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U +#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U /** * @} */ @@ -1165,15 +1208,14 @@ typedef struct /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control * @{ */ -#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ - +#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ /** * @} */ @@ -1181,9 +1223,8 @@ typedef struct /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames * @{ */ -#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080) -#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000) - +#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U +#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U /** * @} */ @@ -1191,9 +1232,8 @@ typedef struct /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames * @{ */ -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040) -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000) - +#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U +#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U /** * @} */ @@ -1201,11 +1241,10 @@ typedef struct /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control * @{ */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ - +#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ /** * @} */ @@ -1213,19 +1252,17 @@ typedef struct /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate * @{ */ -#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004) -#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000) - +#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U +#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U /** * @} */ -/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats +/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats * @{ */ -#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000) -#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000) - +#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U +#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U /** * @} */ @@ -1233,29 +1270,27 @@ typedef struct /** @defgroup ETH_Fixed_Burst ETH Fixed Burst * @{ */ -#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000) -#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000) - +#define ETH_FIXEDBURST_ENABLE 0x00010000U +#define ETH_FIXEDBURST_DISABLE 0x00000000U /** * @} */ -/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA_Burst Length +/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length * @{ */ -#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ -#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ -#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ - +#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ /** * @} */ @@ -1263,18 +1298,18 @@ typedef struct /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length * @{ */ -#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ -#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ -#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ /** * @} @@ -1283,44 +1318,40 @@ typedef struct /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration * @{ */ -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000) -#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002) - +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U +#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U /** * @} */ -/** @defgroup ETH_DMA_Tx_Descriptor_Segment ETH DMA Tx Descriptor Segment +/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment * @{ */ -#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */ -#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */ - +#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ +#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ /** * @} */ -/** @defgroup ETH_DMA_Tx_Descriptor_Checksum_Insertion_Control ETH DMA Tx Descriptor Checksum Insertion Control +/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control * @{ */ -#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */ -#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ - +#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ +#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ +#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ /** * @} */ -/** @defgroup ETH_DMA_Rx_Descriptor_Buffers ETH DMA Rx Descriptor Buffers +/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers * @{ */ -#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ -#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ - +#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ +#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ /** * @} */ @@ -1328,10 +1359,9 @@ typedef struct /** @defgroup ETH_PMT_Flags ETH PMT Flags * @{ */ -#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ -#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ - +#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ /** * @} */ @@ -1339,10 +1369,9 @@ typedef struct /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts * @{ */ -#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ - +#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ /** * @} */ @@ -1350,10 +1379,9 @@ typedef struct /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts * @{ */ -#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ -#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ - +#define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ /** * @} */ @@ -1361,12 +1389,11 @@ typedef struct /** @defgroup ETH_MAC_Flags ETH MAC Flags * @{ */ -#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ -#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ -#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ -#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ -#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ - +#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ +#define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ /** * @} */ @@ -1374,67 +1401,64 @@ typedef struct /** @defgroup ETH_DMA_Flags ETH DMA Flags * @{ */ -#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */ -#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ -#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ -#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ -#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ -#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ -#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ -#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ -#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ -#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ -#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ -#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */ -#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */ -#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ -#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ -#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ -#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ - +#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ +#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ +#define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ +#define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ +#define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ +#define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ /** * @} */ -/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts +/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts * @{ */ -#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ -#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ -#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ -#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ -#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ - +#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ +#define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ /** * @} */ -/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts +/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts * @{ */ -#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ -#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ -#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ -#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ -#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ -#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ -#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ -#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ -#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ -#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */ -#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */ -#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ -#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ -#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ -#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ - +#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ +#define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ +#define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ +#define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ +#define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ +#define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ +#define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ +#define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ +#define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ +#define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ /** * @} */ @@ -1442,12 +1466,12 @@ typedef struct /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state * @{ */ -#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ -#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ -#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */ -#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ -#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */ -#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ +#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ +#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ +#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ +#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ +#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ /** * @} @@ -1457,12 +1481,12 @@ typedef struct /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state * @{ */ -#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ -#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ -#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */ -#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */ -#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ -#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */ +#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ +#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ +#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ +#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ +#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ /** * @} @@ -1471,17 +1495,16 @@ typedef struct /** @defgroup ETH_DMA_overflow ETH DMA overflow * @{ */ -#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ -#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ - +#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ /** * @} */ - /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP +/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP * @{ */ -#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */ +#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ /** * @} @@ -1506,7 +1529,7 @@ typedef struct /** * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag of TDES0 to check . + * @param __FLAG__: specifies the flag of TDES0 to check. * @retval the ETH_DMATxDescFlag (SET or RESET). */ #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) @@ -1576,7 +1599,7 @@ typedef struct * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header * @retval None */ #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) @@ -1819,7 +1842,7 @@ typedef struct * @retval None */ #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ - (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) + (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while(0U) /** * @brief Enables the MMC Counter Freeze. @@ -1880,7 +1903,7 @@ typedef struct * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value * @retval None */ -#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF) +#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) /** * @brief Disables the specified ETHERNET MMC Rx interrupts. * @param __HANDLE__: ETH Handle. @@ -1891,7 +1914,7 @@ typedef struct * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value * @retval None */ -#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF) +#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) /** * @brief Enables the specified ETHERNET MMC Tx interrupts. * @param __HANDLE__: ETH Handle. @@ -1957,17 +1980,17 @@ typedef struct * @retval None */ #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP - + /** * @brief Disables the rising edge trigger to the ETH External interrupt line. * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) /** * @brief Enables falling edge trigger to the ETH External interrupt line. * @retval None - */ + */ #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) /** @@ -1975,27 +1998,22 @@ typedef struct * @retval None */ #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) - /** * @brief Enables rising/falling edge trigger to the ETH External interrupt line. * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() \ - do{ \ - EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ - EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ - } while(0) +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ + EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ + }while(0U) /** * @brief Disables rising/falling edge trigger to the ETH External interrupt line. * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() \ - do{ \ - EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - } while(0) +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ + EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ + }while(0U) /** * @brief Generate a Software interrupt on selected EXTI line. @@ -2006,7 +2024,6 @@ typedef struct /** * @} */ - /* Exported functions --------------------------------------------------------*/ /** @addtogroup ETH_Exported_Functions @@ -2018,7 +2035,6 @@ typedef struct /** @addtogroup ETH_Exported_Functions_Group1 * @{ */ - HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); @@ -2029,7 +2045,6 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /** * @} */ - /* IO operation functions ****************************************************/ /** @addtogroup ETH_Exported_Functions_Group2 @@ -2040,14 +2055,13 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); /* Communication with PHY functions*/ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); - /* Non-Blocking mode: Interrupt */ +/* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); - /* Callback in non blocking modes (Interrupt) */ +/* Callback in non blocking modes (Interrupt) */ void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); - /** * @} */ @@ -2057,6 +2071,7 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); /** @addtogroup ETH_Exported_Functions_Group3 * @{ */ + HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); @@ -2064,22 +2079,21 @@ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef /** * @} */ - + /* Peripheral State functions ************************************************/ /** @addtogroup ETH_Exported_Functions_Group4 * @{ */ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); - /** * @} */ - + /** * @} - */ - + */ + /** * @} */ @@ -2087,7 +2101,7 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); #endif /* STM32F107xC */ /** * @} - */ + */ #ifdef __cplusplus } @@ -2096,5 +2110,4 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); #endif /* __STM32F1xx_HAL_ETH_H */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c index 5a3330d2585..2bbb626f145 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_flash.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -41,7 +41,6 @@ (++) Lock and Unlock the FLASH interface (++) Erase function: Erase page, erase all pages (++) Program functions: half word, word and doubleword - (#) FLASH Option Bytes Programming functions: this group includes all needed functions to manage the Option Bytes: (++) Lock and Unlock the Option Bytes @@ -58,7 +57,7 @@ includes all needed functions to: (++) Handle FLASH interrupts (++) Wait for last FLASH operation according to its status - (++) Get error flag status + (++) Get error flag status [..] In addition to these function, this driver includes a set of macros allowing to handle the following operations: @@ -148,6 +147,7 @@ FLASH_ProcessTypeDef pFlash; */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); static void FLASH_SetErrorCode(void); +extern void FLASH_PageErase(uint32_t PageAddress); /** * @} */ @@ -201,13 +201,13 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); #if defined(FLASH_BANK2_END) } else { /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); } #endif /* FLASH_BANK2_END */ @@ -216,29 +216,29 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { /* Program halfword (16-bit) at a specified address. */ - nbiterations = 1; + nbiterations = 1U; } else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) { /* Program word (32-bit = 2*16-bit) at a specified address. */ - nbiterations = 2; + nbiterations = 2U; } else { /* Program double word (64-bit = 4*16-bit) at a specified address. */ - nbiterations = 4; + nbiterations = 4U; } - for (index = 0; index < nbiterations; index++) + for (index = 0U; index < nbiterations; index++) { - FLASH_Program_HalfWord((Address + (2*index)), (uint16_t)(Data >> (16*index))); + FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); #if defined(FLASH_BANK2_END) if(Address <= FLASH_BANK1_END) { #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); @@ -247,7 +247,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint else { /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperationBank2((uint32_t)FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperationBank2(FLASH_TIMEOUT_VALUE); /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); @@ -321,23 +321,23 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; - /*Program halfword (16-bit) at a specified address.*/ - pFlash.DataRemaining = 1; + /* Program halfword (16-bit) at a specified address. */ + pFlash.DataRemaining = 1U; } else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; - /*Program word (32-bit : 2*16-bit) at a specified address.*/ - pFlash.DataRemaining = 2; + /* Program word (32-bit : 2*16-bit) at a specified address. */ + pFlash.DataRemaining = 2U; } else { pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; - /*Program double word (64-bit : 4*16-bit) at a specified address.*/ - pFlash.DataRemaining = 4; + /* Program double word (64-bit : 4*16-bit) at a specified address. */ + pFlash.DataRemaining = 4U; } - /*Program halfword (16-bit) at a specified address.*/ + /* Program halfword (16-bit) at a specified address. */ FLASH_Program_HalfWord(Address, (uint16_t)Data); return status; @@ -349,7 +349,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u */ void HAL_FLASH_IRQHandler(void) { - uint32_t addresstmp = 0; + uint32_t addresstmp = 0U; /* Check FLASH operation error flags */ #if defined(FLASH_BANK2_END) @@ -359,18 +359,18 @@ void HAL_FLASH_IRQHandler(void) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) #endif /* FLASH_BANK2_END */ { - /*return the faulty address*/ + /* Return the faulty address */ addresstmp = pFlash.Address; /* Reset address */ - pFlash.Address = 0xFFFFFFFF; + pFlash.Address = 0xFFFFFFFFU; - /*Save the Error code*/ + /* Save the Error code */ FLASH_SetErrorCode(); /* FLASH error interrupt user callback */ HAL_FLASH_OperationErrorCallback(addresstmp); - /* Stop the procedure ongoing*/ + /* Stop the procedure ongoing */ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } @@ -395,11 +395,11 @@ void HAL_FLASH_IRQHandler(void) /* Nb of pages to erased can be decreased */ pFlash.DataRemaining--; - /* Check if there are still pages to erase*/ - if(pFlash.DataRemaining != 0) + /* Check if there are still pages to erase */ + if(pFlash.DataRemaining != 0U) { addresstmp = pFlash.Address; - /*Indicate user which sector has been erased*/ + /*Indicate user which sector has been erased */ HAL_FLASH_EndOfOperationCallback(addresstmp); /*Increment sector number*/ @@ -413,9 +413,9 @@ void HAL_FLASH_IRQHandler(void) } else { - /*No more pages to Erase, user callback can be called.*/ - /*Reset Sector and stop Erase pages procedure*/ - pFlash.Address = addresstmp = 0xFFFFFFFF; + /* No more pages to Erase, user callback can be called. */ + /* Reset Sector and stop Erase pages procedure */ + pFlash.Address = addresstmp = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* FLASH EOP interrupt user callback */ HAL_FLASH_EndOfOperationCallback(addresstmp); @@ -431,9 +431,9 @@ void HAL_FLASH_IRQHandler(void) if (HAL_IS_BIT_CLR(FLASH->CR2, FLASH_CR2_MER)) { #endif /* FLASH_BANK2_END */ - /* MassErase ended. Return the selected bank*/ + /* MassErase ended. Return the selected bank */ /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(0); + HAL_FLASH_EndOfOperationCallback(0U); /* Stop Mass Erase procedure*/ pFlash.ProcedureOnGoing = FLASH_PROC_NONE; @@ -447,14 +447,14 @@ void HAL_FLASH_IRQHandler(void) pFlash.DataRemaining--; /* Check if there are still 16-bit data to program */ - if(pFlash.DataRemaining != 0) + if(pFlash.DataRemaining != 0U) { /* Increment address to 16-bit */ - pFlash.Address += 2; + pFlash.Address += 2U; addresstmp = pFlash.Address; /* Shift to have next 16-bit data */ - pFlash.Data = (pFlash.Data >> 16); + pFlash.Data = (pFlash.Data >> 16U); /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); @@ -464,7 +464,7 @@ void HAL_FLASH_IRQHandler(void) } else { - /*Program ended. Return the selected address*/ + /* Program ended. Return the selected address */ /* FLASH EOP interrupt user callback */ if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) { @@ -472,15 +472,15 @@ void HAL_FLASH_IRQHandler(void) } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) { - HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2); + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); } else { - HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6); + HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); } - /* Reset Address and stop Program procedure*/ - pFlash.Address = 0xFFFFFFFF; + /* Reset Address and stop Program procedure */ + pFlash.Address = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } @@ -503,7 +503,7 @@ void HAL_FLASH_IRQHandler(void) pFlash.DataRemaining--; /* Check if there are still pages to erase*/ - if(pFlash.DataRemaining != 0) + if(pFlash.DataRemaining != 0U) { /* Indicate user which page address has been erased*/ HAL_FLASH_EndOfOperationCallback(pFlash.Address); @@ -522,7 +522,7 @@ void HAL_FLASH_IRQHandler(void) /*No more pages to Erase*/ /*Reset Address and stop Erase pages procedure*/ - pFlash.Address = 0xFFFFFFFF; + pFlash.Address = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; /* FLASH EOP interrupt user callback */ @@ -538,7 +538,7 @@ void HAL_FLASH_IRQHandler(void) { /* MassErase ended. Return the selected bank*/ /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(0); + HAL_FLASH_EndOfOperationCallback(0U); pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } @@ -549,14 +549,14 @@ void HAL_FLASH_IRQHandler(void) pFlash.DataRemaining--; /* Check if there are still 16-bit data to program */ - if(pFlash.DataRemaining != 0) + if(pFlash.DataRemaining != 0U) { /* Increment address to 16-bit */ - pFlash.Address += 2; + pFlash.Address += 2U; addresstmp = pFlash.Address; /* Shift to have next 16-bit data */ - pFlash.Data = (pFlash.Data >> 16); + pFlash.Data = (pFlash.Data >> 16U); /* Operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); @@ -574,15 +574,15 @@ void HAL_FLASH_IRQHandler(void) } else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) { - HAL_FLASH_EndOfOperationCallback(pFlash.Address-2); + HAL_FLASH_EndOfOperationCallback(pFlash.Address-2U); } else { - HAL_FLASH_EndOfOperationCallback(pFlash.Address-6); + HAL_FLASH_EndOfOperationCallback(pFlash.Address-6U); } /* Reset Address and stop Program procedure*/ - pFlash.Address = 0xFFFFFFFF; + pFlash.Address = 0xFFFFFFFFU; pFlash.ProcedureOnGoing = FLASH_PROC_NONE; } } @@ -612,7 +612,6 @@ void HAL_FLASH_IRQHandler(void) } } - /** * @brief FLASH end of operation interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure @@ -626,6 +625,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) { /* Prevent unused argument(s) compilation warning */ UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_EndOfOperationCallback could be implemented in the user file */ @@ -643,6 +643,7 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) { /* Prevent unused argument(s) compilation warning */ UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_FLASH_OperationErrorCallback could be implemented in the user file */ @@ -712,12 +713,11 @@ HAL_StatusTypeDef HAL_FLASH_Lock(void) #if defined(FLASH_BANK2_END) /* Set the LOCK Bit to lock the FLASH BANK2 Registers access */ SET_BIT(FLASH->CR2, FLASH_CR2_LOCK); -#endif /* FLASH_BANK2_END */ +#endif /* FLASH_BANK2_END */ return HAL_OK; } - /** * @brief Unlock the FLASH Option Control Registers access. * @retval HAL Status @@ -753,29 +753,27 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) /** * @brief Launch the option byte loading. * @note This function will reset automatically the MCU. - * @retval HAL_StatusTypeDef HAL Status + * @retval None */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +void HAL_FLASH_OB_Launch(void) { /* Initiates a system reset request to launch the option byte loading */ HAL_NVIC_SystemReset(); - - return HAL_OK; } /** * @} */ -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + * @brief Peripheral errors functions * @verbatim =============================================================================== - ##### Peripheral State functions ##### + ##### Peripheral Errors functions ##### =============================================================================== [..] - This subsection permit to get in run-time the status of the FLASH peripheral. + This subsection permit to get in run-time errors of the FLASH peripheral. @endverbatim * @{ @@ -783,13 +781,14 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) /** * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode: The returned value can be: + * @retval FLASH_ErrorCode The returned value can be: * @ref FLASH_Error_Codes */ uint32_t HAL_FLASH_GetError(void) -{ +{ return pFlash.ErrorCode; -} +} + /** * @} */ @@ -804,8 +803,8 @@ uint32_t HAL_FLASH_GetError(void) /** * @brief Program a half-word (16-bit) at a specified address. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. + * @param Address specify the address to be programmed. + * @param Data specify the data to be programmed. * @retval None */ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) @@ -834,8 +833,8 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) /** * @brief Wait for a FLASH operation to complete. - * @param Timeout: maximum flash operation timeout - * @retval HAL_StatusTypeDef HAL Status + * @param Timeout maximum flash operation timeout + * @retval HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { @@ -849,7 +848,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { return HAL_TIMEOUT; } @@ -872,14 +871,14 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) return HAL_ERROR; } - /* If there is no error flag set */ + /* There is no error flag set */ return HAL_OK; } #if defined(FLASH_BANK2_END) /** * @brief Wait for a FLASH BANK2 operation to complete. - * @param Timeout: maximum flash operation timeout + * @param Timeout maximum flash operation timeout * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) @@ -894,7 +893,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) { if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) { return HAL_TIMEOUT; } @@ -926,7 +925,9 @@ HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout) * @retval None */ static void FLASH_SetErrorCode(void) -{ +{ + uint32_t flags = 0U; + #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR_BANK2)) #else @@ -934,6 +935,11 @@ static void FLASH_SetErrorCode(void) #endif /* FLASH_BANK2_END */ { pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; +#if defined(FLASH_BANK2_END) + flags |= FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2; +#else + flags |= FLASH_FLAG_WRPERR; +#endif /* FLASH_BANK2_END */ } #if defined(FLASH_BANK2_END) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR) || __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR_BANK2)) @@ -941,21 +947,21 @@ static void FLASH_SetErrorCode(void) if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) #endif /* FLASH_BANK2_END */ { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; + pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; +#if defined(FLASH_BANK2_END) + flags |= FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2; +#else + flags |= FLASH_FLAG_PGERR; +#endif /* FLASH_BANK2_END */ } - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR); } /* Clear FLASH error pending bits */ -#if defined(FLASH_BANK2_END) - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGERR | FLASH_FLAG_PGERR_BANK2); -#else - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR); -#endif /* FLASH_BANK2_END */ + __HAL_FLASH_CLEAR_FLAG(flags); } /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.h index abb0fa4564c..3016b549591 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_flash.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of Flash HAL module. ****************************************************************************** * @attention @@ -57,7 +57,7 @@ /** @addtogroup FLASH_Private_Constants * @{ */ -#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */ +#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ /** * @} */ @@ -87,18 +87,17 @@ * @{ */ - /** * @brief FLASH Procedure structure definition */ typedef enum { - FLASH_PROC_NONE = 0, - FLASH_PROC_PAGEERASE = 1, - FLASH_PROC_MASSERASE = 2, - FLASH_PROC_PROGRAMHALFWORD = 3, - FLASH_PROC_PROGRAMWORD = 4, - FLASH_PROC_PROGRAMDOUBLEWORD = 5 + FLASH_PROC_NONE = 0U, + FLASH_PROC_PAGEERASE = 1U, + FLASH_PROC_MASSERASE = 2U, + FLASH_PROC_PROGRAMHALFWORD = 3U, + FLASH_PROC_PROGRAMWORD = 4U, + FLASH_PROC_PROGRAMDOUBLEWORD = 5U } FLASH_ProcedureTypeDef; /** @@ -133,10 +132,10 @@ typedef struct * @{ */ -#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_FLASH_ERROR_PROG ((uint32_t)0x01) /*!< Programming error */ -#define HAL_FLASH_ERROR_WRP ((uint32_t)0x02) /*!< Write protection error */ -#define HAL_FLASH_ERROR_OPTV ((uint32_t)0x04) /*!< Option validity error */ +#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ +#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ +#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ /** * @} @@ -145,9 +144,9 @@ typedef struct /** @defgroup FLASH_Type_Program FLASH Type Program * @{ */ -#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!PageAddress; @@ -290,7 +291,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) { /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFF; + *PageError = 0xFFFFFFFFU; /* Erase page by page to be done*/ for(address = pEraseInit->PageAddress; @@ -635,6 +636,10 @@ static void FLASH_MassErase(uint32_t Banks) else { #endif /* FLASH_BANK2_END */ +#if !defined(FLASH_BANK2_END) + /* Prevent unused argument(s) compilation warning */ + UNUSED(Banks); +#endif /* FLASH_BANK2_END */ /* Only bank1 will be erased*/ SET_BIT(FLASH->CR, FLASH_CR_MER); SET_BIT(FLASH->CR, FLASH_CR_STRT); @@ -681,26 +686,26 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP_PAGES0TO31MASK */ #if defined(OB_WRP_PAGES16TO31MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8); + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); #elif defined(OB_WRP_PAGES32TO63MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8); + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); #endif /* OB_WRP_PAGES32TO63MASK */ #if defined(OB_WRP_PAGES64TO95MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16); + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); #endif /* OB_WRP_PAGES64TO95MASK */ #if defined(OB_WRP_PAGES32TO47MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16); + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES96TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO255MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO511MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); #endif /* OB_WRP_PAGES96TO127MASK */ /* Wait for last operation to be completed */ @@ -719,7 +724,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(FLASH_WRP0_WRP0) - if(WRP0_Data != 0xFF) + if(WRP0_Data != 0xFFU) { OB->WRP0 &= WRP0_Data; @@ -729,7 +734,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) #endif /* FLASH_WRP0_WRP0 */ #if defined(FLASH_WRP1_WRP1) - if((status == HAL_OK) && (WRP1_Data != 0xFF)) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) { OB->WRP1 &= WRP1_Data; @@ -739,7 +744,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) #endif /* FLASH_WRP1_WRP1 */ #if defined(FLASH_WRP2_WRP2) - if((status == HAL_OK) && (WRP2_Data != 0xFF)) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) { OB->WRP2 &= WRP2_Data; @@ -749,7 +754,7 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) #endif /* FLASH_WRP2_WRP2 */ #if defined(FLASH_WRP3_WRP3) - if((status == HAL_OK) && (WRP3_Data != 0xFF)) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) { OB->WRP3 &= WRP3_Data; @@ -804,26 +809,26 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #endif /* OB_WRP_PAGES0TO31MASK */ #if defined(OB_WRP_PAGES16TO31MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8); + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); #elif defined(OB_WRP_PAGES32TO63MASK) - WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8); + WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO63MASK) >> 8U); #endif /* OB_WRP_PAGES32TO63MASK */ #if defined(OB_WRP_PAGES64TO95MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16); + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES64TO95MASK) >> 16U); #endif /* OB_WRP_PAGES64TO95MASK */ #if defined(OB_WRP_PAGES32TO47MASK) - WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16); + WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); #endif /* OB_WRP_PAGES32TO47MASK */ #if defined(OB_WRP_PAGES96TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES96TO127MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO255MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO511MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO511MASK) >> 24U); #elif defined(OB_WRP_PAGES48TO127MASK) - WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24); + WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); #endif /* OB_WRP_PAGES96TO127MASK */ @@ -842,7 +847,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(FLASH_WRP0_WRP0) - if(WRP0_Data != 0xFF) + if(WRP0_Data != 0xFFU) { OB->WRP0 |= WRP0_Data; @@ -852,7 +857,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #endif /* FLASH_WRP0_WRP0 */ #if defined(FLASH_WRP1_WRP1) - if((status == HAL_OK) && (WRP1_Data != 0xFF)) + if((status == HAL_OK) && (WRP1_Data != 0xFFU)) { OB->WRP1 |= WRP1_Data; @@ -862,7 +867,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #endif /* FLASH_WRP1_WRP1 */ #if defined(FLASH_WRP2_WRP2) - if((status == HAL_OK) && (WRP2_Data != 0xFF)) + if((status == HAL_OK) && (WRP2_Data != 0xFFU)) { OB->WRP2 |= WRP2_Data; @@ -872,7 +877,7 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) #endif /* FLASH_WRP2_WRP2 */ #if defined(FLASH_WRP3_WRP3) - if((status == HAL_OK) && (WRP3_Data != 0xFF)) + if((status == HAL_OK) && (WRP3_Data != 0xFFU)) { OB->WRP3 |= WRP3_Data; @@ -971,9 +976,9 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) SET_BIT(FLASH->CR, FLASH_CR_OPTPG); #if defined(FLASH_BANK2_END) - OB->USER = (UserConfig | 0xF0); + OB->USER = (UserConfig | 0xF0U); #else - OB->USER = (UserConfig | 0x88); + OB->USER = (UserConfig | 0x88U); #endif /* FLASH_BANK2_END */ /* Wait for last operation to be completed */ @@ -1039,7 +1044,7 @@ static uint32_t FLASH_OB_GetWRP(void) /** * @brief Returns the FLASH Read Protection level. - * @retval FLASH ReadOut Protection Status: + * @retval FLASH RDP level * This parameter can be one of the following values: * @arg @ref OB_RDP_LEVEL_0 No protection * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory @@ -1047,7 +1052,7 @@ static uint32_t FLASH_OB_GetWRP(void) static uint32_t FLASH_OB_GetRDP(void) { uint32_t readstatus = OB_RDP_LEVEL_0; - uint32_t tmp_reg = 0; + uint32_t tmp_reg = 0U; /* Read RDP level bits */ tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.h index a77c2a82ffc..9dd06f54b23 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of Flash HAL Extended module. ****************************************************************************** * @attention @@ -58,9 +58,9 @@ * @{ */ -#define FLASH_SIZE_DATA_REGISTER ((uint32_t)0x1FFFF7E0) -#define OBR_REG_INDEX ((uint32_t)1) -#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP)) +#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U +#define OBR_REG_INDEX 1U +#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP)) /** * @} @@ -74,7 +74,7 @@ #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))) -#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) +#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE)) #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1)) @@ -92,39 +92,39 @@ /* Low Density */ #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \ - ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU)) #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ /* Medium Density */ #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFF) : \ - ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFF)))) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU)))) #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ /* High Density */ #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFF) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFF) : \ - ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF))) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU))) #endif /* STM32F100xE || STM32F101xE || STM32F103xE */ /* XL Density */ #if defined(FLASH_BANK2_END) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFF) : \ - ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFF)) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU)) #endif /* FLASH_BANK2_END */ /* Connectivity Line */ #if (defined(STM32F105xC) || defined(STM32F107xC)) -#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFF) : \ - (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFF) : \ - ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFF))) +#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \ + (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \ + ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU))) #endif /* STM32F105xC || STM32F107xC */ -#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U)) #if defined(FLASH_BANK2_END) #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ @@ -136,40 +136,40 @@ /* Low Density */ #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \ - ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFF))) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU))) #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ /* Medium Density */ #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \ - ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40) ? \ - ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20) ? \ - ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFF))))) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \ + ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \ + ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU))))) #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/ /* High Density */ #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200) ? \ - ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180) ? \ - ((ADDRESS) <= 0x0805FFFF) : ((ADDRESS) <= 0x0803FFFF)))) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \ + ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU)))) #endif /* STM32F100xE || STM32F101xE || STM32F103xE */ /* XL Density */ #if defined(FLASH_BANK2_END) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400) ? \ - ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFF))) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \ + ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU))) #endif /* FLASH_BANK2_END */ /* Connectivity Line */ #if (defined(STM32F105xC) || defined(STM32F107xC)) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100) ? \ - ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80) ? \ - ((ADDRESS) <= 0x0801FFFF) : ((ADDRESS) <= 0x0800FFFF)))) +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \ + ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \ + ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU)))) #endif /* STM32F105xC || STM32F107xC */ @@ -258,12 +258,12 @@ typedef struct * @{ */ #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)) -#define FLASH_PAGE_SIZE ((uint32_t)0x400) +#define FLASH_PAGE_SIZE 0x400U #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */ /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)) -#define FLASH_PAGE_SIZE ((uint32_t)0x800) +#define FLASH_PAGE_SIZE 0x800U #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */ /* STM32F101xG || STM32F103xG */ /* STM32F105xC || STM32F107xC */ @@ -275,8 +275,8 @@ typedef struct /** @defgroup FLASHEx_Type_Erase Type Erase * @{ */ -#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00) /*!CR, ((__INTERRUPT__) & 0x0000FFFF)); \ + SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ /* Enable Bank2 IT */ \ - SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16)); \ - } while(0) + SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ + } while(0U) /** * @brief Disable the specified FLASH interrupt. @@ -629,10 +629,10 @@ typedef struct */ #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \ /* Disable Bank1 IT */ \ - CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFF)); \ + CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \ /* Disable Bank2 IT */ \ - CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16)); \ - } while(0) + CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \ + } while(0U) /** * @brief Get the specified FLASH flag status. @@ -653,7 +653,7 @@ typedef struct (FLASH->OBR & FLASH_OBR_OPTERR) : \ ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \ (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \ - (FLASH->SR2 & ((__FLAG__) >> 16)))) + (FLASH->SR2 & ((__FLAG__) >> 16U)))) /** * @brief Clear the specified FLASH flag. @@ -683,12 +683,12 @@ typedef struct FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \ } \ /* Clear Flag in Bank2 */ \ - if (((__FLAG__) >> 16) != RESET) \ + if (((__FLAG__) >> 16U) != RESET) \ { \ - FLASH->SR2 = ((__FLAG__) >> 16); \ + FLASH->SR2 = ((__FLAG__) >> 16U); \ } \ } \ - } while(0) + } while(0U) #else /** * @brief Enable the specified FLASH interrupt. @@ -744,7 +744,7 @@ typedef struct /* Clear Flag in Bank1 */ \ FLASH->SR = (__FLAG__); \ } \ - } while(0) + } while(0U) #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.c index 0a920f194b1..1d09efbfb30 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.c @@ -2,18 +2,18 @@ ****************************************************************************** * @file stm32f1xx_hal_gpio.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + * @verbatim ============================================================================== ##### GPIO Peripheral features ##### - ============================================================================== + ============================================================================== [..] Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software @@ -50,7 +50,7 @@ ##### How to use this driver ##### ============================================================================== - [..] + [..] (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE(). (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). @@ -135,48 +135,47 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Constants GPIO Private Constants +/** @addtogroup GPIO_Private_Constants GPIO Private Constants * @{ */ - -#define GPIO_MODE ((uint32_t)0x00000003) -#define EXTI_MODE ((uint32_t)0x10000000) -#define GPIO_MODE_IT ((uint32_t)0x00010000) -#define GPIO_MODE_EVT ((uint32_t)0x00020000) -#define RISING_EDGE ((uint32_t)0x00100000) -#define FALLING_EDGE ((uint32_t)0x00200000) -#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010) -#define GPIO_NUMBER ((uint32_t)16) +#define GPIO_MODE 0x00000003U +#define EXTI_MODE 0x10000000U +#define GPIO_MODE_IT 0x00010000U +#define GPIO_MODE_EVT 0x00020000U +#define RISING_EDGE 0x00100000U +#define FALLING_EDGE 0x00200000U +#define GPIO_OUTPUT_TYPE 0x00000010U + +#define GPIO_NUMBER 16U /* Definitions for bit manipulation of CRL and CRH register */ -#define GPIO_CR_MODE_INPUT ((uint32_t)0x00000000) /*!< 00: Input mode (reset state) */ -#define GPIO_CR_CNF_ANALOG ((uint32_t)0x00000000) /*!< 00: Analog mode */ -#define GPIO_CR_CNF_INPUT_FLOATING ((uint32_t)0x00000004) /*!< 01: Floating input (reset state) */ -#define GPIO_CR_CNF_INPUT_PU_PD ((uint32_t)0x00000008) /*!< 10: Input with pull-up / pull-down */ -#define GPIO_CR_CNF_GP_OUTPUT_PP ((uint32_t)0x00000000) /*!< 00: General purpose output push-pull */ -#define GPIO_CR_CNF_GP_OUTPUT_OD ((uint32_t)0x00000004) /*!< 01: General purpose output Open-drain */ -#define GPIO_CR_CNF_AF_OUTPUT_PP ((uint32_t)0x00000008) /*!< 10: Alternate function output Push-pull */ -#define GPIO_CR_CNF_AF_OUTPUT_OD ((uint32_t)0x0000000C) /*!< 11: Alternate function output Open-drain */ +#define GPIO_CR_MODE_INPUT 0x00000000U /*!< 00: Input mode (reset state) */ +#define GPIO_CR_CNF_ANALOG 0x00000000U /*!< 00: Analog mode */ +#define GPIO_CR_CNF_INPUT_FLOATING 0x00000004U /*!< 01: Floating input (reset state) */ +#define GPIO_CR_CNF_INPUT_PU_PD 0x00000008U /*!< 10: Input with pull-up / pull-down */ +#define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000U /*!< 00: General purpose output push-pull */ +#define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004U /*!< 01: General purpose output Open-drain */ +#define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008U /*!< 10: Alternate function output Push-pull */ +#define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000CU /*!< 11: Alternate function output Open-drain */ /** * @} */ - /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ - +/* Exported functions --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Functions GPIO Exported Functions * @{ */ -/** @defgroup GPIO_Exported_Functions_Group1 Initialization and deinitialization functions +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== - ##### Initialization and deinitialization functions ##### + ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to initialize and de-initialize the GPIOs @@ -186,6 +185,7 @@ * @{ */ + /** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral @@ -196,12 +196,12 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { uint32_t position; - uint32_t ioposition = 0x00; - uint32_t iocurrent = 0x00; - uint32_t temp = 0x00; - uint32_t config = 0x00; + uint32_t ioposition = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t temp = 0x00U; + uint32_t config = 0x00U; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ - uint32_t registeroffset = 0; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ + uint32_t registeroffset = 0U; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */ /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); @@ -209,10 +209,10 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ - for (position = 0; position < GPIO_NUMBER; position++) + for (position = 0U; position < GPIO_NUMBER; position++) { /* Get the IO position */ - ioposition = ((uint32_t)0x01) << position; + ioposition = (0x01U << position); /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; @@ -296,7 +296,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register*/ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; - registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2); + registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U); /* Apply the new configuration of the pin to the register */ MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset)); @@ -307,10 +307,10 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { /* Enable AFIO Clock */ __HAL_RCC_AFIO_CLK_ENABLE(); - temp = AFIO->EXTICR[position >> 2]; - CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03))); - SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); - AFIO->EXTICR[position >> 2] = temp; + temp = AFIO->EXTICR[position >> 2U]; + CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U))); + SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + AFIO->EXTICR[position >> 2U] = temp; /* Configure the interrupt mask */ @@ -366,21 +366,21 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t tmp = 0x00; + uint32_t position = 0x00U; + uint32_t iocurrent = 0x00U; + uint32_t tmp = 0x00U; __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */ - uint32_t registeroffset = 0; + uint32_t registeroffset = 0U; /* Check the parameters */ assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); /* Configure the port pins */ - while ((GPIO_Pin >> position) != 0) + while ((GPIO_Pin >> position) != 0U) { /* Get current io position */ - iocurrent = (GPIO_Pin) & ((uint32_t)1 << position); + iocurrent = (GPIO_Pin) & (1U << position); if (iocurrent) { @@ -388,7 +388,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Check if the current bit belongs to first half or last half of the pin count number in order to address CRH or CRL register */ configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH; - registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2); + registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U); /* CRL/CRH default value is floating input(0x04) shifted to correct position */ MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset); @@ -399,12 +399,12 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ - tmp = AFIO->EXTICR[position >> 2]; - tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); - if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) + tmp = AFIO->EXTICR[position >> 2U]; + tmp &= 0x0FU << (4U * (position & 0x03U)); + if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) { - tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - CLEAR_BIT(AFIO->EXTICR[position >> 2], tmp); + tmp = 0x0FU << (4U * (position & 0x03U)); + CLEAR_BIT(AFIO->EXTICR[position >> 2U], tmp); /* Clear EXTI line configuration */ CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); @@ -425,9 +425,9 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) */ /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief GPIO Read and Write + * @brief GPIO Read and Write * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @@ -437,6 +437,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) @endverbatim * @{ */ + /** * @brief Reads the specified input port pin. * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral @@ -490,7 +491,7 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin } else { - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } @@ -548,39 +549,38 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) } /** - * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin: Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { /* EXTI line interrupt detected */ - if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) - { + if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); HAL_GPIO_EXTI_Callback(GPIO_Pin); } } /** - * @brief EXTI line detection callback - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @brief EXTI line detection callbacks. + * @param GPIO_Pin: Specifies the pins connected EXTI line * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { /* Prevent unused argument(s) compilation warning */ UNUSED(GPIO_Pin); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Callback could be implemented in the user file - */ + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ } /** * @} */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.h index 1178290a5eb..ca9251d0864 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_gpio.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention @@ -57,10 +57,10 @@ /* Exported types ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Types GPIO Exported Types * @{ - */ + */ /** - * @brief GPIO Init structure definition + * @brief GPIO Init structure definition */ typedef struct { @@ -69,28 +69,26 @@ typedef struct uint32_t Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIO_mode_define */ - + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. This parameter can be a value of @ref GPIO_pull_define */ - + uint32_t Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIO_speed_define */ }GPIO_InitTypeDef; - + /** * @brief GPIO Bit SET and Bit RESET enumeration */ typedef enum -{ - GPIO_PIN_RESET = 0, +{ + GPIO_PIN_RESET = 0U, GPIO_PIN_SET }GPIO_PinState; - /** * @} */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Constants GPIO Exported Constants @@ -99,7 +97,7 @@ typedef enum /** @defgroup GPIO_pins_define GPIO pins define * @{ - */ + */ #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ @@ -118,12 +116,11 @@ typedef enum #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ +#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */ /** * @} - */ + */ - /** @defgroup GPIO_mode_define GPIO mode define * @brief GPIO Configuration Mode * Elements values convention: 0xX0yz00YZ @@ -134,32 +131,31 @@ typedef enum * - Z : IO Direction mode (Input, Output, Alternate or Analog) * @{ */ -#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */ #define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */ -#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */ +#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */ -#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} */ - - -/** @defgroup GPIO_speed_define GPIO speed define + +/** @defgroup GPIO_speed_define GPIO speed define * @brief GPIO Output Maximum frequency * @{ - */ + */ #define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */ #define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */ #define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */ @@ -168,15 +164,13 @@ typedef enum * @} */ - /** @defgroup GPIO_pull_define GPIO pull define * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ -#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ -#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ - +#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ /** * @} */ @@ -185,40 +179,6 @@ typedef enum * @} */ - -/* Private macros --------------------------------------------------------*/ -/** @addtogroup GPIO_Private_Macros - * @{ - */ - -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) - -#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00) - -#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ - ((PULL) == GPIO_PULLDOWN)) - -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \ - ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ - ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ - ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ - ((MODE) == GPIO_MODE_AF_PP) ||\ - ((MODE) == GPIO_MODE_AF_OD) ||\ - ((MODE) == GPIO_MODE_IT_RISING) ||\ - ((MODE) == GPIO_MODE_IT_FALLING) ||\ - ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING) ||\ - ((MODE) == GPIO_MODE_EVT_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_ANALOG)) - -/** - * @} - */ - - /* Exported macro ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Macros GPIO Exported Macros * @{ @@ -230,8 +190,8 @@ typedef enum * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + /** * @brief Clears the EXTI's line pending flags. * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. @@ -246,8 +206,8 @@ typedef enum * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + /** * @brief Clears the EXTI's line pending bits. * @param __EXTI_LINE__: specifies the EXTI lines to clear. @@ -263,18 +223,14 @@ typedef enum * @retval None */ #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) - -/* Include GPIO HAL Extension module */ -#include "stm32f1xx_hal_gpio_ex.h" - /** * @} */ +/* Include GPIO HAL Extension module */ +#include "stm32f1xx_hal_gpio_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization functions *******************************/ +/* Exported functions --------------------------------------------------------*/ /** @addtogroup GPIO_Exported_Functions * @{ */ @@ -282,38 +238,84 @@ typedef enum /** @addtogroup GPIO_Exported_Functions_Group1 * @{ */ +/* Initialization and de-initialization functions *****************************/ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** * @} */ -/* IO operation functions *******************************************************/ /** @addtogroup GPIO_Exported_Functions_Group2 * @{ */ +/* IO operation functions *****************************************************/ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + /** * @} - */ + */ /** * @} */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ /** * @} - */ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \ + ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH)) +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ /** * @} */ +/** + * @} + */ #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.c index ea3fc90b4a2..cc269d2d658 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_gpio_ex.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief GPIO Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) extension peripheral. diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.h index e2f3479d864..67b3a8cef83 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention @@ -197,70 +197,89 @@ * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) * @retval None */ -#define __HAL_AFIO_REMAP_USART3_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) - +#define __HAL_AFIO_REMAP_USART3_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP); \ + }while(0U) /** * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) * @retval None */ -#define __HAL_AFIO_REMAP_USART3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_PARTIALREMAP) +#define __HAL_AFIO_REMAP_USART3_PARTIAL() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP); \ + }while(0U) /** * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) * @retval None */ -#define __HAL_AFIO_REMAP_USART3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_NOREMAP) +#define __HAL_AFIO_REMAP_USART3_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP); \ + }while(0U) /** * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) * @retval None */ -#define __HAL_AFIO_REMAP_TIM1_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) +#define __HAL_AFIO_REMAP_TIM1_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP); \ + }while(0U) /** * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) * @retval None */ -#define __HAL_AFIO_REMAP_TIM1_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP) +#define __HAL_AFIO_REMAP_TIM1_PARTIAL() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP); \ + }while(0U) /** * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) * @retval None */ -#define __HAL_AFIO_REMAP_TIM1_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_NOREMAP) +#define __HAL_AFIO_REMAP_TIM1_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP); \ + }while(0U) /** * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) * @retval None */ -#define __HAL_AFIO_REMAP_TIM2_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) +#define __HAL_AFIO_REMAP_TIM2_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP); \ + }while(0U) /** * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) * @retval None */ -#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2) +#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2); \ + }while(0U) /** * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) * @retval None */ -#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1) +#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1); \ + }while(0U) /** * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) * @retval None */ -#define __HAL_AFIO_REMAP_TIM2_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_NOREMAP) +#define __HAL_AFIO_REMAP_TIM2_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP); \ + }while(0U) /** * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 @@ -268,7 +287,9 @@ * @note TIM3_ETR on PE0 is not re-mapped. * @retval None */ -#define __HAL_AFIO_REMAP_TIM3_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) +#define __HAL_AFIO_REMAP_TIM3_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP); \ + }while(0U) /** * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 @@ -276,7 +297,9 @@ * @note TIM3_ETR on PE0 is not re-mapped. * @retval None */ -#define __HAL_AFIO_REMAP_TIM3_PARTIAL() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP) +#define __HAL_AFIO_REMAP_TIM3_PARTIAL() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP); \ + }while(0U) /** * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 @@ -284,7 +307,9 @@ * @note TIM3_ETR on PE0 is not re-mapped. * @retval None */ -#define __HAL_AFIO_REMAP_TIM3_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_NOREMAP) +#define __HAL_AFIO_REMAP_TIM3_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP); \ + }while(0U) /** * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. @@ -309,21 +334,27 @@ * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 * @retval None */ -#define __HAL_AFIO_REMAP_CAN1_1() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP1) +#define __HAL_AFIO_REMAP_CAN1_1() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1); \ + }while(0U) /** * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) * @retval None */ -#define __HAL_AFIO_REMAP_CAN1_2() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP2) +#define __HAL_AFIO_REMAP_CAN1_2() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2); \ + }while(0U) /** * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 * @retval None */ -#define __HAL_AFIO_REMAP_CAN1_3() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP3) +#define __HAL_AFIO_REMAP_CAN1_3() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3); \ + }while(0U) #endif /** @@ -486,28 +517,36 @@ * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State * @retval None */ -#define __HAL_AFIO_REMAP_SWJ_ENABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET) +#define __HAL_AFIO_REMAP_SWJ_ENABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET); \ + }while(0U) /** * @brief Enable the Serial wire JTAG configuration * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST * @retval None */ -#define __HAL_AFIO_REMAP_SWJ_NONJTRST() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST) +#define __HAL_AFIO_REMAP_SWJ_NONJTRST() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST); \ + }while(0U) /** * @brief Enable the Serial wire JTAG configuration * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled * @retval None */ -#define __HAL_AFIO_REMAP_SWJ_NOJTAG() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE) +#define __HAL_AFIO_REMAP_SWJ_NOJTAG() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); \ + }while(0U) /** * @brief Disable the Serial wire JTAG configuration * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled * @retval None */ -#define __HAL_AFIO_REMAP_SWJ_DISABLE() MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE) +#define __HAL_AFIO_REMAP_SWJ_DISABLE() do{ CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG); \ + SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE); \ + }while(0U) #if defined(AFIO_MAPR_SPI3_REMAP) diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.c index cd05ea59ee2..7328bd214ab 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_hcd.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief HCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -149,7 +149,7 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) /* Disable the Interrupts */ __HAL_HCD_DISABLE(hhcd); - /*Init the Core (common init.) */ + /* Init the Core (common init.) */ USB_CoreInit(hhcd->Instance, hhcd->Init); /* Force Host Mode*/ @@ -202,8 +202,8 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].max_packet = mps; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].ep_type = ep_type; - hhcd->hc[ch_num].ep_num = epnum & 0x7F; - hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80); + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80U) == 0x80U); hhcd->hc[ch_num].speed = speed; status = USB_HC_Init(hhcd->Instance, @@ -253,7 +253,7 @@ HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) /* DeInit the low level hardware */ HAL_HCD_MspDeInit(hhcd); - __HAL_HCD_DISABLE(hhcd); + __HAL_HCD_DISABLE(hhcd); hhcd->State = HAL_HCD_STATE_RESET; @@ -292,7 +292,7 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) * @} */ -/** @defgroup HCD_Exported_Functions_Group2 IO operation functions +/** @defgroup HCD_Exported_Functions_Group2 IO operation functions * @brief HCD IO operation functions * @verbatim @@ -332,7 +332,7 @@ __weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) */ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, - uint8_t direction , + uint8_t direction, uint8_t ep_type, uint8_t token, uint8_t* pbuff, @@ -342,7 +342,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].ep_is_in = direction; hhcd->hc[ch_num].ep_type = ep_type; - if(token == 0) + if(token == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_SETUP; } @@ -355,21 +355,21 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, switch(ep_type) { case EP_TYPE_CTRL: - if((token == 1) && (direction == 0)) /*send data */ + if((token == 1U) && (direction == 0U)) /*send data */ { - if ( length == 0 ) + if (length == 0U) { /* For Status OUT stage, Length==0, Status Out PID = 1 */ - hhcd->hc[ch_num].toggle_out = 1; + hhcd->hc[ch_num].toggle_out = 1U; } /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) + if ( hhcd->hc[ch_num].toggle_out == 0U) { /* Put the PID 0 */ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } else { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; } if(hhcd->hc[ch_num].urb_state != URB_NOTREADY) { @@ -379,16 +379,16 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, break; case EP_TYPE_BULK: - if(direction == 0) + if(direction == 0U) { /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) + if ( hhcd->hc[ch_num].toggle_out == 0U) { /* Put the PID 0 */ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } else { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; } if(hhcd->hc[ch_num].urb_state != URB_NOTREADY) { @@ -397,7 +397,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, } else { - if( hhcd->hc[ch_num].toggle_in == 0) + if( hhcd->hc[ch_num].toggle_in == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } @@ -409,21 +409,21 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, break; case EP_TYPE_INTR: - if(direction == 0) + if(direction == 0U) { /* Set the Data Toggle bit as per the Flag */ - if ( hhcd->hc[ch_num].toggle_out == 0) + if ( hhcd->hc[ch_num].toggle_out == 0U) { /* Put the PID 0 */ hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } else { /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ; + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; } } else { - if( hhcd->hc[ch_num].toggle_in == 0) + if( hhcd->hc[ch_num].toggle_in == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_DATA0; } @@ -441,8 +441,8 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, hhcd->hc[ch_num].xfer_buff = pbuff; hhcd->hc[ch_num].xfer_len = length; - hhcd->hc[ch_num].urb_state = URB_IDLE; - hhcd->hc[ch_num].xfer_count = 0 ; + hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].xfer_count = 0U; hhcd->hc[ch_num].ch_num = ch_num; hhcd->hc[ch_num].state = HC_IDLE; @@ -450,7 +450,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, } /** - * @brief This function handles HCD interrupt request. + * @brief handle HCD interrupt request. * @param hhcd: HCD handle * @retval None */ @@ -458,12 +458,12 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t index = 0 , interrupt = 0; - + uint32_t index = 0U, interrupt = 0U; + /* ensure that we are in device mode */ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) { - /* avoid spurious interrupt */ + /* Avoid spurious interrupt */ if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) { return; @@ -471,25 +471,25 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); } if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); } if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) { - /* incorrect mode, acknowledge the interrupt */ + /* Incorrect mode, acknowledge the interrupt */ __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); } @@ -503,7 +503,7 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /* Handle Host Port Interrupts */ HAL_HCD_Disconnect_Callback(hhcd); - USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ ); + USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ); __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); } @@ -524,7 +524,7 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) { interrupt = USB_HC_ReadInterrupt(hhcd->Instance); - for (index = 0; index < hhcd->Init.Host_channels ; index++) + for (index = 0U; index < hhcd->Init.Host_channels ; index++) { if (interrupt & (1 << index)) { @@ -550,7 +550,6 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); } - } } @@ -583,7 +582,7 @@ __weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) } /** - * @brief Disonnexion Event callback. + * @brief Disonnection Event callback. * @param hhcd: HCD handle * @retval None */ @@ -608,7 +607,7 @@ __weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) * URB_NOTREADY/ * URB_NYET/ * URB_ERROR/ - * URB_STALL/ + * URB_STALL/ * @retval None */ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) @@ -650,7 +649,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) { __HAL_LOCK(hhcd); __HAL_HCD_ENABLE(hhcd); - USB_DriveVbus(hhcd->Instance, 1); + USB_DriveVbus(hhcd->Instance, 1U); __HAL_UNLOCK(hhcd); return HAL_OK; } @@ -699,7 +698,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) */ /** - * @brief Return the HCD state + * @brief Return the HCD handle state * @param hhcd: HCD handle * @retval HAL state */ @@ -802,7 +801,7 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) { @@ -841,7 +840,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) { hhcd->hc[chnum].state = HC_XFRC; - hhcd->hc[chnum].ErrCnt = 0; + hhcd->hc[chnum].ErrCnt = 0U; __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| @@ -858,7 +857,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[chnum].urb_state = URB_DONE; HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); } - hhcd->hc[chnum].toggle_in ^= 1; + hhcd->hc[chnum].toggle_in ^= 1U; } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH) @@ -876,9 +875,9 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) else if((hhcd->hc[chnum].state == HC_XACTERR) || (hhcd->hc[chnum].state == HC_DATATGLERR)) { - if(hhcd->hc[chnum].ErrCnt++ > 3) + if(hhcd->hc[chnum].ErrCnt++ > 3U) { - hhcd->hc[chnum].ErrCnt = 0; + hhcd->hc[chnum].ErrCnt = 0U; hhcd->hc[chnum].urb_state = URB_ERROR; } else @@ -935,7 +934,7 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR) { @@ -946,7 +945,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) { __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - if( hhcd->hc[chnum].do_ping == 1) + if( hhcd->hc[chnum].do_ping == 1U) { hhcd->hc[chnum].state = HC_NYET; __HAL_HCD_UNMASK_HALT_HC_INT(chnum); @@ -958,7 +957,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET) { hhcd->hc[chnum].state = HC_NYET; - hhcd->hc[chnum].ErrCnt= 0; + hhcd->hc[chnum].ErrCnt= 0U; __HAL_HCD_UNMASK_HALT_HC_INT(chnum); USB_HC_Halt(hhcd->Instance, chnum); __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); @@ -974,7 +973,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC) { - hhcd->hc[chnum].ErrCnt = 0; + hhcd->hc[chnum].ErrCnt = 0U; __HAL_HCD_UNMASK_HALT_HC_INT(chnum); USB_HC_Halt(hhcd->Instance, chnum); __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); @@ -989,7 +988,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK) { - hhcd->hc[chnum].ErrCnt = 0; + hhcd->hc[chnum].ErrCnt = 0U; __HAL_HCD_UNMASK_HALT_HC_INT(chnum); USB_HC_Halt(hhcd->Instance, chnum); hhcd->hc[chnum].state = HC_NAK; @@ -1019,7 +1018,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[chnum].urb_state = URB_DONE; if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK) { - hhcd->hc[chnum].toggle_out ^= 1; + hhcd->hc[chnum].toggle_out ^= 1U; } } else if (hhcd->hc[chnum].state == HC_NAK) @@ -1029,7 +1028,7 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) else if (hhcd->hc[chnum].state == HC_NYET) { hhcd->hc[chnum].urb_state = URB_NOTREADY; - hhcd->hc[chnum].do_ping = 0; + hhcd->hc[chnum].do_ping = 0U; } else if (hhcd->hc[chnum].state == HC_STALL) { @@ -1038,9 +1037,9 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) else if((hhcd->hc[chnum].state == HC_XACTERR) || (hhcd->hc[chnum].state == HC_DATATGLERR)) { - if(hhcd->hc[chnum].ErrCnt++ > 3) + if(hhcd->hc[chnum].ErrCnt++ > 3U) { - hhcd->hc[chnum].ErrCnt = 0; + hhcd->hc[chnum].ErrCnt = 0U; hhcd->hc[chnum].urb_state = URB_ERROR; } else @@ -1068,22 +1067,22 @@ static void HCD_HC_OUT_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint8_t channelnum =0; + uint8_t channelnum =0U; uint32_t pktsts; uint32_t pktcnt; - uint32_t temp = 0; - uint32_t tmpreg = 0; + uint32_t temp = 0U; + uint32_t tmpreg = 0U; temp = hhcd->Instance->GRXSTSP; channelnum = temp & USB_OTG_GRXSTSP_EPNUM; - pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; - pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U; + pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4U; switch (pktsts) { case GRXSTS_PKTSTS_IN: /* Read the data into the host buffer. */ - if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0)) + if ((pktcnt > 0U) && (hhcd->hc[channelnum].xfer_buff != (void *)0U)) { USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt); @@ -1091,14 +1090,14 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) hhcd->hc[channelnum].xfer_buff += pktcnt; hhcd->hc[channelnum].xfer_count += pktcnt; - if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0) + if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U) { /* re-activate the channel when more packets are expected */ tmpreg = USBx_HC(channelnum)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; USBx_HC(channelnum)->HCCHAR = tmpreg; - hhcd->hc[channelnum].toggle_in ^= 1; + hhcd->hc[channelnum].toggle_in ^= 1U; } } break; @@ -1121,7 +1120,7 @@ static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd) static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - __IO uint32_t hprt0 = 0, hprt0_dup = 0; + __IO uint32_t hprt0 = 0, hprt0_dup = 0U; /* Handle Host Port Interrupts */ hprt0 = USBx_HPRT0; @@ -1148,7 +1147,7 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd) if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) { - if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) + if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17U)) { USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_6_MHZ ); } diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.h index 2d0437508fd..abc302f0694 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_hcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_hcd.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention @@ -67,11 +67,11 @@ */ typedef enum { - HAL_HCD_STATE_RESET = 0x00, - HAL_HCD_STATE_READY = 0x01, - HAL_HCD_STATE_ERROR = 0x02, - HAL_HCD_STATE_BUSY = 0x03, - HAL_HCD_STATE_TIMEOUT = 0x04 + HAL_HCD_STATE_RESET = 0x00U, + HAL_HCD_STATE_READY = 0x01U, + HAL_HCD_STATE_ERROR = 0x02U, + HAL_HCD_STATE_BUSY = 0x03U, + HAL_HCD_STATE_TIMEOUT = 0x04U } HCD_StateTypeDef; typedef USB_OTG_GlobalTypeDef HCD_TypeDef; @@ -87,7 +87,7 @@ typedef struct { HCD_TypeDef *Instance; /*!< Register base address */ HCD_InitTypeDef Init; /*!< HCD required parameters */ - HCD_HCTypeDef hc[15]; /*!< Host channels parameters */ + HCD_HCTypeDef hc[15U]; /*!< Host channels parameters */ HAL_LockTypeDef Lock; /*!< HCD peripheral status */ __IO HCD_StateTypeDef State; /*!< HCD communication state */ void *pData; /*!< Pointer Stack Handler */ @@ -104,8 +104,8 @@ typedef struct /** @defgroup HCD_Speed HCD Speed * @{ */ -#define HCD_SPEED_LOW 2 -#define HCD_SPEED_FULL 3 +#define HCD_SPEED_LOW 2U +#define HCD_SPEED_FULL 3U /** * @} @@ -126,7 +126,7 @@ typedef struct #define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) -#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) +#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) #define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c index 7c72e1f840d..3a950bad416 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_i2c.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -669,7 +669,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA hi2c->XferCount--; hi2c->XferSize--; - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U)) + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) { /* Write data to DR */ hi2c->Instance->DR = (*hi2c->pBuffPtr++); @@ -1065,7 +1065,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData hi2c->XferCount--; hi2c->XferSize--; - if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U)) + if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) { /* Write data to DR */ hi2c->Instance->DR = (*hi2c->pBuffPtr++); @@ -2197,6 +2197,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D */ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(DevAddress); + /* Abort Master transfer during Receive or Transmit process */ if(hi2c->Mode == HAL_I2C_MODE_MASTER) { @@ -2704,7 +2707,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, hi2c->XferCount--; } /* Two bytes */ - else if(Size == 2U) + else if(hi2c->XferSize == 2U) { /* Wait until BTF flag is set */ if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.h index 5af2067ef78..36842f5acb6 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_i2c.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention @@ -438,7 +438,7 @@ typedef struct tmpreg = (__HANDLE__)->Instance->SR1; \ tmpreg = (__HANDLE__)->Instance->SR2; \ UNUSED(tmpreg); \ - } while(0) + } while(0U) /** @brief Clears the I2C STOPF pending flag. * @param __HANDLE__: specifies the I2C Handle. @@ -451,7 +451,7 @@ typedef struct tmpreg = (__HANDLE__)->Instance->SR1; \ (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \ UNUSED(tmpreg); \ - } while(0) + } while(0U) /** @brief Enable the I2C peripheral. * @param __HANDLE__: specifies the I2C Handle. diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c index 2246e5e70bc..332717572f6 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c @@ -2,10 +2,10 @@ ****************************************************************************** * @file stm32f1xx_hal_i2s.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief I2S HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: * + Initialization and de-initialization functions * + IO operation functions @@ -16,10 +16,10 @@ =============================================================================== [..] The I2S HAL driver can be used as follow: - + (#) Declare a I2S_HandleTypeDef handle structure. (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: - (##) Enable the SPIx interface clock. + (##) Enable the SPIx interface clock. (##) I2S pins configuration: (+++) Enable the clock for the I2S GPIOs. (+++) Configure these I2S pins as alternate function. @@ -33,14 +33,14 @@ (+++) Enable the DMAx interface clock. (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx Channel. - (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle. + (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx Channel. (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity using HAL_I2S_Init() function. - -@- The specific I2S interrupts (Transmission complete interrupt, + -@- The specific I2S interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. -@- The I2SxCLK source is the system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock). @@ -50,44 +50,44 @@ (+@) External clock source is configured after setting correctly the define constant HSE_VALUE in the stm32f1xx_hal_conf.h file. - (#) Three mode of operations are available within this driver : + (#) Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() + [..] + (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() - + *** Interrupt mode IO operation *** =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() - (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback - (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + [..] + (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_I2S_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() - (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback - (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can add his own code by customization of function pointer HAL_I2S_RxCpltCallback - (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2S_ErrorCallback *** DMA mode IO operation *** ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() - (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback - (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_I2S_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() - (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback - (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can add his own code by customization of function pointer HAL_I2S_RxCpltCallback - (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2S_ErrorCallback (+) Pause the DMA Transfer using HAL_I2S_DMAPause() (+) Resume the DMA Transfer using HAL_I2S_DMAResume() @@ -96,9 +96,9 @@ *** I2S HAL driver macros list *** ============================================= [..] - Below the list of most used macros in USART HAL driver. - - (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) + Below the list of most used macros in I2S HAL driver. + + (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts @@ -119,7 +119,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -144,7 +144,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -152,7 +152,7 @@ /** @addtogroup STM32F1xx_HAL_Driver * @{ */ - + #ifdef HAL_I2S_MODULE_ENABLED #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) @@ -170,52 +170,54 @@ * @{ */ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void I2S_DMAError(DMA_HandleTypeDef *hdma); static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout); +static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s); +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, + uint32_t Timeout); /** * @} */ - + /* Exported functions ---------------------------------------------------------*/ /** @defgroup I2S_Exported_Functions I2S Exported Functions * @{ */ /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialiaze the I2Sx peripheral in simplex mode: + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the I2Sx peripheral in simplex mode: - (+) User must Implement HAL_I2S_MspInit() function in which he configures + (+) User must Implement HAL_I2S_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - (+) Call the function HAL_I2S_Init() to configure the selected device with + (+) Call the function HAL_I2S_Init() to configure the selected device with the selected configuration: (++) Mode - (++) Standard + (++) Standard (++) Data Format (++) MCLK Output (++) Audio frequency (++) Polarity - (+) Call the function HAL_I2S_DeInit() to restore the default configuration - of the selected I2Sx periperal. - @endverbatim + (+) Call the function HAL_I2S_DeInit() to restore the default configuration + of the selected I2Sx peripheral. +@endverbatim * @{ */ /** - * @brief Initializes the I2S according to the specified parameters + * @brief Initializes the I2S according to the specified parameters * in the I2S_InitTypeDef and create the associated handle. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module @@ -223,15 +225,15 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, */ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) { - uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0; - + uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 16U; + uint32_t tmp = 0U, i2sclk = 0U; + /* Check the I2S handle allocation */ if(hi2s == NULL) { return HAL_ERROR; } - + /* Check the I2S parameters */ assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); assert_param(IS_I2S_MODE(hi2s->Init.Mode)); @@ -239,40 +241,50 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); - assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); - - if(hi2s->State == HAL_I2S_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hi2s->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2S_MspInit(hi2s); - } - + assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); + hi2s->State = HAL_I2S_STATE_BUSY; - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT) - { - i2sodd = (uint32_t)0; - i2sdiv = (uint32_t)2; - } + /* Initialize Default I2S IrqHandler ISR */ + hi2s->IrqHandlerISR = I2S_IRQHandler; + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2S_MspInit(hi2s); + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + CLEAR_BIT(hi2s->Instance->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ + SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); + hi2s->Instance->I2SPR = 0x0002U; + + /* Get the I2SCFGR register value */ + tmpreg = hi2s->Instance->I2SCFGR; + + /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */ /* If the requested audio frequency is not the default, compute the prescaler */ - else + if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) { /* Check the frame length (For the Prescaler computing) *******************/ - if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) + /* Set I2S Packet Length value*/ + if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) { - /* Packet length is 16 bits */ - packetlength = 1; + /* Packet length is 32 bits */ + packetlength = 32U; } else { - /* Packet length is 32 bits */ - packetlength = 2; + /* Packet length is 16 bits */ + packetlength = 16U; } - + + /* I2S standard */ + if(hi2s->Init.Standard <= I2S_STANDARD_LSB) + { + /* In I2S standard packet lenght is multiplied by 2 */ + packetlength = packetlength * 2U; + } + if(hi2s->Instance == SPI2) { /* Get the source clock value: based on SPI2 Instance */ @@ -286,68 +298,71 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) else { /* Get the source clock value: based on System Clock value */ - i2sclk = HAL_RCC_GetSysClockFreq(); - } - if(i2sclk == 0) - { - return HAL_ERROR; + i2sclk = HAL_RCC_GetSysClockFreq(); } - + /* Compute the Real divider depending on the MCLK output state, with a floating point */ if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) { /* MCLK output is enabled */ - tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5); + if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) + { + tmp = (uint32_t)(((((i2sclk / (packetlength*4)) * 10) / hi2s->Init.AudioFreq)) + 5); + } + else + { + tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5); + } } else { /* MCLK output is disabled */ - tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5); + tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5); } /* Remove the flatting point */ - tmp = tmp / 10; + tmp = tmp / 10U; /* Check the parity of the divider */ - i2sodd = (uint32_t)(tmp & (uint32_t)1); + i2sodd = (uint16_t)(tmp & (uint16_t)1U); /* Compute the i2sdiv prescaler */ - i2sdiv = (uint32_t)((tmp - i2sodd) / 2); + i2sdiv = (uint16_t)((tmp - i2sodd) / 2U); /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint32_t) (i2sodd << 8); + i2sodd = (uint32_t) (i2sodd << 8U); } /* Test if the divider is 1 or 0 or greater than 0xFF */ - if((i2sdiv < 2) || (i2sdiv > 0xFF)) + if((i2sdiv < 2U) || (i2sdiv > 0xFFU)) { /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } + i2sdiv = 2U; + i2sodd = 0U; - /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - /* And configure the I2S with the I2S_InitStruct values */ - MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\ - SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\ - SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\ - SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD),\ - (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\ - hi2s->Init.Standard | hi2s->Init.DataFormat |\ - hi2s->Init.CPOL)); + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER); + HAL_I2S_ErrorCallback(hi2s); + return HAL_ERROR; + } /* Write to SPIx I2SPR register the computed value */ hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); + /* Configure the I2S with the I2S_InitStruct values */ + tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \ + (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \ + (uint16_t)hi2s->Init.CPOL)))); + /* Write to SPIx I2SCFGR */ + WRITE_REG(hi2s->Instance->I2SCFGR,tmpreg); hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State= HAL_I2S_STATE_READY; + hi2s->State = HAL_I2S_STATE_READY; return HAL_OK; } /** - * @brief DeInitializes the I2S peripheral + * @brief DeInitializes the I2S peripheral * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status @@ -359,17 +374,14 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) { return HAL_ERROR; } - + hi2s->State = HAL_I2S_STATE_BUSY; - - /* Disable the I2S Peripheral Clock */ - __HAL_I2S_DISABLE(hi2s); /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ HAL_I2S_MspDeInit(hi2s); hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_RESET; + hi2s->State = HAL_I2S_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hi2s); @@ -389,7 +401,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) UNUSED(hi2s); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_MspInit could be implemented in the user file - */ + */ } /** @@ -404,9 +416,8 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) UNUSED(hi2s); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_MspDeInit could be implemented in the user file - */ + */ } - /** * @} */ @@ -414,28 +425,28 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) /** @defgroup I2S_Exported_Functions_Group2 IO operation functions * @brief Data transfers functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to manage the I2S data + This subsection provides a set of functions allowing to manage the I2S data transfers. (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when + The end of the data processing will be indicated through the + dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. (#) Blocking mode functions are : (++) HAL_I2S_Transmit() (++) HAL_I2S_Receive() - + (#) No-Blocking mode functions with Interrupt are : (++) HAL_I2S_Transmit_IT() (++) HAL_I2S_Receive_IT() @@ -460,195 +471,200 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) * @param pData: a 16-bit pointer to data buffer. * @param Size: number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. * @param Timeout: Timeout duration - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) { - if((pData == NULL ) || (Size == 0)) + uint32_t tmp1 = 0U; + + if((pData == NULL ) || (Size == 0U)) { - return HAL_ERROR; + return HAL_ERROR; } - - /* Process Locked */ - __HAL_LOCK(hi2s); if(hi2s->State == HAL_I2S_STATE_READY) - { - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + + if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); } else { - hi2s->TxXferSize = Size; + hi2s->TxXferSize = Size; hi2s->TxXferCount = Size; } - - /* Set state and reset error code */ + + /* Process Locked */ + __HAL_LOCK(hi2s); + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->pTxBuffPtr = pData; - - /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + hi2s->State = HAL_I2S_STATE_BUSY_TX; + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) { /* Enable I2S peripheral */ __HAL_I2S_ENABLE(hi2s); } - - while(hi2s->TxXferCount > 0) + + while(hi2s->TxXferCount > 0U) { + hi2s->Instance->DR = (*pData++); + hi2s->TxXferCount--; + /* Wait until TXE flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) { + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + HAL_I2S_ErrorCallback(hi2s); return HAL_TIMEOUT; } - hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); - hi2s->TxXferCount--; /* Check if an underrun occurs */ - if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) + if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) { + /* Clear underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; + hi2s->State = HAL_I2S_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2s); /* Set the error code and execute error callback*/ - hi2s->ErrorCode |= HAL_I2S_ERROR_UDR; - return HAL_ERROR; - } - } + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + HAL_I2S_ErrorCallback(hi2s); - /* Wait until TXE flag is set, to confirm the end of the transcation */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - /* Check if Slave mode is selected */ - if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) - { - /* Wait until Busy flag is reset */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; + return HAL_ERROR; } } - hi2s->State = HAL_I2S_STATE_READY; - + hi2s->State = HAL_I2S_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hi2s); - + return HAL_OK; } else { - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); return HAL_BUSY; } } /** - * @brief Receive an amount of data in blocking mode + * @brief Receive an amount of data in blocking mode * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. + * @param pData: a 16-bit pointer to data buffer * @param Size: number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. * @param Timeout: Timeout duration - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * between Master and Slave(example: audio streaming) * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate - * in continouse way and as the I2S is not disabled at the end of the I2S transaction. + * in continuous way and as the I2S is not disabled at the end of the I2S transaction * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) { - if((pData == NULL ) || (Size == 0)) + uint32_t tmp1 = 0U; + + if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } - - /* Process Locked */ - __HAL_LOCK(hi2s); - + if(hi2s->State == HAL_I2S_STATE_READY) - { - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + { + tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); } else { - hi2s->RxXferSize = Size; + hi2s->RxXferSize = Size; hi2s->RxXferCount = Size; } - - /* Set state and reset error code */ + /* Process Locked */ + __HAL_LOCK(hi2s); + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->pRxBuffPtr = pData; - - /* Check if the I2S is already enabled */ + hi2s->State = HAL_I2S_STATE_BUSY_RX; + + /* Check if the I2S is already enabled */ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) { /* Enable I2S peripheral */ __HAL_I2S_ENABLE(hi2s); } - + + /* Check if Master Receiver mode is selected */ + if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) + { + /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read + access to the SPI_SR register. */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + } + /* Receive data */ - while(hi2s->RxXferCount > 0) + while(hi2s->RxXferCount > 0U) { - /* Wait until RXNE flag is reset */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK) + /* Wait until RXNE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) { + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT); + HAL_I2S_ErrorCallback(hi2s); return HAL_TIMEOUT; } - - (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; - hi2s->RxXferCount--; /* Check if an overrun occurs */ - if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) + if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) { + /* Clear overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; + hi2s->State = HAL_I2S_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hi2s); /* Set the error code and execute error callback*/ - hi2s->ErrorCode |= HAL_I2S_ERROR_OVR; + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); + HAL_I2S_ErrorCallback(hi2s); + return HAL_ERROR; } + + (*pData++) = hi2s->Instance->DR; + hi2s->RxXferCount--; } - - hi2s->State = HAL_I2S_STATE_READY; - + + hi2s->State = HAL_I2S_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hi2s); - + return HAL_OK; } else { - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); return HAL_BUSY; } } @@ -660,45 +676,47 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint * @param pData: a 16-bit pointer to data buffer. * @param Size: number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - + uint32_t tmp1 = 0U; + if(hi2s->State == HAL_I2S_STATE_READY) { - hi2s->pTxBuffPtr = pData; - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + if((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + hi2s->pTxBuffPtr = pData; + tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); } else { - hi2s->TxXferSize = Size; + hi2s->TxXferSize = Size; hi2s->TxXferCount = Size; } + /* Process Locked */ + __HAL_LOCK(hi2s); + + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + /* Enable TXE and ERR interrupt */ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - /* Check if the I2S is already enabled */ + /* Check if the I2S is already enabled */ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) { /* Enable I2S peripheral */ @@ -707,13 +725,11 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, /* Process Unlocked */ __HAL_UNLOCK(hi2s); - + return HAL_OK; } else { - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); return HAL_BUSY; } } @@ -725,47 +741,48 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, * @param pData: a 16-bit pointer to the Receive data buffer. * @param Size: number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). - * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation - * between Master and Slave otherwise the I2S interrupt should be optimized. + * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation + * between Master and Slave otherwise the I2S interrupt should be optimized. * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + uint32_t tmp1 = 0U; + + if(hi2s->State == HAL_I2S_STATE_READY) + { + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - - if(hi2s->State == HAL_I2S_STATE_READY) - { hi2s->pRxBuffPtr = pData; - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); - } + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); + } else { - hi2s->RxXferSize = Size; + hi2s->RxXferSize = Size; hi2s->RxXferCount = Size; } - - /* Enable RXNE and ERR interrupt */ + /* Process Locked */ + __HAL_LOCK(hi2s); + + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + /* Enable TXE and ERR interrupt */ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - /* Check if the I2S is already enabled */ + + /* Check if the I2S is already enabled */ if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) { /* Enable I2S peripheral */ @@ -777,12 +794,11 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u return HAL_OK; } + else { - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } + return HAL_BUSY; + } } /** @@ -792,155 +808,159 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u * @param pData: a 16-bit pointer to the Transmit data buffer. * @param Size: number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + uint32_t *tmp = NULL; + uint32_t tmp1 = 0U; + + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if(hi2s->State == HAL_I2S_STATE_READY) - { + { hi2s->pTxBuffPtr = pData; - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = (Size << 1); - hi2s->TxXferCount = (Size << 1); + hi2s->TxXferSize = (Size << 1U); + hi2s->TxXferCount = (Size << 1U); } else { - hi2s->TxXferSize = Size; + hi2s->TxXferSize = Size; hi2s->TxXferCount = Size; } - /* Set the I2S Tx DMA Half transfert complete callback */ + /* Process Locked */ + __HAL_LOCK(hi2s); + + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + hi2s->State = HAL_I2S_STATE_BUSY_TX; + + /* Set the I2S Tx DMA Half transfer complete callback */ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; - /* Set the I2S Tx DMA transfert complete callback */ + /* Set the I2S Tx DMA transfer complete callback */ hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; /* Set the DMA error callback */ hi2s->hdmatx->XferErrorCallback = I2S_DMAError; - /* Enable the Tx DMA Channel */ - HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); + /* Enable the Tx DMA Stream */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); - /* Check if the I2S is already enabled */ - if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) { /* Enable I2S peripheral */ __HAL_I2S_ENABLE(hi2s); } - /* Check if the I2S Tx request is already enabled */ - if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN)) + /* Check if the I2S Tx request is already enabled */ + if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN) { - /* Enable Tx DMA Request */ + /* Enable Tx DMA Request */ SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); } /* Process Unlocked */ __HAL_UNLOCK(hi2s); - + return HAL_OK; } else { - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); return HAL_BUSY; } } /** - * @brief Receive an amount of data in non-blocking mode with DMA + * @brief Receive an amount of data in non-blocking mode with DMA * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @param pData: a 16-bit pointer to the Receive data buffer. * @param Size: number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization + * configuration phase, the Size parameter means the number of 16-bit data length + * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected + * the Size parameter means the number of 16-bit data length. + * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + uint32_t *tmp = NULL; + uint32_t tmp1 = 0U; + + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(hi2s); - if(hi2s->State == HAL_I2S_STATE_READY) { hi2s->pRxBuffPtr = pData; - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - - if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ - ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) + tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); + if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) { - hi2s->RxXferSize = (Size << 1); - hi2s->RxXferCount = (Size << 1); + hi2s->RxXferSize = (Size << 1U); + hi2s->RxXferCount = (Size << 1U); } else { - hi2s->RxXferSize = Size; + hi2s->RxXferSize = Size; hi2s->RxXferCount = Size; } - - - /* Set the I2S Rx DMA Half transfert complete callback */ + /* Process Locked */ + __HAL_LOCK(hi2s); + + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + /* Set the I2S Rx DMA Half transfer complete callback */ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; - - /* Set the I2S Rx DMA transfert complete callback */ + + /* Set the I2S Rx DMA transfer complete callback */ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; - + /* Set the DMA error callback */ hi2s->hdmarx->XferErrorCallback = I2S_DMAError; - + /* Check if Master Receiver mode is selected */ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) { /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read - access to the SPI_SR register. */ + access to the SPI_SR register. */ __HAL_I2S_CLEAR_OVRFLAG(hi2s); } - - /* Enable the Rx DMA Channel */ - HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize); - - /* Check if the I2S is already enabled */ - if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + + /* Enable the Rx DMA Stream */ + tmp = (uint32_t*)&pData; + HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize); + + /* Check if the I2S is already enabled */ + if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) { /* Enable I2S peripheral */ __HAL_I2S_ENABLE(hi2s); } - /* Check if the I2S Rx request is already enabled */ - if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN)) + /* Check if the I2S Rx request is already enabled */ + if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN) { - /* Enable Rx DMA Request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + /* Enable Rx DMA Request */ + SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN); } /* Process Unlocked */ @@ -950,14 +970,12 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, } else { - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); return HAL_BUSY; } } /** - * @brief Pauses the audio stream playing from the Media. + * @brief Pauses the audio channel playing from the Media. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status @@ -966,26 +984,26 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) { /* Process Locked */ __HAL_LOCK(hi2s); - + if(hi2s->State == HAL_I2S_STATE_BUSY_TX) { /* Disable the I2S DMA Tx request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN); } else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) { /* Disable the I2S DMA Rx request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN); } - + /* Process Unlocked */ __HAL_UNLOCK(hi2s); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Resumes the audio stream playing from the Media. + * @brief Resumes the audio channel playing from the Media. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status @@ -994,33 +1012,33 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) { /* Process Locked */ __HAL_LOCK(hi2s); - + if(hi2s->State == HAL_I2S_STATE_BUSY_TX) { /* Enable the I2S DMA Tx request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN); } else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) { /* Enable the I2S DMA Rx request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN); } /* If the I2S peripheral is still not enabled, enable it */ - if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U) { - /* Enable I2S peripheral */ + /* Enable I2S peripheral */ __HAL_I2S_ENABLE(hi2s); } - + /* Process Unlocked */ __HAL_UNLOCK(hi2s); - + return HAL_OK; } /** - * @brief Resumes the audio stream playing from the Media. + * @brief Resumes the audio channel playing from the Media. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status @@ -1029,34 +1047,31 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) { /* Process Locked */ __HAL_LOCK(hi2s); - - /* Disable the I2S Tx/Rx DMA requests */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Abort the I2S DMA Channel tx */ - if(hi2s->hdmatx != NULL) + + if(hi2s->State == HAL_I2S_STATE_BUSY_TX) { - /* Disable the I2S DMA channel */ - __HAL_DMA_DISABLE(hi2s->hdmatx); + /* Disable the I2S DMA requests */ + CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN); + + /* Disable the I2S DMA Channel */ HAL_DMA_Abort(hi2s->hdmatx); } - /* Abort the I2S DMA Channel rx */ - if(hi2s->hdmarx != NULL) + else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) { - /* Disable the I2S DMA channel */ - __HAL_DMA_DISABLE(hi2s->hdmarx); + /* Disable the I2S DMA requests */ + CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN); + + /* Disable the I2S DMA Channel */ HAL_DMA_Abort(hi2s->hdmarx); } - /* Disable I2S peripheral */ __HAL_I2S_DISABLE(hi2s); - + hi2s->State = HAL_I2S_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2s); - + return HAL_OK; } @@ -1067,52 +1082,9 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) * @retval None */ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) -{ - uint32_t i2ssr = hi2s->Instance->SR; - - /* I2S in mode Receiver ------------------------------------------------*/ - if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) && - ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) - { - I2S_Receive_IT(hi2s); - return; - } - - /* I2S in mode Tramitter -----------------------------------------------*/ - if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) - { - I2S_Transmit_IT(hi2s); - return; - } - - /* I2S interrupt error -------------------------------------------------*/ - if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET) - { - /* I2S Overrun error interrupt occured ---------------------------------*/ - if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) - { - /* Disable RXNE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); - } - - /* I2S Underrun error interrupt occured --------------------------------*/ - if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) - { - /* Disable TXE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); - } - - /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; - /* Call the Error Callback */ - HAL_I2S_ErrorCallback(hi2s); - } +{ + /* Call the IrqHandler ISR set during HAL_I2S_INIT */ + hi2s->IrqHandlerISR(hi2s); } /** @@ -1127,7 +1099,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) UNUSED(hi2s); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_TxHalfCpltCallback could be implemented in the user file - */ + */ } /** @@ -1142,7 +1114,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) UNUSED(hi2s); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_TxCpltCallback could be implemented in the user file - */ + */ } /** @@ -1187,7 +1159,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) UNUSED(hi2s); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_I2S_ErrorCallback could be implemented in the user file - */ + */ } /** @@ -1197,12 +1169,12 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions * @brief Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1243,28 +1215,27 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) * @{ */ /** - * @brief DMA I2S transmit process complete callback + * @brief DMA I2S transmit process complete callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) { - I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - + I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { /* Disable Tx DMA Request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN); - hi2s->TxXferCount = 0; - hi2s->State = HAL_I2S_STATE_READY; + hi2s->TxXferCount = 0U; + hi2s->State = HAL_I2S_STATE_READY; } HAL_I2S_TxCpltCallback(hi2s); } - /** - * @brief DMA I2S transmit process half complete callback + * @brief DMA I2S transmit process half complete callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -1277,27 +1248,27 @@ static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA I2S receive process complete callback + * @brief DMA I2S receive process complete callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) { - I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { /* Disable Rx DMA Request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - hi2s->RxXferCount = 0; - hi2s->State = HAL_I2S_STATE_READY; + CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN); + hi2s->RxXferCount = 0U; + hi2s->State = HAL_I2S_STATE_READY; } - HAL_I2S_RxCpltCallback(hi2s); + HAL_I2S_RxCpltCallback(hi2s); } /** - * @brief DMA I2S receive process half complete callback + * @brief DMA I2S receive process half complete callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -1306,11 +1277,11 @@ static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - HAL_I2S_RxHalfCpltCallback(hi2s); + HAL_I2S_RxHalfCpltCallback(hi2s); } /** - * @brief DMA I2S communication error callback + * @brief DMA I2S communication error callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -1320,14 +1291,13 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma) I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Disable Rx and Tx DMA Request */ - CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); - hi2s->TxXferCount = 0; - hi2s->RxXferCount = 0; + CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); + hi2s->TxXferCount = 0U; + hi2s->RxXferCount = 0U; hi2s->State= HAL_I2S_STATE_READY; - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA); HAL_I2S_ErrorCallback(hi2s); } @@ -1335,15 +1305,15 @@ static void I2S_DMAError(DMA_HandleTypeDef *hdma) * @brief Transmit an amount of data in non-blocking mode with Interrupt * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @retval None + * @retval HAL status */ static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) { /* Transmit data */ hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); hi2s->TxXferCount--; - - if(hi2s->TxXferCount == 0) + + if(hi2s->TxXferCount == 0U) { /* Disable TXE and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); @@ -1355,78 +1325,118 @@ static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) /** * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: I2S handle - * @retval None + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @retval HAL status */ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) { - /* Receive data */ + /* Receive data */ (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; hi2s->RxXferCount--; - - if(hi2s->RxXferCount == 0) + + if(hi2s->RxXferCount == 0U) { /* Disable RXNE and ERR interrupt */ __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - hi2s->State = HAL_I2S_STATE_READY; - HAL_I2S_RxCpltCallback(hi2s); + hi2s->State = HAL_I2S_STATE_READY; + HAL_I2S_RxCpltCallback(hi2s); } } - /** - * @brief This function handles I2S Communication Timeout. + * @brief This function handles I2S interrupt request. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param Flag: Flag checked - * @param Status: Value of the flag expected - * @param Timeout: Duration of the timeout - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout) +static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s) { - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if(Status == RESET) + __IO uint32_t i2ssr = hi2s->Instance->SR; + + if(hi2s->State == HAL_I2S_STATE_BUSY_RX) { - while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET) + /* I2S in mode Receiver ------------------------------------------------*/ + if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Set the I2S State ready */ - hi2s->State= HAL_I2S_STATE_READY; + I2S_Receive_IT(hi2s); + } - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); + /* I2S Overrun error interrupt occured -------------------------------------*/ + if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + { + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - return HAL_TIMEOUT; - } + /* Clear Overrun flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR); + HAL_I2S_ErrorCallback(hi2s); + } + } + + if(hi2s->State == HAL_I2S_STATE_BUSY_TX) + { + /* I2S in mode Transmitter -----------------------------------------------*/ + if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) + { + I2S_Transmit_IT(hi2s); } + + /* I2S Underrun error interrupt occurred --------------------------------*/ + if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) + { + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Clear Underrun flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); + HAL_I2S_ErrorCallback(hi2s); } } - else +} + +/** + * @brief This function handles I2S Communication Timeout. + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * the configuration information for I2S module + * @param Flag: Flag checked + * @param State: Value of the flag expected + * @param Timeout: Duration of the timeout + * @retval HAL status + */ +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, + uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set to status*/ + while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) { - while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET) + if(Timeout != HAL_MAX_DELAY) { - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Set the I2S State ready */ - hi2s->State= HAL_I2S_STATE_READY; + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } } @@ -1443,8 +1453,6 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #endif /* HAL_I2S_MODULE_ENABLED */ - - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.h index 8b65569c1b5..2bf8d58b50c 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_hal_i2s.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_I2S_H @@ -54,87 +54,91 @@ /** @addtogroup I2S * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup I2S_Exported_Types I2S Exported Types * @{ */ -/** - * @brief I2S Init structure definition +/** + * @brief I2S Init structure definition */ typedef struct { - uint32_t Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint32_t Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ - uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ - uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ - uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ - uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ }I2S_InitTypeDef; -/** +/** * @brief HAL State structures definition - */ + */ typedef enum { - HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */ - HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */ - HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ - HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */ - HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */ + HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ + HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ + }HAL_I2S_StateTypeDef; -/** - * @brief I2S handle Structure definition +/** + * @brief I2S handle Structure definition */ -typedef struct +typedef struct __I2S_HandleTypeDef { - SPI_TypeDef *Instance; /* I2S registers base address */ - - I2S_InitTypeDef Init; /* I2S communication parameters */ - - uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */ - - __IO uint16_t TxXferSize; /* I2S Tx transfer size */ - - __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */ - - uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */ - - __IO uint16_t RxXferSize; /* I2S Rx transfer size */ - - __IO uint16_t RxXferCount; /* I2S Rx transfer counter - (This field is initialized at the - same value as transfer size at the - beginning of the transfer and - decremented when a sample is received. + SPI_TypeDef *Instance; /*!< I2S registers base address */ + + I2S_InitTypeDef Init; /*!< I2S communication parameters */ + + uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ + + __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ + + __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ + + uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ + + __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ + + __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter + (This field is initialized at the + same value as transfer size at the + beginning of the transfer and + decremented when a sample is received NbSamplesReceived = RxBufferSize-RxBufferCount) */ - DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */ + void (*IrqHandlerISR) (struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */ - DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */ - - __IO HAL_LockTypeDef Lock; /* I2S locking object */ - - __IO HAL_I2S_StateTypeDef State; /* I2S communication state */ + DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ - __IO uint32_t ErrorCode; /* I2S Error code */ + DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ + + __IO HAL_LockTypeDef Lock; /*!< I2S locking object */ + + __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ + + __IO uint32_t ErrorCode; /*!< I2S Error code + This parameter can be a value of @ref I2S_ErrorCode */ }I2S_HandleTypeDef; /** @@ -145,66 +149,59 @@ typedef struct /** @defgroup I2S_Exported_Constants I2S Exported Constants * @{ */ - -/** @defgroup I2S_Error_Codes I2S Error Codes +/** + * @defgroup I2S_ErrorCode I2S Error Code * @{ */ -#define HAL_I2S_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_I2S_ERROR_UDR ((uint32_t)0x01) /*!< I2S Underrun error */ -#define HAL_I2S_ERROR_OVR ((uint32_t)0x02) /*!< I2S Overrun error */ -#define HAL_I2S_ERROR_FRE ((uint32_t)0x04) /*!< I2S Frame format error */ -#define HAL_I2S_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */ - +#define HAL_I2S_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_I2S_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ +#define HAL_I2S_ERROR_OVR 0x00000002U /*!< OVR error */ +#define HAL_I2S_ERROR_UDR 0x00000004U /*!< UDR error */ +#define HAL_I2S_ERROR_DMA 0x00000008U /*!< DMA transfer error */ +#define HAL_I2S_ERROR_PRESCALER 0x00000010U /*!< Prescaler Calculation error */ /** * @} */ - /** @defgroup I2S_Mode I2S Mode * @{ */ -#define I2S_MODE_SLAVE_TX ((uint32_t) 0x00000000) -#define I2S_MODE_SLAVE_RX ((uint32_t) SPI_I2SCFGR_I2SCFG_0) -#define I2S_MODE_MASTER_TX ((uint32_t) SPI_I2SCFGR_I2SCFG_1) -#define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 |\ - SPI_I2SCFGR_I2SCFG_1)) - +#define I2S_MODE_SLAVE_TX 0x00000000U +#define I2S_MODE_SLAVE_RX ((uint32_t)SPI_I2SCFGR_I2SCFG_0) +#define I2S_MODE_MASTER_TX ((uint32_t)SPI_I2SCFGR_I2SCFG_1) +#define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)) /** * @} */ - + /** @defgroup I2S_Standard I2S Standard * @{ */ -#define I2S_STANDARD_PHILIPS ((uint32_t) 0x00000000) -#define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0) -#define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1) -#define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\ - SPI_I2SCFGR_I2SSTD_1)) -#define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\ - SPI_I2SCFGR_I2SSTD_1 |\ - SPI_I2SCFGR_PCMSYNC)) - +#define I2S_STANDARD_PHILIPS 0x00000000U +#define I2S_STANDARD_MSB ((uint32_t)SPI_I2SCFGR_I2SSTD_0) +#define I2S_STANDARD_LSB ((uint32_t)SPI_I2SCFGR_I2SSTD_1) +#define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)) +#define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)) /** * @} */ - + /** @defgroup I2S_Data_Format I2S Data Format * @{ */ -#define I2S_DATAFORMAT_16B ((uint32_t) 0x00000000) -#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN) +#define I2S_DATAFORMAT_16B 0x00000000U +#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)SPI_I2SCFGR_CHLEN) #define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) #define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) /** * @} */ -/** @defgroup I2S_MCLK_Output I2S MCLK Output +/** @defgroup I2S_MCLK_Output I2S Mclk Output * @{ */ #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE) -#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000) +#define I2S_MCLKOUTPUT_DISABLE 0x00000000U /** * @} */ @@ -212,30 +209,30 @@ typedef struct /** @defgroup I2S_Audio_Frequency I2S Audio Frequency * @{ */ -#define I2S_AUDIOFREQ_192K ((uint32_t)192000) -#define I2S_AUDIOFREQ_96K ((uint32_t)96000) -#define I2S_AUDIOFREQ_48K ((uint32_t)48000) -#define I2S_AUDIOFREQ_44K ((uint32_t)44100) -#define I2S_AUDIOFREQ_32K ((uint32_t)32000) -#define I2S_AUDIOFREQ_22K ((uint32_t)22050) -#define I2S_AUDIOFREQ_16K ((uint32_t)16000) -#define I2S_AUDIOFREQ_11K ((uint32_t)11025) -#define I2S_AUDIOFREQ_8K ((uint32_t)8000) -#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2) +#define I2S_AUDIOFREQ_192K 192000U +#define I2S_AUDIOFREQ_96K 96000U +#define I2S_AUDIOFREQ_48K 48000U +#define I2S_AUDIOFREQ_44K 44100U +#define I2S_AUDIOFREQ_32K 32000U +#define I2S_AUDIOFREQ_22K 22050U +#define I2S_AUDIOFREQ_16K 16000U +#define I2S_AUDIOFREQ_11K 11025U +#define I2S_AUDIOFREQ_8K 8000U +#define I2S_AUDIOFREQ_DEFAULT 2U /** * @} */ -/** @defgroup I2S_Clock_Polarity I2S Clock Polarity +/** @defgroup I2S_Clock_Polarity I2S Clock Polarity * @{ */ -#define I2S_CPOL_LOW ((uint32_t)0x00000000) +#define I2S_CPOL_LOW 0x00000000U #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL) /** * @} */ -/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition +/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition * @{ */ #define I2S_IT_TXE SPI_CR2_TXEIE @@ -245,7 +242,7 @@ typedef struct * @} */ -/** @defgroup I2S_Flag_definition I2S Flag definition +/** @defgroup I2S_Flags_Definition I2S Flags Definition * @{ */ #define I2S_FLAG_TXE SPI_SR_TXE @@ -263,21 +260,21 @@ typedef struct /** * @} - */ - + */ + /* Exported macro ------------------------------------------------------------*/ -/** @defgroup I2S_Exported_macros I2S Exported Macros +/** @defgroup I2S_Exported_Macros I2S Exported Macros * @{ */ -/** @brief Reset I2S handle state +/** @brief Reset I2S handle state * @param __HANDLE__: specifies the I2S Handle. * @retval None */ #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) /** @brief Enable the specified SPI peripheral (in I2S mode). - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__: specifies the I2S Handle. * @retval None */ #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) @@ -296,7 +293,7 @@ typedef struct * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable * @arg I2S_IT_ERR: Error interrupt enable * @retval None - */ + */ #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) /** @brief Disable the specified I2S interrupts. @@ -330,6 +327,7 @@ typedef struct * @arg I2S_FLAG_TXE: Transmit buffer empty flag * @arg I2S_FLAG_UDR: Underrun flag * @arg I2S_FLAG_OVR: Overrun flag + * @arg I2S_FLAG_FRE: Frame error flag * @arg I2S_FLAG_CHSIDE: Channel Side flag * @arg I2S_FLAG_BSY: Busy flag * @retval The new state of __FLAG__ (TRUE or FALSE). @@ -339,25 +337,34 @@ typedef struct /** @brief Clears the I2S OVR pending flag. * @param __HANDLE__: specifies the I2S Handle. * @retval None - */ -#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\ - tmpreg = (__HANDLE__)->Instance->SR;\ - UNUSED(tmpreg); \ - }while(0) + */ +#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg); \ + } while(0U) + /** @brief Clears the I2S UDR pending flag. * @param __HANDLE__: specifies the I2S Handle. * @retval None */ -#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR) +#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg); \ + } while(0U) /** * @} - */ - + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup I2S_Exported_Functions * @{ */ - + /** @addtogroup I2S_Exported_Functions_Group1 * @{ */ @@ -374,7 +381,7 @@ void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); * @{ */ /* I/O operation functions ***************************************************/ - /* Blocking mode: Polling */ +/* Blocking mode: Polling */ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); @@ -415,6 +422,17 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); * @} */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2S_Private_Constants I2S Private Constants + * @{ + */ + +/** + * @} + */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup I2S_Private_Macros I2S Private Macros * @{ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.c index 4773f0d51cd..14511eb4a24 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.c @@ -2,16 +2,15 @@ ****************************************************************************** * @file stm32f1xx_hal_irda.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA SIR ENDEC block (IrDA): * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral State and Errors functions - * + Peripheral Control functions - * + * + Peripheral Control functions + * + Peripheral State and Errors functions @verbatim ============================================================================== ##### How to use this driver ##### @@ -24,7 +23,7 @@ (##) Enable the USARTx interface clock. (##) IRDA pins configuration: (+++) Enable the clock for the IRDA GPIOs. - (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). + (+++) Configure the IRDA pins as alternate function pull-up. (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() and HAL_IRDA_Receive_IT() APIs): (+++) Configure the USARTx interrupt priority. @@ -35,23 +34,23 @@ (+++) Enable the DMAx interface clock. (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle. + (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. - (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle - (used for last byte sending completion detection in DMA non circular mode) + (+++) Configure the IRDAx interrupt priority and enable the NVIC USART IRQ handle + (used for last byte sending completion detection in DMA non circular mode) (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler and Mode(Receiver/Transmitter) in the hirda Init structure. (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_IRDA_MspInit() API. - - -@@- The specific IRDA interrupts (Transmission complete interrupt, + by calling the customized HAL_IRDA_MspInit() API. + [..] + (@) The specific IRDA interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. - - (#) Three operation modes are available within this driver : + [..] + Three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -59,7 +58,7 @@ (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive() - *** Interrupt mode IO operation *** + *** Interrupt mode IO operation *** =================================== [..] (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT() @@ -71,39 +70,61 @@ (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_IRDA_ErrorCallback - *** DMA mode IO operation *** + *** DMA mode IO operation *** ============================== [..] (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA() + (+) At transmission end of half transfer HAL_IRDA_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_IRDA_TxCpltCallback (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA() + (+) At reception end of half transfer HAL_IRDA_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_IRDA_RxCpltCallback + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_IRDA_ErrorCallback + (+) Pause the DMA Transfer using HAL_IRDA_DMAPause() + (+) Resume the DMA Transfer using HAL_IRDA_DMAResume() + (+) Stop the DMA Transfer using HAL_IRDA_DMAStop() *** IRDA HAL driver macros list *** ==================================== [..] Below the list of most used macros in IRDA HAL driver. - + (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral - (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral + (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt (+) __HAL_IRDA_GET_IT_SOURCE: Check whether the specified IRDA interrupt has occurred or not - - [..] - (@) You can refer to the IRDA HAL driver header file for more useful macros + [..] + (@) You can refer to the IRDA HAL driver header file for more useful macros @endverbatim + [..] + (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible IRDA frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | IRDA frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | 1 STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | 1 STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | 1 STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | 1 STB | | + +-------------------------------------------------------------+ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -141,99 +162,78 @@ * @brief HAL IRDA module driver * @{ */ - #ifdef HAL_IRDA_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup IRDA_Private_Constants IRDA Private Constants +/** @addtogroup IRDA_Private_Constants * @{ */ -#define IRDA_DR_MASK_U16_8DATABITS (uint16_t)0x00FF -#define IRDA_DR_MASK_U16_9DATABITS (uint16_t)0x01FF - -#define IRDA_DR_MASK_U8_7DATABITS (uint8_t)0x7F -#define IRDA_DR_MASK_U8_8DATABITS (uint8_t)0xFF - - /** * @} */ - -/* Private macros --------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup IRDA_Private_Functions IRDA Private Functions +/** @addtogroup IRDA_Private_Functions * @{ */ +static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); -static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda); static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma); static void IRDA_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart,uint32_t Timeout); +static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); +static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); /** * @} */ - /* Exported functions ---------------------------------------------------------*/ - -/** @defgroup IRDA_Exported_Functions IRDA Exported Functions +/** @defgroup IRDA_Exported_Functions IrDA Exported Functions * @{ */ -/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim ============================================================================== - ##### Initialization and Configuration functions ##### + ##### Initialization and Configuration functions ##### ============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in IrDA mode. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Parity - (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may - not be rejected. The receiver set up time should be managed by software. The IrDA physical layer - specification specifies a minimum of 10 ms delay between transmission and - reception (IrDA is a half duplex protocol). - (++) Mode: Receiver/transmitter modes - (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode. - - [..] - The HAL_IRDA_Init() function follows IRDA configuration procedures (details for the procedures - are available in reference manuals (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)). + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in IrDA mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) BaudRate + (++) WordLength + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + please refer to Reference manual for possible IRDA frame formats. + (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may + not be rejected. The receiver set up time should be managed by software. The IrDA physical layer + specification specifies a minimum of 10 ms delay between transmission and + reception (IrDA is a half duplex protocol). + (++) Mode: Receiver/transmitter modes + (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode. + [..] + The HAL_IRDA_Init() API follows IRDA configuration procedures (details for the procedures + are available in reference manual). @endverbatim * @{ */ - -/* - Additionnal remark: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible IRDA frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | IRDA frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ -*/ - /** * @brief Initializes the IRDA mode according to the specified * parameters in the IRDA_InitTypeDef and create the associated handle. @@ -248,22 +248,19 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) { return HAL_ERROR; } - - /* Check the IRDA instance parameters */ + + /* Check the parameters */ assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - /* Check the IRDA mode parameter in the IRDA handle */ - assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode)); - - if(hirda->State == HAL_IRDA_STATE_RESET) + + if(hirda->gState == HAL_IRDA_STATE_RESET) { /* Allocate lock resource and initialize it */ hirda->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_IRDA_MspInit(hirda); } - hirda->State = HAL_IRDA_STATE_BUSY; + hirda->gState = HAL_IRDA_STATE_BUSY; /* Disable the IRDA peripheral */ __HAL_IRDA_DISABLE(hirda); @@ -272,8 +269,8 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) IRDA_SetConfig(hirda); /* In IrDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register.*/ + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register.*/ CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN)); CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); @@ -291,7 +288,8 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) /* Initialize the IRDA state*/ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->State= HAL_IRDA_STATE_READY; + hirda->gState= HAL_IRDA_STATE_READY; + hirda->RxState= HAL_IRDA_STATE_READY; return HAL_OK; } @@ -312,9 +310,9 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) /* Check the parameters */ assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - - hirda->State = HAL_IRDA_STATE_BUSY; - + + hirda->gState = HAL_IRDA_STATE_BUSY; + /* Disable the Peripheral */ __HAL_IRDA_DISABLE(hirda); @@ -322,8 +320,9 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) HAL_IRDA_MspDeInit(hirda); hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->State = HAL_IRDA_STATE_RESET; - + hirda->gState = HAL_IRDA_STATE_RESET; + hirda->RxState = HAL_IRDA_STATE_RESET; + /* Release Lock */ __HAL_UNLOCK(hirda); @@ -336,13 +335,13 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval None */ - __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); /* NOTE: This function should not be modified, when the callback is needed, the HAL_IRDA_MspInit can be implemented in the user file - */ + */ } /** @@ -351,13 +350,13 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA module. * @retval None */ - __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); /* NOTE: This function should not be modified, when the callback is needed, the HAL_IRDA_MspDeInit can be implemented in the user file - */ + */ } /** @@ -373,8 +372,6 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) ============================================================================== [..] This subsection provides a set of functions allowing to manage the IRDA data transfers. - - [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, any data on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. @@ -386,7 +383,7 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) The HAL status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. + or DMA, these APIs return the HAL status. The end of the data processing will be indicated through the dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -395,16 +392,16 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected - (#) Blocking mode APIs are : + (#) Blocking mode APIs are: (++) HAL_IRDA_Transmit() (++) HAL_IRDA_Receive() - (#) Non Blocking mode APIs with Interrupt are : + (#) Non Blocking mode APIs with Interrupt are: (++) HAL_IRDA_Transmit_IT() (++) HAL_IRDA_Receive_IT() (++) HAL_IRDA_IRQHandler() - (#) Non Blocking mode functions with DMA are : + (#) Non Blocking mode functions with DMA are: (++) HAL_IRDA_Transmit_DMA() (++) HAL_IRDA_Receive_DMA() (++) HAL_IRDA_DMAPause() @@ -433,13 +430,13 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) */ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp = 0; - uint32_t tmp_state = 0; - - tmp_state = hirda->State; - if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_RX)) + uint16_t* tmp; + uint32_t tickstart = 0U; + + /* Check that a Tx process is not already ongoing */ + if(hirda->gState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -448,64 +445,54 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u __HAL_LOCK(hirda); hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } + hirda->gState = HAL_IRDA_STATE_BUSY_TX; + + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); hirda->TxXferSize = Size; hirda->TxXferCount = Size; - while(hirda->TxXferCount > 0) + while(hirda->TxXferCount > 0U) { + hirda->TxXferCount--; if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) { - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } tmp = (uint16_t*) pData; - WRITE_REG(hirda->Instance->DR,(*tmp & IRDA_DR_MASK_U16_9DATABITS)); + hirda->Instance->DR = (*tmp & (uint16_t)0x01FF); if(hirda->Init.Parity == IRDA_PARITY_NONE) { - pData +=2; + pData +=2U; } else { - pData +=1; + pData +=1U; } } else { - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - WRITE_REG(hirda->Instance->DR, (*pData++ & IRDA_DR_MASK_U8_8DATABITS)); + hirda->Instance->DR = (*pData++ & (uint8_t)0xFF); } - hirda->TxXferCount--; } - - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK) - { + + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { return HAL_TIMEOUT; } - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } - + + /* At end of Tx process, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hirda); - + return HAL_OK; } else @@ -525,13 +512,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u */ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp = 0; - uint32_t tmp_state = 0; + uint16_t* tmp; + uint32_t tickstart = 0U; - tmp_state = hirda->State; - if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(hirda->RxState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -540,63 +527,56 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui __HAL_LOCK(hirda); hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; + + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); + hirda->RxXferSize = Size; hirda->RxXferCount = Size; + /* Check the remain data to be received */ - while(hirda->RxXferCount > 0) + while(hirda->RxXferCount > 0U) { + hirda->RxXferCount--; if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) { - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { return HAL_TIMEOUT; } - tmp = (uint16_t*) pData ; + tmp = (uint16_t*)pData; if(hirda->Init.Parity == IRDA_PARITY_NONE) { - *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_9DATABITS); - pData +=2; + *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x01FF); + pData +=2U; } else { - *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_8DATABITS); - pData +=1; + *tmp = (uint16_t)(hirda->Instance->DR & (uint16_t)0x00FF); + pData +=1U; } } else { - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { + if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { return HAL_TIMEOUT; } if(hirda->Init.Parity == IRDA_PARITY_NONE) { - *pData++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_8DATABITS); + *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x00FF); } else { - *pData++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_7DATABITS); + *pData++ = (uint8_t)(hirda->Instance->DR & (uint8_t)0x007F); } } - hirda->RxXferCount--; - } - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; } + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -604,12 +584,12 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Sends an amount of data in non-blocking mode. + * @brief Sends an amount of data in non blocking mode. * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer @@ -618,12 +598,10 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui */ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - uint32_t tmp_state = 0; - - tmp_state = hirda->State; - if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(hirda->gState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -635,19 +613,12 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData hirda->TxXferCount = Size; hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } + hirda->gState = HAL_IRDA_STATE_BUSY_TX; /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Transmit Data Register Empty Interrupt */ + /* Enable the IRDA Transmit data register empty Interrupt */ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE); return HAL_OK; @@ -659,7 +630,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData } /** - * @brief Receives an amount of data in non-blocking mode. + * @brief Receives an amount of data in non blocking mode. * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer @@ -668,45 +639,36 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData */ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - uint32_t tmp_state = 0; - - tmp_state = hirda->State; - if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(hirda->RxState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - + /* Process Locked */ __HAL_LOCK(hirda); - + hirda->pRxBuffPtr = pData; hirda->RxXferSize = Size; hirda->RxXferCount = Size; hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; + /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Data Register not empty Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); - /* Enable the IRDA Parity Error Interrupt */ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE); /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR); + /* Enable the IRDA Data Register not empty Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); + return HAL_OK; } else @@ -716,7 +678,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, } /** - * @brief Sends an amount of data in non-blocking mode. + * @brief Sends an amount of data in non blocking mode. * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer @@ -725,13 +687,12 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, */ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - uint32_t *tmp = 0; - uint32_t tmp_state = 0; - - tmp_state = hirda->State; - if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_RX)) + uint32_t *tmp; + + /* Check that a Tx process is not already ongoing */ + if(hirda->gState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -742,40 +703,36 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat hirda->pTxBuffPtr = pData; hirda->TxXferSize = Size; hirda->TxXferCount = Size; - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_BUSY_TX; /* Set the IRDA DMA transfer complete callback */ hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; - /* Set the IRDA DMA half transfert complete callback */ + /* Set the IRDA DMA half transfer complete callback */ hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt; /* Set the DMA error callback */ hirda->hdmatx->XferErrorCallback = IRDA_DMAError; - /* Enable the IRDA transmit DMA channel */ + /* Set the DMA abort callback */ + hirda->hdmatx->XferAbortCallback = NULL; + + /* Enable the IRDA transmit DMA Channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size); /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC); + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); /* Enable the DMA transfer for transmit request by setting the DMAT bit in the USART CR3 register */ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - return HAL_OK; } else @@ -785,7 +742,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat } /** - * @brief Receive an amount of data in non-blocking mode. + * @brief Receives an amount of data in non blocking mode. * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @param pData: Pointer to data buffer @@ -795,13 +752,12 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat */ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) { - uint32_t *tmp = 0; - uint32_t tmp_state = 0; - - tmp_state = hirda->State; - if((tmp_state == HAL_IRDA_STATE_READY) || (tmp_state == HAL_IRDA_STATE_BUSY_TX)) + uint32_t *tmp; + + /* Check that a Rx process is not already ongoing */ + if(hirda->RxState == HAL_IRDA_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -811,36 +767,42 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData hirda->pRxBuffPtr = pData; hirda->RxXferSize = Size; - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; /* Set the IRDA DMA transfer complete callback */ hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; - /* Set the IRDA DMA half transfert complete callback */ + /* Set the IRDA DMA half transfer complete callback */ hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt; /* Set the DMA error callback */ hirda->hdmarx->XferErrorCallback = IRDA_DMAError; + /* Set the DMA abort callback */ + hirda->hdmarx->XferAbortCallback = NULL; + /* Enable the DMA channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ + __HAL_IRDA_CLEAR_OREFLAG(hirda); /* Process Unlocked */ __HAL_UNLOCK(hirda); + /* Enable the IRDA Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + + /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + return HAL_OK; } else @@ -857,42 +819,39 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData */ HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) { + uint32_t dmarequest = 0x00U; + /* Process Locked */ __HAL_LOCK(hirda); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + + dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT); + if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest) { /* Disable the IRDA DMA Tx request */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); } - else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + + dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR); + if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest) { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + /* Disable the IRDA DMA Rx request */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); } - else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - /* Disable the IRDA DMA Tx & Rx requests */ - CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_ERROR; - } /* Process Unlocked */ __HAL_UNLOCK(hirda); - return HAL_OK; + return HAL_OK; } /** * @brief Resumes the DMA Transfer. * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. + * the configuration information for the specified IRDA module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) @@ -900,33 +859,25 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) /* Process Locked */ __HAL_LOCK(hirda); - if(hirda->State == HAL_IRDA_STATE_BUSY_TX) + if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) { /* Enable the IRDA DMA Tx request */ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); } - else if(hirda->State == HAL_IRDA_STATE_BUSY_RX) + + if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { - /* Clear the Overrun flag before resumming the Rx transfer*/ + /* Clear the Overrun flag before resuming the Rx transfer */ __HAL_IRDA_CLEAR_OREFLAG(hirda); + + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + /* Enable the IRDA DMA Rx request */ SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); } - else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - /* Clear the Overrun flag before resumming the Rx transfer*/ - __HAL_IRDA_CLEAR_OREFLAG(hirda); - /* Enable the IRDA DMA Tx & Rx request */ - SET_BIT(hirda->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_ERROR; - } - + /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -936,151 +887,610 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) /** * @brief Stops the DMA Transfer. * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. + * the configuration information for the specified IRDA module. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) { + uint32_t dmarequest = 0x00U; /* The Lock is not implemented on this API to allow the user application - to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback(): - when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() - */ - - /* Disable the IRDA Tx/Rx DMA requests */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Abort the IRDA DMA tx channel */ - if(hirda->hdmatx != NULL) + to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() + */ + + /* Stop IRDA DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT); + if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest) { - HAL_DMA_Abort(hirda->hdmatx); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel */ + if(hirda->hdmatx != NULL) + { + HAL_DMA_Abort(hirda->hdmatx); + } + IRDA_EndTxTransfer(hirda); } - /* Abort the IRDA DMA rx channel */ - if(hirda->hdmarx != NULL) + + /* Stop IRDA DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR); + if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest) { - HAL_DMA_Abort(hirda->hdmarx); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel */ + if(hirda->hdmarx != NULL) + { + HAL_DMA_Abort(hirda->hdmarx); + } + IRDA_EndRxTransfer(hirda); } - - hirda->State = HAL_IRDA_STATE_READY; return HAL_OK; } /** - * @brief This function handles IRDA interrupt request. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) + * @brief Abort ongoing transfers (blocking mode). + * @param hirda IRDA handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) { - uint32_t tmp_flag = 0, tmp_it_source = 0; + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE); - tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE); - /* IRDA parity error interrupt occurred -----------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + /* Disable the IRDA DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) { - hirda->ErrorCode |= HAL_IRDA_ERROR_PE; - } + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE); - tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR); - /* IRDA frame error interrupt occurred ------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - hirda->ErrorCode |= HAL_IRDA_ERROR_FE; - } + /* Abort the IRDA DMA Tx channel: use blocking DMA Abort API (no callback) */ + if(hirda->hdmatx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmatx->XferAbortCallback = NULL; - tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE); - /* IRDA noise error interrupt occurred ------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - hirda->ErrorCode |= HAL_IRDA_ERROR_NE; + HAL_DMA_Abort(hirda->hdmatx); + } } - tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE); - /* IRDA Over-Run interrupt occurred ---------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + /* Disable the IRDA DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) { - hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; - } + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - /* Call the Error call Back in case of Errors */ - if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) - { - /* Disable PE and ERR interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - - /* Clear all the error flag at once */ - __HAL_IRDA_CLEAR_PEFLAG(hirda); + /* Abort the IRDA DMA Rx channel: use blocking DMA Abort API (no callback) */ + if(hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = NULL; - /* Set the IRDA state ready to be able to start again the process */ - hirda->State = HAL_IRDA_STATE_READY; - HAL_IRDA_ErrorCallback(hirda); + HAL_DMA_Abort(hirda->hdmarx); + } } - tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_RXNE); - tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE); - /* IRDA in mode Receiver --------------------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - IRDA_Receive_IT(hirda); - } + /* Reset Tx and Rx transfer counters */ + hirda->TxXferCount = 0x00U; + hirda->RxXferCount = 0x00U; - tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE); - tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE); - /* IRDA in mode Transmitter -----------------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - IRDA_Transmit_IT(hirda); - } + /* Reset ErrorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - tmp_flag = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC); - tmp_it_source = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC); - /* IRDA in mode Transmitter (transmission end) -----------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - IRDA_EndTransmit_IT(hirda); - } - -} + /* Restore hirda->RxState and hirda->gState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + hirda->gState = HAL_IRDA_STATE_READY; -/** - * @brief Tx Transfer completed callbacks. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ - __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_TxCpltCallback can be implemented in the user file - */ + return HAL_OK; } /** - * @brief Tx Half Transfer completed callbacks. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ - __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param hirda IRDA handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) { - /* Prevent unused argument(s) compilation warning */ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the IRDA DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(hirda->hdmatx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmatx->XferAbortCallback = NULL; + + HAL_DMA_Abort(hirda->hdmatx); + } + } + + /* Reset Tx transfer counter */ + hirda->TxXferCount = 0x00U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param hirda IRDA handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Disable the IRDA DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = NULL; + + HAL_DMA_Abort(hirda->hdmarx); + } + } + + /* Reset Rx transfer counter */ + hirda->RxXferCount = 0x00U; + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param hirda IRDA handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) +{ + uint32_t AbortCplt = 0x01U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if(hirda->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback; + } + else + { + hirda->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if(hirda->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback; + } + else + { + hirda->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the IRDA DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at IRDA level */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ + if(hirda->hdmatx != NULL) + { + /* IRDA Tx DMA Abort callback has already been initialised : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) + { + hirda->hdmatx->XferAbortCallback = NULL; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* Disable the IRDA DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ + if(hirda->hdmarx != NULL) + { + /* IRDA Rx DMA Abort callback has already been initialised : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + hirda->hdmarx->XferAbortCallback = NULL; + AbortCplt = 0x01U; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if(AbortCplt == 0x01U) + { + /* Reset Tx and Rx transfer counters */ + hirda->TxXferCount = 0x00U; + hirda->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_IRDA_AbortCpltCallback(hirda); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param hirda IRDA handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the IRDA DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(hirda->hdmatx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) + { + /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */ + hirda->hdmatx->XferAbortCallback(hirda->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + hirda->TxXferCount = 0x00U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_IRDA_AbortTransmitCpltCallback(hirda); + } + } + else + { + /* Reset Tx transfer counter */ + hirda->TxXferCount = 0x00U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_IRDA_AbortTransmitCpltCallback(hirda); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param hirda IRDA handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Disable the IRDA DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ + hirda->hdmarx->XferAbortCallback(hirda->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + hirda->RxXferCount = 0x00U; + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_IRDA_AbortReceiveCpltCallback(hirda); + } + } + else + { + /* Reset Rx transfer counter */ + hirda->RxXferCount = 0x00U; + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_IRDA_AbortReceiveCpltCallback(hirda); + } + + return HAL_OK; +} + +/** + * @brief This function handles IRDA interrupt request. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) +{ + uint32_t isrflags = READ_REG(hirda->Instance->SR); + uint32_t cr1its = READ_REG(hirda->Instance->CR1); + uint32_t cr3its = READ_REG(hirda->Instance->CR3); + uint32_t errorflags = 0x00U; + uint32_t dmarequest = 0x00U; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); + if(errorflags == RESET) + { + /* IRDA in mode Receiver -----------------------------------------------*/ + if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + IRDA_Receive_IT(hirda); + return; + } + } + + /* If some errors occur */ + if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + { + /* IRDA parity error interrupt occurred -------------------------------*/ + if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + hirda->ErrorCode |= HAL_IRDA_ERROR_PE; + } + + /* IRDA noise error interrupt occurred --------------------------------*/ + if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + hirda->ErrorCode |= HAL_IRDA_ERROR_NE; + } + + /* IRDA frame error interrupt occurred --------------------------------*/ + if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + hirda->ErrorCode |= HAL_IRDA_ERROR_FE; + } + + /* IRDA Over-Run interrupt occurred -----------------------------------*/ + if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; + } + /* Call IRDA Error Call back function if need be -----------------------*/ + if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE) + { + /* IRDA in mode Receiver ---------------------------------------------*/ + if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + IRDA_Receive_IT(hirda); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR); + if(((hirda->ErrorCode & HAL_IRDA_ERROR_ORE) != RESET) || dmarequest) + { + /* Blocking error : transfer is aborted + Set the IRDA state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + IRDA_EndRxTransfer(hirda); + + /* Disable the IRDA DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel */ + if(hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError; + + if(HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hirda->hdmarx->XferAbortCallback(hirda->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_IRDA_ErrorCallback(hirda); + } + } + else + { + /* Call user error callback */ + HAL_IRDA_ErrorCallback(hirda); + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ + HAL_IRDA_ErrorCallback(hirda); + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + } + } + return; + } /* End if some error occurs */ + + /* IRDA in mode Transmitter ------------------------------------------------*/ + if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) + { + IRDA_Transmit_IT(hirda); + return; + } + + /* IRDA in mode Transmitter end --------------------------------------------*/ + if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) + { + IRDA_EndTransmit_IT(hirda); + return; + } +} + +/** + * @brief Tx Transfer complete callbacks. + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callbacks. + * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); /* NOTE: This function should not be modified, when the callback is needed, the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file - */ + */ } /** - * @brief Rx Transfer completed callbacks. + * @brief Rx Transfer complete callbacks. * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None @@ -1091,7 +1501,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) UNUSED(hirda); /* NOTE: This function should not be modified, when the callback is needed, the HAL_IRDA_RxCpltCallback can be implemented in the user file - */ + */ } /** @@ -1106,22 +1516,67 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) UNUSED(hirda); /* NOTE : This function should not be modified, when the callback is needed, the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file - */ + */ } /** - * @brief IRDA error callbacks. + * @brief IRDA error callbacks. * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ - __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) +__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) { /* Prevent unused argument(s) compilation warning */ UNUSED(hirda); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_ErrorCallback can be implemented in the user file - */ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_IRDA_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief IRDA Abort Complete callback. + * @param hirda IRDA handle. + * @retval None + */ +__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA Abort Transmit Complete callback. + * @param hirda IRDA handle. + * @retval None + */ +__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA Abort ReceiveComplete callback. + * @param hirda IRDA handle. + * @retval None + */ +__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file. + */ } /** @@ -1138,11 +1593,9 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) [..] This subsection provides a set of functions allowing to return the State of IrDA communication process and also return Peripheral Errors occurred during communication process - (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state - of the IRDA peripheral. - (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during - communication. - + (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state of the IrDA peripheral. + (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during communication. + @endverbatim * @{ */ @@ -1155,7 +1608,11 @@ __weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) */ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) { - return hirda->State; + uint32_t temp1 = 0x00U, temp2 = 0x00U; + temp1 = hirda->gState; + temp2 = hirda->RxState; + + return (HAL_IRDA_StateTypeDef)(temp1 | temp2); } /** @@ -1173,14 +1630,6 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) * @} */ -/** - * @} - */ - -/** @defgroup IRDA_Private_Functions IRDA Private Functions - * @brief IRDA Private functions - * @{ - */ /** * @brief DMA IRDA transmit process complete callback. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains @@ -1191,15 +1640,15 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - hirda->TxXferCount = 0; - + hirda->TxXferCount = 0U; + /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the IRDA CR3 register */ + in the IRDA CR3 register */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Enable the IRDA Transmit Complete Interrupt */ + + /* Enable the IRDA Transmit Complete Interrupt */ __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); } /* DMA Circular mode */ @@ -1212,74 +1661,82 @@ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA IRDA receive process half complete callback * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + HAL_IRDA_TxHalfCpltCallback(hirda); } /** * @brief DMA IRDA receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @param hdma: DMA handle * @retval None */ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - hirda->RxXferCount = 0; + hirda->RxXferCount = 0U; + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the IRDA CR3 register */ + in the IRDA CR3 register */ CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; } - HAL_IRDA_RxCpltCallback(hirda); } /** * @brief DMA IRDA receive process half complete callback * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - HAL_IRDA_RxHalfCpltCallback(hirda); } /** - * @brief DMA IRDA communication error callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief DMA IRDA communication error callback. + * @param hdma: DMA handle * @retval None */ -static void IRDA_DMAError(DMA_HandleTypeDef *hdma) +static void IRDA_DMAError(DMA_HandleTypeDef *hdma) { + uint32_t dmarequest = 0x00U; IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hirda->RxXferCount = 0; - hirda->TxXferCount = 0; + /* Stop IRDA DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT); + if((hirda->gState == HAL_IRDA_STATE_BUSY_TX) && dmarequest) + { + hirda->TxXferCount = 0U; + IRDA_EndTxTransfer(hirda); + } + + /* Stop IRDA DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR); + if((hirda->RxState == HAL_IRDA_STATE_BUSY_RX) && dmarequest) + { + hirda->RxXferCount = 0U; + IRDA_EndRxTransfer(hirda); + } + hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; - hirda->State= HAL_IRDA_STATE_READY; HAL_IRDA_ErrorCallback(hirda); } @@ -1290,113 +1747,238 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) * the configuration information for the specified IRDA module. * @param Flag: specifies the IRDA flag to check. * @param Status: The new Flag status (SET or RESET). + * @param Tickstart: Tick start value * @param Timeout: Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait until flag is set */ - if(Status == RESET) + while((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) { - while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State= HAL_IRDA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_TIMEOUT; - } + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_TIMEOUT; } } } - else + return HAL_OK; +} + +/** + * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion). + * @param hirda: IRDA handle. + * @retval None + */ +static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; +} + +/** + * @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion). + * @param hirda: IRDA handle. + * @retval None + */ +static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; +} + +/** + * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hirda->RxXferCount = 0x00U; + hirda->TxXferCount = 0x00U; + + HAL_IRDA_ErrorCallback(hirda); +} + +/** + * @brief DMA IRDA Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hirda->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(hirda->hdmarx != NULL) { - while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET) + if(hirda->hdmarx->XferAbortCallback != NULL) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + return; + } + } - hirda->State= HAL_IRDA_STATE_READY; + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hirda->TxXferCount = 0x00U; + hirda->RxXferCount = 0x00U; - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_TIMEOUT; - } - } + /* Reset ErrorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ + HAL_IRDA_AbortCpltCallback(hirda); +} + +/** + * @brief DMA IRDA Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hirda->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(hirda->hdmatx != NULL) + { + if(hirda->hdmatx->XferAbortCallback != NULL) + { + return; } } - return HAL_OK; + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hirda->TxXferCount = 0x00U; + hirda->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ + HAL_IRDA_AbortCpltCallback(hirda); } /** - * @brief Send an amount of data in non-blocking mode. - * Function called under interruption only, once - * interruptions have been enabled by HAL_IRDA_Transmit_IT() - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to + * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hirda->TxXferCount = 0x00U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ + HAL_IRDA_AbortTransmitCpltCallback(hirda); +} + +/** + * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to + * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hirda->RxXferCount = 0x00U; + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ + HAL_IRDA_AbortReceiveCpltCallback(hirda); +} + +/** + * @brief Send an amount of data in non blocking mode. + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { - uint16_t* tmp = 0; - uint32_t tmp_state = 0; - - tmp_state = hirda->State; - if((tmp_state == HAL_IRDA_STATE_BUSY_TX) || (tmp_state == HAL_IRDA_STATE_BUSY_TX_RX)) + uint16_t* tmp; + + /* Check that a Tx process is ongoing */ + if(hirda->gState == HAL_IRDA_STATE_BUSY_TX) { if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) { tmp = (uint16_t*) hirda->pTxBuffPtr; - WRITE_REG(hirda->Instance->DR, (uint16_t)(*tmp & IRDA_DR_MASK_U16_9DATABITS)); + hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); if(hirda->Init.Parity == IRDA_PARITY_NONE) { - hirda->pTxBuffPtr += 2; + hirda->pTxBuffPtr += 2U; } else { - hirda->pTxBuffPtr += 1; + hirda->pTxBuffPtr += 1U; } } else { - WRITE_REG(hirda->Instance->DR, (uint8_t)(*hirda->pTxBuffPtr++ & IRDA_DR_MASK_U8_8DATABITS)); + hirda->Instance->DR = (uint8_t)(*hirda->pTxBuffPtr++ & (uint8_t)0x00FF); } - - if(--hirda->TxXferCount == 0) + + if(--hirda->TxXferCount == 0U) { /* Disable the IRDA Transmit Data Register Empty Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - - /* Enable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); - } + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); + /* Enable the IRDA Transmit Complete Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); + } return HAL_OK; } else @@ -1414,86 +1996,69 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) { /* Disable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC); - - /* Check if a receive process is ongoing or not */ - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State = HAL_IRDA_STATE_READY; - } + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE); + /* Tx process is ended, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; HAL_IRDA_TxCpltCallback(hirda); return HAL_OK; } - /** - * @brief Receive an amount of data in non-blocking mode. + * @brief Receives an amount of data in non blocking mode. * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) { - uint16_t* tmp = 0; - uint32_t tmp_state = 0; - - tmp_state = hirda->State; - if((tmp_state == HAL_IRDA_STATE_BUSY_RX) || (tmp_state == HAL_IRDA_STATE_BUSY_TX_RX)) + uint16_t* tmp; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if(hirda->RxState == HAL_IRDA_STATE_BUSY_RX) { + uhdata = (uint16_t) READ_REG(hirda->Instance->DR); if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B) { tmp = (uint16_t*) hirda->pRxBuffPtr; if(hirda->Init.Parity == IRDA_PARITY_NONE) { - *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_9DATABITS); - hirda->pRxBuffPtr += 2; + *tmp = (uint16_t)(uhdata & (uint16_t)0x01FF); + hirda->pRxBuffPtr += 2U; } else { - *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_8DATABITS); - hirda->pRxBuffPtr += 1; + *tmp = (uint16_t)(uhdata & (uint16_t)0x00FF); + hirda->pRxBuffPtr += 1U; } - } + } else { if(hirda->Init.Parity == IRDA_PARITY_NONE) { - *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_8DATABITS); + *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x00FF); } else { - *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_7DATABITS); + *hirda->pRxBuffPtr++ = (uint8_t)(uhdata & (uint8_t)0x007F); } } - if(--hirda->RxXferCount == 0) + if(--hirda->RxXferCount == 0U) { + /* Disable the IRDA Data Register not empty Interrupt */ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_TX; - } - else - { - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - /* Disable the IRDA Parity Error Interrupt */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); - - hirda->State = HAL_IRDA_STATE_READY; - } + /* Disable the IRDA Parity Error Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); + + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + /* Rx process is completed, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; HAL_IRDA_RxCpltCallback(hirda); return HAL_OK; @@ -1502,7 +2067,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) } else { - return HAL_BUSY; + return HAL_BUSY; } } @@ -1515,38 +2080,43 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) { /* Check the parameters */ + assert_param(IS_IRDA_INSTANCE(hirda->Instance)); assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); assert_param(IS_IRDA_MODE(hirda->Init.Mode)); - - /*------- IRDA-associated USART registers setting : CR2 Configuration ------*/ + assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode)); + + /*-------------------------- USART CR2 Configuration ------------------------*/ /* Clear STOP[13:12] bits */ CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP); - /*------- IRDA-associated USART registers setting : CR1 Configuration ------*/ + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE and RE bits */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE); + /* Configure the USART Word Length, Parity and mode: - Set the M bits according to hirda->Init.WordLength value - Set PCE and PS bits according to hirda->Init.Parity value - Set TE and RE bits according to hirda->Init.Mode value */ - MODIFY_REG(hirda->Instance->CR1, - ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)), - (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode); + Set the M bits according to hirda->Init.WordLength value + Set PCE and PS bits according to hirda->Init.Parity value + Set TE and RE bits according to hirda->Init.Mode value */ + /* Write to USART CR1 */ + SET_BIT(hirda->Instance->CR1, (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode); - /*------- IRDA-associated USART registers setting : CR3 Configuration ------*/ + /*-------------------------- USART CR3 Configuration -----------------------*/ /* Clear CTSE and RTSE bits */ - CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_RTSE | USART_CR3_CTSE); - /*------- IRDA-associated USART registers setting : BRR Configuration ------*/ + /*-------------------------- USART BRR Configuration -----------------------*/ if(hirda->Instance == USART1) { - hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate); + SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate)); } else { - hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate); + SET_BIT(hirda->Instance->BRR, IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate)); } } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.h index a339d2f97a7..983bc22e820 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_irda.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_hal_irda.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -57,7 +57,7 @@ /* Exported types ------------------------------------------------------------*/ /** @defgroup IRDA_Exported_Types IRDA Exported Types * @{ - */ + */ /** * @brief IRDA Init Structure definition @@ -79,8 +79,8 @@ typedef struct at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref IRDA_Transfer_Mode */ uint8_t Prescaler; /*!< Specifies the Prescaler value prescaler value to be programmed @@ -93,52 +93,100 @@ typedef struct }IRDA_InitTypeDef; /** - * @brief HAL IRDA State structures definition + * @brief HAL IRDA State structures definition + * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState. + * - gState contains IRDA state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized. HAL IRDA Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef enum { - HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_IRDA_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */ + HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing + Value is allowed for gState only */ + HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ }HAL_IRDA_StateTypeDef; - /** - * @brief IRDA handle Structure definition + * @brief IRDA handle Structure definition */ typedef struct { USART_TypeDef *Instance; /*!< USART registers base address */ - + IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ - + uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ - + uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ - - uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */ - + + __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */ + uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */ - + uint16_t RxXferSize; /*!< IRDA Rx Transfer size */ - - uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */ - + + __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */ + DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */ - + DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */ - + HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_IRDA_StateTypeDef State; /*!< IRDA communication state */ - - __IO uint32_t ErrorCode; /*!< IRDA Error code */ - + + __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ + + __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations. + This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< IRDA Error code */ }IRDA_HandleTypeDef; /** @@ -149,44 +197,39 @@ typedef struct /** @defgroup IRDA_Exported_Constants IRDA Exported constants * @{ */ - -/** @defgroup IRDA_Error_Codes IRDA Error Codes +/** @defgroup IRDA_Error_Code IRDA Error Code * @{ - */ -#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_IRDA_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ -#define HAL_IRDA_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ -#define HAL_IRDA_ERROR_FE ((uint32_t)0x04) /*!< frame error */ -#define HAL_IRDA_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ -#define HAL_IRDA_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ - + */ +#define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */ +#define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */ +#define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */ +#define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */ /** * @} */ - /** @defgroup IRDA_Word_Length IRDA Word Length * @{ */ -#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) +#define IRDA_WORDLENGTH_8B 0x00000000U #define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /** * @} */ - -/** @defgroup IRDA_Parity IRDA Parity +/** @defgroup IRDA_Parity IRDA Parity * @{ */ -#define IRDA_PARITY_NONE ((uint32_t)0x00000000) +#define IRDA_PARITY_NONE 0x00000000U #define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) #define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /** * @} */ - -/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode +/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode * @{ */ #define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) @@ -196,11 +239,11 @@ typedef struct * @} */ -/** @defgroup IRDA_Low_Power IRDA Low Power +/** @defgroup IRDA_Low_Power IRDA Low Power * @{ */ -#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) -#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) +#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) +#define IRDA_POWERMODE_NORMAL 0x00000000U /** * @} */ @@ -224,26 +267,23 @@ typedef struct /** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask (16 bits) in the Y register - * - Y : Interrupt source register (4 bits) - * - 0001: CR1 register - * - 0010: CR2 register - * - 0011: CR3 register - * + * - XXXX : Interrupt mask in the XX register + * - Y : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register * @{ */ +#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) +#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) +#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) +#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) +#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) -#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_PEIE)) -#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TXEIE)) -#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_TCIE)) -#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE)) -#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE)) - -#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28 | USART_CR2_LBDIE)) - -#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_CTSIE)) -#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28 | USART_CR3_EIE)) +#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) +#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) +#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE)) /** * @} */ @@ -252,19 +292,20 @@ typedef struct * @} */ - /* Exported macro ------------------------------------------------------------*/ /** @defgroup IRDA_Exported_Macros IRDA Exported Macros * @{ */ -/** @brief Reset IRDA handle state +/** @brief Reset IRDA handle gstate & RxState * @param __HANDLE__: specifies the IRDA Handle. * IRDA Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None */ -#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET) +#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ + } while(0U) /** @brief Flush the IRDA DR register * @param __HANDLE__: specifies the USART Handle. @@ -309,7 +350,6 @@ typedef struct * USART_SR register followed by a write operation to USART_DR register. * @note TXE flag is cleared only by a write to the USART_DR register. * - * @retval None */ #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) @@ -317,21 +357,19 @@ typedef struct * @param __HANDLE__: specifies the IRDA Handle. * IRDA Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \ -do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - tmpreg = (__HANDLE__)->Instance->DR; \ - UNUSED(tmpreg); \ - }while(0) \ - + */ +#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ + } while(0U) + /** @brief Clear the IRDA FE pending flag. * @param __HANDLE__: specifies the IRDA Handle. * IRDA Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None */ #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) @@ -339,7 +377,6 @@ do{ \ * @param __HANDLE__: specifies the IRDA Handle. * IRDA Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None */ #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) @@ -347,7 +384,6 @@ do{ \ * @param __HANDLE__: specifies the IRDA Handle. * IRDA Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None */ #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) @@ -355,7 +391,6 @@ do{ \ * @param __HANDLE__: specifies the IRDA Handle. * IRDA Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None */ #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) @@ -371,12 +406,10 @@ do{ \ * @arg IRDA_IT_IDLE: Idle line detection interrupt * @arg IRDA_IT_PE: Parity Error interrupt * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK))) - /** @brief Disable the specified IRDA interrupt. * @param __HANDLE__: specifies the IRDA Handle. * IRDA Handle selects the USARTx or UARTy peripheral @@ -389,10 +422,9 @@ do{ \ * @arg IRDA_IT_IDLE: Idle line detection interrupt * @arg IRDA_IT_PE: Parity Error interrupt * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK))) /** @brief Check whether the specified IRDA interrupt has occurred or not. @@ -409,22 +441,20 @@ do{ \ * @arg IRDA_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:((((__IT__) >> 28) == IRDA_CR2_REG_INDEX)? \ +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK)) /** @brief Enable UART/USART associated to IRDA Handle * @param __HANDLE__: specifies the IRDA Handle. * IRDA Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None - */ + */ #define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) /** @brief Disable UART/USART associated to IRDA Handle * @param __HANDLE__: specifies the IRDA Handle. * IRDA Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None */ #define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) @@ -432,80 +462,27 @@ do{ \ * @} */ -/* Private macros --------------------------------------------------------*/ -/** @defgroup IRDA_Private_Macros IRDA Private Macros - * @{ - */ - -#define IRDA_CR1_REG_INDEX 1 -#define IRDA_CR2_REG_INDEX 2 -#define IRDA_CR3_REG_INDEX 3 - -#define IRDA_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) -#define IRDA_DIVMANT(__PCLK__, __BAUD__) (IRDA_DIV((__PCLK__), (__BAUD__))/100) -#define IRDA_DIVFRAQ(__PCLK__, __BAUD__) (((IRDA_DIV((__PCLK__), (__BAUD__)) - (IRDA_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) -/* UART BRR = mantissa + overflow + fraction - = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */ -#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4) + \ - (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0)) + \ - (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F)) - -/** Ensure that IRDA Baud rate is less or equal to maximum value - * __BAUDRATE__: specifies the IRDA Baudrate set by the user. - * The maximum Baud Rate is 115200bps - * Returns : True or False - */ -#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201) - -#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \ - ((LENGTH) == IRDA_WORDLENGTH_9B)) - -#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \ - ((PARITY) == IRDA_PARITY_EVEN) || \ - ((PARITY) == IRDA_PARITY_ODD)) - -#define IS_IRDA_MODE(MODE) ((((MODE) & (~((uint32_t)IRDA_MODE_TX_RX))) == 0x00) && \ - ((MODE) != (uint32_t)0x00000000)) - -#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \ - ((MODE) == IRDA_POWERMODE_NORMAL)) - -/** IRDA interruptions flag mask - * - */ -#define IRDA_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ - USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE ) - -/** - * @} - */ - - /* Exported functions --------------------------------------------------------*/ - -/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions +/** @addtogroup IRDA_Exported_Functions * @{ */ -/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions +/** @addtogroup IRDA_Exported_Functions_Group1 * @{ */ - -/* Initialization and de-initialization functions ****************************/ +/* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda); void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); - /** * @} */ -/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions +/** @addtogroup IRDA_Exported_Functions_Group2 * @{ */ - -/* IO operation functions *****************************************************/ +/* IO operation functions *******************************************************/ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); @@ -515,29 +492,92 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda); + void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda); void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); +/** + * @} + */ + +/** @addtogroup IRDA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); +/** + * @} + */ /** * @} */ -/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup IRDA_Private_Constants IRDA Private Constants * @{ */ -/* Peripheral State and Error functions ***************************************/ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); +/** @brief IRDA interruptions flag mask + * + */ +#define IRDA_IT_MASK 0x0000FFFFU +#define IRDA_CR1_REG_INDEX 1U +#define IRDA_CR2_REG_INDEX 2U +#define IRDA_CR3_REG_INDEX 3U /** * @} */ +/* Private macros --------------------------------------------------------*/ +/** @defgroup IRDA_Private_Macros IRDA Private Macros + * @{ + */ +#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \ + ((LENGTH) == IRDA_WORDLENGTH_9B)) +#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \ + ((PARITY) == IRDA_PARITY_EVEN) || \ + ((PARITY) == IRDA_PARITY_ODD)) +#define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U)) +#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \ + ((MODE) == IRDA_POWERMODE_NORMAL)) +#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U) + +#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_))) +#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U) +#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ +#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \ + (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \ + (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup IRDA_Private_Functions IRDA Private Functions + * @{ + */ + /** * @} */ @@ -549,7 +589,7 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c index 1919221a66e..debd2aed9b8 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c @@ -2,66 +2,73 @@ ****************************************************************************** * @file stm32f1xx_hal_iwdg.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief IWDG HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: - * + Initialization and Configuration functions + * + Initialization and Start functions * + IO operation functions - * + Peripheral State functions - @verbatim -================================================================================ - ##### IWDG specific features ##### -================================================================================ - [..] + * + @verbatim + ============================================================================== + ##### IWDG Generic features ##### + ============================================================================== + [..] (+) The IWDG can be started by either software or hardware (configurable through option byte). - (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and - thus stays active even if the main clock fails. - (+) Once the IWDG is started, the LSI is forced ON and cannot be disabled - (LSI cannot be disabled too), and the counter starts counting down from - the reset value of 0xFFF. When it reaches the end of count value (0x000) - a system reset is generated. - (+) The IWDG counter should be refreshed at regular intervals, otherwise the - watchdog generates an MCU reset when the counter reaches 0. + + (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even + if the main clock fails. + + (+) Once the IWDG is started, the LSI is forced ON and both can not be + disabled. The counter starts counting down from the reset value (0xFFF). + When it reaches the end of count value (0x000) a reset signal is + generated (IWDG reset). + + (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, + the IWDG_RLR value is reloaded in the counter and the watchdog reset is + prevented. + (+) The IWDG is implemented in the VDD voltage domain that is still functional in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - (+) IWDGRST flag in RCC_CSR register can be used to inform when an IWDG + IWDGRST flag in RCC_CSR register can be used to inform when an IWDG reset occurs. - (+) Min-max timeout value at 40KHz (LSI): 0.1us / 26.2s . - The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx - devices provide the capability to measure the LSI frequency (LSI clock - connected internally to TIM5 CH4 input capture). The measured value - can be used to have an IWDG timeout with an acceptable accuracy. - For more information, please refer to the STM32F1xx Reference manual. - Note: LSI Calibration is only available on: High density, XL-density and Connectivity line devices. + (+) Debug mode : When the microcontroller enters debug mode (core halted), + the IWDG counter either continues to work normally or stops, depending + on DBG_IWDG_STOP configuration bit in DBG module, accessible through + __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros + + [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s + The IWDG timeout may vary due to LSI frequency dispersion. STM32F1xx + devices provide the capability to measure the LSI frequency (LSI clock + connected internally to TIM5 CH4 input capture). The measured value + can be used to have an IWDG timeout with an acceptable accuracy. ##### How to use this driver ##### ============================================================================== - [..] - (+) Use IWDG using HAL_IWDG_Init() function to : - (++) Enable write access to IWDG_PR, IWDG_RLR. - (++) Configure the IWDG prescaler, counter reload value. - This reload value will be loaded in the IWDG counter each time the counter - is reloaded, then the IWDG will start counting down from this value. - (+) Use IWDG using HAL_IWDG_Start() function to : - (++) Reload IWDG counter with value defined in the IWDG_RLR register. - (++) Start the IWDG, when the IWDG is used in software mode (no need - to enable the LSI, it will be enabled by hardware). - (+) Then the application program must refresh the IWDG counter at regular + [..] + (#) Use IWDG using HAL_IWDG_Init() function to : + (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI + clock is forced ON and IWDG counter starts downcounting. + (++) Enable write access to configuration register: IWDG_PR & IWDG_RLR. + (++) Configure the IWDG prescaler and counter reload value. This reload + value will be loaded in the IWDG counter each time the watchdog is + reloaded, then the IWDG will start counting down from this value. + (++) wait for status flags to be reset" + + (#) Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using - HAL_IWDG_Refresh() function. - + HAL_IWDG_Refresh() function. + *** IWDG HAL driver macros list *** ==================================== [..] - Below the list of most used macros in IWDG HAL driver. - + Below the list of most used macros in IWDG HAL driver: (+) __HAL_IWDG_START: Enable the IWDG peripheral - (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register - (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status + (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in + the reload register @endverbatim ****************************************************************************** @@ -75,7 +82,7 @@ * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. + * and/or other materials provided with the distribution * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. @@ -92,7 +99,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -101,22 +108,21 @@ * @{ */ +#ifdef HAL_IWDG_MODULE_ENABLED /** @defgroup IWDG IWDG * @brief IWDG HAL module driver. * @{ */ -#ifdef HAL_IWDG_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ - -/** @defgroup IWDG_Private_Constants IWDG Private Constants +/** @defgroup IWDG_Private_Defines IWDG Private Defines * @{ */ - -#define IWDG_DEFAULT_TIMEOUT (uint32_t)1000 - +/* Status register need 5 RC LSI divided by prescaler clock to be updated. With + higher prescaler (256), and according to HSI variation, we need to wait at + least 6 cycles so 48 ms. */ +#define HAL_IWDG_DEFAULT_TIMEOUT 48U /** * @} */ @@ -124,38 +130,41 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ -/** @defgroup IWDG_Exported_Functions IWDG Exported Functions +/** @addtogroup IWDG_Exported_Functions * @{ */ -/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim +/** @addtogroup IWDG_Exported_Functions_Group1 + * @brief Initialization and Start functions. + * +@verbatim =============================================================================== - ##### Initialization and de-initialization functions ##### + ##### Initialization and Start functions ##### =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the IWDG according to the specified parameters - in the IWDG_InitTypeDef and create the associated handle - (+) Initialize the IWDG MSP - (+) DeInitialize IWDG MSP - + [..] This section provides functions allowing to: + (+) Initialize the IWDG according to the specified parameters in the + IWDG_InitTypeDef of associated handle. + (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog + is reloaded in order to exit function with correct time base. + @endverbatim * @{ */ /** - * @brief Initializes the IWDG according to the specified - * parameters in the IWDG_InitTypeDef and creates the associated handle. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * @brief Initialize the IWDG according to the specified parameters in the + * IWDG_InitTypeDef and start watchdog. Before exiting function, + * watchdog is refreshed in order to have correct time base. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { + uint32_t tickstart; + /* Check the IWDG handle allocation */ if(hiwdg == NULL) { @@ -165,147 +174,33 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) /* Check the parameters */ assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); - assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); - - /* Check pending flag, if previous update not done, return error */ - if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET) - &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)) - { - return HAL_ERROR; - } - - if(hiwdg->State == HAL_IWDG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hiwdg->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ - HAL_IWDG_MspInit(hiwdg); - } - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_BUSY; - - /* Enable write access to IWDG_PR and IWDG_RLR registers */ - IWDG_ENABLE_WRITE_ACCESS(hiwdg); - - /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */ - MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler); - MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the IWDG MSP. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval None - */ -__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hiwdg); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_IWDG_MspInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start the IWDG. - (+) Refresh the IWDG. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the IWDG. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) -{ - /* Process Locked */ - __HAL_LOCK(hiwdg); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_BUSY; + assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); - /* Start the IWDG peripheral */ + /* Enable IWDG. LSI is turned on automaticaly */ __HAL_IWDG_START(hiwdg); - - /* Reload IWDG counter with value defined in the RLR register */ - __HAL_IWDG_RELOAD_COUNTER(hiwdg); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hiwdg); - - /* Return function status */ - return HAL_OK; -} -/** - * @brief Refreshes the IWDG. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) -{ - uint32_t tickstart = 0; - - /* Process Locked */ - __HAL_LOCK(hiwdg); + /* Enable write access to IWDG_PR and IWDG_RLR registers by writing 0x5555 in KR */ + IWDG_ENABLE_WRITE_ACCESS(hiwdg); - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_BUSY; + /* Write to IWDG registers the Prescaler & Reload values to work with */ + hiwdg->Instance->PR = hiwdg->Init.Prescaler; + hiwdg->Instance->RLR = hiwdg->Init.Reload; + /* Check pending flag, if previous update not done, return timeout */ tickstart = HAL_GetTick(); - /* Wait until RVU flag is RESET */ - while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) + /* Wait for register to be updated */ + while(hiwdg->Instance->SR != RESET) { - if((HAL_GetTick() - tickstart ) > IWDG_DEFAULT_TIMEOUT) + if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT) { - /* Set IWDG state */ - hiwdg->State = HAL_IWDG_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hiwdg); - return HAL_TIMEOUT; } } - + /* Reload IWDG counter with value defined in the reload register */ __HAL_IWDG_RELOAD_COUNTER(hiwdg); - - /* Change IWDG peripheral state */ - hiwdg->State = HAL_IWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hiwdg); - + /* Return function status */ return HAL_OK; } @@ -314,30 +209,33 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) * @} */ -/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim +/** @addtogroup IWDG_Exported_Functions_Group2 + * @brief IO operation functions + * +@verbatim =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Refresh the IWDG. @endverbatim * @{ */ /** - * @brief Returns the IWDG state. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains + * @brief Refresh the IWDG. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains * the configuration information for the specified IWDG module. - * @retval HAL state + * @retval HAL status */ -HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg) +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) { - return hiwdg->State; + /* Reload IWDG counter with value defined in the reload register */ + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + + /* Return function status */ + return HAL_OK; } /** diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.h index 4a8c682609b..af20632cc2d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_iwdg.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_IWDG_H @@ -52,53 +52,35 @@ /** @addtogroup IWDG * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ - /** @defgroup IWDG_Exported_Types IWDG Exported Types * @{ */ /** - * @brief IWDG HAL State Structure definition - */ -typedef enum -{ - HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */ - HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */ - HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */ - HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */ - HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */ - -}HAL_IWDG_StateTypeDef; - -/** - * @brief IWDG Init structure definition - */ + * @brief IWDG Init structure definition + */ typedef struct { - uint32_t Prescaler; /*!< Select the prescaler of the IWDG. + uint32_t Prescaler; /*!< Select the prescaler of the IWDG. This parameter can be a value of @ref IWDG_Prescaler */ - - uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. + + uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ -}IWDG_InitTypeDef; +} IWDG_InitTypeDef; -/** - * @brief IWDG Handle Structure definition - */ +/** + * @brief IWDG Handle Structure definition + */ typedef struct { - IWDG_TypeDef *Instance; /*!< Register base address */ - + IWDG_TypeDef *Instance; /*!< Register base address */ + IWDG_InitTypeDef Init; /*!< IWDG required parameters */ - - HAL_LockTypeDef Lock; /*!< IWDG Locking object */ - - __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */ - + }IWDG_HandleTypeDef; /** @@ -106,190 +88,149 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ - /** @defgroup IWDG_Exported_Constants IWDG Exported Constants * @{ */ -/** @defgroup IWDG_Registers_BitMask IWDG Registers BitMask - * @brief IWDG registers bit mask +/** @defgroup IWDG_Prescaler IWDG Prescaler * @{ */ -/* --- KR Register ---*/ -/* KR register bit mask */ -#define IWDG_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */ -#define IWDG_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */ -#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */ -#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */ - +#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */ +#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ +#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ +#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ +#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ +#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ +#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ /** * @} */ -/** @defgroup IWDG_Flag_definition IWDG Flag definition - * @{ - */ -#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update Flag */ -#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update Flag */ - /** * @} */ -/** @defgroup IWDG_Prescaler IWDG Prescaler + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Macros IWDG Exported Macros * @{ - */ -#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */ -#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */ -#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */ -#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */ -#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */ -#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */ -#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */ + */ /** - * @} - */ + * @brief Enable the IWDG peripheral. + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) +/** + * @brief Reload IWDG counter with value defined in the reload register + * (write access to IWDG_PR & IWDG_RLR registers disabled). + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) /** * @} */ -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Macros IWDG Exported Macros +/* Exported functions --------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Functions IWDG Exported Functions * @{ */ -/** @brief Reset IWDG handle state - * @param __HANDLE__: IWDG handle. - * @retval None +/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions + * @{ */ -#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET) - +/* Initialization/Start functions ********************************************/ +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); /** - * @brief Enables the IWDG peripheral. - * @param __HANDLE__: IWDG handle - * @retval None + * @} */ -#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) +/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions + * @{ + */ +/* I/O operation functions ****************************************************/ +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param __HANDLE__: IWDG handle - * @retval None + * @} */ -#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup IWDG_Private_Constants IWDG Private Constants + * @{ + */ /** - * @brief Gets the selected IWDG's flag status. - * @param __HANDLE__: IWDG handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag - * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag - * @retval The new state of __FLAG__ (TRUE or FALSE). + * @brief IWDG Key Register BitMask */ -#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) +#define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ +#define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ +#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ +#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ /** * @} - */ - -/* Private macro -------------------------------------------------------------*/ + */ +/* Private macros ------------------------------------------------------------*/ /** @defgroup IWDG_Private_Macros IWDG Private Macros * @{ */ - /** - * @brief Enables write access to IWDG_PR and IWDG_RLR registers. - * @param __HANDLE__: IWDG handle + * @brief Enable write access to IWDG_PR and IWDG_RLR registers. + * @param __HANDLE__ IWDG handle * @retval None */ -#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) +#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) /** - * @brief Disables write access to IWDG_PR and IWDG_RLR registers. - * @param __HANDLE__: IWDG handle + * @brief Disable write access to IWDG_PR and IWDG_RLR registers. + * @param __HANDLE__ IWDG handle * @retval None */ #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) - -#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ - ((__PRESCALER__) == IWDG_PRESCALER_8) || \ - ((__PRESCALER__) == IWDG_PRESCALER_16) || \ - ((__PRESCALER__) == IWDG_PRESCALER_32) || \ - ((__PRESCALER__) == IWDG_PRESCALER_64) || \ - ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ - ((__PRESCALER__) == IWDG_PRESCALER_256)) - - -#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF) - - /** - * @} - */ - - - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup IWDG_Exported_Functions - * @{ + * @brief Check IWDG prescaler value. + * @param __PRESCALER__ IWDG prescaler value + * @retval None */ +#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ + ((__PRESCALER__) == IWDG_PRESCALER_8) || \ + ((__PRESCALER__) == IWDG_PRESCALER_16) || \ + ((__PRESCALER__) == IWDG_PRESCALER_32) || \ + ((__PRESCALER__) == IWDG_PRESCALER_64) || \ + ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ + ((__PRESCALER__) == IWDG_PRESCALER_256)) -/** @addtogroup IWDG_Exported_Functions_Group1 - * @{ +/** + * @brief Check IWDG reload value. + * @param __RELOAD__ IWDG reload value + * @retval None */ -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); -void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); +#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) /** * @} */ - -/** @addtogroup IWDG_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg); -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @} */ - -/** @addtogroup IWDG_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); /** * @} - */ + */ -/** - * @} - */ - -/** - * @} - */ -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_mmc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_mmc.c new file mode 100644 index 00000000000..61001b49195 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_mmc.c @@ -0,0 +1,2598 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_mmc.c + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief MMC card HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (MMC) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + MMC card Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + the user in HAL_MMC_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDMMC memories which uses the HAL + SDMMC driver functions to interface with MMC and eMMC cards devices. + It is used as follows: + + (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API: + (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); + (##) SDMMC pins configuration for MMC card + (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) DMA Configuration if you need to use DMA process (HAL_MMC_ReadBlocks_DMA() + and HAL_MMC_WriteBlocks_DMA() APIs). + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); + (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. + (##) NVIC configuration if you need to use interrupt process when using DMA transfer. + (+++) Configure the SDMMC and DMA interrupt priorities using functions + HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority + (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() + and __HAL_MMC_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() + and __HAL_MMC_CLEAR_IT() + (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT() + and HAL_MMC_WriteBlocks_IT() APIs). + (+++) Configure the SDMMC interrupt priorities using function + HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() + and __HAL_MMC_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() + and __HAL_MMC_CLEAR_IT() + (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization + + + *** MMC Card Initialization and configuration *** + ================================================ + [..] + To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes + SDMMC IP (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Initialize the SDMMC peripheral interface with defaullt configuration. + The initialization process is done at 400KHz. You can change or adapt + this frequency by adjusting the "ClockDiv" field. + The MMC Card frequency (SDMMC_CK) is computed as follows: + + SDMMC_CK = SDMMCCLK / (ClockDiv + 2) + + In initialization mode and according to the MMC Card standard, + make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. + + (#) Initialize the MMC card. The API used is HAL_MMC_InitCard(). + This phase allows the card initialization and identification + and check the MMC Card type (Standard Capacity or High Capacity) + The initialization flow is compatible with MMC standard. + + This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case + of plug-off plug-in. + + (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer + frequency is set to 24MHz. You can change or adapt this frequency by adjusting + the "ClockDiv" field. + In transfer mode and according to the MMC Card standard, make sure that the + SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. + To be able to use a frequency higher than 24MHz, you should use the SDMMC + peripheral in bypass mode. Refer to the corresponding reference manual + for more details. + + (#) Select the corresponding MMC Card according to the address read with the step 2. + + (#) Configure the MMC Card in wide bus mode: 4-bits data. + + *** MMC Card Read operation *** + ============================== + [..] + (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + + (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Rx interrupt event. + + (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Rx interrupt event. + + *** MMC Card Write operation *** + =============================== + [..] + (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + + (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Tx interrupt event. + + (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Tx interrupt event. + + *** MMC card status *** + ====================== + [..] + (+) The MMC Status contains status bits that are related to the MMC Memory + Card proprietary features. To get MMC card status use the HAL_MMC_GetCardStatus(). + + *** MMC card information *** + =========================== + [..] + (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo(). + It returns useful information about the MMC card such as block size, card type, + block number ... + + *** MMC card CSD register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. + + *** MMC card CID register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register. + Some of the CID parameters are useful for card initialization and identification. + + *** MMC HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in MMC HAL driver. + + (+) __HAL_MMC_ENABLE : Enable the MMC device + (+) __HAL_MMC_DISABLE : Disable the MMC device + (+) __HAL_MMC_DMA_ENABLE: Enable the SDMMC DMA transfer + (+) __HAL_MMC_DMA_DISABLE: Disable the SDMMC DMA transfer + (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt + (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt + (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not + (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags + + [..] + (@) You can refer to the MMC HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_hal.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @addtogroup MMC + * @{ + */ + +#ifdef HAL_MMC_MODULE_ENABLED + +#if defined(STM32F103xE) || defined(STM32F103xG) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup MMC_Private_Defines + * @{ + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Functions MMC Private Functions + * @{ + */ +static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus); +static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc); +static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc); +static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc); +static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void MMC_DMAError(DMA_HandleTypeDef *hdma); +static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma); +static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup MMC_Exported_Functions + * @{ + */ + +/** @addtogroup MMC_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the MMC + card device to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the MMC according to the specified parameters in the + MMC_HandleTypeDef and create the associated handle. + * @param hmmc: Pointer to the MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) +{ + /* Check the MMC handle allocation */ + if(hmmc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance)); + assert_param(IS_SDIO_CLOCK_EDGE(hmmc->Init.ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(hmmc->Init.ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(hmmc->Init.BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl)); + assert_param(IS_SDIO_CLKDIV(hmmc->Init.ClockDiv)); + + if(hmmc->State == HAL_MMC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hmmc->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_MMC_MspInit(hmmc); + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize the Card parameters */ + HAL_MMC_InitCard(hmmc); + + /* Initialize the error code */ + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; + + /* Initialize the MMC state */ + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the MMC Card. + * @param hmmc: Pointer to MMC handle + * @note This function initializes the MMC card. It could be used when a card + re-initialization is needed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate = HAL_MMC_ERROR_NONE; + MMC_InitTypeDef Init; + + /* Default SDMMC peripheral configuration for MMC card initialization */ + Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDIO_BUS_WIDE_1B; + Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + Init.ClockDiv = SDIO_INIT_CLK_DIV; + + /* Initialize SDMMC peripheral interface with default configuration */ + SDIO_Init(hmmc->Instance, Init); + + /* Disable SDMMC Clock */ + __HAL_MMC_DISABLE(hmmc); + + /* Set Power State to ON */ + SDIO_PowerState_ON(hmmc->Instance); + + /* Enable SDMMC Clock */ + __HAL_MMC_ENABLE(hmmc); + + /* Required power up waiting time before starting the SD initialization + sequence */ + HAL_Delay(2U); + + /* Identify card operating voltage */ + errorstate = MMC_PowerON(hmmc); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Card initialization */ + errorstate = MMC_InitCard(hmmc); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief De-Initializes the MMC card. + * @param hmmc: Pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) +{ + /* Check the MMC handle allocation */ + if(hmmc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDIO_ALL_INSTANCE(hmmc->Instance)); + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Set SD power state to off */ + MMC_PowerOFF(hmmc); + + /* De-Initialize the MSP layer */ + HAL_MMC_MspDeInit(hmmc); + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_RESET; + + return HAL_OK; +} + + +/** + * @brief Initializes the MMC MSP. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MMC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize MMC MSP. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MMC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup MMC_Exported_Functions_Group2 + * @brief Data transfer functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data + transfer from/to MMC card. + +@endverbatim + * @{ + */ + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param pData: pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of MMC blocks to read + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t tickstart = HAL_GetTick(); + uint32_t count = 0U, *tempbuff = (uint32_t *)pData; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockAdd *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hmmc->Instance, &config); + + /* Read block(s) in polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd); + } + else + { + hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK; + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ +#ifdef SDIO_STA_STBITERR + while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_STA_STBITERR)) +#else /* SDIO_STA_STBITERR not defined */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND)) +#endif /* SDIO_STA_STBITERR */ + { + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + *(tempbuff + count) = SDIO_ReadFIFO(hmmc->Instance); + } + tempbuff += 8U; + } + + if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock read */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Empty FIFO if there is still any data */ + while ((__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXDAVL))) + { + *tempbuff = SDIO_ReadFIFO(hmmc->Instance); + tempbuff++; + + if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to write block(s) to a specified address in a card. The Data + * transfer is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param pData: pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of MMC blocks to write + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t tickstart = HAL_GetTick(); + uint32_t count = 0U; + uint32_t *tempbuff = (uint32_t *)pData; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockAdd *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd); + } + else + { + hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK; + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hmmc->Instance, &config); + + /* Write block(s) in polling mode */ +#ifdef SDIO_STA_STBITERR + while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) +#else /* SDIO_STA_STBITERR not defined */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND)) +#endif /* SDIO_STA_STBITERR */ + { + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXFIFOHE)) + { + /* Write data to SDIO Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + SDIO_WriteFIFO(hmmc->Instance, (tempbuff + count)); + } + tempbuff += 8U; + } + + if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock write */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the IT transfer process through the MMC Rx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pRxBuffPtr = (uint32_t *)pData; + hmmc->RxXferSize = BLOCKSIZE * NumberOfBlocks; + + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF)); + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockAdd *= 512U; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hmmc->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Read Blocks in IT mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the IT transfer process through the MMC Tx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pTxBuffPtr = (uint32_t *)pData; + hmmc->TxXferSize = BLOCKSIZE * NumberOfBlocks; + + /* Enable transfer interrupts */ + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE)); + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockAdd *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd); + } + else + { + hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hmmc->Instance, &config); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the DMA transfer process through the MMC Rx + * interrupt event. + * @param hmmc: Pointer MMC handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + +#ifdef SDIO_STA_STBITER + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR)); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND)); +#endif /* SDIO_STA_STBITERR */ + + /* Set the DMA transfer complete callback */ + hmmc->hdmarx->XferCpltCallback = MMC_DMAReceiveCplt; + + /* Set the DMA error callback */ + hmmc->hdmarx->XferErrorCallback = MMC_DMAError; + + /* Set the DMA Abort callback */ + hmmc->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); + + /* Enable MMC DMA transfer */ + __HAL_MMC_DMA_ENABLE(hmmc); + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockAdd *= 512U; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hmmc->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, BlockAdd); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, BlockAdd); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the DMA transfer process through the MMC Tx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + /* Enable MMC Error interrupts */ +#ifdef SDIO_STA_STBITER + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR)); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR)); +#endif /* SDIO_STA_STBITERR */ + + /* Set the DMA transfer complete callback */ + hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt; + + /* Set the DMA error callback */ + hmmc->hdmatx->XferErrorCallback = MMC_DMAError; + + /* Set the DMA Abort callback */ + hmmc->hdmatx->XferAbortCallback = NULL; + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockAdd *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, BlockAdd); + } + else + { + hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, BlockAdd); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Enable SDIO DMA transfer */ + __HAL_MMC_DMA_ENABLE(hmmc); + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hmmc->Instance, &config); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Erases the specified memory area of the given MMC card. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd) +{ + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + + if(BlockEndAdd < BlockStartAdd) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(BlockEndAdd > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Check if the card command class supports erase command */ + if((hmmc->MmcCard.Class) & SDIO_CCCC_ERASE == 0U) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + if((SDIO_GetResponse(hmmc->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Check the Card capacity in term of Logical number of blocks */ + if ((hmmc->MmcCard.LogBlockNbr) < CAPACITY) + { + BlockStartAdd *= 512U; + BlockEndAdd *= 512U; + } + + /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ + errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, BlockStartAdd); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */ + errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, BlockEndAdd); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD38 ERASE */ + errorstate = SDMMC_CmdErase(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles MMC card interrupt request. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + /* Check for SDIO interrupt flags */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DATAEND) != RESET) + { + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_DATAEND); + +#ifdef SDIO_STA_STBITERR + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR | SDIO_IT_STBITERR); +#else /* SDIO_STA_STBITERR not defined */ + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR | SDIO_IT_RXOVERR); +#endif + + if((hmmc->Context & MMC_CONTEXT_IT) != RESET) + { + if(((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + HAL_MMC_ErrorCallback(hmmc); + } + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) + { + HAL_MMC_RxCpltCallback(hmmc); + } + else + { + HAL_MMC_TxCpltCallback(hmmc); + } + } + else if((hmmc->Context & MMC_CONTEXT_DMA) != RESET) + { + if((hmmc->Context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + HAL_MMC_ErrorCallback(hmmc); + } + } + if(((hmmc->Context & MMC_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hmmc->Context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == RESET)) + { + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the MMC DCTRL register */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + hmmc->State = HAL_MMC_STATE_READY; + + HAL_MMC_TxCpltCallback(hmmc); + } + } + } + + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXFIFOHE) != RESET) + { + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_TXFIFOHE); + + MMC_Write_IT(hmmc); + } + + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXFIFOHF) != RESET) + { + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_FLAG_RXFIFOHF); + + MMC_Read_IT(hmmc); + } + +#ifdef SDIO_STA_STBITERR + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR) != RESET) + { + /* Set Error code */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DTIMEOUT) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXOVERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXUNDERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_STBITERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + } + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS | SDIO_FLAG_STBITERR); + + /* Disable all interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR |SDIO_IT_STBITERR); + + if((hmmc->Context & MMC_CONTEXT_DMA) != RESET) + { + /* Abort the MMC DMA Streams */ + if(hmmc->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) + { + MMC_DMATxAbort(hmmc->hdmatx); + } + } + else if(hmmc->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) + { + MMC_DMARxAbort(hmmc->hdmarx); + } + } + else + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + HAL_MMC_AbortCallback(hmmc); + } + } + else if((hmmc->Context & MMC_CONTEXT_IT) != RESET) + { + /* Set the MMC state to ready to be able to start again the process */ + hmmc->State = HAL_MMC_STATE_READY; + HAL_MMC_ErrorCallback(hmmc); + } + } +#else /* SDIO_STA_STBITERR not defined */ + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR) != RESET) + { + /* Set Error code */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DCRCFAIL) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_DTIMEOUT) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_RXOVERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_IT_TXUNDERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + } + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + + /* Disable all interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); + + if((hmmc->Context & MMC_CONTEXT_DMA) != RESET) + { + /* Abort the MMC DMA Streams */ + if(hmmc->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) + { + MMC_DMATxAbort(hmmc->hdmatx); + } + } + else if(hmmc->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) + { + MMC_DMARxAbort(hmmc->hdmarx); + } + } + else + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + HAL_MMC_AbortCallback(hmmc); + } + } + else if((hmmc->Context & MMC_CONTEXT_IT) != RESET) + { + /* Set the MMC state to ready to be able to start again the process */ + hmmc->State = HAL_MMC_STATE_READY; + HAL_MMC_ErrorCallback(hmmc); + } + } +#endif /* SDIO_STA_STBITERR */ +} + +/** + * @brief return the MMC state + * @param hmmc: Pointer to mmc handle + * @retval HAL state + */ +HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) +{ + return hmmc->State; +} + +/** +* @brief Return the MMC error code +* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. +* @retval MMC Error Code +*/ +uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) +{ + return hmmc->ErrorCode; +} + +/** + * @brief Tx Transfer completed callbacks + * @param hmmc: Pointer to MMC handle + * @retval None + */ + __weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief MMC error callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief MMC Abort callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_ErrorCallback can be implemented in the user file + */ +} + + +/** + * @} + */ + +/** @addtogroup MMC_Exported_Functions_Group3 + * @brief management functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the MMC card + operations and get the related information + +@endverbatim + * @{ + */ + +/** + * @brief Returns information the information of the card which are stored on + * the CID register. + * @param hmmc: Pointer to MMC handle + * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that + * contains all CID register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +{ + uint32_t tmp = 0U; + + /* Byte 0 */ + tmp = (uint8_t)((hmmc->CID[0U] & 0xFF000000U) >> 24U); + pCID->ManufacturerID = tmp; + + /* Byte 1 */ + tmp = (uint8_t)((hmmc->CID[0U] & 0x00FF0000U) >> 16U); + pCID->OEM_AppliID = tmp << 8U; + + /* Byte 2 */ + tmp = (uint8_t)((hmmc->CID[0U] & 0x000000FF00U) >> 8U); + pCID->OEM_AppliID |= tmp; + + /* Byte 3 */ + tmp = (uint8_t)(hmmc->CID[0U] & 0x000000FFU); + pCID->ProdName1 = tmp << 24U; + + /* Byte 4 */ + tmp = (uint8_t)((hmmc->CID[1U] & 0xFF000000U) >> 24U); + pCID->ProdName1 |= tmp << 16U; + + /* Byte 5 */ + tmp = (uint8_t)((hmmc->CID[1U] & 0x00FF0000U) >> 16U); + pCID->ProdName1 |= tmp << 8U; + + /* Byte 6 */ + tmp = (uint8_t)((hmmc->CID[1U] & 0x0000FF00U) >> 8U); + pCID->ProdName1 |= tmp; + + /* Byte 7 */ + tmp = (uint8_t)(hmmc->CID[1U] & 0x000000FFU); + pCID->ProdName2 = tmp; + + /* Byte 8 */ + tmp = (uint8_t)((hmmc->CID[2U] & 0xFF000000U) >> 24U); + pCID->ProdRev = tmp; + + /* Byte 9 */ + tmp = (uint8_t)((hmmc->CID[2U] & 0x00FF0000U) >> 16U); + pCID->ProdSN = tmp << 24U; + + /* Byte 10 */ + tmp = (uint8_t)((hmmc->CID[2U] & 0x0000FF00U) >> 8U); + pCID->ProdSN |= tmp << 16U; + + /* Byte 11 */ + tmp = (uint8_t)(hmmc->CID[2U] & 0x000000FFU); + pCID->ProdSN |= tmp << 8U; + + /* Byte 12 */ + tmp = (uint8_t)((hmmc->CID[3U] & 0xFF000000U) >> 24U); + pCID->ProdSN |= tmp; + + /* Byte 13 */ + tmp = (uint8_t)((hmmc->CID[3U] & 0x00FF0000U) >> 16U); + pCID->Reserved1 |= (tmp & 0xF0U) >> 4U; + pCID->ManufactDate = (tmp & 0x0FU) << 8U; + + /* Byte 14 */ + tmp = (uint8_t)((hmmc->CID[3U] & 0x0000FF00U) >> 8U); + pCID->ManufactDate |= tmp; + + /* Byte 15 */ + tmp = (uint8_t)(hmmc->CID[3U] & 0x000000FFU); + pCID->CID_CRC = (tmp & 0xFEU) >> 1U; + pCID->Reserved2 = 1U; + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the CSD register. + * @param hmmc: Pointer to MMC handle + * @param pCSD: Pointer to a HAL_MMC_CardInfoTypeDef structure that + * contains all CSD register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD) +{ + uint32_t tmp = 0U; + + /* Byte 0 */ + tmp = (hmmc->CSD[0U] & 0xFF000000U) >> 24U; + pCSD->CSDStruct = (uint8_t)((tmp & 0xC0U) >> 6U); + pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U); + pCSD->Reserved1 = tmp & 0x03U; + + /* Byte 1 */ + tmp = (hmmc->CSD[0U] & 0x00FF0000U) >> 16U; + pCSD->TAAC = (uint8_t)tmp; + + /* Byte 2 */ + tmp = (hmmc->CSD[0U] & 0x0000FF00U) >> 8U; + pCSD->NSAC = (uint8_t)tmp; + + /* Byte 3 */ + tmp = hmmc->CSD[0U] & 0x000000FFU; + pCSD->MaxBusClkFrec = (uint8_t)tmp; + + /* Byte 4 */ + tmp = (hmmc->CSD[1U] & 0xFF000000U) >> 24U; + pCSD->CardComdClasses = (uint16_t)(tmp << 4U); + + /* Byte 5 */ + tmp = (hmmc->CSD[1U] & 0x00FF0000U) >> 16U; + pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0U) >> 4U); + pCSD->RdBlockLen = (uint8_t)(tmp & 0x0FU); + + /* Byte 6 */ + tmp = (hmmc->CSD[1U] & 0x0000FF00U) >> 8U; + pCSD->PartBlockRead = (uint8_t)((tmp & 0x80U) >> 7U); + pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U); + pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U); + pCSD->DSRImpl = (uint8_t)((tmp & 0x10U) >> 4U); + pCSD->Reserved2 = 0; /*!< Reserved */ + + pCSD->DeviceSize = (tmp & 0x03U) << 10U; + + /* Byte 7 */ + tmp = (uint8_t)(hmmc->CSD[1U] & 0x000000FFU); + pCSD->DeviceSize |= (tmp) << 2U; + + /* Byte 8 */ + tmp = (uint8_t)((hmmc->CSD[2U] & 0xFF000000U) >> 24U); + pCSD->DeviceSize |= (tmp & 0xC0U) >> 6U; + + pCSD->MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U; + pCSD->MaxRdCurrentVDDMax = (tmp & 0x07U); + + /* Byte 9 */ + tmp = (uint8_t)((hmmc->CSD[2U] & 0x00FF0000U) >> 16U); + pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U; + pCSD->MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U; + pCSD->DeviceSizeMul = (tmp & 0x03U) << 1U; + /* Byte 10 */ + tmp = (uint8_t)((hmmc->CSD[2] & 0x0000FF00U) >> 8U); + pCSD->DeviceSizeMul |= (tmp & 0x80U) >> 7U; + + hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hmmc->MmcCard.BlockNbr *= (1U << (pCSD->DeviceSizeMul + 2U)); + hmmc->MmcCard.BlockSize = 1U << (pCSD->RdBlockLen); + + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); + hmmc->MmcCard.LogBlockSize = 512U; + + pCSD->EraseGrSize = (tmp & 0x40U) >> 6U; + pCSD->EraseGrMul = (tmp & 0x3FU) << 1U; + + /* Byte 11 */ + tmp = (uint8_t)(hmmc->CSD[2U] & 0x000000FFU); + pCSD->EraseGrMul |= (tmp & 0x80U) >> 7U; + pCSD->WrProtectGrSize = (tmp & 0x7FU); + + /* Byte 12 */ + tmp = (uint8_t)((hmmc->CSD[3U] & 0xFF000000U) >> 24U); + pCSD->WrProtectGrEnable = (tmp & 0x80U) >> 7U; + pCSD->ManDeflECC = (tmp & 0x60U) >> 5U; + pCSD->WrSpeedFact = (tmp & 0x1CU) >> 2U; + pCSD->MaxWrBlockLen = (tmp & 0x03U) << 2U; + + /* Byte 13 */ + tmp = (uint8_t)((hmmc->CSD[3U] & 0x00FF0000U) >> 16U); + pCSD->MaxWrBlockLen |= (tmp & 0xC0U) >> 6U; + pCSD->WriteBlockPaPartial = (tmp & 0x20U) >> 5U; + pCSD->Reserved3 = 0U; + pCSD->ContentProtectAppli = (tmp & 0x01U); + + /* Byte 14 */ + tmp = (uint8_t)((hmmc->CSD[3U] & 0x0000FF00U) >> 8U); + pCSD->FileFormatGrouop = (tmp & 0x80U) >> 7U; + pCSD->CopyFlag = (tmp & 0x40U) >> 6U; + pCSD->PermWrProtect = (tmp & 0x20U) >> 5U; + pCSD->TempWrProtect = (tmp & 0x10U) >> 4U; + pCSD->FileFormat = (tmp & 0x0CU) >> 2U; + pCSD->ECC = (tmp & 0x03U); + + /* Byte 15 */ + tmp = (uint8_t)(hmmc->CSD[3U] & 0x000000FFU); + pCSD->CSD_CRC = (tmp & 0xFEU) >> 1U; + pCSD->Reserved4 = 1U; + + return HAL_OK; +} + +/** + * @brief Gets the MMC card info. + * @param hmmc: Pointer to MMC handle + * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that + * will contain the MMC card status information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +{ + pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); + pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); + pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd); + pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr); + pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize); + pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr); + pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize); + + return HAL_OK; +} + +/** + * @brief Enables wide bus operation for the requested card if supported by + * card. + * @param hmmc: Pointer to MMC handle + * @param WideMode: Specifies the MMC card wide bus mode + * This parameter can be one of the following values: + * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer + * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer + * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode) +{ + __IO uint32_t count = 0U; + SDIO_InitTypeDef Init; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t response = 0U, busy = 0U; + + /* Check the parameters */ + assert_param(IS_SDIO_BUS_WIDE(WideMode)); + + /* Chnage Satte */ + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Update Clock for Bus mode update */ + Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = WideMode; + Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + Init.ClockDiv = SDIO_INIT_CLK_DIV; + /* Initialize SDIO*/ + SDIO_Init(hmmc->Instance, Init); + + if(WideMode == SDIO_BUS_WIDE_8B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else if(WideMode == SDIO_BUS_WIDE_4B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else if(WideMode == SDIO_BUS_WIDE_1B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else + { + /* WideMode is not a valid argument*/ + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + } + + /* Check for switch error and violation of the trial number of sending CMD 13 */ + while(busy == 0U) + { + if(count++ == SDMMC_MAX_TRIAL) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + return HAL_ERROR; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Get command response */ + response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + + /* Get operating voltage*/ + busy = (((response >> 7U) == 1U) ? 0U : 1U); + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_DATATIMEOUT; + while((response & 0x00000100U) == 0U) + { + if(count-- == 0U) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + return HAL_ERROR; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Get command response */ + response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + } + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Configure the SDIO peripheral */ + Init.ClockEdge = hmmc->Init.ClockEdge; + Init.ClockBypass = hmmc->Init.ClockBypass; + Init.ClockPowerSave = hmmc->Init.ClockPowerSave; + Init.BusWide = WideMode; + Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl; + Init.ClockDiv = hmmc->Init.ClockDiv; + SDIO_Init(hmmc->Instance, Init); + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief Gets the current mmc card data state. + * @param hmmc: pointer to MMC handle + * @retval Card state + */ +HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef cardstate = HAL_MMC_CARD_TRANSFER; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t resp1 = 0U; + + errorstate = MMC_SendStatus(hmmc, &resp1); + if(errorstate != HAL_OK) + { + hmmc->ErrorCode |= errorstate; + } + + cardstate = (HAL_MMC_CardStateTypeDef)((resp1 >> 9U) & 0x0FU); + + return cardstate; +} + +/** + * @brief Abort the current transfer and disable the MMC. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information for MMC module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + + if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) + { + /* Disable the MMC DMA request */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + /* Abort the MMC DMA Tx Stream */ + if(hmmc->hdmatx != NULL) + { + HAL_DMA_Abort(hmmc->hdmatx); + } + /* Abort the MMC DMA Rx Stream */ + if(hmmc->hdmarx != NULL) + { + HAL_DMA_Abort(hmmc->hdmarx); + } + } + + hmmc->State = HAL_MMC_STATE_READY; + CardState = HAL_MMC_GetCardState(hmmc); + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + } + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Abort the current transfer and disable the MMC (IT mode). + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information for MMC module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + + if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) + { + /* Disable the MMC DMA request */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + /* Abort the MMC DMA Tx Stream */ + if(hmmc->hdmatx != NULL) + { + hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; + if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) + { + hmmc->hdmatx = NULL; + } + } + /* Abort the MMC DMA Rx Stream */ + if(hmmc->hdmarx != NULL) + { + hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; + if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) + { + hmmc->hdmarx = NULL; + } + } + } + + /* No transfer ongoing on both DMA channels*/ + if((hmmc->hdmatx == NULL) && (hmmc->hdmarx == NULL)) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + } + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + HAL_MMC_AbortCallback(hmmc); + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup MMC_Private_Functions + * @{ + */ + +/** + * @brief DMA MMC transmit process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + + /* Enable DATAEND Interrupt */ + __HAL_MMC_ENABLE_IT(hmmc, (SDIO_IT_DATAEND)); +} + +/** + * @brief DMA MMC receive process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + /* Send stop command in multiblock write */ + if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + HAL_MMC_ErrorCallback(hmmc); + } + } + + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the MMC DCTRL register */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + HAL_MMC_RxCpltCallback(hmmc); +} + +/** + * @brief DMA MMC communication error callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMAError(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + + if((hmmc->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hmmc->hdmatx->ErrorCode == HAL_DMA_ERROR_TE)) + { + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + + /* Disable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); + + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + CardState = HAL_MMC_GetCardState(hmmc); + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + } + + hmmc->State= HAL_MMC_STATE_READY; + } + + HAL_MMC_ErrorCallback(hmmc); +} + +/** + * @brief DMA MMC Tx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + + if(hmmc->hdmatx != NULL) + { + hmmc->hdmatx = NULL; + } + + /* All DMA channels are aborted */ + if(hmmc->hdmarx == NULL) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + HAL_MMC_AbortCallback(hmmc); + } + else + { + HAL_MMC_ErrorCallback(hmmc); + } + } + } +} + +/** + * @brief DMA MMC Rx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + + if(hmmc->hdmarx != NULL) + { + hmmc->hdmarx = NULL; + } + + /* All DMA channels are aborted */ + if(hmmc->hdmatx == NULL) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + HAL_MMC_AbortCallback(hmmc); + } + else + { + HAL_MMC_ErrorCallback(hmmc); + } + } + } +} + + +/** + * @brief Initializes the mmc card. + * @param hmmc: Pointer to MMC handle + * @retval MMC Card error state + */ +static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardCSDTypeDef CSD; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint16_t mmc_rca = 1; + + /* Check the power State */ + if(SDIO_GetPowerState(hmmc->Instance) == 0U) + { + /* Power off */ + return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + } + + /* Send CMD2 ALL_SEND_CID */ + errorstate = SDMMC_CmdSendCID(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card identification number data */ + hmmc->CID[0U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + hmmc->CID[1U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP2); + hmmc->CID[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3); + hmmc->CID[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4); + } + + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* MMC Card publishes its RCA. */ + errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get the MMC card RCA */ + hmmc->MmcCard.RelCardAdd = mmc_rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card Specific Data */ + hmmc->CSD[0U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + hmmc->CSD[1U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP2); + hmmc->CSD[2U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP3); + hmmc->CSD[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4); + } + + /* Get the Card Class */ + hmmc->MmcCard.Class = (SDIO_GetResponse(hmmc->Instance, SDIO_RESP2) >> 20U); + + /* Get CSD parameters */ + HAL_MMC_GetCardCSD(hmmc, &CSD); + + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Configure SDIO peripheral interface */ + SDIO_Init(hmmc->Instance, hmmc->Init); + + /* All cards are initialized */ + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Enquires cards about their operating voltage and configures clock + * controls and stores MMC information that will be needed in future + * in the MMC handle. + * @param hmmc: Pointer to MMC handle + * @retval error state + */ +static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) +{ + __IO uint32_t count = 0U; + uint32_t response = 0U, validvoltage = 0U; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + while(validvoltage == 0U) + { + if(count++ == SDMMC_MAX_VOLT_TRIAL) + { + return HAL_MMC_ERROR_INVALID_VOLTRANGE; + } + + /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */ + errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + } + + /* When power routine is finished and command returns valid voltage */ + if ((response & eMMC_HIGH_VOLTAGE_RANGE) == MMC_HIGH_VOLTAGE_RANGE) + { + /* When voltage range of the card is within 2.7V and 3.6V */ + hmmc->MmcCard.CardType = MMC_HIGH_VOLTAGE_CARD; + } + else + { + /* When voltage range of the card is within 1.65V and 1.95V or 2.7V and 3.6V */ + hmmc->MmcCard.CardType = MMC_DUAL_VOLTAGE_CARD; + } + + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Turns the SDIO output signals off. + * @param hmmc: Pointer to MMC handle + * @retval HAL status + */ +static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc) +{ + /* Set Power State to OFF */ + SDIO_PowerState_OFF(hmmc->Instance); + + return HAL_OK; +} + +/** + * @brief Returns the current card's status. + * @param hmmc: Pointer to MMC handle + * @param pCardStatus: pointer to the buffer that will contain the MMC card + * status (Card Status register) + * @retval error state + */ +static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) +{ + uint32_t errorstate = HAL_MMC_ERROR_NONE; + + if(pCardStatus == NULL) + { + return HAL_MMC_ERROR_PARAM; + } + + /* Send Status command */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); + if(errorstate != HAL_OK) + { + return errorstate; + } + + /* Get MMC card status */ + *pCardStatus = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Wrap up reading in non-blocking mode. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval HAL status + */ +static HAL_StatusTypeDef MMC_Read_IT(MMC_HandleTypeDef *hmmc) +{ + uint32_t count = 0U; + uint32_t* tmp; + + tmp = (uint32_t*)hmmc->pRxBuffPtr; + + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + *(tmp + count) = SDIO_ReadFIFO(hmmc->Instance); + } + + hmmc->pRxBuffPtr += 8U; + + return HAL_OK; +} + +/** + * @brief Wrap up writing in non-blocking mode. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval HAL status + */ +static HAL_StatusTypeDef MMC_Write_IT(MMC_HandleTypeDef *hmmc) +{ + uint32_t count = 0U; + uint32_t* tmp; + + tmp = (uint32_t*)hmmc->pTxBuffPtr; + + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + SDIO_WriteFIFO(hmmc->Instance, (tmp + count)); + } + + hmmc->pTxBuffPtr += 8U; + + return HAL_OK; +} + +/** + * @} + */ + +#endif /* STM32F103xE || STM32F103xG */ + +#endif /* HAL_MMC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_mmc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_mmc.h new file mode 100644 index 00000000000..7fa628e88ef --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_mmc.h @@ -0,0 +1,718 @@ +/** + ****************************************************************************** + * @file stm32f1xx_hal_mmc.h + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief Header file of MMC HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_HAL_MMC_H +#define __STM32F1xx_HAL_MMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F103xE) || defined(STM32F103xG) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_sdmmc.h" + +/** @addtogroup STM32F1xx_HAL_Driver + * @{ + */ + +/** @defgroup MMC MMC + * @brief MMC HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup MMC_Exported_Types MMC Exported Types + * @{ + */ + +/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure + * @{ + */ +typedef enum +{ + HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */ + HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */ + HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */ + HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */ + HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */ + HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */ + HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */ + HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */ +}HAL_MMC_StateTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure + * @{ + */ +typedef enum +{ + HAL_MMC_CARD_READY = 0x00000001U, /*!< Card state is ready */ + HAL_MMC_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */ + HAL_MMC_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */ + HAL_MMC_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */ + HAL_MMC_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */ + HAL_MMC_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */ + HAL_MMC_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */ + HAL_MMC_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */ + HAL_MMC_CARD_ERROR = 0x000000FFU /*!< Card response Error */ +}HAL_MMC_CardStateTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition + * @{ + */ +#define MMC_InitTypeDef SDIO_InitTypeDef +#define MMC_TypeDef SDIO_TypeDef + +/** + * @brief MMC Card Information Structure definition + */ +typedef struct +{ + uint32_t CardType; /*!< Specifies the card Type */ + + uint32_t Class; /*!< Specifies the class of the card class */ + + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ + + uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ + + uint32_t BlockSize; /*!< Specifies one block size in bytes */ + + uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ + + uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ + +}HAL_MMC_CardInfoTypeDef; + +/** + * @brief MMC handle Structure definition + */ +typedef struct +{ + MMC_TypeDef *Instance; /*!< MMC registers base address */ + + MMC_InitTypeDef Init; /*!< MMC required parameters */ + + HAL_LockTypeDef Lock; /*!< MMC locking object */ + + uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< MMC Tx Transfer size */ + + uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< MMC Rx Transfer size */ + + __IO uint32_t Context; /*!< MMC transfer context */ + + __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ + + __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ + + DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */ + + DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */ + + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ + + uint32_t CSD[4U]; /*!< MMC card specific data table */ + + uint32_t CID[4U]; /*!< MMC card identification number table */ + +}MMC_HandleTypeDef; + +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register + * @{ + */ +typedef struct +{ + __IO uint8_t CSDStruct; /*!< CSD structure */ + __IO uint8_t SysSpecVersion; /*!< System specification version */ + __IO uint8_t Reserved1; /*!< Reserved */ + __IO uint8_t TAAC; /*!< Data read access time 1 */ + __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ + __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ + __IO uint16_t CardComdClasses; /*!< Card command classes */ + __IO uint8_t RdBlockLen; /*!< Max. read data block length */ + __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ + __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ + __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ + __IO uint8_t DSRImpl; /*!< DSR implemented */ + __IO uint8_t Reserved2; /*!< Reserved */ + __IO uint32_t DeviceSize; /*!< Device Size */ + __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ + __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ + __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ + __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ + __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ + __IO uint8_t EraseGrSize; /*!< Erase group size */ + __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ + __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ + __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ + __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ + __IO uint8_t WrSpeedFact; /*!< Write speed factor */ + __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ + __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ + __IO uint8_t Reserved3; /*!< Reserved */ + __IO uint8_t ContentProtectAppli; /*!< Content protection application */ + __IO uint8_t FileFormatGrouop; /*!< File format group */ + __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ + __IO uint8_t PermWrProtect; /*!< Permanent write protection */ + __IO uint8_t TempWrProtect; /*!< Temporary write protection */ + __IO uint8_t FileFormat; /*!< File format */ + __IO uint8_t ECC; /*!< ECC code */ + __IO uint8_t CSD_CRC; /*!< CSD CRC */ + __IO uint8_t Reserved4; /*!< Always 1 */ + +}HAL_MMC_CardCSDTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register + * @{ + */ +typedef struct +{ + __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ + __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ + __IO uint32_t ProdName1; /*!< Product Name part1 */ + __IO uint8_t ProdName2; /*!< Product Name part2 */ + __IO uint8_t ProdRev; /*!< Product Revision */ + __IO uint32_t ProdSN; /*!< Product Serial Number */ + __IO uint8_t Reserved1; /*!< Reserved1 */ + __IO uint16_t ManufactDate; /*!< Manufacturing Date */ + __IO uint8_t CID_CRC; /*!< CID CRC */ + __IO uint8_t Reserved2; /*!< Always 1 */ + +}HAL_MMC_CardCIDTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group6 MMC Card Status returned by ACMD13 + * @{ + */ +typedef struct +{ + __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */ + __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */ + __IO uint16_t CardType; /*!< Carries information about card type */ + __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */ + __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */ + __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */ + __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */ + __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */ + __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */ + __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */ + +}HAL_MMC_CardStatusTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup MMC_Exported_Constants Exported Constants + * @{ + */ + +#define BLOCKSIZE 512U /*!< Block size is 512 bytes */ + +#define CAPACITY 0x400000U /*!< Log Block Nuumber for 2 G bytes Cards */ + +/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition + * @{ + */ +#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration structure + * @{ + */ +#define MMC_CONTEXT_NONE 0x00000000U /*!< None */ +#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */ +#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */ +#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */ +#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */ +#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */ +#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */ +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode + * @{ + */ +/** + * @brief + */ +#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */ +#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */ +#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */ +#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */ +#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards + * @{ + */ +#define MMC_HIGH_VOLTAGE_CARD 0x00000000U +#define MMC_DUAL_VOLTAGE_CARD 0x00000001U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup MMC_Exported_macros MMC Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/** + * @brief Enable the MMC device. + * @retval None + */ +#define __HAL_MMC_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the MMC device. + * @retval None + */ +#define __HAL_MMC_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the MMC device interrupt. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval None + */ +#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the MMC device interrupt. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval None + */ +#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified MMC flag is set or not. + * @param __HANDLE__: MMC Handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @retval The new state of MMC FLAG (SET or RESET). + */ +#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the MMC's pending flags. + * @param __HANDLE__: MMC Handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @retval None + */ +#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified MMC interrupt has occurred or not. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval The new state of MMC IT (SET or RESET). + */ +#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Clear the MMC's interrupt pending bits. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval None + */ +#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MMC_Exported_Functions MMC Exported Functions + * @{ + */ + +/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc); +void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); +void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +/* Non-Blocking mode: IT */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); + +void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); + +/* Callback in non blocking modes (DMA) */ +void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions + * @{ + */ +HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup MMC_Private_Types MMC Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup MMC_Private_Defines MMC Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Variables MMC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Constants MMC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MMC_Private_Macros MMC Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Functions MMC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F103xE || STM32F103xG */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F1xx_HAL_MMC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.c index 1896069e27b..0509cb6cf12 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_nand.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device. @@ -14,7 +14,7 @@ ============================================================================== [..] This driver is a generic layered driver which contains a set of APIs used to - control NAND flash memories. It uses the FSMC/FSMC layer functions to interface + control NAND flash memories. It uses the FSMC layer functions to interface with NAND devices. This driver is used as follows: (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() @@ -25,9 +25,12 @@ structure declared by the function caller. (+) Access NAND flash memory by read/write operations using the functions - HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea() + HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(), + HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(), + HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(), + HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b() to read/write page(s)/spare area(s). These functions use specific device - information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef + information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef structure. The read/write address information is contained by the Nand_Address_Typedef structure passed as parameter. @@ -55,7 +58,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -119,16 +122,7 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup NAND_Private_Functions NAND Private Functions - * @{ - */ -static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - +/* Exported functions --------------------------------------------------------*/ /** @defgroup NAND_Exported_Functions NAND Exported Functions * @{ */ @@ -168,7 +162,6 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_Timing { /* Allocate lock resource and initialize it */ hnand->Lock = HAL_UNLOCKED; - /* Initialize the low level hardware (MSP) */ HAL_NAND_MspInit(hnand); } @@ -291,8 +284,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) /* Clear NAND interrupt FIFO empty pending bit */ __FSMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FSMC_FLAG_FEMPT); - } - + } } /** @@ -338,8 +330,9 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) */ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) { - __IO uint32_t data = 0; - uint32_t deviceaddress = 0; + __IO uint32_t data = 0U; + __IO uint32_t data1 = 0U; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -367,20 +360,34 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - /* Read the electronic signature from NAND flash */ - data = *(__IO uint32_t *)deviceaddress; - - /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1st_CYCLE(data); - pNAND_ID->Device_Id = ADDR_2nd_CYCLE(data); - pNAND_ID->Third_Id = ADDR_3rd_CYCLE(data); - pNAND_ID->Fourth_Id = ADDR_4th_CYCLE(data); + /* Read the electronic signature from NAND flash */ + if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) + { + data = *(__IO uint32_t *)deviceaddress; + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); + pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); + } + else + { + data = *(__IO uint32_t *)deviceaddress; + data1 = *((__IO uint32_t *)deviceaddress + 4U); + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1); + pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1); + } /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Process unlocked */ - __HAL_UNLOCK(hnand); + __HAL_UNLOCK(hnand); return HAL_OK; } @@ -393,18 +400,18 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN */ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) { - uint32_t deviceaddress = 0; - + uint32_t deviceaddress = 0U; + /* Process Locked */ __HAL_LOCK(hnand); - + /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } - /* Identify the device address */ + /* Identify the device address */ if(hnand->Init.NandBank == FSMC_NAND_BANK2) { deviceaddress = NAND_DEVICE1; @@ -414,25 +421,45 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) deviceaddress = NAND_DEVICE2; } - /* Update the NAND controller state */ + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; /* Send NAND reset command */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; - - - /* Update the NAND controller state */ + + + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Process unlocked */ - __HAL_UNLOCK(hnand); - + __HAL_UNLOCK(hnand); + return HAL_OK; + +} + +/** + * @brief Configure the device: Enter the physical parameters of the device + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +{ + hnand->Config.PageSize = pDeviceConfig->PageSize; + hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; + hnand->Config.BlockSize = pDeviceConfig->BlockSize; + hnand->Config.BlockNbr = pDeviceConfig->BlockNbr; + hnand->Config.PlaneSize = pDeviceConfig->PlaneSize; + hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr; + hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable; + return HAL_OK; } /** - * @brief Read Page(s) from NAND memory block + * @brief Read Page(s) from NAND memory block (8-bits addressing) * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure @@ -440,12 +467,142 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) * @param NumPageToRead : number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) { - __IO uint32_t index = 0; - uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS; - NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; + __IO uint32_t index = 0U; + uint32_t tickstart = 0U; + uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + if(hnand->Init.NandBank == FSMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) read loop */ + while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead); + + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512U) + { + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + + /* Check if an extra command is needed for reading pages */ + if(hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + } + + /* Get Data into Buffer */ + for(; index < size; index++) + { + *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; + } + + /* Increment read pages number */ + numPagesRead++; + + /* Decrement pages to read */ + NumPageToRead--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Read Page(s) from NAND memory block (16-bits addressing) + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress : pointer to NAND address structure + * @param pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned + * @param NumPageToRead : number of pages to read from block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) +{ + __IO uint32_t index = 0U; + uint32_t tickstart = 0U; + uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -469,50 +626,88 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; - /* Save the content of pAddress as it will be modified */ - nandaddress.Block = pAddress->Block; - nandaddress.Page = pAddress->Page; - nandaddress.Zone = pAddress->Zone; + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) read loop */ - while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) - { + while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { /* update the buffer size */ - size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread); - - /* Get the address offset */ - addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead); /* Send read page command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512U) + { + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset); + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } } *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + + if(hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + } + /* Get Data into Buffer */ for(; index < size; index++) { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; + *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress; } /* Increment read pages number */ - numpagesread++; + numPagesRead++; /* Decrement pages to read */ NumPageToRead--; /* Increment the NAND address */ - addressstatus = NAND_AddressIncrement(hnand, &nandaddress); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -522,11 +717,10 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType __HAL_UNLOCK(hnand); return HAL_OK; - } /** - * @brief Write Page(s) to NAND memory block + * @brief Write Page(s) to NAND memory block (8-bits addressing) * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure @@ -534,13 +728,11 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType * @param NumPageToWrite : number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) { - __IO uint32_t index = 0; - uint32_t tickstart = 0; - uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS; - NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; + __IO uint32_t index = 0U; + uint32_t tickstart = 0U; + uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -564,35 +756,56 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; - /* Save the content of pAddress as it will be modified */ - nandaddress.Block = pAddress->Block; - nandaddress.Page = pAddress->Page; - nandaddress.Zone = pAddress->Zone; + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) write loop */ - while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) - { + while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { /* update the buffer size */ - size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten); - - /* Get the address offset */ - addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); + size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten); /* Send write page command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset); + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } } + /* Write data to memory */ for(; index < size; index++) { @@ -601,39 +814,164 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Increment written pages number */ + numPagesWritten++; + + /* Decrement pages to write */ + NumPageToWrite--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} + +/** + * @brief Write Page(s) to NAND memory block (16-bits addressing) + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress : pointer to NAND address structure + * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned + * @param NumPageToWrite : number of pages to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite) +{ + __IO uint32_t index = 0U; + uint32_t tickstart = 0U; + uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + if(hnand->Init.NandBank == FSMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) write loop */ + while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten); + + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512U) + { + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } + + /* Write data to memory */ + for(; index < size; index++) + { + *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++; + } + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) { + /* Get tick */ + tickstart = HAL_GetTick(); + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { return HAL_TIMEOUT; } - } + } /* Increment written pages number */ - numpageswritten++; + numPagesWritten++; /* Decrement pages to write */ NumPageToWrite--; /* Increment the NAND address */ - addressstatus = NAND_AddressIncrement(hnand, &nandaddress); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Process unlocked */ - __HAL_UNLOCK(hnand); + __HAL_UNLOCK(hnand); return HAL_OK; } /** - * @brief Read Spare area(s) from NAND memory + * @brief Read Spare area(s) from NAND memory (8-bits addressing) * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure @@ -641,12 +979,11 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp * @param NumSpareAreaToRead: Number of spare area to read * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) { - __IO uint32_t index = 0; - uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS; - NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; + __IO uint32_t index = 0U; + uint32_t tickstart = 0U; + uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -670,50 +1007,230 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; - /* Save the content of pAddress as it will be modified */ - nandaddress.Block = pAddress->Block; - nandaddress.Page = pAddress->Page; - nandaddress.Zone = pAddress->Zone; + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnaddress = COLUMN_ADDRESS(hnand); /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS)) + while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read); + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead); + + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512U) + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } - /* Get the address offset */ - addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + + if(hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + } - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + /* Get Data into Buffer */ + for(; index < size; index++) + { + *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; + } + + /* Increment read spare areas number */ + numSpareAreaRead++; + + /* Decrement spare areas to read */ + NumSpareAreaToRead--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_OK; +} - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset); +/** + * @brief Read Spare area(s) from NAND memory (16-bits addressing) + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress : pointer to NAND address structure + * @param pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param NumSpareAreaToRead: Number of spare area to read + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) +{ + __IO uint32_t index = 0U; + uint32_t tickstart = 0U; + uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U; + + /* Process Locked */ + __HAL_LOCK(hnand); - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + if(hnand->Init.NandBank == FSMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U); + + /* Spare area(s) read loop */ + while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead); + + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset); - } + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + + if(hnand->Config.ExtraCommandEnable == ENABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + } /* Get Data into Buffer */ - for ( ;index < size; index++) + for(; index < size; index++) { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; + *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress; } /* Increment read spare areas number */ - num_spare_area_read++; + numSpareAreaRead++; /* Decrement spare areas to read */ NumSpareAreaToRead--; /* Increment the NAND address */ - addressstatus = NAND_AddressIncrement(hnand, &nandaddress); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -726,7 +1243,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres } /** - * @brief Write Spare area(s) to NAND memory + * @brief Write Spare area(s) to NAND memory (8-bits addressing) * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure @@ -734,13 +1251,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres * @param NumSpareAreaTowrite : number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { - __IO uint32_t index = 0; - uint32_t tickstart = 0; - uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS; - NAND_AddressTypeDef nandaddress; - uint32_t addressoffset = 0; + __IO uint32_t index = 0U; + uint32_t tickstart = 0U; + uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -764,33 +1279,60 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre /* Update the FSMC_NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; - /* Save the content of pAddress as it will be modified */ - nandaddress.Block = pAddress->Block; - nandaddress.Page = pAddress->Page; - nandaddress.Zone = pAddress->Zone; + /* Page address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnaddress = COLUMN_ADDRESS(hnand); /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) - { + while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { /* update the buffer size */ - size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written); - - /* Get the address offset */ - addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); - - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(addressoffset); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(addressoffset); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(addressoffset); + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } } /* Write data to memory */ @@ -814,13 +1356,13 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre } /* Increment written spare areas number */ - num_spare_area_written++; + numSpareAreaWritten++; /* Decrement spare areas to write */ NumSpareAreaTowrite--; /* Increment the NAND address */ - addressstatus = NAND_AddressIncrement(hnand, &nandaddress); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -829,6 +1371,138 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre /* Process unlocked */ __HAL_UNLOCK(hnand); + return HAL_OK; +} + +/** + * @brief Write Spare area(s) to NAND memory (16-bits addressing) + * @param hnand: pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @param pAddress : pointer to NAND address structure + * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param NumSpareAreaTowrite : number of spare areas to write to block + * @retval HAL status + */ +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +{ + __IO uint32_t index = 0U; + uint32_t tickstart = 0U; + uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U; + + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Check the NAND controller state */ + if(hnand->State == HAL_NAND_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Identify the device address */ + if(hnand->Init.NandBank == FSMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } + + /* Update the FSMC_NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U); + + /* Spare area(s) write loop */ + while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* update the buffer size */ + size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten); + + /* Cards with page size <= 512 bytes */ + if((hnand->Config.PageSize) <= 512U) + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } + else /* (hnand->Config.PageSize) > 512 */ + { + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + + if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + } + } + + /* Write data to memory */ + for(; index < size; index++) + { + *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++; + } + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + + /* Read status until NAND is ready */ + while(HAL_NAND_Read_Status(hnand) != NAND_READY) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Increment written spare areas number */ + numSpareAreaWritten++; + + /* Decrement spare areas to write */ + NumSpareAreaTowrite--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + return HAL_OK; } @@ -841,8 +1515,8 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre */ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { - uint32_t deviceaddress = 0; - uint32_t tickstart = 0; + uint32_t deviceaddress = 0U; + uint32_t tickstart = 0U; /* Process Locked */ __HAL_LOCK(hnand); @@ -869,15 +1543,9 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy /* Send Erase block command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1st_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2nd_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3rd_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - - /* for 512 and 1 GB devices, 4th cycle is required */ - if(hnand->Info.BlockNbr >= 1024) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4th_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - } + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; @@ -913,8 +1581,8 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy */ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) { - uint32_t data = 0; - uint32_t deviceaddress = 0; + uint32_t data = 0U; + uint32_t deviceaddress = 0U; /* Identify the device address */ if(hnand->Init.NandBank == FSMC_NAND_BANK2) @@ -962,17 +1630,17 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA pAddress->Page++; /* Check NAND address is valid */ - if(pAddress->Page == hnand->Info.BlockSize) + if(pAddress->Page == hnand->Config.BlockSize) { - pAddress->Page = 0; + pAddress->Page = 0U; pAddress->Block++; - if(pAddress->Block == hnand->Info.ZoneSize) + if(pAddress->Block == hnand->Config.PlaneSize) { - pAddress->Block = 0; - pAddress->Zone++; + pAddress->Block = 0U; + pAddress->Plane++; - if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr)) + if(pAddress->Plane == (hnand->Config.PlaneNbr)) { status = NAND_INVALID_ADDRESS; } @@ -1024,7 +1692,7 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) /* Update the NAND state */ hnand->State = HAL_NAND_STATE_READY; - return HAL_OK; + return HAL_OK; } /** @@ -1033,7 +1701,7 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) * the configuration information for NAND module. * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) +HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) { /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) @@ -1082,7 +1750,7 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, return status; } - + /** * @} */ @@ -1118,49 +1786,6 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) * @} */ -/** - * @} - */ - -/** @addtogroup NAND_Private_Functions - * @{ - */ - -/** - * @brief Increment the NAND memory address. - * @param hnand: pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param Address: address to be incremented. - * @retval The new status of the increment address operation. It can be: - * - NAND_VALID_ADDRESS: When the new address is valid address - * - NAND_INVALID_ADDRESS: When the new address is invalid address - */ -static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address) -{ - uint32_t status = NAND_VALID_ADDRESS; - - Address->Page++; - - if(Address->Page == hnand->Info.BlockSize) - { - Address->Page = 0; - Address->Block++; - - if(Address->Block == hnand->Info.ZoneSize) - { - Address->Block = 0; - Address->Zone++; - - if(Address->Zone == hnand->Info.BlockNbr) - { - status = NAND_INVALID_ADDRESS; - } - } - } - - return (status); -} - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.h index 0e37fb1fcfb..88eb5485e4d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nand.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_hal_nand.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -55,69 +55,6 @@ * @{ */ -/** @addtogroup NAND_Private_Constants - * @{ - */ - -#define NAND_DEVICE1 FSMC_BANK2 -#define NAND_DEVICE2 FSMC_BANK3 -#define NAND_WRITE_TIMEOUT ((uint32_t)1000) - -#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */ -#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */ - -#define NAND_CMD_AREA_A ((uint8_t)0x00) -#define NAND_CMD_AREA_B ((uint8_t)0x01) -#define NAND_CMD_AREA_C ((uint8_t)0x50) -#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) - -#define NAND_CMD_WRITE0 ((uint8_t)0x80) -#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) -#define NAND_CMD_ERASE0 ((uint8_t)0x60) -#define NAND_CMD_ERASE1 ((uint8_t)0xD0) -#define NAND_CMD_READID ((uint8_t)0x90) -#define NAND_CMD_STATUS ((uint8_t)0x70) -#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) -#define NAND_CMD_RESET ((uint8_t)0xFF) - -/* NAND memory status */ -#define NAND_VALID_ADDRESS ((uint32_t)0x00000100) -#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200) -#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400) -#define NAND_BUSY ((uint32_t)0x00000000) -#define NAND_ERROR ((uint32_t)0x00000001) -#define NAND_READY ((uint32_t)0x00000040) - -/** - * @} - */ - -/** @addtogroup NAND_Private_Macros - * @{ - */ - -/** - * @brief NAND memory address computation. - * @param __ADDRESS__: NAND memory address. - * @param __HANDLE__ : NAND handle. - * @retval NAND Raw address value - */ -#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ - (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize))) - -/** - * @brief NAND memory address cycling. - * @param __ADDRESS__: NAND memory address. - * @retval NAND address cycling value. - */ -#define ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ -#define ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ -#define ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ -#define ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ - -/** - * @} - */ /* Exported typedef ----------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ @@ -130,10 +67,10 @@ */ typedef enum { - HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */ - HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */ - HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */ - HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */ + HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ + HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ + HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ + HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ }HAL_NAND_StateTypeDef; /** @@ -157,11 +94,11 @@ typedef struct */ typedef struct { - uint16_t Page; /*!< NAND memory Page address */ + uint16_t Page; /*!< NAND memory Page address */ - uint16_t Zone; /*!< NAND memory Zone address */ + uint16_t Plane; /*!< NAND memory Plane address */ - uint16_t Block; /*!< NAND memory Block address */ + uint16_t Block; /*!< NAND memory Block address */ }NAND_AddressTypeDef; @@ -170,31 +107,43 @@ typedef struct */ typedef struct { - uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */ + uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes + for 8 bits adressing or words for 16 bits addressing */ - uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */ + uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes + for 8 bits adressing or words for 16 bits addressing */ + + uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ - uint32_t BlockSize; /*!< NAND memory block size number of pages */ + uint32_t BlockNbr; /*!< NAND memory number of total blocks */ + + uint32_t PlaneNbr; /*!< NAND memory number of planes */ - uint32_t BlockNbr; /*!< NAND memory number of blocks */ + uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */ - uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */ -}NAND_InfoTypeDef; + FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This + parameter is mandatory for some NAND parts after the read + command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. + Example: Toshiba THTH58BYG3S0HBAI6. + This parameter could be ENABLE or DISABLE + Please check the Read Mode sequnece in the NAND device datasheet */ +}NAND_DeviceConfigTypeDef; /** * @brief NAND handle Structure definition */ typedef struct { - FSMC_NAND_TypeDef *Instance; /*!< Register base address */ + FSMC_NAND_TypeDef *Instance; /*!< Register base address */ - FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ + FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ + + HAL_LockTypeDef Lock; /*!< NAND locking object */ - HAL_LockTypeDef Lock; /*!< NAND locking object */ + __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ - __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ + NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ - NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */ }NAND_HandleTypeDef; /** @@ -202,10 +151,10 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ /** @defgroup NAND_Exported_Macros NAND Exported Macros - * @{ - */ + * @{ + */ /** @brief Reset NAND handle state * @param __HANDLE__: specifies the NAND handle. @@ -229,10 +178,15 @@ typedef struct /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); -void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); -void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); -void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); + +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); + +HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); + +void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); +void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); +void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); +void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /** * @} @@ -243,15 +197,22 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); */ /* IO operation functions ****************************************************/ -HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); -HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); -uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); + +HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); + +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); +uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); +uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); /** * @} @@ -262,9 +223,9 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_Address */ /* NAND Control functions ****************************************************/ -HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); +HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); +HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); +HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); /** * @} @@ -282,6 +243,88 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); * @} */ +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup NAND_Private_Constants + * @{ + */ + +#define NAND_DEVICE1 FSMC_BANK2 +#define NAND_DEVICE2 FSMC_BANK3 +#define NAND_WRITE_TIMEOUT 1000U + +#define CMD_AREA (1U<<16U) /* A16 = CLE high */ +#define ADDR_AREA (1U<<17U) /* A17 = ALE high */ + +#define NAND_CMD_AREA_A ((uint8_t)0x00) +#define NAND_CMD_AREA_B ((uint8_t)0x01) +#define NAND_CMD_AREA_C ((uint8_t)0x50) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) + +#define NAND_CMD_WRITE0 ((uint8_t)0x80) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) +#define NAND_CMD_ERASE0 ((uint8_t)0x60) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0) +#define NAND_CMD_READID ((uint8_t)0x90) +#define NAND_CMD_STATUS ((uint8_t)0x70) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) +#define NAND_CMD_RESET ((uint8_t)0xFF) + +/* NAND memory status */ +#define NAND_VALID_ADDRESS 0x00000100U +#define NAND_INVALID_ADDRESS 0x00000200U +#define NAND_TIMEOUT_ERROR 0x00000400U +#define NAND_BUSY 0x00000000U +#define NAND_ERROR 0x00000001U +#define NAND_READY 0x00000040U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup NAND_Private_Macros + * @{ + */ + +/** + * @brief NAND memory address computation. + * @param __ADDRESS__: NAND memory address. + * @param __HANDLE__ : NAND handle. + * @retval NAND Raw address value + */ +#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ + (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) + +/** + * @brief NAND memory Column address computation. + * @param __HANDLE__: NAND handle. + * @retval NAND Raw address value + */ +#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) + +/** + * @brief NAND memory address cycling. + * @param __ADDRESS__: NAND memory address. + * @retval NAND address cycling value. + */ +#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ +#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd addressing cycle */ +#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16U) /* 3rd addressing cycle */ +#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24U) /* 4th addressing cycle */ + +/** + * @brief NAND memory Columns cycling. + * @param __ADDRESS__: NAND memory address. + * @retval NAND Column address cycling value. + */ +#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ +#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd Column addressing cycle */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.c index a6d9ad74ee2..9aa2df5633e 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_nor.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. @@ -295,6 +295,7 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnor); + UNUSED(Timeout); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NOR_MspWait could be implemented in the user file */ @@ -327,7 +328,7 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) */ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -387,7 +388,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I */ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -437,7 +438,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) */ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -496,7 +497,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint */ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -557,7 +558,7 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u */ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -595,10 +596,10 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET); /* Read buffer */ - while( uwBufferSize > 0) + while( uwBufferSize > 0U) { *pData++ = *(__IO uint16_t *)uwAddress; - uwAddress += 2; + uwAddress += 2U; uwBufferSize--; } @@ -629,7 +630,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr { uint16_t * p_currentaddress = (uint16_t *)NULL; uint16_t * p_endaddress = (uint16_t *)NULL; - uint32_t lastloadedaddress = 0, deviceaddress = 0; + uint32_t lastloadedaddress = 0U, deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -663,7 +664,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr /* Initialize variables */ p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); - p_endaddress = p_currentaddress + (uwBufferSize-1); + p_endaddress = p_currentaddress + (uwBufferSize-1U); lastloadedaddress = (uint32_t)(uwAddress); /* Issue unlock command sequence */ @@ -672,7 +673,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr /* Write Buffer Load Command */ NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG); - NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1)); + NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1U)); /* Load Data into NOR Buffer */ while(p_currentaddress <= p_endaddress) @@ -707,7 +708,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr */ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -766,7 +767,10 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd */ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { - uint32_t deviceaddress = 0; + /* Prevent unused argument(s) compilation warning */ + UNUSED(Address); + + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -824,7 +828,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) */ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) { - uint32_t deviceaddress = 0; + uint32_t deviceaddress = 0U; /* Process Locked */ __HAL_LOCK(hnor); @@ -985,7 +989,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres { HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; uint16_t tmp_sr1 = 0, tmp_sr2 = 0; - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ HAL_NOR_MspWait(hnor, Timeout); @@ -997,7 +1001,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { status = HAL_NOR_STATUS_TIMEOUT; } diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.h index fc0b0ffea6e..a577715d22a 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_nor.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention @@ -101,7 +101,7 @@ */ #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ - ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \ + ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) /** @@ -126,11 +126,11 @@ */ typedef enum { - HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */ - HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */ - HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */ - HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */ - HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */ + HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ + HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ + HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ + HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ + HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ }HAL_NOR_StateTypeDef; /** @@ -138,7 +138,7 @@ typedef enum */ typedef enum { - HAL_NOR_STATUS_SUCCESS = 0, + HAL_NOR_STATUS_SUCCESS = 0U, HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.c index 558a9b0a850..198e8041f73 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pccard.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief PCCARD HAL module driver. * This file provides a generic firmware to drive PCCARD memories mounted * as external device. @@ -95,9 +95,9 @@ * @{ */ -#define PCCARD_TIMEOUT_READ_ID (uint32_t)0x0000FFFF -#define PCCARD_TIMEOUT_SECTOR (uint32_t)0x0000FFFF -#define PCCARD_TIMEOUT_STATUS (uint32_t)0x01000000 +#define PCCARD_TIMEOUT_READ_ID 0x0000FFFFU +#define PCCARD_TIMEOUT_SECTOR 0x0000FFFFU +#define PCCARD_TIMEOUT_STATUS 0x01000000U #define PCCARD_STATUS_OK (uint8_t)0x58 #define PCCARD_STATUS_WRITE_OK (uint8_t)0x50 @@ -262,8 +262,8 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard) */ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus) { - uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0; - uint8_t status = 0; + uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -281,7 +281,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp *pStatus = PCCARD_READY; /* Send the Identify Command */ - *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECEC; + *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECECU; /* Read CF IDs and timeout treatment */ do @@ -292,14 +292,14 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp timeout--; }while((status != PCCARD_STATUS_OK) && timeout); - if(timeout == 0) + if(timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } else { /* Read CF ID bytes */ - for(index = 0; index < 16; index++) + for(index = 0U; index < 16U; index++) { CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA); } @@ -325,8 +325,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp */ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) { - uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0; - uint8_t status = 0; + uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -345,22 +345,22 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t /* Set the parameters to write a sector */ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00; - *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress); - *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0; + *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress); + *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0; do { /* wait till the Status = 0x80 */ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - }while((status == 0x80) && timeout); + }while((status == 0x80U) && timeout); - if(timeout == 0) + if(timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } - timeout = 0xFFFF; + timeout = 0xFFFFU; do { @@ -369,7 +369,7 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t timeout--; }while((status != PCCARD_STATUS_OK) && timeout); - if(timeout == 0) + if(timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } @@ -401,8 +401,8 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t */ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) { - uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0; - uint8_t status = 0; + uint32_t timeout = PCCARD_TIMEOUT_SECTOR, index = 0U; + uint8_t status = 0U; /* Process Locked */ __HAL_LOCK(hpccard); @@ -421,7 +421,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ /* Set the parameters to write a sector */ *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00; - *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100 ) | ((uint16_t)SectorAddress); + *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress); *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0; do @@ -431,7 +431,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ timeout--; }while((status != PCCARD_STATUS_OK) && timeout); - if(timeout == 0) + if(timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } @@ -449,7 +449,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ timeout--; }while((status != PCCARD_STATUS_WRITE_OK) && timeout); - if(timeout == 0) + if(timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } @@ -474,7 +474,7 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ */ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus) { - uint32_t timeout = 0x400; + uint32_t timeout = 0x400U; uint8_t status = 0; /* Process Locked */ @@ -509,7 +509,7 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16 timeout--; } - if(timeout == 0) + if(timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } @@ -684,7 +684,7 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard) timeout--; } - if(timeout == 0) + if(timeout == 0U) { status_cf = PCCARD_TIMEOUT_ERROR; } @@ -704,7 +704,7 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard) */ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard) { - uint8_t data = 0, status_cf = PCCARD_BUSY; + uint8_t data = 0U, status_cf = PCCARD_BUSY; /* Check the PCCARD controller state */ if(hpccard->State == HAL_PCCARD_STATE_BUSY) diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.h index 38a916f3cc7..e76a882f370 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pccard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pccard.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of PCCARD HAL module. ****************************************************************************** * @attention @@ -60,10 +60,10 @@ */ #define PCCARD_DEVICE_ADDRESS FSMC_BANK4 -#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x08000000)) /* Attribute space size to @0x9BFF FFFF */ +#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x08000000U)) /* Attribute space size to @0x9BFF FFFF */ #define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */ -#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x0C000000)) /* IO space size to @0x9FFF FFFF */ -#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FSMC_BANK4 + 0x0C0001F0)) /* IO space size to @0x9FFF FFFF */ +#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x0C000000U)) /* IO space size to @0x9FFF FFFF */ +#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FSMC_BANK4 + 0x0C0001F0U)) /* IO space size to @0x9FFF FFFF */ /* Compact Flash-ATA registers description */ #define ATA_DATA ((uint8_t)0x00) /* Data register */ @@ -89,7 +89,7 @@ #define PCCARD_PROGR ((uint8_t)0x01) #define PCCARD_READY ((uint8_t)0x40) -#define PCCARD_SECTOR_SIZE ((uint32_t)255) /* In half words */ +#define PCCARD_SECTOR_SIZE 255U /* In half words */ /* Compact Flash redefinition */ @@ -98,18 +98,17 @@ #define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector #define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector #define HAL_CF_Reset HAL_PCCARD_Reset - + #define HAL_CF_GetStatus HAL_PCCARD_GetStatus #define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus - + #define CF_SUCCESS HAL_PCCARD_STATUS_SUCCESS #define CF_ONGOING HAL_PCCARD_STATUS_ONGOING #define CF_ERROR HAL_PCCARD_STATUS_ERROR #define CF_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT #define CF_StatusTypedef HAL_PCCARD_StatusTypeDef - -#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS +#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS #define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS #define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS #define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS @@ -136,15 +135,15 @@ */ typedef enum { - HAL_PCCARD_STATE_RESET = 0x00, /*!< PCCARD peripheral not yet initialized or disabled */ - HAL_PCCARD_STATE_READY = 0x01, /*!< PCCARD peripheral ready */ - HAL_PCCARD_STATE_BUSY = 0x02, /*!< PCCARD peripheral busy */ - HAL_PCCARD_STATE_ERROR = 0x04 /*!< PCCARD peripheral error */ + HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */ + HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */ + HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */ + HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */ }HAL_PCCARD_StateTypeDef; typedef enum { - HAL_PCCARD_STATUS_SUCCESS = 0, + HAL_PCCARD_STATUS_SUCCESS = 0U, HAL_PCCARD_STATUS_ONGOING, HAL_PCCARD_STATUS_ERROR, HAL_PCCARD_STATUS_TIMEOUT diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.c index fe6211b1d5c..8e0ddbe30bd 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pcd.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -149,7 +149,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); */ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { - uint32_t index = 0; + uint32_t index = 0U; /* Check the PCD handle allocation */ if(hpcd == NULL) @@ -173,7 +173,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) /* Disable the Interrupts */ __HAL_PCD_DISABLE(hpcd); - + /*Init the Core (common init.) */ USB_CoreInit(hpcd->Instance, hpcd->Init); @@ -181,35 +181,35 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) USB_SetCurrentMode(hpcd->Instance , USB_DEVICE_MODE); /* Init endpoints structures */ - for (index = 0; index < 15 ; index++) + for (index = 0U; index < 15U ; index++) { /* Init ep structure */ - hpcd->IN_ep[index].is_in = 1; + hpcd->IN_ep[index].is_in = 1U; hpcd->IN_ep[index].num = index; hpcd->IN_ep[index].tx_fifo_num = index; /* Control until ep is actvated */ hpcd->IN_ep[index].type = EP_TYPE_CTRL; - hpcd->IN_ep[index].maxpacket = 0; - hpcd->IN_ep[index].xfer_buff = 0; - hpcd->IN_ep[index].xfer_len = 0; + hpcd->IN_ep[index].maxpacket = 0U; + hpcd->IN_ep[index].xfer_buff = 0U; + hpcd->IN_ep[index].xfer_len = 0U; } - - for (index = 0; index < 15 ; index++) + + for (index = 0U; index < 15U ; index++) { - hpcd->OUT_ep[index].is_in = 0; + hpcd->OUT_ep[index].is_in = 0U; hpcd->OUT_ep[index].num = index; hpcd->IN_ep[index].tx_fifo_num = index; /* Control until ep is activated */ hpcd->OUT_ep[index].type = EP_TYPE_CTRL; - hpcd->OUT_ep[index].maxpacket = 0; - hpcd->OUT_ep[index].xfer_buff = 0; - hpcd->OUT_ep[index].xfer_len = 0; + hpcd->OUT_ep[index].maxpacket = 0U; + hpcd->OUT_ep[index].xfer_buff = 0U; + hpcd->OUT_ep[index].xfer_len = 0U; } /* Init Device */ USB_DevInit(hpcd->Instance, hpcd->Init); - hpcd->USB_Address = 0; + hpcd->USB_Address = 0U; hpcd->State= HAL_PCD_STATE_READY; USB_DevDisconnect (hpcd->Instance); @@ -228,7 +228,7 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) { return HAL_ERROR; } - + hpcd->State = HAL_PCD_STATE_BUSY; /* Stop Device */ @@ -310,7 +310,7 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) * @retval HAL status */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) -{ +{ __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); USB_StopDevice(hpcd->Instance); @@ -328,8 +328,8 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t index = 0, ep_intr = 0, epint = 0, epnum = 0; - uint32_t fifoemptymsk = 0, temp = 0; + uint32_t index = 0U, ep_intr = 0U, epint = 0U, epnum = 0U; + uint32_t fifoemptymsk = 0U, temp = 0U; USB_OTG_EPTypeDef *ep = NULL; /* ensure that we are in device mode */ @@ -349,14 +349,14 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) { - epnum = 0; + epnum = 0U; /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); while ( ep_intr ) { - if (ep_intr & 0x1) + if (ep_intr & 0x1U) { epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum); @@ -380,7 +380,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } } epnum++; - ep_intr >>= 1; + ep_intr >>= 1U; } } @@ -389,17 +389,17 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Read in the device interrupt bits */ ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); - epnum = 0; + epnum = 0U; while ( ep_intr ) { - if (ep_intr & 0x1) /* In ITR */ + if (ep_intr & 0x1U) /* In ITR */ { epint = USB_ReadDevInEPInterrupt(hpcd->Instance, epnum); - + if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { - fifoemptymsk = 0x1 << epnum; + fifoemptymsk = 0x1U << epnum; USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); @@ -428,7 +428,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } } epnum++; - ep_intr >>= 1; + ep_intr >>= 1U; } } @@ -453,20 +453,20 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); } - + /* Handle Reset Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - USB_FlushTxFifo(hpcd->Instance , 0 ); + USB_FlushTxFifo(hpcd->Instance , 0x10U); - for (index = 0; index < hpcd->Init.dev_endpoints ; index++) + for (index = 0U; index < hpcd->Init.dev_endpoints ; index++) { - USBx_INEP(index)->DIEPINT = 0xFF; - USBx_OUTEP(index)->DOEPINT = 0xFF; + USBx_INEP(index)->DIEPINT = 0xFFU; + USBx_OUTEP(index)->DOEPINT = 0xFFU; } - USBx_DEVICE->DAINT = 0xFFFFFFFF; - USBx_DEVICE->DAINTMSK |= 0x10001; + USBx_DEVICE->DAINT = 0xFFFFFFFFU; + USBx_DEVICE->DAINTMSK |= 0x10001U; USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM); USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM); @@ -488,13 +488,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) hpcd->Init.speed = USB_OTG_SPEED_FULL; hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; - hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT); + hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT); HAL_PCD_ResetCallback(hpcd); __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); } - + /* Handle RxQLevel Interrupt */ if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) { @@ -502,19 +502,19 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) temp = USBx->GRXSTSP; ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; - if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_DATA_UPDT) { - if((temp & USB_OTG_GRXSTSP_BCNT) != 0) + if((temp & USB_OTG_GRXSTSP_BCNT) != 0U) { - USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4); - ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + USB_ReadPacket(USBx, ep->xfer_buff, (temp & USB_OTG_GRXSTSP_BCNT) >> 4U); + ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U; + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U; } } - else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17U) == STS_SETUP_UPDT) { - USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8); - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4U; } USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); } @@ -569,9 +569,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) * @retval HAL status */ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) -{ - uint32_t wInterrupt_Mask = 0; - +{ if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR)) { /* servicing of the endpoint correct transfer interrupt */ @@ -583,7 +581,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); HAL_PCD_ResetCallback(hpcd); - HAL_PCD_SetAddress(hpcd, 0); + HAL_PCD_SetAddress(hpcd, 0U); } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVR)) @@ -596,30 +594,25 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP)) - { + { hpcd->Instance->CNTR &= ~(USB_CNTR_LP_MODE); - - /*set wInterrupt_Mask global variable*/ - wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; - - /*Set interrupt mask*/ - hpcd->Instance->CNTR = wInterrupt_Mask; + hpcd->Instance->CNTR &= ~(USB_CNTR_FSUSP); HAL_PCD_ResumeCallback(hpcd); - + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); } if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP)) - { - /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - + { /* Force low-power mode in the macrocell */ hpcd->Instance->CNTR |= USB_CNTR_FSUSP; + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); + hpcd->Instance->CNTR |= USB_CNTR_LP_MODE; - if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0) + if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0U) { HAL_PCD_SuspendCallback(hpcd); } @@ -841,7 +834,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); - HAL_PCDEx_SetConnectionState (hpcd, 0); + HAL_PCDEx_SetConnectionState (hpcd, 0U); USB_DevDisconnect(hpcd->Instance); __HAL_UNLOCK(hpcd); return HAL_OK; @@ -874,17 +867,17 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep = NULL; - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; } - ep->num = ep_addr & 0x7F; + ep->num = ep_addr & 0x7FU; - ep->is_in = (0x80 & ep_addr) != 0; + ep->is_in = (0x80U & ep_addr) != 0U; ep->maxpacket = ep_mps; ep->type = ep_type; @@ -904,17 +897,17 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { PCD_EPTypeDef *ep = NULL; - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; } else { - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; } - ep->num = ep_addr & 0x7F; + ep->num = ep_addr & 0x7FU; - ep->is_in = (0x80 & ep_addr) != 0; + ep->is_in = (0x80U & ep_addr) != 0U; __HAL_LOCK(hpcd); USB_DeactivateEndpoint(hpcd->Instance , ep); @@ -935,18 +928,16 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u { PCD_EPTypeDef *ep = NULL; - ep = &hpcd->OUT_ep[ep_addr & 0x7F]; + ep = &hpcd->OUT_ep[ep_addr & 0x7FU]; /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; - - __HAL_LOCK(hpcd); - - if ((ep_addr & 0x7F) == 0 ) + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & 0x7FU; + + if ((ep_addr & 0x7FU) == 0U) { USB_EP0StartXfer(hpcd->Instance , ep); } @@ -954,8 +945,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u { USB_EPStartXfer(hpcd->Instance , ep); } - __HAL_UNLOCK(hpcd); - + return HAL_OK; } @@ -967,7 +957,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u */ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { - return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count; + return hpcd->OUT_ep[ep_addr & 0xF].xfer_count; } /** * @brief Send an amount of data @@ -981,18 +971,16 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, { PCD_EPTypeDef *ep = NULL; - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; /*setup and start the Xfer */ ep->xfer_buff = pBuf; ep->xfer_len = len; - ep->xfer_count = 0; - ep->is_in = 1; - ep->num = ep_addr & 0x7F; - - __HAL_LOCK(hpcd); - - if ((ep_addr & 0x7F) == 0 ) + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & 0x7FU; + + if ((ep_addr & 0x7FU) == 0U) { USB_EP0StartXfer(hpcd->Instance , ep); } @@ -1000,9 +988,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, { USB_EPStartXfer(hpcd->Instance , ep); } - - __HAL_UNLOCK(hpcd); - + return HAL_OK; } @@ -1016,22 +1002,22 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { PCD_EPTypeDef *ep = NULL; - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; } else { ep = &hpcd->OUT_ep[ep_addr]; } - ep->is_stall = 1; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); + ep->is_stall = 1U; + ep->num = ep_addr & 0x7FU; + ep->is_in = ((ep_addr & 0x80U) == 0x80U); __HAL_LOCK(hpcd); USB_EPSetStall(hpcd->Instance , ep); - if((ep_addr & 0x7F) == 0) + if((ep_addr & 0x7FU) == 0U) { USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); } @@ -1050,18 +1036,18 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { PCD_EPTypeDef *ep = NULL; - if ((0x80 & ep_addr) == 0x80) + if ((0x80U & ep_addr) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; } else { ep = &hpcd->OUT_ep[ep_addr]; } - ep->is_stall = 0; - ep->num = ep_addr & 0x7F; - ep->is_in = ((ep_addr & 0x80) == 0x80); + ep->is_stall = 0U; + ep->num = ep_addr & 0x7FU; + ep->is_in = ((ep_addr & 0x80U) == 0x80U); __HAL_LOCK(hpcd); USB_EPClearStall(hpcd->Instance , ep); @@ -1080,9 +1066,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) { __HAL_LOCK(hpcd); - if ((ep_addr & 0x80) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F); + USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7FU); } else { @@ -1167,8 +1153,8 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; USB_OTG_EPTypeDef *ep = NULL; int32_t len = 0; - uint32_t len32b = 0; - uint32_t fifoemptymsk = 0; + uint32_t len32b = 0U; + uint32_t fifoemptymsk = 0U; ep = &hpcd->IN_ep[epnum]; len = ep->xfer_len - ep->xfer_count; @@ -1178,20 +1164,20 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t len = ep->maxpacket; } - len32b = (len + 3) / 4; + len32b = (len + 3U) / 4U; while ((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b && ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) + ep->xfer_len != 0U) { /* Write the FIFO */ len = ep->xfer_len - ep->xfer_count; - if (len > ep->maxpacket) + if ((uint32_t)len > ep->maxpacket) { len = ep->maxpacket; } - len32b = (len + 3) / 4; + len32b = (len + 3U) / 4U; USB_WritePacket(USBx, ep->xfer_buff, epnum, len); @@ -1201,7 +1187,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t if(len <= 0) { - fifoemptymsk = 0x1 << epnum; + fifoemptymsk = 0x01U << epnum; USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; } @@ -1248,13 +1234,13 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) ep->xfer_buff += ep->xfer_count; /* TX COMPLETE */ - HAL_PCD_DataInStageCallback(hpcd, 0); + HAL_PCD_DataInStageCallback(hpcd, 0U); - if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0)) + if((hpcd->USB_Address > 0U)&& ( ep->xfer_len == 0U)) { hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF); - hpcd->USB_Address = 0; + hpcd->USB_Address = 0U; } } @@ -1264,10 +1250,10 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* DIR = 1 & CTR_RX => SETUP or OUT int */ /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ - ep = &hpcd->OUT_ep[0]; + ep = &hpcd->OUT_ep[0U]; wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - if ((wEPVal & USB_EP_SETUP) != 0) + if ((wEPVal & USB_EP_SETUP) != 0U) { /* Get SETUP Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); @@ -1279,20 +1265,20 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) HAL_PCD_SetupStageCallback(hpcd); } - else if ((wEPVal & USB_EP_CTR_RX) != 0) + else if ((wEPVal & USB_EP_CTR_RX) != 0U) { PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); /* Get Control Data OUT Packet*/ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) + if (ep->xfer_count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); ep->xfer_buff+=ep->xfer_count; } /* Process Control Data OUT Packet*/ - HAL_PCD_DataOutStageCallback(hpcd, 0); + HAL_PCD_DataOutStageCallback(hpcd, 0U); PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); @@ -1305,17 +1291,17 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* process related endpoint register */ wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex); - if ((wEPVal & USB_EP_CTR_RX) != 0) + if ((wEPVal & USB_EP_CTR_RX) != 0U) { /* clear int flag */ PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); ep = &hpcd->OUT_ep[epindex]; /* OUT double Buffering*/ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if (count != 0) + if (count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); } @@ -1326,7 +1312,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /*read from endpoint BUF0Addr buffer*/ count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (count != 0) + if (count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); } @@ -1335,7 +1321,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /*read from endpoint BUF1Addr buffer*/ count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (count != 0) + if (count != 0U) { USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); } @@ -1346,7 +1332,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) ep->xfer_count+=count; ep->xfer_buff+=count; - if ((ep->xfer_len == 0) || (count < ep->maxpacket)) + if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) { /* RX COMPLETE */ HAL_PCD_DataOutStageCallback(hpcd, ep->num); @@ -1358,7 +1344,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } /* if((wEPVal & EP_CTR_RX) */ - if ((wEPVal & USB_EP_CTR_TX) != 0) + if ((wEPVal & USB_EP_CTR_TX) != 0U) { ep = &hpcd->IN_ep[epindex]; @@ -1366,10 +1352,10 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); /* IN double Buffering*/ - if (ep->doublebuffer == 0) + if (ep->doublebuffer == 0U) { ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) + if (ep->xfer_count != 0U) { USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count); } @@ -1380,7 +1366,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /*read from endpoint BUF0Addr buffer*/ ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) + if (ep->xfer_count != 0U) { USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count); } @@ -1389,7 +1375,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) { /*read from endpoint BUF1Addr buffer*/ ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - if (ep->xfer_count != 0) + if (ep->xfer_count != 0U) { USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count); } @@ -1401,7 +1387,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) ep->xfer_buff+=ep->xfer_count; /* Zero Length Packet? */ - if (ep->xfer_len == 0) + if (ep->xfer_len == 0U) { /* TX COMPLETE */ HAL_PCD_DataInStageCallback(hpcd, ep->num); diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.h index 87f186eafdb..d92c82fdcd6 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pcd.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -69,11 +69,11 @@ */ typedef enum { - HAL_PCD_STATE_RESET = 0x00, - HAL_PCD_STATE_READY = 0x01, - HAL_PCD_STATE_ERROR = 0x02, - HAL_PCD_STATE_BUSY = 0x03, - HAL_PCD_STATE_TIMEOUT = 0x04 + HAL_PCD_STATE_RESET = 0x00U, + HAL_PCD_STATE_READY = 0x01U, + HAL_PCD_STATE_ERROR = 0x02U, + HAL_PCD_STATE_BUSY = 0x03U, + HAL_PCD_STATE_TIMEOUT = 0x04U } PCD_StateTypeDef; #if defined (USB) @@ -118,11 +118,11 @@ typedef struct PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ __IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */ - PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ __IO PCD_StateTypeDef State; /*!< PCD communication state */ - uint32_t Setup[12]; /*!< Setup packet buffer */ + uint32_t Setup[12U]; /*!< Setup packet buffer */ void *pData; /*!< Pointer to upper stack Handler */ } PCD_HandleTypeDef; @@ -141,9 +141,9 @@ typedef struct /** @defgroup PCD_Speed PCD Speed * @{ */ -#define PCD_SPEED_HIGH 0 /* Not Supported */ -#define PCD_SPEED_HIGH_IN_FULL 1 /* Not Supported */ -#define PCD_SPEED_FULL 2 +#define PCD_SPEED_HIGH 0U /* Not Supported */ +#define PCD_SPEED_HIGH_IN_FULL 1U /* Not Supported */ +#define PCD_SPEED_FULL 2U /** * @} */ @@ -151,7 +151,7 @@ typedef struct /** @defgroup PCD_PHY_Module PCD PHY Module * @{ */ -#define PCD_PHY_EMBEDDED 2 +#define PCD_PHY_EMBEDDED 2U /** * @} */ @@ -160,7 +160,7 @@ typedef struct * @{ */ #ifndef USBD_FS_TRDT_VALUE - #define USBD_FS_TRDT_VALUE 5 + #define USBD_FS_TRDT_VALUE 5U #endif /* USBD_FS_TRDT_VALUE */ /** * @} @@ -182,14 +182,14 @@ typedef struct #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) -#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) #define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ ~(USB_OTG_PCGCCTL_STOPCLK) #define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10) +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) @@ -200,13 +200,13 @@ typedef struct do{ \ EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ - } while(0) + } while(0U) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() \ do{ \ EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE); \ EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ - } while(0) + } while(0U) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() \ do{ \ @@ -214,7 +214,7 @@ typedef struct EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ - } while(0) + } while(0U) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE) #endif /* USB_OTG_FS */ @@ -234,13 +234,13 @@ typedef struct do{ \ EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \ EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \ - } while(0) + } while(0U) #define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() \ do{ \ EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE); \ EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \ - } while(0) + } while(0U) #define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() \ do{ \ @@ -248,7 +248,7 @@ typedef struct EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \ EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \ EXTI->FTSR |= USB_WAKEUP_EXTI_LINE; \ - } while(0) + } while(0U) #endif /* USB */ /** @@ -338,15 +338,15 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @{ */ #if defined (USB_OTG_FS) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08) -#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C) -#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10) +#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U +#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU +#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U -#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB EXTI Line */ +#define USB_OTG_FS_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB EXTI Line */ #endif /* USB_OTG_FS */ #if defined (USB) -#define USB_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB EXTI Line */ +#define USB_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB EXTI Line */ #endif /* USB */ /** * @} @@ -382,8 +382,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /** @defgroup PCD_ENDP_Kind PCD Endpoint Kind * @{ */ -#define PCD_SNG_BUF 0 -#define PCD_DBL_BUF 1 +#define PCD_SNG_BUF 0U +#define PCD_DBL_BUF 1U /** * @} */ @@ -398,10 +398,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); */ #if defined (USB) /* SetENDPOINT */ -#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue)) +#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2U)= (uint16_t)(wRegValue)) /* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2)) +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2U)) /* ENDPOINT transfer */ #define USB_EP0StartXfer USB_EPStartXfer @@ -414,7 +414,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) ))) + ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) ))) /** * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) @@ -472,12 +472,12 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\ /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wState))!= 0)\ + if((USB_EPTX_DTOG1 & (wState))!= 0U)\ { \ _wRegVal ^= USB_EPTX_DTOG1; \ } \ /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wState))!= 0) \ + if((USB_EPTX_DTOG2 & (wState))!= 0U) \ { \ _wRegVal ^= USB_EPTX_DTOG2; \ } \ @@ -496,12 +496,12 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\ /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & (wState))!= 0) \ + if((USB_EPRX_DTOG1 & (wState))!= 0U) \ { \ _wRegVal ^= USB_EPRX_DTOG1; \ } \ /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wState))!= 0) \ + if((USB_EPRX_DTOG2 & (wState))!= 0U) \ { \ _wRegVal ^= USB_EPRX_DTOG2; \ } \ @@ -521,22 +521,22 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\ /* toggle first bit ? */ \ - if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \ + if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \ { \ _wRegVal ^= USB_EPRX_DTOG1; \ } \ /* toggle second bit ? */ \ - if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \ + if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ { \ _wRegVal ^= USB_EPRX_DTOG2; \ } \ /* toggle first bit ? */ \ - if((USB_EPTX_DTOG1 & (wStatetx))!= 0) \ + if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ { \ _wRegVal ^= USB_EPTX_DTOG1; \ } \ /* toggle second bit ? */ \ - if((USB_EPTX_DTOG2 & (wStatetx))!= 0) \ + if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ { \ _wRegVal ^= USB_EPTX_DTOG2; \ } \ @@ -609,9 +609,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK)) + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK)) #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK)) + PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK)) /** * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. @@ -630,11 +630,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum: Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\ +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0U)\ { \ PCD_RX_DTOG((USBx), (bEpNum)); \ } -#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\ +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0U)\ { \ PCD_TX_DTOG((USBx), (bEpNum)); \ } @@ -651,10 +651,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) -#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400))) -#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400))) +#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U)*2U+ ((uint32_t)(USBx) + 0x400U))) +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+2U)*2U+ ((uint32_t)(USBx) + 0x400U))) +#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+4U)*2U+ ((uint32_t)(USBx) + 0x400U))) +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+6U)*2U+ ((uint32_t)(USBx) + 0x400U))) #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\ uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \ @@ -668,8 +668,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wAddr: address to be set (must be word aligned). * @retval None */ -#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) -#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1)) +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U)) +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U)) /** * @brief Gets address of the tx/rx buffer. @@ -688,26 +688,26 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 5;\ - if(((wCount) & 0x1f) == 0)\ + (wNBlocks) = (wCount) >> 5U;\ + if(((wCount) & 0x1FU) == 0U)\ { \ (wNBlocks)--;\ } \ - *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \ + *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | 0x8000U); \ }/* PCD_CALC_BLK32 */ #define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\ - (wNBlocks) = (wCount) >> 1;\ - if(((wCount) & 0x1) != 0)\ + (wNBlocks) = (wCount) >> 1U;\ + if(((wCount) & 0x01U) != 0U)\ { \ (wNBlocks)++;\ } \ - *pdwReg = (uint16_t)((wNBlocks) << 10);\ + *pdwReg = (uint16_t)((wNBlocks) << 10U);\ }/* PCD_CALC_BLK2 */ #define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\ uint16_t wNBlocks;\ - if((wCount) > 62) \ + if((wCount) > 62U) \ { \ PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \ } \ @@ -738,8 +738,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum: Endpoint Number. * @retval Counter value */ -#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff) -#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff) +#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3FFU) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3FFU) /** * @brief Sets buffer 0/1 address in a double buffer endpoint. diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.c index b26902f2b5d..edadc8fb529 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Extended PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -97,7 +97,7 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) { uint8_t index = 0; - uint32_t Tx_Offset = 0; + uint32_t Tx_Offset = 0U; /* TXn min size = 16 words. (n : Transmit FIFO index) When a TxFIFO is not used, the Configuration should be as follows: @@ -111,20 +111,20 @@ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uin Tx_Offset = hpcd->Instance->GRXFSIZ; - if(fifo == 0) + if(fifo == 0U) { - hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset; + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16U) | Tx_Offset; } else { - Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; - for (index = 0; index < (fifo - 1); index++) + Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16U; + for(index = 0; index < (fifo - 1); index++) { - Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16); + Tx_Offset += (hpcd->Instance->DIEPTXF[index] >> 16U); } /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset; + hpcd->Instance->DIEPTXF[fifo - 1U] = (size << 16U) | Tx_Offset; } @@ -171,9 +171,9 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep = NULL; /* initialize ep structure*/ - if ((0x80 & ep_addr) == 0x80) + if ((ep_addr & 0x80U) == 0x80U) { - ep = &hpcd->IN_ep[ep_addr & 0x7F]; + ep = &hpcd->IN_ep[ep_addr & 0x7FU]; } else { @@ -184,17 +184,17 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, if (ep_kind == PCD_SNG_BUF) { /*Single Buffer*/ - ep->doublebuffer = 0; + ep->doublebuffer = 0U; /*Configure te PMA*/ ep->pmaadress = (uint16_t)pmaadress; } else /*USB_DBL_BUF*/ { /*Double Buffer Endpoint*/ - ep->doublebuffer = 1; + ep->doublebuffer = 1U; /*Configure the PMA*/ - ep->pmaaddr0 = pmaadress & 0xFFFF; - ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16; + ep->pmaaddr0 = pmaadress & 0x0000FFFFU; + ep->pmaaddr1 = (pmaadress & 0xFFFF0000U) >> 16U; } return HAL_OK; diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.h index 54d52ddada5..09aae9018f9 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pcd_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of Extended PCD HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.c index 71ab9a39955..84b2d130d3c 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pwr.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief PWR HAL module driver. * * This file provides firmware functions to manage the following @@ -65,10 +65,10 @@ /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask * @{ */ -#define PVD_MODE_IT ((uint32_t)0x00010000) -#define PVD_MODE_EVT ((uint32_t)0x00020000) -#define PVD_RISING_EDGE ((uint32_t)0x00000001) -#define PVD_FALLING_EDGE ((uint32_t)0x00000002) +#define PVD_MODE_IT 0x00010000U +#define PVD_MODE_EVT 0x00020000U +#define PVD_RISING_EDGE 0x00000001U +#define PVD_FALLING_EDGE 0x00000002U /** * @} */ @@ -79,8 +79,8 @@ */ /* ------------- PWR registers bit address in the alias region ---------------*/ #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) -#define PWR_CR_OFFSET 0x00 -#define PWR_CSR_OFFSET 0x04 +#define PWR_CR_OFFSET 0x00U +#define PWR_CSR_OFFSET 0x04U #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) /** @@ -92,16 +92,16 @@ */ /* --- CR Register ---*/ /* Alias word address of LPSDSR bit */ -#define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPDS) -#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4))) +#define LPSDSR_BIT_NUMBER PWR_CR_LPDS_Pos +#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPSDSR_BIT_NUMBER * 4U))) /* Alias word address of DBP bit */ -#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) -#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))) +#define DBP_BIT_NUMBER PWR_CR_DBP_Pos +#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))) /* Alias word address of PVDE bit */ -#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) -#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))) +#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos +#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))) /** * @} @@ -113,7 +113,7 @@ /* --- CSR Register ---*/ /* Alias word address of EWUP1 bit */ -#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4))) +#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (POSITION_VAL(VAL) * 4U))) /** * @} */ @@ -436,6 +436,9 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { /* Check the parameters */ /* No check on Regulator because parameter not used in SLEEP mode */ + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); /* Clear SLEEPDEEP bit of Cortex System Control Register */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.h index db20f8b95f5..af065b89d57 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_pwr.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -116,13 +116,13 @@ typedef struct /** @defgroup PWR_PVD_Mode PWR PVD Mode * @{ */ -#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ -#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ /** * @} @@ -142,7 +142,7 @@ typedef struct /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode * @{ */ -#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) +#define PWR_MAINREGULATOR_ON 0x00000000U #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /** diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.c index 868908a35f2..5d6e69f1bd7 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rcc.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -96,10 +96,6 @@ /** @defgroup RCC_Private_Constants RCC Private Constants * @{ */ -/* Bits position in in the CFGR register */ -#define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE) -#define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1) -#define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2) /** * @} */ @@ -125,7 +121,9 @@ */ /* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ +static void RCC_Delay(uint32_t mdelay); + +/* Exported functions --------------------------------------------------------*/ /** @defgroup RCC_Exported_Functions RCC Exported Functions * @{ @@ -233,13 +231,13 @@ void HAL_RCC_DeInit(void) CLEAR_REG(RCC->CFGR); /* Set HSITRIM bits to the reset value */ - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM))); + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos)); -#if (defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)) +#if defined(RCC_CFGR2_SUPPORT) /* Reset CFGR2 register */ CLEAR_REG(RCC->CFGR2); -#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ +#endif /* RCC_CFGR2_SUPPORT */ /* Disable all interrupts */ CLEAR_REG(RCC->CIR); @@ -264,7 +262,7 @@ void HAL_RCC_DeInit(void) */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(RCC_OscInitStruct != NULL); @@ -412,7 +410,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /* To have a fully stabilized clock in the specified range, a software delay of 1ms should be added.*/ - HAL_Delay(1); + RCC_Delay(1); } else { @@ -435,25 +433,35 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { + FlagStatus pwrclkchanged = RESET; + /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - /* Enable Power Clock*/ + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - while((PWR->CR & PWR_CR_DBP) == RESET) + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } + } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); @@ -486,6 +494,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } } + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } } #if defined(RCC_CR_PLL2ON) @@ -694,7 +708,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check the parameters */ assert_param(RCC_ClkInitStruct != NULL); @@ -827,7 +841,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER]; + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); @@ -887,13 +901,17 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui */ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) { - GPIO_InitTypeDef gpio = {0}; + GPIO_InitTypeDef gpio = {0U}; /* Check the parameters */ assert_param(IS_RCC_MCO(RCC_MCOx)); assert_param(IS_RCC_MCODIV(RCC_MCODiv)); assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - + + /* Prevent unused argument(s) compilation warning */ + UNUSED(RCC_MCOx); + UNUSED(RCC_MCODiv); + /* Configure the MCO1 pin in alternate function mode */ gpio.Mode = GPIO_MODE_AF_PP; gpio.Speed = GPIO_SPEED_FREQ_HIGH; @@ -902,9 +920,9 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M /* MCO1 Clock Enable */ MCO1_CLK_ENABLE(); - + HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); - + /* Configure the MCO clock source */ __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); } @@ -963,22 +981,22 @@ void HAL_RCC_DisableCSS(void) */ uint32_t HAL_RCC_GetSysClockFreq(void) { -#if defined(RCC_CFGR2_PREDIV1SRC) - const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13}; - const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16}; +#if defined(RCC_CFGR2_PREDIV1SRC) + const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else - const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; + const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; #if defined(RCC_CFGR2_PREDIV1) - const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16}; + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; #else - const uint8_t aPredivFactorTable[2] = { 1, 2}; + const uint8_t aPredivFactorTable[2] = {1, 2}; #endif /*RCC_CFGR2_PREDIV1*/ #endif - uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0; - uint32_t sysclockfreq = 0; + uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + uint32_t sysclockfreq = 0U; #if defined(RCC_CFGR2_PREDIV1SRC) - uint32_t prediv2 = 0, pll2mul = 0; + uint32_t prediv2 = 0U, pll2mul = 0U; #endif /*RCC_CFGR2_PREDIV1SRC*/ tmpreg = RCC->CFGR; @@ -993,13 +1011,13 @@ uint32_t HAL_RCC_GetSysClockFreq(void) } case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { - pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)]; + pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) { #if defined(RCC_CFGR2_PREDIV1) - prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)]; + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else - prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)]; + prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /*RCC_CFGR2_PREDIV1*/ #if defined(RCC_CFGR2_PREDIV1SRC) @@ -1007,8 +1025,8 @@ uint32_t HAL_RCC_GetSysClockFreq(void) { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ - prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1; - pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2; + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul); } else @@ -1019,7 +1037,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ - if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)]) + if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) { pllclk = pllclk / 2; } @@ -1069,7 +1087,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void) uint32_t HAL_RCC_GetPCLK1Freq(void) { /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]); + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); } /** @@ -1081,7 +1099,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void) uint32_t HAL_RCC_GetPCLK2Freq(void) { /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]); + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); } /** @@ -1130,7 +1148,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->HSIState = RCC_HSI_OFF; } - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); /* Get the LSE configuration -----------------------------------------------*/ if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) @@ -1239,6 +1257,21 @@ void HAL_RCC_NMI_IRQHandler(void) } } +/** + * @brief This function provides delay (in milliseconds) based on CPU cycles method. + * @param mdelay: specifies the delay time length, in milliseconds. + * @retval None + */ +static void RCC_Delay(uint32_t mdelay) +{ + __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); + do + { + __NOP(); + } + while (Delay --); +} + /** * @brief RCC Clock Security System interrupt callback * @retval none diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.h index f91c2737827..ebfc2805e64 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rcc.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -54,176 +54,6 @@ * @{ */ -/** @addtogroup RCC_Private_Constants - * @{ - */ - -/** @defgroup RCC_Timeout RCC Timeout - * @{ - */ - -/* Disable Backup domain write protection state change timeout */ -#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -/* LSE state change timeout */ -#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ -#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms (minimum Tick + 1) */ -#define LSI_VALUE ((uint32_t)40000) /* 40kHz */ -/** - * @} - */ - -/** @defgroup RCC_Register_Offset Register offsets - * @{ - */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -#define RCC_CR_OFFSET 0x00 -#define RCC_CFGR_OFFSET 0x04 -#define RCC_CIR_OFFSET 0x08 -#define RCC_BDCR_OFFSET 0x20 -#define RCC_CSR_OFFSET 0x24 - -/** - * @} - */ - -/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion - * @brief RCC registers bit address in the alias region - * @{ - */ -#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) -#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) -#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) -#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) -#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) - -/* --- CR Register ---*/ -/* Alias word address of HSION bit */ -#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION) -#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4))) -/* Alias word address of HSEON bit */ -#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON) -#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4))) -/* Alias word address of CSSON bit */ -#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON) -#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4))) -/* Alias word address of PLLON bit */ -#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON) -#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4))) - -/* --- CSR Register ---*/ -/* Alias word address of LSION bit */ -#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION) -#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4))) - -/* Alias word address of RMVF bit */ -#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF) -#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4))) - -/* --- BDCR Registers ---*/ -/* Alias word address of LSEON bit */ -#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEON) -#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4))) - -/* Alias word address of LSEON bit */ -#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_BDCR_LSEBYP) -#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4))) - -/* Alias word address of RTCEN bit */ -#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_BDCR_RTCEN) -#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4))) - -/* Alias word address of BDRST bit */ -#define RCC_BDRST_BIT_NUMBER POSITION_VAL(RCC_BDCR_BDRST) -#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32) + (RCC_BDRST_BIT_NUMBER * 4))) - -/** - * @} - */ - -/* CR register byte 2 (Bits[23:16]) base address */ -#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02)) - -/* CIR register byte 1 (Bits[15:8]) base address */ -#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01)) - -/* CIR register byte 2 (Bits[23:16]) base address */ -#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02)) - -/* Defines used for Flags */ -#define CR_REG_INDEX ((uint8_t)1) -#define BDCR_REG_INDEX ((uint8_t)2) -#define CSR_REG_INDEX ((uint8_t)3) - -#define RCC_FLAG_MASK ((uint8_t)0x1F) - -/** - * @} - */ - -/** @addtogroup RCC_Private_Macros - * @{ - */ -/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy - * @{ - */ -#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE -#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE -#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET -#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET -/** - * @} - */ - -#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ - ((__SOURCE__) == RCC_PLLSOURCE_HSE)) -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) -#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ - ((__HSE__) == RCC_HSE_BYPASS)) -#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ - ((__LSE__) == RCC_LSE_BYPASS)) -#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) -#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) -#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) -#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ - ((__PLL__) == RCC_PLL_ON)) - -#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ - (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ - (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ - (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) -#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) -#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) -#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ - ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ - ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ - ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ - ((__HCLK__) == RCC_SYSCLK_DIV512)) -#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ - ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ - ((__PCLK__) == RCC_HCLK_DIV16)) -#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) -#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) -#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) - -/** - * @} - */ - /* Exported types ------------------------------------------------------------*/ /** @defgroup RCC_Exported_Types RCC Exported Types @@ -279,7 +109,7 @@ typedef struct * @{ */ -#define RCC_PLLSOURCE_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ /** @@ -289,11 +119,11 @@ typedef struct /** @defgroup RCC_Oscillator_Type Oscillator Type * @{ */ -#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) -#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) -#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) -#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) -#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) +#define RCC_OSCILLATORTYPE_NONE 0x00000000U +#define RCC_OSCILLATORTYPE_HSE 0x00000001U +#define RCC_OSCILLATORTYPE_HSI 0x00000002U +#define RCC_OSCILLATORTYPE_LSE 0x00000004U +#define RCC_OSCILLATORTYPE_LSI 0x00000008U /** * @} */ @@ -301,7 +131,7 @@ typedef struct /** @defgroup RCC_HSE_Config HSE Config * @{ */ -#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ /** @@ -311,8 +141,8 @@ typedef struct /** @defgroup RCC_LSE_Config LSE Config * @{ */ -#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */ -#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ +#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ +#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ /** @@ -322,10 +152,10 @@ typedef struct /** @defgroup RCC_HSI_Config HSI Config * @{ */ -#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ +#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ /** * @} @@ -334,7 +164,7 @@ typedef struct /** @defgroup RCC_LSI_Config LSI Config * @{ */ -#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ /** @@ -344,9 +174,9 @@ typedef struct /** @defgroup RCC_PLL_Config PLL Config * @{ */ -#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */ -#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */ -#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */ +#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */ +#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ +#define RCC_PLL_ON 0x00000002U /*!< PLL activation */ /** * @} @@ -355,10 +185,10 @@ typedef struct /** @defgroup RCC_System_Clock_Type System Clock Type * @{ */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */ -#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ /** * @} @@ -419,7 +249,7 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RTC Clock Source * @{ */ -#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */ #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ #define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ @@ -431,7 +261,7 @@ typedef struct /** @defgroup RCC_MCO_Index MCO Index * @{ */ -#define RCC_MCO1 ((uint32_t)0x00000000) +#define RCC_MCO1 0x00000000U #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ /** @@ -441,7 +271,7 @@ typedef struct /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler * @{ */ -#define RCC_MCODIV_1 ((uint32_t)0x00000000) +#define RCC_MCODIV_1 0x00000000U /** * @} @@ -470,21 +300,21 @@ typedef struct * @{ */ /* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */ -#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */ -#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ +#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ +#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ /* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */ -#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ -#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */ -#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ -#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ -#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ -#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ +#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ +#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ +#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ +#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ /* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< External Low Speed oscillator Ready */ +#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ /** * @} @@ -513,7 +343,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -521,7 +351,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -529,7 +359,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CRC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -537,7 +367,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) @@ -582,7 +412,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -590,7 +420,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -598,7 +428,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -606,7 +436,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -614,7 +444,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_BKP_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -622,7 +452,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_PWR_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -630,7 +460,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) @@ -659,14 +489,14 @@ typedef struct #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) -#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) -#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) -#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) -#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) -#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) +#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) /** * @} @@ -685,7 +515,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -693,7 +523,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -701,7 +531,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -709,7 +539,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -717,7 +547,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -725,7 +555,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -733,7 +563,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -741,7 +571,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART1_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -749,7 +579,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */\ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) @@ -776,22 +606,22 @@ typedef struct #define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) #define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) -#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) -#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) /** * @} @@ -882,7 +712,7 @@ typedef struct * This parameter must be a number between 0 and 0x1F. */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ - (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_CR_HSITRIM))) + (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos)) /** * @} @@ -957,7 +787,7 @@ typedef struct CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ } \ - }while(0) + }while(0U) /** * @} @@ -1005,7 +835,7 @@ typedef struct CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ } \ - }while(0) + }while(0U) /** * @} @@ -1315,9 +1145,9 @@ typedef struct * @arg @ref RCC_FLAG_LPWRRST Low Power reset. * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \ - ((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \ - RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ + ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ + RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) /** * @} @@ -1377,6 +1207,176 @@ void HAL_RCC_CSSCallback(void); * @} */ +/** @addtogroup RCC_Private_Constants + * @{ + */ + +/** @defgroup RCC_Timeout RCC Timeout + * @{ + */ + +/* Disable Backup domain write protection state change timeout */ +#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */ +/* LSE state change timeout */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ + +/** + * @} + */ + +/** @defgroup RCC_Register_Offset Register offsets + * @{ + */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) +#define RCC_CR_OFFSET 0x00U +#define RCC_CFGR_OFFSET 0x04U +#define RCC_CIR_OFFSET 0x08U +#define RCC_BDCR_OFFSET 0x20U +#define RCC_CSR_OFFSET 0x24U + +/** + * @} + */ + +/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion + * @brief RCC registers bit address in the alias region + * @{ + */ +#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) +#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) +#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) +#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) +#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) + +/* --- CR Register ---*/ +/* Alias word address of HSION bit */ +#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos +#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) +/* Alias word address of HSEON bit */ +#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos +#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) +/* Alias word address of CSSON bit */ +#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos +#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) +/* Alias word address of PLLON bit */ +#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos +#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) + +/* --- CSR Register ---*/ +/* Alias word address of LSION bit */ +#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos +#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) + +/* Alias word address of RMVF bit */ +#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos +#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) + +/* --- BDCR Registers ---*/ +/* Alias word address of LSEON bit */ +#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos +#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) + +/* Alias word address of LSEON bit */ +#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos +#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) + +/* Alias word address of RTCEN bit */ +#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos +#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) + +/* Alias word address of BDRST bit */ +#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos +#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) + +/** + * @} + */ + +/* CR register byte 2 (Bits[23:16]) base address */ +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) + +/* Defines used for Flags */ +#define CR_REG_INDEX ((uint8_t)1) +#define BDCR_REG_INDEX ((uint8_t)2) +#define CSR_REG_INDEX ((uint8_t)3) + +#define RCC_FLAG_MASK ((uint8_t)0x1F) + +/** + * @} + */ + +/** @addtogroup RCC_Private_Macros + * @{ + */ +/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +/** + * @} + */ + +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ + (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ + ((__PLL__) == RCC_PLL_ON)) + +#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ + (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ + (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) +#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) +#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) + +/** + * @} + */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.c index d2c21ba1ee2..65114651c58 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Extended RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: @@ -56,16 +56,16 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup RCCEx_Private_Constants RCCEx Private Constants - * @{ - */ + * @{ + */ /** * @} */ /* Private macro -------------------------------------------------------------*/ /** @defgroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ + * @{ + */ /** * @} */ @@ -79,8 +79,8 @@ */ /** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions - * @brief Extended Peripheral Control functions - * + * @brief Extended Peripheral Control functions + * @verbatim =============================================================================== ##### Extended Peripheral Control functions ##### @@ -117,9 +117,9 @@ */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - uint32_t tickstart = 0, temp_reg = 0; + uint32_t tickstart = 0U, temp_reg = 0U; #if defined(STM32F105xC) || defined(STM32F107xC) - uint32_t pllactive = 0; + uint32_t pllactive = 0U; #endif /* STM32F105xC || STM32F107xC */ /* Check the parameters */ @@ -131,21 +131,32 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - /* Enable Power Clock*/ + FlagStatus pwrclkchanged = RESET; + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + { __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while((PWR->CR & PWR_CR_DBP) == RESET) + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + /* Enable write access to Backup domain */ + SET_BIT(PWR->CR, PWR_CR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) { - return HAL_TIMEOUT; - } + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } } /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ @@ -163,7 +174,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Wait for LSERDY if LSE was enabled */ if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) { - /* Get timeout */ + /* Get Start Tick */ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ @@ -177,6 +188,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } } /*------------------------------ ADC clock Configuration ------------------*/ @@ -294,7 +311,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - uint32_t srcclk = 0; + uint32_t srcclk = 0U; /* Set all possible values for the extended clock type parameter------------*/ PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; @@ -387,26 +404,21 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) */ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ - || defined(STM32F105xC) || defined(STM32F107xC) -#if defined(STM32F105xC) || defined(STM32F107xC) - const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13}; - const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16}; -#else - const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; - const uint8_t aPredivFactorTable[2] = { 1, 2}; -#endif -#endif - uint32_t temp_reg = 0, frequency = 0; -#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ - || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ - || defined(STM32F105xC) || defined(STM32F107xC) - uint32_t prediv1 = 0, pllclk = 0, pllmul = 0; -#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F105xC) || defined(STM32F107xC) - uint32_t pll2mul = 0, pll3mul = 0, prediv2 = 0; + const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13}; + const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; + + uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; + uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U; #endif /* STM32F105xC || STM32F107xC */ +#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \ + defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) + const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16}; + const uint8_t aPredivFactorTable[2] = {1, 2}; + + uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U; +#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ + uint32_t temp_reg = 0U, frequency = 0U; /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); @@ -424,14 +436,14 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* Check if PLL is enabled */ if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON)) { - pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)]; + pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos]; if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2) { #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) - prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)]; + prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos]; #else - prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)]; + prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos]; #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */ #if defined(STM32F105xC) || defined(STM32F107xC) @@ -439,8 +451,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { /* PLL2 selected as Prediv1 source */ /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */ - prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1; - pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2; + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2; pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul); } else @@ -451,7 +463,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */ /* In this case need to divide pllclk by 2 */ - if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)]) + if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos]) { pllclk = pllclk / 2; } @@ -499,8 +511,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ -#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ - || defined(STM32F107xC) +#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) case RCC_PERIPHCLK_I2S2: { #if defined(STM32F103xE) || defined(STM32F103xG) @@ -518,8 +529,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) { /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ - prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1; - pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2; + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } @@ -543,8 +554,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON)) { /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */ - prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1; - pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2; + prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1; + pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2; frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul)); } } @@ -569,18 +580,18 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) { - frequency = HSE_VALUE / 128; + frequency = HSE_VALUE / 128U; } /* Clock not enabled for RTC*/ else { - frequency = 0; + frequency = 0U; } break; } case RCC_PERIPHCLK_ADC: { - frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> POSITION_VAL(RCC_CFGR_ADCPRE_DIV4)) + 1) * 2); + frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2); break; } default: @@ -597,8 +608,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) #if defined(STM32F105xC) || defined(STM32F107xC) /** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function - * @brief PLLI2S Management functions - * + * @brief PLLI2S Management functions + * @verbatim =============================================================================== ##### Extended PLLI2S Management functions ##### @@ -619,7 +630,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) */ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/ if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) @@ -689,7 +700,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) */ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Disable PLL I2S as not requested by I2S2 or I2S3*/ if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC)) @@ -723,8 +734,8 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) */ /** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function - * @brief PLL2 Management functions - * + * @brief PLL2 Management functions + * @verbatim =============================================================================== ##### Extended PLL2 Management functions ##### @@ -745,7 +756,7 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) */ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ @@ -816,7 +827,7 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init) */ HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock). */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.h index fbd5772b699..098ecd762e4 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -61,14 +61,14 @@ #if defined(STM32F105xC) || defined(STM32F107xC) /* Alias word address of PLLI2SON bit */ -#define PLLI2SON_BITNUMBER POSITION_VAL(RCC_CR_PLL3ON) -#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLI2SON_BITNUMBER * 4))) +#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos +#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U))) /* Alias word address of PLL2ON bit */ -#define PLL2ON_BITNUMBER POSITION_VAL(RCC_CR_PLL2ON) -#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLL2ON_BITNUMBER * 4))) +#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos +#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U))) -#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define PLL2_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */ +#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */ #endif /* STM32F105xC || STM32F107xC */ @@ -346,17 +346,17 @@ typedef struct /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection * @{ */ -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001) -#define RCC_PERIPHCLK_ADC ((uint32_t)0x00000002) +#define RCC_PERIPHCLK_RTC 0x00000001U +#define RCC_PERIPHCLK_ADC 0x00000002U #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\ || defined(STM32F107xC) -#define RCC_PERIPHCLK_I2S2 ((uint32_t)0x00000004) -#define RCC_PERIPHCLK_I2S3 ((uint32_t)0x00000008) +#define RCC_PERIPHCLK_I2S2 0x00000004U +#define RCC_PERIPHCLK_I2S3 0x00000008U #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\ || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\ || defined(STM32F105xC) || defined(STM32F107xC) -#define RCC_PERIPHCLK_USB ((uint32_t)0x00000010) +#define RCC_PERIPHCLK_USB 0x00000010U #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ /** @@ -380,9 +380,9 @@ typedef struct /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source * @{ */ -#define RCC_I2S2CLKSOURCE_SYSCLK ((uint32_t)0x00000000) +#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U #if defined(STM32F105xC) || defined(STM32F107xC) -#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC +#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC #endif /* STM32F105xC || STM32F107xC */ /** @@ -392,9 +392,9 @@ typedef struct /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source * @{ */ -#define RCC_I2S3CLKSOURCE_SYSCLK ((uint32_t)0x00000000) +#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U #if defined(STM32F105xC) || defined(STM32F107xC) -#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC +#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC #endif /* STM32F105xC || STM32F107xC */ /** @@ -410,7 +410,7 @@ typedef struct * @{ */ #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE -#define RCC_USBCLKSOURCE_PLL_DIV1_5 ((uint32_t)0x00000000) +#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U /** * @} @@ -424,7 +424,7 @@ typedef struct * @{ */ #define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE -#define RCC_USBCLKSOURCE_PLL_DIV3 ((uint32_t)0x00000000) +#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U /** * @} @@ -466,7 +466,7 @@ typedef struct * @{ */ -#define RCC_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) +#define RCC_HSE_PREDIV_DIV1 0x00000000U #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\ || defined(STM32F100xE) @@ -522,9 +522,9 @@ typedef struct /** @defgroup RCCEx_PLL2_Config PLL Config * @{ */ -#define RCC_PLL2_NONE ((uint32_t)0x00000000) -#define RCC_PLL2_OFF ((uint32_t)0x00000001) -#define RCC_PLL2_ON ((uint32_t)0x00000002) +#define RCC_PLL2_NONE 0x00000000U +#define RCC_PLL2_OFF 0x00000001U +#define RCC_PLL2_ON 0x00000002U /** * @} @@ -617,8 +617,8 @@ typedef struct * @{ */ /* Flags in the CR register */ -#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL2RDY))) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL3RDY))) +#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /** * @} */ @@ -650,7 +650,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */ @@ -663,7 +663,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ @@ -675,7 +675,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN)) @@ -688,7 +688,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN)) @@ -701,7 +701,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -709,7 +709,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -717,7 +717,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN)) #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN)) @@ -730,7 +730,7 @@ typedef struct __HAL_RCC_ETHMAC_CLK_ENABLE(); \ __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ - } while(0) + } while(0U) /** * @brief Disable ETHERNET clock. */ @@ -738,7 +738,7 @@ typedef struct __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ __HAL_RCC_ETHMAC_CLK_DISABLE(); \ - } while(0) + } while(0U) #endif /* STM32F107xC*/ @@ -802,7 +802,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ @@ -817,7 +817,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -825,7 +825,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USART3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -833,7 +833,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -841,7 +841,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) @@ -857,7 +857,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */ @@ -870,7 +870,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -878,7 +878,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -886,7 +886,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -894,7 +894,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_UART4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -902,7 +902,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_UART5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -910,7 +910,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DAC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -918,7 +918,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) @@ -936,7 +936,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -944,7 +944,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_DAC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -952,7 +952,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CEC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -960,7 +960,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) @@ -975,7 +975,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM12_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -983,7 +983,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -991,7 +991,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -999,7 +999,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1007,7 +1007,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_UART4_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1015,7 +1015,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_UART5_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1023,7 +1023,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) @@ -1041,7 +1041,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) #endif /* STM32F105xC || STM32F107xC */ @@ -1053,7 +1053,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM13_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1061,7 +1061,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM14_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1069,7 +1069,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) @@ -1188,7 +1188,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */ @@ -1200,7 +1200,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1208,7 +1208,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1216,7 +1216,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN)) #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN)) @@ -1233,7 +1233,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN)) #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */ @@ -1246,7 +1246,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1254,7 +1254,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) @@ -1267,7 +1267,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_ADC3_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1275,7 +1275,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) @@ -1288,7 +1288,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1296,7 +1296,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN)) #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN)) @@ -1309,7 +1309,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM10_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1317,7 +1317,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM11_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ @@ -1325,7 +1325,7 @@ typedef struct /* Delay after an RCC peripheral clock enabling */ \ tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ UNUSED(tmpreg); \ - } while(0) + } while(0U) #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.c index 331d428e995..2f609f4d855 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rtc.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: @@ -171,7 +171,7 @@ * @{ */ #define RTC_ALARM_RESETVALUE_REGISTER (uint16_t)0xFFFF -#define RTC_ALARM_RESETVALUE (uint32_t)0xFFFFFFFF +#define RTC_ALARM_RESETVALUE 0xFFFFFFFFU /** * @} @@ -243,7 +243,7 @@ static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { - uint32_t prescaler = 0; + uint32_t prescaler = 0U; /* Check input parameters */ if(hrtc == NULL) { @@ -310,7 +310,7 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) prescaler = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_RTC); /* Check that RTC clock is enabled*/ - if (prescaler == 0) + if (prescaler == 0U) { /* Should not happen. Frequency is not available*/ hrtc->State = HAL_RTC_STATE_ERROR; @@ -319,12 +319,12 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) else { /* RTC period = RTCCLK/(RTC_PR + 1) */ - prescaler = prescaler - 1; + prescaler = prescaler - 1U; } } /* Configure the RTC_PRLH / RTC_PRLL */ - MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16)); + MODIFY_REG(hrtc->Instance->PRLH, RTC_PRLH_PRL, (prescaler >> 16U)); MODIFY_REG(hrtc->Instance->PRLL, RTC_PRLL_PRL, (prescaler & RTC_PRLL_PRL)); /* Wait for synchro */ @@ -336,9 +336,9 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) } /* Initialize date to 1st of January 2000 */ - hrtc->DateToUpdate.Year = 0x00; + hrtc->DateToUpdate.Year = 0x00U; hrtc->DateToUpdate.Month = RTC_MONTH_JANUARY; - hrtc->DateToUpdate.Date = 0x01; + hrtc->DateToUpdate.Date = 0x01U; /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -383,7 +383,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { CLEAR_REG(hrtc->Instance->CNTL); CLEAR_REG(hrtc->Instance->CNTH); - WRITE_REG(hrtc->Instance->PRLL, 0x00008000); + WRITE_REG(hrtc->Instance->PRLL, 0x00008000U); CLEAR_REG(hrtc->Instance->PRLH); /* Reset All CRH/CRL bits */ @@ -479,7 +479,7 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) */ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { - uint32_t counter_time = 0, counter_alarm = 0; + uint32_t counter_time = 0U, counter_alarm = 0U; /* Check input parameters */ if((hrtc == NULL) || (sTime == NULL)) @@ -501,8 +501,8 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim assert_param(IS_RTC_MINUTES(sTime->Minutes)); assert_param(IS_RTC_SECONDS(sTime->Seconds)); - counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600) + \ - ((uint32_t)sTime->Minutes * 60) + \ + counter_time = (uint32_t)(((uint32_t)sTime->Hours * 3600U) + \ + ((uint32_t)sTime->Minutes * 60U) + \ ((uint32_t)sTime->Seconds)); } else @@ -511,8 +511,8 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600) + \ - ((uint32_t)(RTC_Bcd2ToByte(sTime->Minutes)) * 60) + \ + counter_time = (((uint32_t)(RTC_Bcd2ToByte(sTime->Hours)) * 3600U) + \ + ((uint32_t)(RTC_Bcd2ToByte(sTime->Minutes)) * 60U) + \ ((uint32_t)(RTC_Bcd2ToByte(sTime->Seconds)))); } @@ -541,7 +541,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim if(counter_alarm < counter_time) { /* Add 1 day to alarm counter*/ - counter_alarm += (uint32_t)(24 * 3600); + counter_alarm += (uint32_t)(24U * 3600U); /* Write new Alarm counter in RTC registers */ if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) @@ -578,7 +578,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim */ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { - uint32_t counter_time = 0, counter_alarm = 0, days_elapsed = 0, hours = 0; + uint32_t counter_time = 0U, counter_alarm = 0U, days_elapsed = 0U, hours = 0U; /* Check input parameters */ if((hrtc == NULL) || (sTime == NULL)) @@ -599,17 +599,17 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim counter_time = RTC_ReadTimeCounter(hrtc); /* Fill the structure fields with the read parameters */ - hours = counter_time / 3600; - sTime->Minutes = (uint8_t)((counter_time % 3600) / 60); - sTime->Seconds = (uint8_t)((counter_time % 3600) % 60); + hours = counter_time / 3600U; + sTime->Minutes = (uint8_t)((counter_time % 3600U) / 60U); + sTime->Seconds = (uint8_t)((counter_time % 3600U) % 60U); - if (hours >= 24) + if (hours >= 24U) { /* Get number of days elapsed from last calculation */ - days_elapsed = (hours / 24); + days_elapsed = (hours / 24U); /* Set Hours in RTC_TimeTypeDef structure*/ - sTime->Hours = (hours % 24); + sTime->Hours = (hours % 24U); /* Read Alarm counter in RTC registers */ counter_alarm = RTC_ReadAlarmCounter(hrtc); @@ -627,7 +627,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim } /* Set updated time in decreasing counter by number of days elapsed */ - counter_time -= (days_elapsed * 24 * 3600); + counter_time -= (days_elapsed * 24U * 3600U); /* Write time counter in RTC registers */ if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) @@ -689,7 +689,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim */ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { - uint32_t counter_time = 0, counter_alarm = 0, hours = 0; + uint32_t counter_time = 0U, counter_alarm = 0U, hours = 0U; /* Check input parameters */ if((hrtc == NULL) || (sDate == NULL)) @@ -737,11 +737,11 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat counter_time = RTC_ReadTimeCounter(hrtc); /* Fill the structure fields with the read parameters */ - hours = counter_time / 3600; - if (hours > 24) + hours = counter_time / 3600U; + if (hours > 24U) { /* Set updated time in decreasing counter by number of days elapsed */ - counter_time -= ((hours / 24) * 24 * 3600); + counter_time -= ((hours / 24U) * 24U * 3600U); /* Write time counter in RTC registers */ if (RTC_WriteTimeCounter(hrtc, counter_time) != HAL_OK) { @@ -763,7 +763,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat if(counter_alarm < counter_time) { /* Add 1 day to alarm counter*/ - counter_alarm += (uint32_t)(24 * 3600); + counter_alarm += (uint32_t)(24U * 3600U); /* Write new Alarm counter in RTC registers */ if (RTC_WriteAlarmCounter(hrtc, counter_alarm) != HAL_OK) @@ -803,7 +803,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { - RTC_TimeTypeDef stime = {0}; + RTC_TimeTypeDef stime = {0U}; /* Check input parameters */ if((hrtc == NULL) || (sDate == NULL)) @@ -868,8 +868,8 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t counter_alarm = 0, counter_time; - RTC_TimeTypeDef stime = {0}; + uint32_t counter_alarm = 0U, counter_time; + RTC_TimeTypeDef stime = {0U}; /* Check input parameters */ if((hrtc == NULL) || (sAlarm == NULL)) @@ -893,8 +893,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } /* Convert time in seconds */ - counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600) + \ - ((uint32_t)stime.Minutes * 60) + \ + counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \ + ((uint32_t)stime.Minutes * 60U) + \ ((uint32_t)stime.Seconds)); if(Format == RTC_FORMAT_BIN) @@ -903,8 +903,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600) + \ - ((uint32_t)sAlarm->AlarmTime.Minutes * 60) + \ + counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \ + ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \ ((uint32_t)sAlarm->AlarmTime.Seconds)); } else @@ -913,8 +913,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600) + \ - ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60) + \ + counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \ + ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \ ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); } @@ -922,7 +922,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA if (counter_alarm < counter_time) { /* Add 1 day to alarm counter*/ - counter_alarm += (uint32_t)(24 * 3600); + counter_alarm += (uint32_t)(24U * 3600U); } /* Write Alarm counter in RTC registers */ @@ -960,8 +960,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA */ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t counter_alarm = 0, counter_time; - RTC_TimeTypeDef stime = {0}; + uint32_t counter_alarm = 0U, counter_time; + RTC_TimeTypeDef stime = {0U}; /* Check input parameters */ if((hrtc == NULL) || (sAlarm == NULL)) @@ -985,8 +985,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } /* Convert time in seconds */ - counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600) + \ - ((uint32_t)stime.Minutes * 60) + \ + counter_time = (uint32_t)(((uint32_t)stime.Hours * 3600U) + \ + ((uint32_t)stime.Minutes * 60U) + \ ((uint32_t)stime.Seconds)); if(Format == RTC_FORMAT_BIN) @@ -995,8 +995,8 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600) + \ - ((uint32_t)sAlarm->AlarmTime.Minutes * 60) + \ + counter_alarm = (uint32_t)(((uint32_t)sAlarm->AlarmTime.Hours * 3600U) + \ + ((uint32_t)sAlarm->AlarmTime.Minutes * 60U) + \ ((uint32_t)sAlarm->AlarmTime.Seconds)); } else @@ -1005,16 +1005,16 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600) + \ - ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60) + \ - ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + counter_alarm = (((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)) * 3600U) + \ + ((uint32_t)(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)) * 60U) + \ + ((uint32_t)RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); } /* Check that requested alarm should expire in the same day (otherwise add 1 day) */ if (counter_alarm < counter_time) { /* Add 1 day to alarm counter*/ - counter_alarm += (uint32_t)(24 * 3600); + counter_alarm += (uint32_t)(24U * 3600U); } /* Write alarm counter in RTC registers */ @@ -1065,12 +1065,15 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef */ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { - uint32_t counter_alarm = 0; + uint32_t counter_alarm = 0U; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Alarm); /* Check input parameters */ if((hrtc == NULL) || (sAlarm == NULL)) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ @@ -1082,9 +1085,9 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /* Fill the structure with the read parameters */ /* Set hours in a day range (between 0 to 24)*/ - sAlarm->AlarmTime.Hours = (uint32_t)((counter_alarm / 3600) % 24); - sAlarm->AlarmTime.Minutes = (uint32_t)((counter_alarm % 3600) / 60); - sAlarm->AlarmTime.Seconds = (uint32_t)((counter_alarm % 3600) % 60); + sAlarm->AlarmTime.Hours = (uint32_t)((counter_alarm / 3600U) % 24U); + sAlarm->AlarmTime.Minutes = (uint32_t)((counter_alarm % 3600U) / 60U); + sAlarm->AlarmTime.Seconds = (uint32_t)((counter_alarm % 3600U) % 60U); if(Format != RTC_FORMAT_BIN) { @@ -1107,6 +1110,9 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA */ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(Alarm); + /* Check the parameters */ assert_param(IS_RTC_ALARM(Alarm)); @@ -1306,7 +1312,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Check input parameters */ if(hrtc == NULL) @@ -1353,8 +1359,8 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) */ static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc) { - uint16_t high1 = 0, high2 = 0, low = 0; - uint32_t timecounter = 0; + uint16_t high1 = 0U, high2 = 0U, low = 0U; + uint32_t timecounter = 0U; high1 = READ_REG(hrtc->Instance->CNTH & RTC_CNTH_RTC_CNT); low = READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT); @@ -1363,12 +1369,12 @@ static uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc) if (high1 != high2) { /* In this case the counter roll over during reading of CNTL and CNTH registers, read again CNTL register then return the counter value */ - timecounter = (((uint32_t) high2 << 16 ) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT)); + timecounter = (((uint32_t) high2 << 16U) | READ_REG(hrtc->Instance->CNTL & RTC_CNTL_RTC_CNT)); } else { /* No counter roll over during reading of CNTL and CNTH registers, counter value is equal to first value of CNTL and CNTH */ - timecounter = (((uint32_t) high1 << 16 ) | low); + timecounter = (((uint32_t) high1 << 16U) | low); } return timecounter; @@ -1393,7 +1399,7 @@ static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t else { /* Set RTC COUNTER MSB word */ - WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16)); + WRITE_REG(hrtc->Instance->CNTH, (TimeCounter >> 16U)); /* Set RTC COUNTER LSB word */ WRITE_REG(hrtc->Instance->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); @@ -1415,12 +1421,12 @@ static HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t */ static uint32_t RTC_ReadAlarmCounter(RTC_HandleTypeDef* hrtc) { - uint16_t high1 = 0, low = 0; + uint16_t high1 = 0U, low = 0U; high1 = READ_REG(hrtc->Instance->ALRH & RTC_CNTH_RTC_CNT); low = READ_REG(hrtc->Instance->ALRL & RTC_CNTL_RTC_CNT); - return (((uint32_t) high1 << 16 ) | low); + return (((uint32_t) high1 << 16U) | low); } /** @@ -1442,7 +1448,7 @@ static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef* hrtc, uint32_t else { /* Set RTC COUNTER MSB word */ - WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16)); + WRITE_REG(hrtc->Instance->ALRH, (AlarmCounter >> 16U)); /* Set RTC COUNTER LSB word */ WRITE_REG(hrtc->Instance->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR)); @@ -1464,7 +1470,7 @@ static HAL_StatusTypeDef RTC_WriteAlarmCounter(RTC_HandleTypeDef* hrtc, uint32_t */ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; tickstart = HAL_GetTick(); /* Wait till RTC is in INIT state and if Time out is reached exit */ @@ -1491,7 +1497,7 @@ static HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) */ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart = 0; + uint32_t tickstart = 0U; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1516,15 +1522,15 @@ static HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef* hrtc) */ static uint8_t RTC_ByteToBcd2(uint8_t Value) { - uint32_t bcdhigh = 0; + uint32_t bcdhigh = 0U; - while(Value >= 10) + while(Value >= 10U) { bcdhigh++; - Value -= 10; + Value -= 10U; } - return ((uint8_t)(bcdhigh << 4) | Value); + return ((uint8_t)(bcdhigh << 4U) | Value); } /** @@ -1534,8 +1540,8 @@ static uint8_t RTC_ByteToBcd2(uint8_t Value) */ static uint8_t RTC_Bcd2ToByte(uint8_t Value) { - uint32_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + uint32_t tmp = 0U; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U; return (tmp + (Value & (uint8_t)0x0F)); } @@ -1548,8 +1554,8 @@ static uint8_t RTC_Bcd2ToByte(uint8_t Value) */ static void RTC_DateUpdate(RTC_HandleTypeDef* hrtc, uint32_t DayElapsed) { - uint32_t year = 0, month = 0, day = 0; - uint32_t loop = 0; + uint32_t year = 0U, month = 0U, day = 0U; + uint32_t loop = 0U; /* Get the current year*/ year = hrtc->DateToUpdate.Year; @@ -1558,35 +1564,35 @@ static void RTC_DateUpdate(RTC_HandleTypeDef* hrtc, uint32_t DayElapsed) month = hrtc->DateToUpdate.Month; day = hrtc->DateToUpdate.Date; - for (loop = 0; loop < DayElapsed; loop++) + for (loop = 0U; loop < DayElapsed; loop++) { - if((month == 1) || (month == 3) || (month == 5) || (month == 7) || \ - (month == 8) || (month == 10) || (month == 12)) + if((month == 1U) || (month == 3U) || (month == 5U) || (month == 7U) || \ + (month == 8U) || (month == 10U) || (month == 12U)) { - if(day < 31) + if(day < 31U) { day++; } /* Date structure member: day = 31 */ else { - if(month != 12) + if(month != 12U) { month++; - day = 1; + day = 1U; } /* Date structure member: day = 31 & month =12 */ else { - month = 1; - day = 1; + month = 1U; + day = 1U; year++; } } } - else if((month == 4) || (month == 6) || (month == 9) || (month == 11)) + else if((month == 4U) || (month == 6U) || (month == 9U) || (month == 11U)) { - if(day < 30) + if(day < 30U) { day++; } @@ -1594,16 +1600,16 @@ static void RTC_DateUpdate(RTC_HandleTypeDef* hrtc, uint32_t DayElapsed) else { month++; - day = 1; + day = 1U; } } - else if(month == 2) + else if(month == 2U) { - if(day < 28) + if(day < 28U) { day++; } - else if(day == 28) + else if(day == 28U) { /* Leap year */ if(RTC_IsLeapYear(year)) @@ -1613,13 +1619,13 @@ static void RTC_DateUpdate(RTC_HandleTypeDef* hrtc, uint32_t DayElapsed) else { month++; - day = 1; + day = 1U; } } - else if(day == 29) + else if(day == 29U) { month++; - day = 1; + day = 1U; } } } @@ -1643,23 +1649,23 @@ static void RTC_DateUpdate(RTC_HandleTypeDef* hrtc, uint32_t DayElapsed) */ static uint8_t RTC_IsLeapYear(uint16_t nYear) { - if((nYear % 4) != 0) + if((nYear % 4U) != 0U) { - return 0; + return 0U; } - if((nYear % 100) != 0) + if((nYear % 100U) != 0U) { - return 1; + return 1U; } - if((nYear % 400) == 0) + if((nYear % 400U) == 0U) { - return 1; + return 1U; } else { - return 0; + return 0U; } } @@ -1680,19 +1686,19 @@ static uint8_t RTC_IsLeapYear(uint16_t nYear) */ static uint8_t RTC_WeekDayNum(uint32_t nYear, uint8_t nMonth, uint8_t nDay) { - uint32_t year = 0, weekday = 0; + uint32_t year = 0U, weekday = 0U; - year = 2000 + nYear; + year = 2000U + nYear; - if(nMonth < 3) + if(nMonth < 3U) { /*D = { [(23 x month)/9] + day + 4 + year + [(year-1)/4] - [(year-1)/100] + [(year-1)/400] } mod 7*/ - weekday = (((23 * nMonth)/9) + nDay + 4 + year + ((year-1)/4) - ((year-1)/100) + ((year-1)/400)) % 7; + weekday = (((23U * nMonth)/9U) + nDay + 4U + year + ((year-1U)/4U) - ((year-1U)/100U) + ((year-1U)/400U)) % 7U; } else { /*D = { [(23 x month)/9] + day + 4 + year + [year/4] - [year/100] + [year/400] - 2 } mod 7*/ - weekday = (((23 * nMonth)/9) + nDay + 4 + year + (year/4) - (year/100) + (year/400) - 2 ) % 7; + weekday = (((23U * nMonth)/9U) + nDay + 4U + year + (year/4U) - (year/100U) + (year/400U) - 2U ) % 7U; } return (uint8_t)weekday; diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.h index b81c1f16117..1889c0ca20c 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rtc.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -58,14 +58,14 @@ * @{ */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= (uint32_t)0xFFFFF) || ((PREDIV) == RTC_AUTO_1_SECOND)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) +#define IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) -#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) -#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) #define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A) #define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \ ((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \ @@ -83,7 +83,7 @@ /** @defgroup RTC_Timeout_Value Default Timeout Value * @{ */ -#define RTC_TIMEOUT_VALUE 1000 +#define RTC_TIMEOUT_VALUE 1000U /** * @} */ @@ -137,11 +137,11 @@ typedef struct */ typedef enum { - HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ }HAL_RTCStateTypeDef; @@ -207,7 +207,7 @@ typedef struct /** @defgroup RTC_Automatic_Prediv_1_Second Automatic calculation of prediv for 1sec timebase * @{ */ -#define RTC_AUTO_1_SECOND ((uint32_t)0xFFFFFFFF) +#define RTC_AUTO_1_SECOND 0xFFFFFFFFU /** * @} @@ -216,8 +216,8 @@ typedef struct /** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format * @{ */ -#define RTC_FORMAT_BIN ((uint32_t)0x000000000) -#define RTC_FORMAT_BCD ((uint32_t)0x000000001) +#define RTC_FORMAT_BIN 0x000000000U +#define RTC_FORMAT_BCD 0x000000001U /** * @} @@ -263,7 +263,7 @@ typedef struct /** @defgroup RTC_Alarms_Definitions Alarms Definitions * @{ */ -#define RTC_ALARM_A 0 /*!< Specify alarm ID (mainly for legacy purposes) */ +#define RTC_ALARM_A 0U /*!< Specify alarm ID (mainly for legacy purposes) */ /** * @} @@ -274,7 +274,7 @@ typedef struct * @{ */ -#define RTC_OUTPUTSOURCE_NONE ((uint32_t)0x00000000) /*!< No output on the TAMPER pin */ +#define RTC_OUTPUTSOURCE_NONE 0x00000000U /*!< No output on the TAMPER pin */ #define RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO /*!< RTC clock with a frequency divided by 64 on the TAMPER pin */ #define RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE /*!< Alarm pulse signal on the TAMPER pin */ #define RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin */ @@ -453,14 +453,22 @@ typedef struct * @brief ALARM EXTI line configuration: set rising & falling edge trigger. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() \ +do{ \ + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Disable the ALARM Extended Interrupt Rising & Falling Trigger. * This parameter can be: * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()(); +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() \ +do{ \ + __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** * @brief Check whether the specified ALARM EXTI interrupt flag is set or not. diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.c index 8d90e937d6b..1a8d9dca54b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extension peripheral: @@ -197,7 +197,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T { return HAL_ERROR; } - + /* Prevent unused argument(s) compilation warning */ + UNUSED(Tamper); + assert_param(IS_RTC_TAMPER(Tamper)); /* Process Locked */ @@ -287,7 +289,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -485,13 +487,16 @@ __weak void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc) */ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) { - uint32_t tmp = 0; + uint32_t tmp = 0U; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); tmp = (uint32_t)BKP_BASE; - tmp += (BackupRegister * 4); + tmp += (BackupRegister * 4U); *(__IO uint32_t *) tmp = (Data & BKP_DR1_D); } @@ -507,14 +512,17 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 */ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) { - uint32_t backupregister = 0; - uint32_t pvalue = 0; + uint32_t backupregister = 0U; + uint32_t pvalue = 0U; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); backupregister = (uint32_t)BKP_BASE; - backupregister += (BackupRegister * 4); + backupregister += (BackupRegister * 4U); pvalue = (*(__IO uint32_t *)(backupregister)) & BKP_DR1_D; @@ -539,7 +547,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo { return HAL_ERROR; } - + /* Prevent unused argument(s) compilation warning */ + UNUSED(SmoothCalibPeriod); + UNUSED(SmoothCalibPlusPulses); + /* Check the parameters */ assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.h index 25d18442595..d6b8d437bc4 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rtc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of RTC HAL Extension module. ****************************************************************************** * @attention @@ -73,14 +73,14 @@ #define IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1) #define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ - ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) -#if RTC_BKP_NUMBER > 10 -#define IS_RTC_BKP(BKP) (((BKP) <= (uint32_t) RTC_BKP_DR10) || (((BKP) >= (uint32_t) RTC_BKP_DR11) && ((BKP) <= (uint32_t) RTC_BKP_DR42))) +#if RTC_BKP_NUMBER > 10U +#define IS_RTC_BKP(BKP) (((BKP) <= (uint32_t)RTC_BKP_DR10) || (((BKP) >= (uint32_t)RTC_BKP_DR11) && ((BKP) <= (uint32_t)RTC_BKP_DR42))) #else -#define IS_RTC_BKP(BKP) ((BKP) <= (uint32_t) RTC_BKP_NUMBER) +#define IS_RTC_BKP(BKP) ((BKP) <= (uint32_t)RTC_BKP_NUMBER) #endif -#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007F) +#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007FU) /** * @} @@ -129,7 +129,7 @@ typedef struct * @{ */ #define RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ -#define RTC_TAMPERTRIGGER_HIGHLEVEL ((uint32_t)0x00000000) /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ +#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x00000000U /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ /** * @} @@ -138,52 +138,52 @@ typedef struct /** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions * @{ */ -#if RTC_BKP_NUMBER > 0 -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) +#if RTC_BKP_NUMBER > 0U +#define RTC_BKP_DR1 0x00000001U +#define RTC_BKP_DR2 0x00000002U +#define RTC_BKP_DR3 0x00000003U +#define RTC_BKP_DR4 0x00000004U +#define RTC_BKP_DR5 0x00000005U +#define RTC_BKP_DR6 0x00000006U +#define RTC_BKP_DR7 0x00000007U +#define RTC_BKP_DR8 0x00000008U +#define RTC_BKP_DR9 0x00000009U +#define RTC_BKP_DR10 0x0000000AU #endif /* RTC_BKP_NUMBER > 0 */ -#if RTC_BKP_NUMBER > 10 -#define RTC_BKP_DR11 ((uint32_t)0x00000010) -#define RTC_BKP_DR12 ((uint32_t)0x00000011) -#define RTC_BKP_DR13 ((uint32_t)0x00000012) -#define RTC_BKP_DR14 ((uint32_t)0x00000013) -#define RTC_BKP_DR15 ((uint32_t)0x00000014) -#define RTC_BKP_DR16 ((uint32_t)0x00000015) -#define RTC_BKP_DR17 ((uint32_t)0x00000016) -#define RTC_BKP_DR18 ((uint32_t)0x00000017) -#define RTC_BKP_DR19 ((uint32_t)0x00000018) -#define RTC_BKP_DR20 ((uint32_t)0x00000019) -#define RTC_BKP_DR21 ((uint32_t)0x0000001A) -#define RTC_BKP_DR22 ((uint32_t)0x0000001B) -#define RTC_BKP_DR23 ((uint32_t)0x0000001C) -#define RTC_BKP_DR24 ((uint32_t)0x0000001D) -#define RTC_BKP_DR25 ((uint32_t)0x0000001E) -#define RTC_BKP_DR26 ((uint32_t)0x0000001F) -#define RTC_BKP_DR27 ((uint32_t)0x00000020) -#define RTC_BKP_DR28 ((uint32_t)0x00000021) -#define RTC_BKP_DR29 ((uint32_t)0x00000022) -#define RTC_BKP_DR30 ((uint32_t)0x00000023) -#define RTC_BKP_DR31 ((uint32_t)0x00000024) -#define RTC_BKP_DR32 ((uint32_t)0x00000025) -#define RTC_BKP_DR33 ((uint32_t)0x00000026) -#define RTC_BKP_DR34 ((uint32_t)0x00000027) -#define RTC_BKP_DR35 ((uint32_t)0x00000028) -#define RTC_BKP_DR36 ((uint32_t)0x00000029) -#define RTC_BKP_DR37 ((uint32_t)0x0000002A) -#define RTC_BKP_DR38 ((uint32_t)0x0000002B) -#define RTC_BKP_DR39 ((uint32_t)0x0000002C) -#define RTC_BKP_DR40 ((uint32_t)0x0000002D) -#define RTC_BKP_DR41 ((uint32_t)0x0000002E) -#define RTC_BKP_DR42 ((uint32_t)0x0000002F) +#if RTC_BKP_NUMBER > 10U +#define RTC_BKP_DR11 0x00000010U +#define RTC_BKP_DR12 0x00000011U +#define RTC_BKP_DR13 0x00000012U +#define RTC_BKP_DR14 0x00000013U +#define RTC_BKP_DR15 0x00000014U +#define RTC_BKP_DR16 0x00000015U +#define RTC_BKP_DR17 0x00000016U +#define RTC_BKP_DR18 0x00000017U +#define RTC_BKP_DR19 0x00000018U +#define RTC_BKP_DR20 0x00000019U +#define RTC_BKP_DR21 0x0000001AU +#define RTC_BKP_DR22 0x0000001BU +#define RTC_BKP_DR23 0x0000001CU +#define RTC_BKP_DR24 0x0000001DU +#define RTC_BKP_DR25 0x0000001EU +#define RTC_BKP_DR26 0x0000001FU +#define RTC_BKP_DR27 0x00000020U +#define RTC_BKP_DR28 0x00000021U +#define RTC_BKP_DR29 0x00000022U +#define RTC_BKP_DR30 0x00000023U +#define RTC_BKP_DR31 0x00000024U +#define RTC_BKP_DR32 0x00000025U +#define RTC_BKP_DR33 0x00000026U +#define RTC_BKP_DR34 0x00000027U +#define RTC_BKP_DR35 0x00000028U +#define RTC_BKP_DR36 0x00000029U +#define RTC_BKP_DR37 0x0000002AU +#define RTC_BKP_DR38 0x0000002BU +#define RTC_BKP_DR39 0x0000002CU +#define RTC_BKP_DR40 0x0000002DU +#define RTC_BKP_DR41 0x0000002EU +#define RTC_BKP_DR42 0x0000002FU #endif /* RTC_BKP_NUMBER > 10 */ /** diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.c index f5443003a55..4a26b229d48 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.c @@ -2,15 +2,15 @@ ****************************************************************************** * @file stm32f1xx_hal_sd.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions - * + Peripheral State functions + * + SD card Control functions * @verbatim ============================================================================== @@ -43,45 +43,58 @@ (+++) Configure the SDIO and DMA interrupt priorities using functions HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ() - (+++) SDIO interrupts are managed using the macros __HAL_SD_SDIO_ENABLE_IT() - and __HAL_SD_SDIO_DISABLE_IT() inside the communication process. - (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_SDIO_GET_IT() - and __HAL_SD_SDIO_CLEAR_IT() + (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT() + and __HAL_SD_DISABLE_IT() inside the communication process. + (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT() + and __HAL_SD_CLEAR_IT() + (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT() + and HAL_SD_WriteBlocks_IT() APIs). + (+++) Configure the SDIO interrupt priorities using function + HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDIO IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDIO interrupts are managed using the macros __HAL_SD_ENABLE_IT() + and __HAL_SD_DISABLE_IT() inside the communication process. + (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_GET_IT() + and __HAL_SD_CLEAR_IT() (#) At this stage, you can perform SD read/write/erase operations after SD card initialization *** SD Card Initialization and configuration *** ================================================ [..] - To initialize the SD Card, use the HAL_SD_Init() function. It Initializes - the SD Card and put it into StandBy State (Ready for data transfer). + To initialize the SD Card, use the HAL_SD_Init() function. It Initializes + SDIO IP(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). This function provide the following operations: - - (#) Apply the SD Card initialization process at 400KHz and check the SD Card - type (Standard Capacity or High Capacity). You can change or adapt this - frequency by adjusting the "ClockDiv" field. + + (#) Initialize the SDIO peripheral interface with defaullt configuration. + The initialization process is done at 400KHz. You can change or adapt + this frequency by adjusting the "ClockDiv" field. The SD Card frequency (SDIO_CK) is computed as follows: SDIO_CK = SDIOCLK / (ClockDiv + 2) In initialization mode and according to the SD Card standard, make sure that the SDIO_CK frequency doesn't exceed 400KHz. - - (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo - structure. This structure provide also ready computed SD Card capacity - and Block size. - - -@- These information are stored in SD handle structure in case of future use. - - (#) Configure the SD Card Data transfer frequency. The card transfer - frequency is set to SDIOCLK / (SDIO_TRANSFER_CLK_DIV + 2). You can change or adapt this frequency by adjusting - the "ClockDiv" field. - The SD Card frequency (SDIO_CK) is computed as follows: - SDIO_CK = SDIOCLK / (ClockDiv + 2) + This phase of initialization is done through SDIO_Init() and + SDIO_PowerState_ON() SDIO low level APIs. + + (#) Initialize the SD card. The API used is HAL_SD_InitCard(). + This phase allows the card initialization and identification + and check the SD Card type (Standard Capacity or High Capacity) + The initialization flow is compatible with SD standard. + This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case + of plug-off plug-in. + + (#) Configure the SD Card Data transfer frequency. By Default, the card transfer + frequency is set to 24MHz. You can change or adapt this frequency by adjusting + the "ClockDiv" field. In transfer mode and according to the SD Card standard, make sure that the SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. + To be able to use a frequency higher than 24MHz, you should use the SDIO + peripheral in bypass mode. Refer to the corresponding reference manual + for more details. (#) Select the corresponding SD Card according to the address read with the step 2. @@ -91,65 +104,101 @@ ============================== [..] (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). + This function allows the read of 512 bytes blocks. You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the DMA transfer process through the SD Rx interrupt event. + + (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT(). + This function allows the read of 512 bytes blocks. You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. - After this, you have to call the function HAL_SD_CheckReadOperation(), to insure - that the read transfer is done correctly in both DMA and SD sides. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the IT transfer process through the SD Rx interrupt event. *** SD Card Write operation *** =============================== [..] (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). + This function allows the read of 512 bytes blocks. You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). - This function support only 512-bytes block length (the block size should be - chosen as 512 byte). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the DMA transfer process through the SD Tx interrupt event. + + (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT(). + This function allows the read of 512 bytes blocks. You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. - After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure - that the write transfer is done correctly in both DMA and SD sides. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the IT transfer process through the SD Tx interrupt event. *** SD card status *** ====================== [..] - (+) At any time, you can check the SD Card status and get the SD card state - by using the HAL_SD_GetStatus() function. This function checks first if the - SD card is still connected and then get the internal SD Card transfer state. - (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() - function. + (+) The SD Status contains status bits that are related to the SD Memory + Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus(). + + *** SD card information *** + =========================== + [..] + (+) To get SD card information, you can use the function HAL_SD_GetCardInfo(). + It returns useful information about the SD card such as block size, card type, + block number ... + + *** SD card CSD register *** + ============================ + [..] + (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. + + *** SD card CID register *** + ============================ + [..] + (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register. + Some of the CSD parameters are useful for card initialization and identification. *** SD HAL driver macros list *** ================================== [..] Below the list of most used macros in SD HAL driver. - (+) __HAL_SD_SDIO_ENABLE : Enable the SD device - (+) __HAL_SD_SDIO_DISABLE : Disable the SD device - (+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer - (+) __HAL_SD_SDIO_DMA_DISABLE: Disable the SDIO DMA transfer - (+) __HAL_SD_SDIO_ENABLE_IT: Enable the SD device interrupt - (+) __HAL_SD_SDIO_DISABLE_IT: Disable the SD device interrupt - (+) __HAL_SD_SDIO_GET_FLAG:Check whether the specified SD flag is set or not - (+) __HAL_SD_SDIO_CLEAR_FLAG: Clear the SD's pending flags + + (+) __HAL_SD_ENABLE : Enable the SD device + (+) __HAL_SD_DISABLE : Disable the SD device + (+) __HAL_SD_DMA_ENABLE: Enable the SDIO DMA transfer + (+) __HAL_SD_DMA_DISABLE: Disable the SDIO DMA transfer + (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt + (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt + (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not + (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags + + [..] + (@) You can refer to the SD HAL driver header file for more useful macros - -@- You can refer to the SD HAL driver header file for more useful macros - @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -179,105 +228,23 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" -#ifdef HAL_SD_MODULE_ENABLED - #if defined(STM32F103xE) || defined(STM32F103xG) /** @addtogroup STM32F1xx_HAL_Driver * @{ */ -/** @defgroup SD SD - * @brief SD HAL module driver +/** @addtogroup SD * @{ */ +#ifdef HAL_SD_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ - -/** @defgroup SD_Private_Define SD Private Constant +/** @addtogroup SD_Private_Defines * @{ */ -/** - * @brief SDIO Data block size - */ -#define DATA_BLOCK_SIZE ((uint32_t)(9 << 4)) -/** - * @brief SDIO Static flags, TimeOut, FIFO Address - */ -#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ - SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ - SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ - SDIO_FLAG_DBCKEND)) - -#define SDIO_CMD0TIMEOUT ((uint32_t)0x00010000) - -/** - * @brief Mask for errors Card Status R1 (OCR Register) - */ -#define SD_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) -#define SD_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000) -#define SD_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000) -#define SD_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000) -#define SD_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000) -#define SD_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000) -#define SD_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000) -#define SD_OCR_COM_CRC_FAILED ((uint32_t)0x00800000) -#define SD_OCR_ILLEGAL_CMD ((uint32_t)0x00400000) -#define SD_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000) -#define SD_OCR_CC_ERROR ((uint32_t)0x00100000) -#define SD_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) -#define SD_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) -#define SD_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) -#define SD_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000) -#define SD_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000) -#define SD_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000) -#define SD_OCR_ERASE_RESET ((uint32_t)0x00002000) -#define SD_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008) -#define SD_OCR_ERRORBITS ((uint32_t)0xFDFFE008) - -/** - * @brief Masks for R6 Response - */ -#define SD_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000) -#define SD_R6_ILLEGAL_CMD ((uint32_t)0x00004000) -#define SD_R6_COM_CRC_FAILED ((uint32_t)0x00008000) - -#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000) -#define SD_HIGH_CAPACITY ((uint32_t)0x40000000) -#define SD_STD_CAPACITY ((uint32_t)0x00000000) -#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) - -#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF) -#define SD_ALLZERO ((uint32_t)0x00000000) - -#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000) -#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000) -#define SD_CARD_LOCKED ((uint32_t)0x02000000) - -#define SD_DATATIMEOUT ((uint32_t)0xFFFFFFFF) -#define SD_0TO7BITS ((uint32_t)0x000000FF) -#define SD_8TO15BITS ((uint32_t)0x0000FF00) -#define SD_16TO23BITS ((uint32_t)0x00FF0000) -#define SD_24TO31BITS ((uint32_t)0xFF000000) -#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF) - -#define SD_HALFFIFO ((uint32_t)0x00000008) -#define SD_HALFFIFOBYTES ((uint32_t)0x00000020) - -/** - * @brief Command Class Supported - */ -#define SD_CCCC_LOCK_UNLOCK ((uint32_t)0x00000080) -#define SD_CCCC_WRITE_PROT ((uint32_t)0x00000040) -#define SD_CCCC_ERASE ((uint32_t)0x00000020) - -/** - * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SD_SDIO_SEND_IF_COND ((uint32_t)SD_CMD_HS_SEND_EXT_CSD) - + /** * @} */ @@ -286,120 +253,170 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ - /** @defgroup SD_Private_Functions SD Private Functions * @{ */ - -static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t Addr); -static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); -static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus); -static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD); -static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA); -static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd); -static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); -static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma); -static void SD_DMA_RxError(DMA_HandleTypeDef *hdma); -static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma); -static void SD_DMA_TxError(DMA_HandleTypeDef *hdma); - +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd); +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd); +static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd); +static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); +static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd); +static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd); +static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd); +static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SD_DMAError(DMA_HandleTypeDef *hdma); +static void SD_DMATxAbort(DMA_HandleTypeDef *hdma); +static void SD_DMARxAbort(DMA_HandleTypeDef *hdma); /** * @} */ - -/** @defgroup SD_Exported_Functions SD Exported Functions + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SD_Exported_Functions * @{ */ -/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @addtogroup SD_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions * @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== [..] This section provides functions allowing to initialize/de-initialize the SD card device to be ready for use. - - + @endverbatim * @{ */ /** - * @brief Initializes the SD card according to the specified parameters in the + * @brief Initializes the SD according to the specified parameters in the SD_HandleTypeDef and create the associated handle. - * @param hsd: SD handle - * @param SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information - * @retval HAL SD error state + * @param hsd: Pointer to the SD handle + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo) -{ - __IO HAL_SD_ErrorTypedef errorstate = SD_OK; - SD_InitTypeDef tmpinit = {0}; +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) +{ + /* Check the SD handle allocation */ + if(hsd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance)); + assert_param(IS_SDIO_CLOCK_EDGE(hsd->Init.ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(hsd->Init.ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(hsd->Init.BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); + assert_param(IS_SDIO_CLKDIV(hsd->Init.ClockDiv)); + + if(hsd->State == HAL_SD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsd->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_SD_MspInit(hsd); + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize the Card parameters */ + HAL_SD_InitCard(hsd); + + /* Initialize the error code */ + hsd->ErrorCode = HAL_DMA_ERROR_NONE; - /* Initialize the low level hardware (MSP) */ - HAL_SD_MspInit(hsd); + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; + + /* Initialize the SD state */ + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the SD Card. + * @param hsd: Pointer to SD handle + * @note This function initializes the SD card. It could be used when a card + re-initialization is needed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate = HAL_SD_ERROR_NONE; + SD_InitTypeDef Init; /* Default SDIO peripheral configuration for SD card initialization */ - tmpinit.ClockEdge = SDIO_CLOCK_EDGE_RISING; - tmpinit.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; - tmpinit.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; - tmpinit.BusWide = SDIO_BUS_WIDE_1B; - tmpinit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; - tmpinit.ClockDiv = SDIO_INIT_CLK_DIV; - + Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; + Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; + Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDIO_BUS_WIDE_1B; + Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; + Init.ClockDiv = SDIO_INIT_CLK_DIV; + /* Initialize SDIO peripheral interface with default configuration */ - SDIO_Init(hsd->Instance, tmpinit); + SDIO_Init(hsd->Instance, Init); + + /* Disable SDIO Clock */ + __HAL_SD_DISABLE(hsd); - /* Identify card operating voltage */ - errorstate = SD_PowerON(hsd); + /* Set Power State to ON */ + SDIO_PowerState_ON(hsd->Instance); - if(errorstate != SD_OK) - { - return errorstate; - } + /* Enable SDIO Clock */ + __HAL_SD_ENABLE(hsd); - /* Initialize the present SDIO card(s) and put them in idle state */ - errorstate = SD_Initialize_Cards(hsd); + /* Required power up waiting time before starting the SD initialization + sequence */ + HAL_Delay(2U); - if (errorstate != SD_OK) + /* Identify card operating voltage */ + errorstate = SD_PowerON(hsd); + if(errorstate != HAL_SD_ERROR_NONE) { - return errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; } - - /* Read CSD/CID MSD registers */ - errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo); - - if (errorstate == SD_OK) + + /* Card initialization */ + errorstate = SD_InitCard(hsd); + if(errorstate != HAL_SD_ERROR_NONE) { - /* Select the Card */ - errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16)); + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; } - - /* Configure SDIO peripheral interface */ - SDIO_Init(hsd->Instance, hsd->Init); - - return errorstate; + + return HAL_OK; } /** * @brief De-Initializes the SD card. - * @param hsd: SD handle + * @param hsd: Pointer to SD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) { + /* Check the SD handle allocation */ + if(hsd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDIO_ALL_INSTANCE(hsd->Instance)); + + hsd->State = HAL_SD_STATE_BUSY; /* Set SD power state to off */ SD_PowerOFF(hsd); @@ -407,19 +424,23 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) /* De-Initialize the MSP layer */ HAL_SD_MspDeInit(hsd); + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_RESET; + return HAL_OK; } /** * @brief Initializes the SD MSP. - * @param hsd: SD handle + * @param hsd: Pointer to SD handle * @retval None */ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_MspInit could be implemented in the user file */ @@ -427,13 +448,14 @@ __weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) /** * @brief De-Initialize SD MSP. - * @param hsd: SD handle + * @param hsd: Pointer to SD handle * @retval None */ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsd); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SD_MspDeInit could be implemented in the user file */ @@ -443,13 +465,13 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) * @} */ -/** @defgroup SD_Exported_Functions_Group2 IO operation functions +/** @addtogroup SD_Exported_Functions_Group2 * @brief Data transfer functions * @verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== + ============================================================================== + ##### IO operation functions ##### + ============================================================================== [..] This subsection provides a set of functions allowing to manage the data transfer from/to SD card. @@ -460,2989 +482,2433 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) /** * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by polling mode. - * @param hsd: SD handle - * @param pReadBuffer: pointer to the buffer that will contain the received data - * @param ReadAddr: Address from where data is to be read - * @param BlockSize: SD card Data block size (in bytes) - * This parameter should be 512 - * @param NumberOfBlocks: Number of SD blocks to read - * @retval SD Card error state + * is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param pData: pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of SD blocks to read + * @param Timeout: Specify timeout value + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - SDIO_DataInitTypeDef sdio_datainitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - ReadAddr /= 512; - } - - /* Set Block Size for Card */ - sdio_cmdinitstructure.Argument = (uint32_t) BlockSize; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t tickstart = HAL_GetTick(); + uint32_t count = 0U, *tempbuff = (uint32_t *)pData; - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize; - sdio_datainitstructure.DataBlockSize = DATA_BLOCK_SIZE; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - if(NumberOfBlocks > 1) - { - /* Send CMD18 READ_MULT_BLOCK with argument data address */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; - } - else + if(NULL == pData) { - /* Send CMD17 READ_SINGLE_BLOCK */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; } - - sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1) + + if(hsd->State == HAL_SD_STATE_READY) { - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); + hsd->ErrorCode = HAL_DMA_ERROR_NONE; - if (errorstate != SD_OK) + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { - return errorstate; + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hsd->Instance, &config); + + /* Read block(s) in polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + } + else + { + hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK; + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + /* Poll on SDIO flags */ - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) + while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_STA_STBITERR)) { - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) { /* Read data from SDIO Rx FIFO */ - for (count = 0; count < 8; count++) + for(count = 0U; count < 8U; count++) { *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance); } - - tempbuff += 8; + tempbuff += 8U; } - } - } - else - { - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); - - if (errorstate != SD_OK) - { - return errorstate; - } + + if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } - /* In case of single block transfer, no need of stop transfer at all */ - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) - { - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) + /* Send stop transmission command in case of multiblock read */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + if(hsd->SdCard.CardType != CARD_SECURED) { - /* Read data from SDIO Rx FIFO */ - for (count = 0; count < 8; count++) + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) { - *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance); + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } - - tempbuff += 8; } } - } - - /* Send stop transmission command in case of multiblock read */ - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1)) - { - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\ - (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) + + /* Get error state */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) { - /* Send stop transmission command */ - errorstate = HAL_SD_StopTransfer(hsd); + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } - } - - /* Get error state */ - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - errorstate = SD_RX_OVERRUN; + /* Empty FIFO if there is still any data */ + while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))) + { + *tempbuff = SDIO_ReadFIFO(hsd->Instance); + tempbuff++; + + if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + return HAL_ERROR; + } + } - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - errorstate = SD_START_BIT_ERR; + hsd->State = HAL_SD_STATE_READY; - return errorstate; + return HAL_OK; } else { - /* No error flag set */ - } - - count = SD_DATATIMEOUT; - - /* Empty FIFO if there is still any data */ - while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0)) - { - *tempbuff = SDIO_ReadFIFO(hsd->Instance); - tempbuff++; - count--; + hsd->ErrorCode |= HAL_SD_ERROR_BUSY; + return HAL_ERROR; } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - return errorstate; } /** * @brief Allows to write block(s) to a specified address in a card. The Data - * transfer is managed by polling mode. - * @param hsd: SD handle - * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit - * @param WriteAddr: Address from where data is to be written - * @param BlockSize: SD card Data block size (in bytes) - * This parameter should be 512. - * @param NumberOfBlocks: Number of SD blocks to write - * @retval SD Card error state + * transfer is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param pData: pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of SD blocks to write + * @param Timeout: Specify timeout value + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) { - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - SDIO_DataInitTypeDef sdio_datainitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0; - uint32_t *tempbuff = (uint32_t *)pWriteBuffer; - uint8_t cardstate = 0; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - WriteAddr /= 512; - } - - /* Set Block Size for Card */ - sdio_cmdinitstructure.Argument = (uint32_t)BlockSize; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - if(NumberOfBlocks > 1) - { - /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; - } - else - { - /* Send CMD24 WRITE_SINGLE_BLOCK */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; - } - - sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - if(NumberOfBlocks > 1) - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); - } - else - { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); - } + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t tickstart = HAL_GetTick(); + uint32_t count = 0U; + uint32_t *tempbuff = (uint32_t *)pData; - if (errorstate != SD_OK) + if(NULL == pData) { - return errorstate; + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; } - - /* Set total number of bytes to write */ - totalnumberofbytes = NumberOfBlocks * BlockSize; - - /* Configure the SD DPSM (Data Path State Machine) */ - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = NumberOfBlocks * BlockSize; - sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - /* Write block(s) in polling mode */ - if(NumberOfBlocks > 1) + + if(hsd->State == HAL_SD_STATE_READY) { - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) + hsd->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + } + else + { + hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK; + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + } + if(errorstate != HAL_SD_ERROR_NONE) { - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE)) + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hsd->Instance, &config); + + /* Write block(s) in polling mode */ + while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR)) + { + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE)) { - if ((totalnumberofbytes - bytestransferred) < 32) - { - restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1); - - /* Write data to SDIO Tx FIFO */ - for (count = 0; count < restwords; count++) - { - SDIO_WriteFIFO(hsd->Instance, tempbuff); - tempbuff++; - bytestransferred += 4; - } - } - else + /* Write data to SDIO Tx FIFO */ + for(count = 0U; count < 8U; count++) { - /* Write data to SDIO Tx FIFO */ - for (count = 0; count < 8; count++) - { - SDIO_WriteFIFO(hsd->Instance, (tempbuff + count)); - } - - tempbuff += 8; - bytestransferred += 32; + SDIO_WriteFIFO(hsd->Instance, (tempbuff + count)); } + tempbuff += 8U; } - } - } - else - { - /* In case of single data block transfer no need of stop command at all */ - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) - { - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE)) + + if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout)) { - if ((totalnumberofbytes - bytestransferred) < 32) - { - restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes - bytestransferred) / 4 + 1); - - /* Write data to SDIO Tx FIFO */ - for (count = 0; count < restwords; count++) - { - SDIO_WriteFIFO(hsd->Instance, tempbuff); - tempbuff++; - bytestransferred += 4; - } - } - else + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock write */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) { - /* Write data to SDIO Tx FIFO */ - for (count = 0; count < 8; count++) - { - SDIO_WriteFIFO(hsd->Instance, (tempbuff + count)); - } - - tempbuff += 8; - bytestransferred += 32; + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } } - } - } - - /* Send stop transmission command in case of multiblock write */ - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1)) - { - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send stop transmission command */ - errorstate = HAL_SD_StopTransfer(hsd); } - } - - /* Get error state */ - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR); - errorstate = SD_TX_UNDERRUN; + /* Get error state */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - errorstate = SD_START_BIT_ERR; + hsd->State = HAL_SD_STATE_READY; - return errorstate; + return HAL_OK; } else { - /* No error flag set */ - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - /* Wait till the card is in programming state */ - errorstate = SD_IsCardProgramming(hsd, &cardstate); - - while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) - { - errorstate = SD_IsCardProgramming(hsd, &cardstate); + hsd->ErrorCode |= HAL_SD_ERROR_BUSY; + return HAL_ERROR; } - - return errorstate; } /** * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by DMA mode. - * @note This API should be followed by the function HAL_SD_CheckReadOperation() - * to check the completion of the read process - * @param hsd: SD handle - * @param pReadBuffer: Pointer to the buffer that will contain the received data - * @param ReadAddr: Address from where data is to be read - * @param BlockSize: SD card Data block size - * @note BlockSize must be 512 bytes. + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the IT transfer process through the SD Rx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Number of blocks to read. - * @retval SD Card error state + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - SDIO_DataInitTypeDef sdio_datainitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; - - /* Initialize handle flags */ - hsd->SdTransferCplt = 0; - hsd->DmaTransferCplt = 0; - hsd->SdTransferErr = SD_OK; - - /* Initialize SD Read operation */ - if(NumberOfBlocks > 1) - { - hsd->SdOperation = SD_READ_MULTIPLE_BLOCK; - } - else - { - hsd->SdOperation = SD_READ_SINGLE_BLOCK; - } - - /* Enable transfer interrupts */ - __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\ - SDIO_IT_DTIMEOUT |\ - SDIO_IT_DATAEND |\ - SDIO_IT_RXOVERR |\ - SDIO_IT_STBITERR)); - - /* Enable SDIO DMA transfer */ - __HAL_SD_SDIO_DMA_ENABLE(hsd); + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; - /* Configure DMA user callbacks */ - hsd->hdmarx->XferCpltCallback = SD_DMA_RxCplt; - hsd->hdmarx->XferErrorCallback = SD_DMA_RxError; - - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks)/4); - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - ReadAddr /= 512; - } - - /* Set Block Size for Card */ - sdio_cmdinitstructure.Argument = (uint32_t)BlockSize; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks; - sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - /* Check number of blocks command */ - if(NumberOfBlocks > 1) - { - /* Send CMD18 READ_MULT_BLOCK with argument data address */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK; - } - else + if(NULL == pData) { - /* Send CMD17 READ_SINGLE_BLOCK */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK; + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; } - sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - if(NumberOfBlocks > 1) + if(hsd->State == HAL_SD_STATE_READY) { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK); + hsd->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + hsd->pRxBuffPtr = (uint32_t *)pData; + hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; + + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_FLAG_RXFIFOHF | SDIO_IT_STBITERR)); + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hsd->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Read Blocks in IT mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; } else { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); + return HAL_BUSY; } - - /* Update the SD transfer error in SD handle */ - hsd->SdTransferErr = errorstate; - - return errorstate; } - /** * @brief Writes block(s) to a specified address in a card. The Data transfer - * is managed by DMA mode. - * @note This API should be followed by the function HAL_SD_CheckWriteOperation() - * to check the completion of the write process (by SD current status polling). - * @param hsd: SD handle - * @param pWriteBuffer: pointer to the buffer that will contain the data to transmit - * @param WriteAddr: Address from where data is to be read - * @param BlockSize: the SD card Data block size - * @note BlockSize must be 512 bytes. + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the IT transfer process through the SD Tx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written * @param NumberOfBlocks: Number of blocks to write - * @retval SD Card error state + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - SDIO_DataInitTypeDef sdio_datainitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0; + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; - /* Initialize handle flags */ - hsd->SdTransferCplt = 0; - hsd->DmaTransferCplt = 0; - hsd->SdTransferErr = SD_OK; - - /* Initialize SD Write operation */ - if(NumberOfBlocks > 1) - { - hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK; - } - else - { - hsd->SdOperation = SD_WRITE_SINGLE_BLOCK; - } - - /* Enable transfer interrupts */ - __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\ - SDIO_IT_DTIMEOUT |\ - SDIO_IT_DATAEND |\ - SDIO_IT_TXUNDERR |\ - SDIO_IT_STBITERR)); - - /* Configure DMA user callbacks */ - hsd->hdmatx->XferCpltCallback = SD_DMA_TxCplt; - hsd->hdmatx->XferErrorCallback = SD_DMA_TxError; - - /* Enable the DMA Channel */ - HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks)/4); - - /* Enable SDIO DMA transfer */ - __HAL_SD_SDIO_DMA_ENABLE(hsd); - - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - BlockSize = 512; - WriteAddr /= 512; - } - - /* Set Block Size for Card */ - sdio_cmdinitstructure.Argument = (uint32_t)BlockSize; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) + if(NULL == pData) { - return errorstate; - } - - /* Check number of blocks command */ - if(NumberOfBlocks <= 1) - { - /* Send CMD24 WRITE_SINGLE_BLOCK */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK; - } - else - { - /* Send CMD25 WRITE_MULT_BLOCK with argument data address */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK; + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; } - sdio_cmdinitstructure.Argument = (uint32_t)WriteAddr; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - if(NumberOfBlocks > 1) + if(hsd->State == HAL_SD_STATE_READY) { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK); + hsd->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + hsd->pTxBuffPtr = (uint32_t *)pData; + hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; + + /* Enable transfer interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_DATAEND | SDIO_FLAG_TXFIFOHE | SDIO_IT_STBITERR)); + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + } + else + { + hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hsd->Instance, &config); + + return HAL_OK; } else { - errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK); - } - - if (errorstate != SD_OK) - { - return errorstate; + return HAL_BUSY; } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = BlockSize * NumberOfBlocks; - sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - hsd->SdTransferErr = errorstate; - - return errorstate; } /** - * @brief This function waits until the SD DMA data read transfer is finished. - * This API should be called after HAL_SD_ReadBlocks_DMA() function - * to insure that all data sent by the card is already transferred by the - * DMA controller. - * @param hsd: SD handle - * @param Timeout: Timeout duration - * @retval SD Card error state + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the DMA transfer process through the SD Rx + * interrupt event. + * @param hsd: Pointer SD handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout) +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t timeout = Timeout; - uint32_t tmp1, tmp2; - HAL_SD_ErrorTypedef tmp3; - - /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */ - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - - while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0)) - { - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - timeout--; - } - - timeout = Timeout; - - /* Wait until the Rx transfer is no longer active */ - while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXACT)) && (timeout > 0)) - { - timeout--; - } + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; - /* Send stop command in multiblock read */ - if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK) + if(NULL == pData) { - errorstate = HAL_SD_StopTransfer(hsd); + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; } - if ((timeout == 0) && (errorstate == SD_OK)) + if(hsd->State == HAL_SD_STATE_READY) { - errorstate = SD_DATA_TIMEOUT; + hsd->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_DATAEND | SDIO_IT_STBITERR)); + + /* Set the DMA transfer complete callback */ + hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt; + + /* Set the DMA error callback */ + hsd->hdmarx->XferErrorCallback = SD_DMAError; + + /* Set the DMA Abort callback */ + hsd->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); + + /* Enable SD DMA transfer */ + __HAL_SD_DMA_ENABLE(hsd); + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hsd->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, BlockAdd); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, BlockAdd); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - /* Return error state */ - if (hsd->SdTransferErr != SD_OK) + else { - return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr); + return HAL_BUSY; } - - return errorstate; } /** - * @brief This function waits until the SD DMA data write transfer is finished. - * This API should be called after HAL_SD_WriteBlocks_DMA() function - * to insure that all data sent by the card is already transferred by the - * DMA controller. - * @param hsd: SD handle - * @param Timeout: Timeout duration - * @retval SD Card error state + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the DMA transfer process through the SD Tx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout) +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t timeout = Timeout; - uint32_t tmp1, tmp2; - HAL_SD_ErrorTypedef tmp3; - - /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */ - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - - while (((tmp1 & tmp2) == 0) && (tmp3 == SD_OK) && (timeout > 0)) - { - tmp1 = hsd->DmaTransferCplt; - tmp2 = hsd->SdTransferCplt; - tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr; - timeout--; - } + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; - timeout = Timeout; - - /* Wait until the Tx transfer is no longer active */ - while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXACT)) && (timeout > 0)) - { - timeout--; - } - - /* Send stop command in multiblock write */ - if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK) + if(NULL == pData) { - errorstate = HAL_SD_StopTransfer(hsd); + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; } - if ((timeout == 0) && (errorstate == SD_OK)) + if(hsd->State == HAL_SD_STATE_READY) { - errorstate = SD_DATA_TIMEOUT; + hsd->ErrorCode = HAL_DMA_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + /* Enable SD Error interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR)); + + /* Set the DMA transfer complete callback */ + hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt; + + /* Set the DMA error callback */ + hsd->hdmatx->XferErrorCallback = SD_DMAError; + + /* Set the DMA Abort callback */ + hsd->hdmatx->XferAbortCallback = NULL; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockAdd *= 512U; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, BlockAdd); + } + else + { + hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, BlockAdd); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Enable SDIO DMA transfer */ + __HAL_SD_DMA_ENABLE(hsd); + + /* Enable the DMA Channel */ + HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4); + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hsd->Instance, &config); + + return HAL_OK; } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - /* Return error state */ - if (hsd->SdTransferErr != SD_OK) + else { - return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr); - } - - /* Wait until write is complete */ - while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK) - { + return HAL_BUSY; } - - return errorstate; } /** * @brief Erases the specified memory area of the given SD card. - * @param hsd: SD handle - * @param Startaddr: Start byte address - * @param Endaddr: End byte address - * @retval SD Card error state + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t Startaddr, uint64_t Endaddr) +HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - - uint32_t delay = 0; - __IO uint32_t maxdelay = 0; - uint8_t cardstate = 0; + uint32_t errorstate = HAL_SD_ERROR_NONE; - /* Check if the card command class supports erase command */ - if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0) + if(hsd->State == HAL_SD_STATE_READY) { - errorstate = SD_REQUEST_NOT_APPLICABLE; + hsd->ErrorCode = HAL_DMA_ERROR_NONE; - return errorstate; - } - - /* Get max delay value */ - maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2); - - if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) - { - errorstate = SD_LOCK_UNLOCK_FAILED; + if(BlockEndAdd < BlockStartAdd) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } - return errorstate; - } - - /* Get start and end block for high capacity cards */ - if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - Startaddr /= 512; - Endaddr /= 512; - } - - /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ - sdio_cmdinitstructure.Argument =(uint32_t)Startaddr; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_START; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + if(BlockEndAdd > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START); + hsd->State = HAL_SD_STATE_BUSY; - if (errorstate != SD_OK) + /* Check if the card command class supports erase command */ + if(((hsd->SdCard.Class) & SDIO_CCCC_ERASE) == 0U) { - return errorstate; + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } - /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ - sdio_cmdinitstructure.Argument = (uint32_t)Endaddr; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_ERASE_GRP_END; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END); + /* Get start and end block for high capacity cards */ + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + BlockStartAdd *= 512U; + BlockEndAdd *= 512U; + } - if (errorstate != SD_OK) + /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ + if(hsd->SdCard.CardType != CARD_SECURED) { - return errorstate; + /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ + errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, BlockStartAdd); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ + errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, BlockEndAdd); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } } + + /* Send CMD38 ERASE */ + errorstate = SDMMC_CmdErase(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; } - - /* Send CMD38 ERASE */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_ERASE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE); - - if (errorstate != SD_OK) - { - return errorstate; - } - - for (; delay < maxdelay; delay++) - { - } - - /* Wait untill the card is in programming state */ - errorstate = SD_IsCardProgramming(hsd, &cardstate); - - delay = SD_DATATIMEOUT; - - while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING))) + else { - errorstate = SD_IsCardProgramming(hsd, &cardstate); - delay--; + return HAL_BUSY; } - - return errorstate; } /** * @brief This function handles SD card interrupt request. - * @param hsd: SD handle + * @param hsd: Pointer to SD handle * @retval None */ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) -{ +{ + uint32_t errorstate = HAL_SD_ERROR_NONE; + /* Check for SDIO interrupt flags */ - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DATAEND)) + if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DATAEND) != RESET) { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_IT_DATAEND); - - /* SD transfer is complete */ - hsd->SdTransferCplt = 1; - - /* No transfer error */ - hsd->SdTransferErr = SD_OK; - - HAL_SD_XferCpltCallback(hsd); - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DCRCFAIL)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - - hsd->SdTransferErr = SD_DATA_CRC_FAIL; - - HAL_SD_XferErrorCallback(hsd); - - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DTIMEOUT)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DATAEND); - hsd->SdTransferErr = SD_DATA_TIMEOUT; + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR | SDIO_IT_STBITERR); - HAL_SD_XferErrorCallback(hsd); + if((hsd->Context & SD_CONTEXT_IT) != RESET) + { + if(((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET)) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; + HAL_SD_ErrorCallback(hsd); + } + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) != RESET) || ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != RESET)) + { + HAL_SD_RxCpltCallback(hsd); + } + else + { + HAL_SD_TxCpltCallback(hsd); + } + } + else if((hsd->Context & SD_CONTEXT_DMA) != RESET) + { + if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != RESET) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; + HAL_SD_ErrorCallback(hsd); + } + } + if(((hsd->Context & SD_CONTEXT_READ_SINGLE_BLOCK) == RESET) && ((hsd->Context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == RESET)) + { + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the SD DCTRL register */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); + + hsd->State = HAL_SD_STATE_READY; + + HAL_SD_TxCpltCallback(hsd); + } + } } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_RXOVERR)) + + else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXFIFOHE) != RESET) { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - - hsd->SdTransferErr = SD_RX_OVERRUN; + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_TXFIFOHE); - HAL_SD_XferErrorCallback(hsd); + SD_Write_IT(hsd); } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_TXUNDERR)) + + else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXFIFOHF) != RESET) { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR); - - hsd->SdTransferErr = SD_TX_UNDERRUN; + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXFIFOHF); - HAL_SD_XferErrorCallback(hsd); + SD_Read_IT(hsd); } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR)) + + else if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_RXOVERR | SDIO_IT_TXUNDERR | SDIO_IT_STBITERR) != RESET) { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); + /* Set Error code */ + if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DCRCFAIL) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + } + if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_DTIMEOUT) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + } + if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_RXOVERR) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + } + if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_TXUNDERR) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + } + if(__HAL_SD_GET_FLAG(hsd, SDIO_IT_STBITERR) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + } + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS | SDIO_FLAG_STBITERR); - hsd->SdTransferErr = SD_START_BIT_ERR; + /* Disable all interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR |SDIO_IT_STBITERR); - HAL_SD_XferErrorCallback(hsd); - } - else - { - /* No error flag set */ + if((hsd->Context & SD_CONTEXT_DMA) != RESET) + { + /* Abort the SD DMA Streams */ + if(hsd->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + { + SD_DMATxAbort(hsd->hdmatx); + } + } + else if(hsd->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + { + SD_DMARxAbort(hsd->hdmarx); + } + } + else + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_READY; + HAL_SD_AbortCallback(hsd); + } + } + else if((hsd->Context & SD_CONTEXT_IT) != RESET) + { + /* Set the SD state to ready to be able to start again the process */ + hsd->State = HAL_SD_STATE_READY; + HAL_SD_ErrorCallback(hsd); + } } - - /* Disable all SDIO peripheral interrupt sources */ - __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND |\ - SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\ - SDIO_IT_RXOVERR | SDIO_IT_STBITERR); } - /** - * @brief SD end of transfer callback. - * @param hsd: SD handle - * @retval None + * @brief return the SD state + * @param hsd: Pointer to sd handle + * @retval HAL state */ -__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd) +HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_XferCpltCallback could be implemented in the user file - */ + return hsd->State; } /** - * @brief SD Transfer Error callback. - * @param hsd: SD handle - * @retval None - */ -__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd) +* @brief Return the SD error code +* @param hsd : Pointer to a SD_HandleTypeDef structure that contains + * the configuration information. +* @retval SD Error Code +*/ +uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_XferErrorCallback could be implemented in the user file - */ + return hsd->ErrorCode; } /** - * @brief SD Transfer complete Rx callback in non blocking mode. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief Tx Transfer completed callbacks + * @param hsd: Pointer to SD handle * @retval None */ -__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma) + __weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_RxCpltCallback could be implemented in the user file - */ -} + UNUSED(hsd); -/** - * @brief SD DMA transfer complete Rx error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_RxErrorCallback could be implemented in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_TxCpltCallback can be implemented in the user file + */ } /** - * @brief SD Transfer complete Tx callback in non blocking mode. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief Rx Transfer completed callbacks + * @param hsd: Pointer SD handle * @retval None */ -__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma) +__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_TxCpltCallback could be implemented in the user file - */ -} + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_RxCpltCallback can be implemented in the user file + */ +} /** - * @brief SD DMA transfer complete error Tx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief SD error callbacks + * @param hsd: Pointer SD handle * @retval None */ -__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma) +__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) { /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SD_DMA_TxErrorCallback could be implemented in the user file + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_ErrorCallback can be implemented in the user file */ } /** - * @} - */ - -/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the SD card - operations. - -@endverbatim - * @{ - */ - -/** - * @brief Returns information about specific card. - * @param hsd: SD handle - * @param pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that - * contains all SD cardinformation - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t tmp = 0; - - pCardInfo->CardType = (uint8_t)(hsd->CardType); - pCardInfo->RCA = (uint16_t)(hsd->RCA); - - /* Byte 0 */ - tmp = (hsd->CSD[0] & 0xFF000000) >> 24; - pCardInfo->SD_csd.CSDStruct = (uint8_t)((tmp & 0xC0) >> 6); - pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2); - pCardInfo->SD_csd.Reserved1 = tmp & 0x03; - - /* Byte 1 */ - tmp = (hsd->CSD[0] & 0x00FF0000) >> 16; - pCardInfo->SD_csd.TAAC = (uint8_t)tmp; - - /* Byte 2 */ - tmp = (hsd->CSD[0] & 0x0000FF00) >> 8; - pCardInfo->SD_csd.NSAC = (uint8_t)tmp; - - /* Byte 3 */ - tmp = hsd->CSD[0] & 0x000000FF; - pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp; - - /* Byte 4 */ - tmp = (hsd->CSD[1] & 0xFF000000) >> 24; - pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4); - - /* Byte 5 */ - tmp = (hsd->CSD[1] & 0x00FF0000) >> 16; - pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4); - pCardInfo->SD_csd.RdBlockLen = (uint8_t)(tmp & 0x0F); - - /* Byte 6 */ - tmp = (hsd->CSD[1] & 0x0000FF00) >> 8; - pCardInfo->SD_csd.PartBlockRead = (uint8_t)((tmp & 0x80) >> 7); - pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6); - pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5); - pCardInfo->SD_csd.DSRImpl = (uint8_t)((tmp & 0x10) >> 4); - pCardInfo->SD_csd.Reserved2 = 0; /*!< Reserved */ - - if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0)) - { - pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10; - - /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF); - pCardInfo->SD_csd.DeviceSize |= (tmp) << 2; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24); - pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6; - - pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3; - pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07); - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16); - pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5; - pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2; - pCardInfo->SD_csd.DeviceSizeMul = (tmp & 0x03) << 1; - /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8); - pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7; - - pCardInfo->CardCapacity = (pCardInfo->SD_csd.DeviceSize + 1) ; - pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2)); - pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen); - pCardInfo->CardCapacity *= pCardInfo->CardBlockSize; - } - else if (hsd->CardType == HIGH_CAPACITY_SD_CARD) - { - /* Byte 7 */ - tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF); - pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24); - - pCardInfo->SD_csd.DeviceSize |= (tmp << 8); - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16); - - pCardInfo->SD_csd.DeviceSize |= (tmp); - - /* Byte 10 */ - tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8); - - pCardInfo->CardCapacity = (uint64_t)(((uint64_t)pCardInfo->SD_csd.DeviceSize + 1) * 512 * 1024); - pCardInfo->CardBlockSize = 512; - } - else - { - /* Not supported card type */ - errorstate = SD_ERROR; - } - - pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6; - pCardInfo->SD_csd.EraseGrMul = (tmp & 0x3F) << 1; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF); - pCardInfo->SD_csd.EraseGrMul |= (tmp & 0x80) >> 7; - pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F); - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24); - pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7; - pCardInfo->SD_csd.ManDeflECC = (tmp & 0x60) >> 5; - pCardInfo->SD_csd.WrSpeedFact = (tmp & 0x1C) >> 2; - pCardInfo->SD_csd.MaxWrBlockLen = (tmp & 0x03) << 2; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16); - pCardInfo->SD_csd.MaxWrBlockLen |= (tmp & 0xC0) >> 6; - pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5; - pCardInfo->SD_csd.Reserved3 = 0; - pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01); - - /* Byte 14 */ - tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8); - pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7; - pCardInfo->SD_csd.CopyFlag = (tmp & 0x40) >> 6; - pCardInfo->SD_csd.PermWrProtect = (tmp & 0x20) >> 5; - pCardInfo->SD_csd.TempWrProtect = (tmp & 0x10) >> 4; - pCardInfo->SD_csd.FileFormat = (tmp & 0x0C) >> 2; - pCardInfo->SD_csd.ECC = (tmp & 0x03); - - /* Byte 15 */ - tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF); - pCardInfo->SD_csd.CSD_CRC = (tmp & 0xFE) >> 1; - pCardInfo->SD_csd.Reserved4 = 1; - - /* Byte 0 */ - tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24); - pCardInfo->SD_cid.ManufacturerID = tmp; - - /* Byte 1 */ - tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.OEM_AppliID = tmp << 8; - - /* Byte 2 */ - tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8); - pCardInfo->SD_cid.OEM_AppliID |= tmp; - - /* Byte 3 */ - tmp = (uint8_t)(hsd->CID[0] & 0x000000FF); - pCardInfo->SD_cid.ProdName1 = tmp << 24; - - /* Byte 4 */ - tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24); - pCardInfo->SD_cid.ProdName1 |= tmp << 16; - - /* Byte 5 */ - tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.ProdName1 |= tmp << 8; - - /* Byte 6 */ - tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8); - pCardInfo->SD_cid.ProdName1 |= tmp; - - /* Byte 7 */ - tmp = (uint8_t)(hsd->CID[1] & 0x000000FF); - pCardInfo->SD_cid.ProdName2 = tmp; - - /* Byte 8 */ - tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24); - pCardInfo->SD_cid.ProdRev = tmp; - - /* Byte 9 */ - tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.ProdSN = tmp << 24; - - /* Byte 10 */ - tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8); - pCardInfo->SD_cid.ProdSN |= tmp << 16; - - /* Byte 11 */ - tmp = (uint8_t)(hsd->CID[2] & 0x000000FF); - pCardInfo->SD_cid.ProdSN |= tmp << 8; - - /* Byte 12 */ - tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24); - pCardInfo->SD_cid.ProdSN |= tmp; - - /* Byte 13 */ - tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16); - pCardInfo->SD_cid.Reserved1 |= (tmp & 0xF0) >> 4; - pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8; - - /* Byte 14 */ - tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8); - pCardInfo->SD_cid.ManufactDate |= tmp; - - /* Byte 15 */ - tmp = (uint8_t)(hsd->CID[3] & 0x000000FF); - pCardInfo->SD_cid.CID_CRC = (tmp & 0xFE) >> 1; - pCardInfo->SD_cid.Reserved2 = 1; - - return errorstate; -} - -/** - * @brief Enables wide bus operation for the requested card if supported by - * card. - * @param hsd: SD handle - * @param WideMode: Specifies the SD card wide bus mode - * This parameter can be one of the following values: - * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer (Only for MMC) - * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer - * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - SDIO_InitTypeDef init = {0}; - - /* MMC Card does not support this feature */ - if (hsd->CardType == MULTIMEDIA_CARD) - { - errorstate = SD_UNSUPPORTED_FEATURE; - } - else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == HIGH_CAPACITY_SD_CARD)) - { - if (WideMode == SDIO_BUS_WIDE_8B) - { - errorstate = SD_UNSUPPORTED_FEATURE; - } - else if (WideMode == SDIO_BUS_WIDE_4B) - { - errorstate = SD_WideBus_Enable(hsd); - } - else if (WideMode == SDIO_BUS_WIDE_1B) - { - errorstate = SD_WideBus_Disable(hsd); - } - else - { - /* WideMode is not a valid argument*/ - errorstate = SD_INVALID_PARAMETER; - } - - if (errorstate == SD_OK) - { - /* Configure the SDIO peripheral */ - init.ClockEdge = hsd->Init.ClockEdge; - init.ClockBypass = hsd->Init.ClockBypass; - init.ClockPowerSave = hsd->Init.ClockPowerSave; - init.BusWide = WideMode; - init.HardwareFlowControl = hsd->Init.HardwareFlowControl; - init.ClockDiv = hsd->Init.ClockDiv; - - /* Configure SDIO peripheral interface */ - SDIO_Init(hsd->Instance, init); - } - else - { - /* An error occured while enabling/disabling the wide bus*/ - } - } - else - { - /* Not supported card type */ - errorstate = SD_ERROR; - } - - return errorstate; -} - -/** - * @brief Aborts an ongoing data transfer. - * @param hsd: SD handle - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Send CMD12 STOP_TRANSMISSION */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_STOP_TRANSMISSION; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION); - - return errorstate; -} - -/** - * @brief Switches the SD card to High Speed mode. - * This API must be used after "Transfer State" - * @note This operation should be followed by the configuration - * of PLL to have SDIOCK clock between 67 and 75 MHz - * @param hsd: SD handle - * @retval SD Card error state - */ -HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - SDIO_DataInitTypeDef sdio_datainitstructure = {0}; - - uint8_t SD_hs[64] = {0}; - uint32_t SD_scr[2] = {0, 0}; - uint32_t SD_SPEC = 0 ; - uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs; - - /* Initialize the Data control register */ - hsd->Instance->DCTRL = 0; - - /* Get SCR Register */ - errorstate = SD_FindSCR(hsd, SD_scr); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Test the Version supported by the card*/ - SD_SPEC = (SD_scr[1] & 0x01000000) | (SD_scr[1] & 0x02000000); - - if (SD_SPEC != SD_ALLZERO) - { - /* Set Block Size for Card */ - sdio_cmdinitstructure.Argument = (uint32_t)64; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = 64; - sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - /* Send CMD6 switch mode */ - sdio_cmdinitstructure.Argument = 0x80FFFF01; - sdio_cmdinitstructure.CmdIndex = SD_CMD_HS_SWITCH; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH); - - if (errorstate != SD_OK) - { - return errorstate; - } - - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) - { - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) - { - for (count = 0; count < 8; count++) - { - *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance); - } - - tempbuff += 8; - } - } - - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - - errorstate = SD_START_BIT_ERR; - - return errorstate; - } - else - { - /* No error flag set */ - } - - count = SD_DATATIMEOUT; - - while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0)) - { - *tempbuff = SDIO_ReadFIFO(hsd->Instance); - tempbuff++; - count--; - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - /* Test if the switch mode HS is ok */ - if ((SD_hs[13]& 2) != 2) - { - errorstate = SD_UNSUPPORTED_FEATURE; - } - } - - return errorstate; -} - -/** - * @} - */ - -/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in runtime the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the current SD card's status. - * @param hsd: SD handle - * @param pSDstatus: Pointer to the buffer that will contain the SD card status - * SD Status register) - * @retval SD Card error state + * @brief SD Abort callbacks + * @param hsd: Pointer SD handle + * @retval None */ -HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) +__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) { - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - SDIO_DataInitTypeDef sdio_datainitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t count = 0; - - /* Check SD response */ - if ((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) - { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; - } - - /* Set block size for card if it is not equal to current block size for card */ - sdio_cmdinitstructure.Argument = 64; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Send CMD55 */ - sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = 64; - sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); - - /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_STATUS; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STATUS); - - if (errorstate != SD_OK) - { - return errorstate; - } - - /* Get status data */ - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) - { - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) - { - for (count = 0; count < 8; count++) - { - *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance); - } - - pSDstatus += 8; - } - } - - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - - errorstate = SD_DATA_TIMEOUT; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; - - return errorstate; - } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - - errorstate = SD_START_BIT_ERR; - - return errorstate; - } - else - { - /* No error flag set */ - } - - count = SD_DATATIMEOUT; - while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0)) - { - *pSDstatus = SDIO_ReadFIFO(hsd->Instance); - pSDstatus++; - count--; - } - - /* Clear all the static status flags*/ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - return errorstate; + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_ErrorCallback can be implemented in the user file + */ } + /** - * @brief Gets the current sd card data status. - * @param hsd: SD handle - * @retval Data Transfer state + * @} */ -HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd) -{ - HAL_SD_CardStateTypedef cardstate = SD_CARD_TRANSFER; - /* Get SD card state */ - cardstate = SD_GetState(hsd); - - /* Find SD status according to card state*/ - if (cardstate == SD_CARD_TRANSFER) - { - return SD_TRANSFER_OK; - } - else if(cardstate == SD_CARD_ERROR) - { - return SD_TRANSFER_ERROR; - } - else - { - return SD_TRANSFER_BUSY; - } -} +/** @addtogroup SD_Exported_Functions_Group3 + * @brief management functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the SD card + operations and get the related information + +@endverbatim + * @{ + */ /** - * @brief Gets the SD card status. - * @param hsd: SD handle - * @param pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that - * will contain the SD card status information - * @retval SD Card error state + * @brief Returns information the information of the card which are stored on + * the CID register. + * @param hsd: Pointer to SD handle + * @param pCID: Pointer to a HAL_SD_CIDTypeDef structure that + * contains all CID register parameters + * @retval HAL status */ -HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus) +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t tmp = 0; - uint32_t sd_status[16]; - - errorstate = HAL_SD_SendSDStatus(hsd, sd_status); - - if (errorstate != SD_OK) - { - return errorstate; - } + uint32_t tmp = 0U; /* Byte 0 */ - tmp = (sd_status[0] & 0xC0) >> 6; - pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp; + tmp = (uint8_t)((hsd->CID[0U] & 0xFF000000U) >> 24U); + pCID->ManufacturerID = tmp; - /* Byte 0 */ - tmp = (sd_status[0] & 0x20) >> 5; - pCardStatus->SECURED_MODE = (uint8_t)tmp; + /* Byte 1 */ + tmp = (uint8_t)((hsd->CID[0U] & 0x00FF0000U) >> 16U); + pCID->OEM_AppliID = tmp << 8U; /* Byte 2 */ - tmp = (sd_status[2] & 0xFF); - pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8); + tmp = (uint8_t)((hsd->CID[0U] & 0x000000FF00U) >> 8U); + pCID->OEM_AppliID |= tmp; /* Byte 3 */ - tmp = (sd_status[3] & 0xFF); - pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp; + tmp = (uint8_t)(hsd->CID[0U] & 0x000000FFU); + pCID->ProdName1 = tmp << 24U; /* Byte 4 */ - tmp = (sd_status[4] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24); + tmp = (uint8_t)((hsd->CID[1U] & 0xFF000000U) >> 24U); + pCID->ProdName1 |= tmp << 16; /* Byte 5 */ - tmp = (sd_status[5] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16); + tmp = (uint8_t)((hsd->CID[1U] & 0x00FF0000U) >> 16U); + pCID->ProdName1 |= tmp << 8U; /* Byte 6 */ - tmp = (sd_status[6] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8); + tmp = (uint8_t)((hsd->CID[1U] & 0x0000FF00U) >> 8U); + pCID->ProdName1 |= tmp; /* Byte 7 */ - tmp = (sd_status[7] & 0xFF); - pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp; + tmp = (uint8_t)(hsd->CID[1U] & 0x000000FFU); + pCID->ProdName2 = tmp; /* Byte 8 */ - tmp = (sd_status[8] & 0xFF); - pCardStatus->SPEED_CLASS = (uint8_t)tmp; + tmp = (uint8_t)((hsd->CID[2U] & 0xFF000000U) >> 24U); + pCID->ProdRev = tmp; /* Byte 9 */ - tmp = (sd_status[9] & 0xFF); - pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp; + tmp = (uint8_t)((hsd->CID[2U] & 0x00FF0000U) >> 16U); + pCID->ProdSN = tmp << 24U; /* Byte 10 */ - tmp = (sd_status[10] & 0xF0) >> 4; - pCardStatus->AU_SIZE = (uint8_t)tmp; + tmp = (uint8_t)((hsd->CID[2U] & 0x0000FF00U) >> 8U); + pCID->ProdSN |= tmp << 16U; /* Byte 11 */ - tmp = (sd_status[11] & 0xFF); - pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8); + tmp = (uint8_t)(hsd->CID[2U] & 0x000000FFU); + pCID->ProdSN |= tmp << 8U; /* Byte 12 */ - tmp = (sd_status[12] & 0xFF); - pCardStatus->ERASE_SIZE |= (uint8_t)tmp; - - /* Byte 13 */ - tmp = (sd_status[13] & 0xFC) >> 2; - pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp; + tmp = (uint8_t)((hsd->CID[3U] & 0xFF000000U) >> 24U); + pCID->ProdSN |= tmp; /* Byte 13 */ - tmp = (sd_status[13] & 0x3); - pCardStatus->ERASE_OFFSET = (uint8_t)tmp; - - return errorstate; -} - -/** - * @} - */ + tmp = (uint8_t)((hsd->CID[3U] & 0x00FF0000U) >> 16U); + pCID->Reserved1 |= (tmp & 0xF0U) >> 4U; + pCID->ManufactDate = (tmp & 0x0FU) << 8U; -/** - * @} - */ + /* Byte 14 */ + tmp = (uint8_t)((hsd->CID[3U] & 0x0000FF00U) >> 8U); + pCID->ManufactDate |= tmp; -/** @addtogroup SD_Private_Functions - * @{ - */ + /* Byte 15 */ + tmp = (uint8_t)(hsd->CID[3U] & 0x000000FFU); + pCID->CID_CRC = (tmp & 0xFEU) >> 1U; + pCID->Reserved2 = 1U; -/** - * @brief SD DMA transfer complete Rx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - - /* DMA transfer is complete */ - hsd->DmaTransferCplt = 1; - - /* Wait until SD transfer is complete */ - while(hsd->SdTransferCplt == 0) - { - } - - /* Transfer complete user callback */ - HAL_SD_DMA_RxCpltCallback(hsd->hdmarx); + return HAL_OK; } /** - * @brief SD DMA transfer Error Rx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None + * @brief Returns information the information of the card which are stored on + * the CSD register. + * @param hsd: Pointer to SD handle + * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that + * contains all CSD register parameters + * @retval HAL status */ -static void SD_DMA_RxError(DMA_HandleTypeDef *hdma) +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) { - SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + uint32_t tmp = 0U; - /* Transfer complete user callback */ - HAL_SD_DMA_RxErrorCallback(hsd->hdmarx); -} - -/** - * @brief SD DMA transfer complete Tx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + /* Byte 0 */ + tmp = (hsd->CSD[0U] & 0xFF000000U) >> 24U; + pCSD->CSDStruct = (uint8_t)((tmp & 0xC0U) >> 6U); + pCSD->SysSpecVersion = (uint8_t)((tmp & 0x3CU) >> 2U); + pCSD->Reserved1 = tmp & 0x03U; - /* DMA transfer is complete */ - hsd->DmaTransferCplt = 1; + /* Byte 1 */ + tmp = (hsd->CSD[0U] & 0x00FF0000U) >> 16U; + pCSD->TAAC = (uint8_t)tmp; - /* Wait until SD transfer is complete */ - while(hsd->SdTransferCplt == 0) - { - } + /* Byte 2 */ + tmp = (hsd->CSD[0U] & 0x0000FF00U) >> 8U; + pCSD->NSAC = (uint8_t)tmp; - /* Transfer complete user callback */ - HAL_SD_DMA_TxCpltCallback(hsd->hdmatx); -} - -/** - * @brief SD DMA transfer Error Tx callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SD_DMA_TxError(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Byte 3 */ + tmp = hsd->CSD[0U] & 0x000000FFU; + pCSD->MaxBusClkFrec = (uint8_t)tmp; - /* Transfer complete user callback */ - HAL_SD_DMA_TxErrorCallback(hsd->hdmatx); -} - -/** - * @brief Returns the SD current state. - * @param hsd: SD handle - * @retval SD card current state - */ -static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd) -{ - uint32_t resp1 = 0; + /* Byte 4 */ + tmp = (hsd->CSD[1U] & 0xFF000000U) >> 24U; + pCSD->CardComdClasses = (uint16_t)(tmp << 4U); - if (SD_SendStatus(hsd, &resp1) != SD_OK) - { - return SD_CARD_ERROR; - } - else - { - return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F); - } -} - -/** - * @brief Initializes all cards or single card as the case may be Card(s) come - * into standby state. - * @param hsd: SD handle - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint16_t sd_rca = 1; + /* Byte 5 */ + tmp = (hsd->CSD[1U] & 0x00FF0000U) >> 16U; + pCSD->CardComdClasses |= (uint16_t)((tmp & 0xF0U) >> 4U); + pCSD->RdBlockLen = (uint8_t)(tmp & 0x0FU); - if(SDIO_GetPowerState(hsd->Instance) == 0) /* Power off */ + /* Byte 6 */ + tmp = (hsd->CSD[1U] & 0x0000FF00U) >> 8U; + pCSD->PartBlockRead = (uint8_t)((tmp & 0x80U) >> 7U); + pCSD->WrBlockMisalign = (uint8_t)((tmp & 0x40U) >> 6U); + pCSD->RdBlockMisalign = (uint8_t)((tmp & 0x20U) >> 5U); + pCSD->DSRImpl = (uint8_t)((tmp & 0x10U) >> 4U); + pCSD->Reserved2 = 0U; /*!< Reserved */ + + if(hsd->SdCard.CardType == CARD_SDSC) { - errorstate = SD_REQUEST_NOT_APPLICABLE; + pCSD->DeviceSize = (tmp & 0x03U) << 10U; - return errorstate; - } - - if(hsd->CardType != SECURE_DIGITAL_IO_CARD) - { - /* Send CMD2 ALL_SEND_CID */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_ALL_SEND_CID; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + /* Byte 7 */ + tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU); + pCSD->DeviceSize |= (tmp) << 2U; - /* Check for error conditions */ - errorstate = SD_CmdResp2Error(hsd); + /* Byte 8 */ + tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U); + pCSD->DeviceSize |= (tmp & 0xC0U) >> 6U; - if(errorstate != SD_OK) - { - return errorstate; - } + pCSD->MaxRdCurrentVDDMin = (tmp & 0x38U) >> 3U; + pCSD->MaxRdCurrentVDDMax = (tmp & 0x07U); + + /* Byte 9 */ + tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U); + pCSD->MaxWrCurrentVDDMin = (tmp & 0xE0U) >> 5U; + pCSD->MaxWrCurrentVDDMax = (tmp & 0x1CU) >> 2U; + pCSD->DeviceSizeMul = (tmp & 0x03U) << 1U; + /* Byte 10 */ + tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U); + pCSD->DeviceSizeMul |= (tmp & 0x80U) >> 7U; - /* Get Card identification number data */ - hsd->CID[0] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); - hsd->CID[1] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2); - hsd->CID[2] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3); - hsd->CID[3] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4); + hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hsd->SdCard.BlockNbr *= (1U << (pCSD->DeviceSizeMul + 2U)); + hsd->SdCard.BlockSize = 1U << (pCSD->RdBlockLen); + + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); + hsd->SdCard.LogBlockSize = 512U; } - - if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\ - (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD)) + else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) { - /* Send CMD3 SET_REL_ADDR with argument 0 */ - /* SD Card publishes its RCA. */ - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_REL_ADDR; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + /* Byte 7 */ + tmp = (uint8_t)(hsd->CSD[1U] & 0x000000FFU); + pCSD->DeviceSize = (tmp & 0x3FU) << 16U; - /* Check for error conditions */ - errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca); + /* Byte 8 */ + tmp = (uint8_t)((hsd->CSD[2U] & 0xFF000000U) >> 24U); - if(errorstate != SD_OK) - { - return errorstate; - } - } - - if (hsd->CardType != SECURE_DIGITAL_IO_CARD) - { - /* Get the SD card RCA */ - hsd->RCA = sd_rca; + pCSD->DeviceSize |= (tmp << 8U); - /* Send CMD9 SEND_CSD with argument as card's RCA */ - sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_CSD; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_LONG; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + /* Byte 9 */ + tmp = (uint8_t)((hsd->CSD[2U] & 0x00FF0000U) >> 16U); - /* Check for error conditions */ - errorstate = SD_CmdResp2Error(hsd); + pCSD->DeviceSize |= (tmp); - if(errorstate != SD_OK) - { - return errorstate; - } + /* Byte 10 */ + tmp = (uint8_t)((hsd->CSD[2U] & 0x0000FF00U) >> 8U); - /* Get Card Specific Data */ - hsd->CSD[0] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); - hsd->CSD[1] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2); - hsd->CSD[2] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3); - hsd->CSD[3] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4); + hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr = (((uint64_t)pCSD->DeviceSize + 1U) * 1024U); + hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize = 512U; + } + else + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } - /* All cards are initialized */ - return errorstate; -} - -/** - * @brief Selects od Deselects the corresponding card. - * @param hsd: SD handle - * @param Addr: Address of the card to be selected - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t Addr) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; + pCSD->EraseGrSize = (tmp & 0x40U) >> 6U; + pCSD->EraseGrMul = (tmp & 0x3FU) << 1U; + + /* Byte 11 */ + tmp = (uint8_t)(hsd->CSD[2U] & 0x000000FFU); + pCSD->EraseGrMul |= (tmp & 0x80U) >> 7U; + pCSD->WrProtectGrSize = (tmp & 0x7FU); + + /* Byte 12 */ + tmp = (uint8_t)((hsd->CSD[3U] & 0xFF000000U) >> 24U); + pCSD->WrProtectGrEnable = (tmp & 0x80U) >> 7U; + pCSD->ManDeflECC = (tmp & 0x60U) >> 5U; + pCSD->WrSpeedFact = (tmp & 0x1CU) >> 2U; + pCSD->MaxWrBlockLen = (tmp & 0x03U) << 2U; + + /* Byte 13 */ + tmp = (uint8_t)((hsd->CSD[3U] & 0x00FF0000U) >> 16U); + pCSD->MaxWrBlockLen |= (tmp & 0xC0U) >> 6U; + pCSD->WriteBlockPaPartial = (tmp & 0x20U) >> 5U; + pCSD->Reserved3 = 0U; + pCSD->ContentProtectAppli = (tmp & 0x01U); - /* Send CMD7 SDIO_SEL_DESEL_CARD */ - sdio_cmdinitstructure.Argument = (uint32_t)Addr; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SEL_DESEL_CARD; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + /* Byte 14 */ + tmp = (uint8_t)((hsd->CSD[3U] & 0x0000FF00U) >> 8U); + pCSD->FileFormatGrouop = (tmp & 0x80U) >> 7U; + pCSD->CopyFlag = (tmp & 0x40U) >> 6U; + pCSD->PermWrProtect = (tmp & 0x20U) >> 5U; + pCSD->TempWrProtect = (tmp & 0x10U) >> 4U; + pCSD->FileFormat = (tmp & 0x0CU) >> 2U; + pCSD->ECC = (tmp & 0x03U); - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD); + /* Byte 15 */ + tmp = (uint8_t)(hsd->CSD[3U] & 0x000000FFU); + pCSD->CSD_CRC = (tmp & 0xFEU) >> 1U; + pCSD->Reserved4 = 1U; - return errorstate; + return HAL_OK; } /** - * @brief Enquires cards about their operating voltage and configures clock - * controls and stores SD information that will be needed in future - * in the SD handle. - * @param hsd: SD handle - * @retval SD Card error state + * @brief Gets the SD status info. + * @param hsd: Pointer to SD handle + * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that + * will contain the SD card status information + * @retval HAL status */ -static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd) +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus) { - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - __IO HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t response = 0, count = 0, validvoltage = 0; - uint32_t sdtype = SD_STD_CAPACITY; - - /* Power ON Sequence -------------------------------------------------------*/ - /* Disable SDIO Clock */ - __HAL_SD_SDIO_DISABLE(hsd); - - /* Set Power State to ON */ - SDIO_PowerState_ON(hsd->Instance); - - /* 1ms: required power up waiting time before starting the SD initialization - sequence */ - HAL_Delay(1); - - /* Enable SDIO Clock */ - __HAL_SD_SDIO_ENABLE(hsd); - - /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/ - /* No CMD response required */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_GO_IDLE_STATE; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_NO; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdError(hsd); - - if(errorstate != SD_OK) - { - /* CMD Response TimeOut (wait for CMDSENT flag) */ - return errorstate; - } - - /* CMD8: SEND_IF_COND ------------------------------------------------------*/ - /* Send CMD8 to verify SD card interface operating condition */ - /* Argument: - [31:12]: Reserved (shall be set to '0') - - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - - [7:0]: Check Pattern (recommended 0xAA) */ - /* CMD Response: R7 */ - sdio_cmdinitstructure.Argument = SD_CHECK_PATTERN; - sdio_cmdinitstructure.CmdIndex = SD_SDIO_SEND_IF_COND; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + uint32_t tmp = 0U; + uint32_t sd_status[16U]; + uint32_t errorstate = HAL_SD_ERROR_NONE; - /* Check for error conditions */ - errorstate = SD_CmdResp7Error(hsd); - - if (errorstate == SD_OK) + errorstate = SD_SendSDStatus(hsd, sd_status); + if(errorstate != HAL_OK) { - /* SD Card 2.0 */ - hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; - sdtype = SD_HIGH_CAPACITY; + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; } - - /* Send CMD55 */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - /* If errorstate is Command TimeOut, it is a MMC card */ - /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch) - or SD card 1.x */ - if(errorstate == SD_OK) + else { - /* SD CARD */ - /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)) - { - - /* SEND CMD55 APP_CMD with RCA as 0 */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Send CMD41 */ - sdio_cmdinitstructure.Argument = SD_VOLTAGE_WINDOW_SD | sdtype; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_OP_COND; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp3Error(hsd); - - if(errorstate != SD_OK) - { - return errorstate; - } - - /* Get command response */ - response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); - - /* Get operating voltage*/ - validvoltage = (((response >> 31) == 1) ? 1 : 0); - - count++; - } + /* Byte 0 */ + tmp = (sd_status[0U] & 0xC0U) >> 6U; + pStatus->DataBusWidth = (uint8_t)tmp; - if(count >= SD_MAX_VOLT_TRIAL) - { - errorstate = SD_INVALID_VOLTRANGE; - - return errorstate; - } + /* Byte 0 */ + tmp = (sd_status[0U] & 0x20U) >> 5U; + pStatus->SecuredMode = (uint8_t)tmp; - if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ - { - hsd->CardType = HIGH_CAPACITY_SD_CARD; - } + /* Byte 2 */ + tmp = (sd_status[0U] & 0x00FF0000U) >> 16U; + pStatus->CardType = (uint16_t)(tmp << 8U); + + /* Byte 3 */ + tmp = (sd_status[0U] & 0xFF000000U) >> 24U; + pStatus->CardType |= (uint16_t)tmp; + + /* Byte 4 */ + tmp = (sd_status[1U] & 0xFFU); + pStatus->ProtectedAreaSize = (uint32_t)(tmp << 24U); + + /* Byte 5 */ + tmp = (sd_status[1U] & 0xFF00U) >> 8U; + pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 16U); + + /* Byte 6 */ + tmp = (sd_status[1U] & 0xFF0000U) >> 16U; + pStatus->ProtectedAreaSize |= (uint32_t)(tmp << 8U); + + /* Byte 7 */ + tmp = (sd_status[1U] & 0xFF000000U) >> 24U; + pStatus->ProtectedAreaSize |= (uint32_t)tmp; + + /* Byte 8 */ + tmp = (sd_status[2U] & 0xFFU); + pStatus->SpeedClass = (uint8_t)tmp; + + /* Byte 9 */ + tmp = (sd_status[2U] & 0xFF00U) >> 8U; + pStatus->PerformanceMove = (uint8_t)tmp; + + /* Byte 10 */ + tmp = (sd_status[2U] & 0xF00000U) >> 20U; + pStatus->AllocationUnitSize = (uint8_t)tmp; - } /* else MMC Card */ + /* Byte 11 */ + tmp = (sd_status[2U] & 0xFF000000U) >> 24U; + pStatus->EraseSize = (uint16_t)(tmp << 8U); + + /* Byte 12 */ + tmp = (sd_status[3U] & 0xFFU); + pStatus->EraseSize |= (uint16_t)tmp; + + /* Byte 13 */ + tmp = (sd_status[3U] & 0xFC00U) >> 10U; + pStatus->EraseTimeout = (uint8_t)tmp; + + /* Byte 13 */ + tmp = (sd_status[3U] & 0x0300U) >> 8U; + pStatus->EraseOffset = (uint8_t)tmp; + } - return errorstate; + return HAL_OK; } /** - * @brief Turns the SDIO output signals off. - * @param hsd: SD handle - * @retval SD Card error state + * @brief Gets the SD card info. + * @param hsd: Pointer to SD handle + * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that + * will contain the SD card status information + * @retval HAL status */ -static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd) +HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - - /* Set Power State to OFF */ - SDIO_PowerState_OFF(hsd->Instance); + pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); + pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); + pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); + pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); + pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); + pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); + pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); + pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); - return errorstate; + return HAL_OK; } /** - * @brief Returns the current card's status. - * @param hsd: SD handle - * @param pCardStatus: pointer to the buffer that will contain the SD card - * status (Card Status register) - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) -{ - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - if(pCardStatus == NULL) - { - errorstate = SD_INVALID_PARAMETER; - - return errorstate; - } + * @brief Enables wide bus operation for the requested card if supported by + * card. + * @param hsd: Pointer to SD handle + * @param WideMode: Specifies the SD card wide bus mode + * This parameter can be one of the following values: + * @arg SDIO_BUS_WIDE_8B: 8-bit data transfer + * @arg SDIO_BUS_WIDE_4B: 4-bit data transfer + * @arg SDIO_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) +{ + SDIO_InitTypeDef Init; + uint32_t errorstate = HAL_SD_ERROR_NONE; - /* Send Status command */ - sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); + /* Check the parameters */ + assert_param(IS_SDIO_BUS_WIDE(WideMode)); - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS); + /* Chnage Satte */ + hsd->State = HAL_SD_STATE_BUSY; - if(errorstate != SD_OK) + if(hsd->SdCard.CardType != CARD_SECURED) { - return errorstate; + if(WideMode == SDIO_BUS_WIDE_8B) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + else if(WideMode == SDIO_BUS_WIDE_4B) + { + errorstate = SD_WideBus_Enable(hsd); + + hsd->ErrorCode |= errorstate; + } + else if(WideMode == SDIO_BUS_WIDE_1B) + { + errorstate = SD_WideBus_Disable(hsd); + + hsd->ErrorCode |= errorstate; + } + else + { + /* WideMode is not a valid argument*/ + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + } + } + else + { + /* MMC Card does not support this feature */ + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; } - /* Get SD card status */ - *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + else + { + /* Configure the SDIO peripheral */ + Init.ClockEdge = hsd->Init.ClockEdge; + Init.ClockBypass = hsd->Init.ClockBypass; + Init.ClockPowerSave = hsd->Init.ClockPowerSave; + Init.BusWide = WideMode; + Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + Init.ClockDiv = hsd->Init.ClockDiv; + SDIO_Init(hsd->Instance, Init); + } + + /* Change State */ + hsd->State = HAL_SD_STATE_READY; - return errorstate; + return HAL_OK; } + /** - * @brief Checks for error conditions for CMD0. - * @param hsd: SD handle - * @retval SD Card error state + * @brief Gets the current sd card data state. + * @param hsd: pointer to SD handle + * @retval Card state */ -static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd) +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t timeout = SDIO_CMD0TIMEOUT, tmp; - - tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT); - - while((timeout > 0) && (!tmp)) - { - tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT); - timeout--; - } + HAL_SD_CardStateTypeDef cardstate = HAL_SD_CARD_TRANSFER; + uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t resp1 = 0; - if(timeout == 0) + errorstate = SD_SendStatus(hsd, &resp1); + if(errorstate != HAL_OK) { - errorstate = SD_CMD_RSP_TIMEOUT; - return errorstate; + hsd->ErrorCode |= errorstate; } + + cardstate = (HAL_SD_CardStateTypeDef)((resp1 >> 9U) & 0x0FU); - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - return errorstate; + return cardstate; } /** - * @brief Checks for error conditions for R7 response. - * @param hsd: SD handle - * @retval SD Card error state + * @brief Abort the current transfer and disable the SD. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information for SD module. + * @retval HAL status */ -static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd) +HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorstate = SD_ERROR; - uint32_t timeout = SDIO_CMD0TIMEOUT, tmp; + HAL_SD_CardStateTypeDef CardState; - tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT); + /* DIsable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); - while((!tmp) && (timeout > 0)) - { - tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT); - timeout--; - } + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - - if((timeout == 0) || tmp) + if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) { - /* Card is not V2.0 compliant or card does not support the set voltage range */ - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); + /* Disable the SD DMA request */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); - return errorstate; + /* Abort the SD DMA Tx Stream */ + if(hsd->hdmatx != NULL) + { + HAL_DMA_Abort(hsd->hdmatx); + } + /* Abort the SD DMA Rx Stream */ + if(hsd->hdmarx != NULL) + { + HAL_DMA_Abort(hsd->hdmarx); + } } - if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDREND)) + hsd->State = HAL_SD_STATE_READY; + CardState = HAL_SD_GetCardState(hsd); + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { - /* Card is SD V2.0 compliant */ - errorstate = SD_OK; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CMDREND); - - return errorstate; + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); } - - return errorstate; + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + return HAL_ERROR; + } + return HAL_OK; } /** - * @brief Checks for error conditions for R1 response. - * @param hsd: SD handle - * @param SD_CMD: The sent command index - * @retval SD Card error state + * @brief Abort the current transfer and disable the SD (IT mode). + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information for SD module. + * @retval HAL status */ -static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD) +HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t response_r1 = 0; + HAL_SD_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) - { - } + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - - return errorstate; - } - else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) + if((hsd->hdmatx != NULL) || (hsd->hdmarx != NULL)) { - errorstate = SD_CMD_CRC_FAIL; + /* Disable the SD DMA request */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); - - return errorstate; - } - else - { - /* No error flag set */ + /* Abort the SD DMA Tx Stream */ + if(hsd->hdmatx != NULL) + { + hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; + if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + { + hsd->hdmatx = NULL; + } + } + /* Abort the SD DMA Rx Stream */ + if(hsd->hdmarx != NULL) + { + hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; + if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + { + hsd->hdmarx = NULL; + } + } } - /* Check response received is of desired command */ - if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD) + /* No transfer ongoing on both DMA channels*/ + if((hsd->hdmatx == NULL) && (hsd->hdmarx == NULL)) { - errorstate = SD_ILLEGAL_CMD; - - return errorstate; + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + } + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + HAL_SD_AbortCallback(hsd); + } } - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + return HAL_OK; +} + +/** + * @} + */ - /* We have received response, retrieve it for analysis */ - response_r1 = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); +/** + * @} + */ - if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO) - { - return errorstate; - } +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief DMA SD transmit process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) - { - return(SD_ADDR_OUT_OF_RANGE); - } + /* Enable DATAEND Interrupt */ + __HAL_SD_ENABLE_IT(hsd, (SDIO_IT_DATAEND)); +} + +/** + * @brief DMA SD receive process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + uint32_t errorstate = HAL_SD_ERROR_NONE; - if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED) + /* Send stop command in multiblock write */ + if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA)) { - return(SD_ADDR_MISALIGNED); + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; + HAL_SD_ErrorCallback(hsd); + } } - if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR) - { - return(SD_BLOCK_LEN_ERR); - } + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the SD DCTRL register */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDIO_DCTRL_DMAEN); - if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR) - { - return(SD_ERASE_SEQ_ERR); - } + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM) - { - return(SD_BAD_ERASE_PARAM); - } + hsd->State = HAL_SD_STATE_READY; + + HAL_SD_RxCpltCallback(hsd); +} + +/** + * @brief DMA SD communication error callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMAError(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + HAL_SD_CardStateTypeDef CardState; - if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION) + if((hsd->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hsd->hdmatx->ErrorCode == HAL_DMA_ERROR_TE)) { - return(SD_WRITE_PROT_VIOLATION); + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + /* Disable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDIO_IT_DATAEND | SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT|\ + SDIO_IT_TXUNDERR| SDIO_IT_RXOVERR); + + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + CardState = HAL_SD_GetCardState(hsd); + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + } + + hsd->State= HAL_SD_STATE_READY; } + + HAL_SD_ErrorCallback(hsd); +} + +/** + * @brief DMA SD Tx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + HAL_SD_CardStateTypeDef CardState; - if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED) + if(hsd->hdmatx != NULL) { - return(SD_LOCK_UNLOCK_FAILED); + hsd->hdmatx = NULL; } - if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED) + /* All DMA channels are aborted */ + if(hsd->hdmarx == NULL) { - return(SD_COM_CRC_FAILED); + CardState = HAL_SD_GetCardState(hsd); + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_READY; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + HAL_SD_AbortCallback(hsd); + } + else + { + HAL_SD_ErrorCallback(hsd); + } + } } +} + +/** + * @brief DMA SD Rx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + HAL_SD_CardStateTypeDef CardState; - if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD) + if(hsd->hdmarx != NULL) { - return(SD_ILLEGAL_CMD); + hsd->hdmarx = NULL; } - if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED) + /* All DMA channels are aborted */ + if(hsd->hdmatx == NULL) { - return(SD_CARD_ECC_FAILED); + CardState = HAL_SD_GetCardState(hsd); + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_READY; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + HAL_SD_AbortCallback(hsd); + } + else + { + HAL_SD_ErrorCallback(hsd); + } + } } +} + + +/** + * @brief Initializes the sd card. + * @param hsd: Pointer to SD handle + * @retval SD Card error state + */ +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) +{ + HAL_SD_CardCSDTypeDef CSD; + uint32_t errorstate = HAL_SD_ERROR_NONE; + uint16_t sd_rca = 1U; - if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR) + /* Check the power State */ + if(SDIO_GetPowerState(hsd->Instance) == 0U) { - return(SD_CC_ERROR); + /* Power off */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR) + if(hsd->SdCard.CardType != CARD_SECURED) { - return(SD_GENERAL_UNKNOWN_ERROR); + /* Send CMD2 ALL_SEND_CID */ + errorstate = SDMMC_CmdSendCID(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card identification number data */ + hsd->CID[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + hsd->CID[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2); + hsd->CID[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3); + hsd->CID[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4); + } } - if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN) + if(hsd->SdCard.CardType != CARD_SECURED) { - return(SD_STREAM_READ_UNDERRUN); + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* SD Card publishes its RCA. */ + errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } } - - if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN) + if(hsd->SdCard.CardType != CARD_SECURED) { - return(SD_STREAM_WRITE_OVERRUN); + /* Get the SD card RCA */ + hsd->SdCard.RelCardAdd = sd_rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card Specific Data */ + hsd->CSD[0U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + hsd->CSD[1U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP2); + hsd->CSD[2U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP3); + hsd->CSD[3U] = SDIO_GetResponse(hsd->Instance, SDIO_RESP4); + } } - if((response_r1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE) - { - return(SD_CID_CSD_OVERWRITE); - } + /* Get the Card Class */ + hsd->SdCard.Class = (SDIO_GetResponse(hsd->Instance, SDIO_RESP2) >> 20U); - if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP) + /* Get CSD parameters */ + HAL_SD_GetCardCSD(hsd, &CSD); + + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) { - return(SD_WP_ERASE_SKIP); + return errorstate; } + + /* Configure SDIO peripheral interface */ + SDIO_Init(hsd->Instance, hsd->Init); + + /* All cards are initialized */ + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Enquires cards about their operating voltage and configures clock + * controls and stores SD information that will be needed in future + * in the SD handle. + * @param hsd: Pointer to SD handle + * @retval error state + */ +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) +{ + __IO uint32_t count = 0U; + uint32_t response = 0U, validvoltage = 0U; + uint32_t errorstate = HAL_SD_ERROR_NONE; - if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED) + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) { - return(SD_CARD_ECC_DISABLED); + return errorstate; } - if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET) + /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ + errorstate = SDMMC_CmdOperCond(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) { - return(SD_ERASE_RESET); + hsd->SdCard.CardVersion = CARD_V1_X; + + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while(validvoltage == 0U) + { + if(count++ == SDMMC_MAX_VOLT_TRIAL) + { + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0U); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Send CMD41 */ + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_STD_CAPACITY); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + } + /* Card type is SDSC */ + hsd->SdCard.CardType = CARD_SDSC; } - - if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR) + else { - return(SD_AKE_SEQ_ERROR); + hsd->SdCard.CardVersion = CARD_V2_X; + + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while(validvoltage == 0U) + { + if(count++ == SDMMC_MAX_VOLT_TRIAL) + { + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0U); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send CMD41 */ + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_HIGH_CAPACITY); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Get command response */ + response = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + } + + if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + { + hsd->SdCard.CardType = CARD_SDHC_SDXC; + } + else + { + hsd->SdCard.CardType = CARD_SDSC; + } } - return errorstate; + return HAL_SD_ERROR_NONE; } /** - * @brief Checks for error conditions for R3 (OCR) response. - * @param hsd: SD handle - * @retval SD Card error state + * @brief Turns the SDIO output signals off. + * @param hsd: Pointer to SD handle + * @retval HAL status */ -static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd) +static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd) { - HAL_SD_ErrorTypedef errorstate = SD_OK; - - while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) - { - } - - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + /* Set Power State to OFF */ + SDIO_PowerState_OFF(hsd->Instance); - return errorstate; + return HAL_OK; } /** - * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param hsd: SD handle - * @retval SD Card error state + * @brief Send Status info command. + * @param hsd: pointer to SD handle + * @param pSDstatus: Pointer to the buffer that will contain the SD card status + * SD Status register) + * @retval error state */ -static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd) +static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) { - HAL_SD_ErrorTypedef errorstate = SD_OK; + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t tickstart = HAL_GetTick(); + uint32_t count = 0U; - while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) + /* Check SD response */ + if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } - - if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) + + /* Set block size for card if it is not equal to current block size for card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); + if(errorstate != HAL_SD_ERROR_NONE) { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - + hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; } - else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) + + /* Send CMD55 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); - + hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; } - else - { - /* No error flag set */ - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - return errorstate; -} - -/** - * @brief Checks for error conditions for R6 (RCA) response. - * @param hsd: SD handle - * @param SD_CMD: The sent command index - * @param pRCA: Pointer to the variable that will contain the SD card relative - * address RCA - * @retval SD Card error state - */ -static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA) -{ - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t response_r1 = 0; + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 64U; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_64B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hsd->Instance, &config); - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) + /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ + errorstate = SDMMC_CmdStatusRegister(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) { + hsd->ErrorCode |= HAL_SD_ERROR_NONE; + return errorstate; } - if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) + /* Get status data */ + while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND)) { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF)) + { + for(count = 0U; count < 8U; count++) + { + *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance); + } + + pSDstatus += 8U; + } - return errorstate; + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } } - else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) + + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); - - return errorstate; + return HAL_SD_ERROR_DATA_TIMEOUT; } - else + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) { - /* No error flag set */ + return HAL_SD_ERROR_DATA_CRC_FAIL; } - - /* Check response received is of desired command */ - if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD) + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) { - errorstate = SD_ILLEGAL_CMD; - - return errorstate; + return HAL_SD_ERROR_RX_OVERRUN; } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - /* We have received response, retrieve it. */ - response_r1 = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); - - if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO) + + while ((__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))) { - *pRCA = (uint16_t) (response_r1 >> 16); + *pSDstatus = SDIO_ReadFIFO(hsd->Instance); + pSDstatus++; - return errorstate; + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } } - if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } + /* Clear all the static status flags*/ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Returns the current card's status. + * @param hsd: Pointer to SD handle + * @param pCardStatus: pointer to the buffer that will contain the SD card + * status (Card Status register) + * @retval error state + */ +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) +{ + uint32_t errorstate = HAL_SD_ERROR_NONE; - if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD) + if(pCardStatus == NULL) { - return(SD_ILLEGAL_CMD); + return HAL_SD_ERROR_PARAM; } - if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED) + /* Send Status command */ + errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_OK) { - return(SD_COM_CRC_FAILED); + return errorstate; } - return errorstate; + /* Get SD card status */ + *pCardStatus = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); + + return HAL_SD_ERROR_NONE; } /** * @brief Enables the SDIO wide bus mode. - * @param hsd: SD handle - * @retval SD Card error state + * @param hsd: pointer to SD handle + * @retval error state */ -static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd) +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) { - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; + uint32_t scr[2U] = {0U, 0U}; + uint32_t errorstate = HAL_SD_ERROR_NONE; - uint32_t scr[2] = {0, 0}; - - if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) + if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - - if(errorstate != SD_OK) + if(errorstate != HAL_OK) { return errorstate; } /* If requested card supports wide bus operation */ - if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO) + if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA.*/ - sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_OK) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - sdio_cmdinitstructure.Argument = 2; - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); + if(errorstate != HAL_OK) { return errorstate; } - - return errorstate; + + return HAL_SD_ERROR_NONE; } else { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } -} +} /** * @brief Disables the SDIO wide bus mode. - * @param hsd: SD handle - * @retval SD Card error state + * @param hsd: Pointer to SD handle + * @retval error state */ -static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd) +static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) { - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; - - uint32_t scr[2] = {0, 0}; + uint32_t scr[2U] = {0U, 0U}; + uint32_t errorstate = HAL_SD_ERROR_NONE; - if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED) + if((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { - errorstate = SD_LOCK_UNLOCK_FAILED; - - return errorstate; + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - - if(errorstate != SD_OK) + if(errorstate != HAL_OK) { return errorstate; } /* If requested card supports 1 bit mode operation */ - if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO) + if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA */ - sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_OK) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_SD_SET_BUSWIDTH; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); + if(errorstate != HAL_OK) { return errorstate; } - return errorstate; + return HAL_SD_ERROR_NONE; } else { - errorstate = SD_REQUEST_NOT_APPLICABLE; - - return errorstate; + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } } /** * @brief Finds the SD card SCR register value. - * @param hsd: SD handle + * @param hsd: Pointer to SD handle * @param pSCR: pointer to the buffer that will contain the SCR value - * @retval SD Card error state + * @retval error state */ -static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) { - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - SDIO_DataInitTypeDef sdio_datainitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; - uint32_t index = 0; - uint32_t tempscr[2] = {0, 0}; + SDIO_DataInitTypeDef config; + uint32_t errorstate = HAL_SD_ERROR_NONE; + uint32_t tickstart = HAL_GetTick(); + uint32_t index = 0U; + uint32_t tempscr[2U] = {0U, 0U}; /* Set Block Size To 8 Bytes */ - /* Send CMD55 APP_CMD with argument as card's RCA */ - sdio_cmdinitstructure.Argument = (uint32_t)8; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SET_BLOCKLEN; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); + if(errorstate != HAL_OK) { return errorstate; } - + /* Send CMD55 APP_CMD with argument as card's RCA */ - sdio_cmdinitstructure.Argument = (uint32_t)((hsd->RCA) << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_APP_CMD; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); + if(errorstate != HAL_OK) { return errorstate; } - sdio_datainitstructure.DataTimeOut = SD_DATATIMEOUT; - sdio_datainitstructure.DataLength = 8; - sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B; - sdio_datainitstructure.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; - sdio_datainitstructure.TransferMode = SDIO_TRANSFER_MODE_BLOCK; - sdio_datainitstructure.DPSM = SDIO_DPSM_ENABLE; - SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure); + + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 8U; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_8B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + SDIO_ConfigData(hsd->Instance, &config); /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ - sdio_cmdinitstructure.Argument = 0; - sdio_cmdinitstructure.CmdIndex = SD_CMD_SD_APP_SEND_SCR; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - /* Check for error conditions */ - errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR); - - if(errorstate != SD_OK) + errorstate = SDMMC_CmdSendSCR(hsd->Instance); + if(errorstate != HAL_OK) { return errorstate; } - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR)) + while(!__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND)) { - if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) { *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance); index++; } - } - - if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) - { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - errorstate = SD_DATA_TIMEOUT; - - return errorstate; + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } } - else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) + + if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT)) { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - - errorstate = SD_DATA_CRC_FAIL; + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT); - return errorstate; + return HAL_SD_ERROR_DATA_TIMEOUT; } - else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL)) { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - - errorstate = SD_RX_OVERRUN; + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL); - return errorstate; + return HAL_SD_ERROR_DATA_CRC_FAIL; } - else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR)) + else if(__HAL_SD_GET_FLAG(hsd, SDIO_FLAG_RXOVERR)) { - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR); - - errorstate = SD_START_BIT_ERR; + __HAL_SD_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR); - return errorstate; + return HAL_SD_ERROR_RX_OVERRUN; } else { /* No error flag set */ + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); + + *(pSCR + 1U) = ((tempscr[0U] & SDMMC_0TO7BITS) << 24U) | ((tempscr[0U] & SDMMC_8TO15BITS) << 8U) |\ + ((tempscr[0U] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[0U] & SDMMC_24TO31BITS) >> 24U); + + *(pSCR) = ((tempscr[1U] & SDMMC_0TO7BITS) << 24U) | ((tempscr[1U] & SDMMC_8TO15BITS) << 8U) |\ + ((tempscr[1U] & SDMMC_16TO23BITS) >> 8U) | ((tempscr[1U] & SDMMC_24TO31BITS) >> 24U); } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) |\ - ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); - - *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) |\ - ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); - - return errorstate; + + return HAL_SD_ERROR_NONE; } /** - * @brief Checks if the SD card is in programming state. - * @param hsd: SD handle - * @param pStatus: pointer to the variable that will contain the SD card state - * @retval SD Card error state + * @brief Wrap up reading in non-blocking mode. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval HAL status */ -static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus) +static HAL_StatusTypeDef SD_Read_IT(SD_HandleTypeDef *hsd) { - SDIO_CmdInitTypeDef sdio_cmdinitstructure = {0}; - HAL_SD_ErrorTypedef errorstate = SD_OK; - __IO uint32_t responseR1 = 0; - - sdio_cmdinitstructure.Argument = (uint32_t)(hsd->RCA << 16); - sdio_cmdinitstructure.CmdIndex = SD_CMD_SEND_STATUS; - sdio_cmdinitstructure.Response = SDIO_RESPONSE_SHORT; - sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO; - sdio_cmdinitstructure.CPSM = SDIO_CPSM_ENABLE; - SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); - - while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)) - { - } - - if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT)) - { - errorstate = SD_CMD_RSP_TIMEOUT; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT); - - return errorstate; - } - else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL)) - { - errorstate = SD_CMD_CRC_FAIL; - - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL); - - return errorstate; - } - else - { - /* No error flag set */ - } - - /* Check response received is of desired command */ - if((uint32_t)SDIO_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS) - { - errorstate = SD_ILLEGAL_CMD; - - return errorstate; - } - - /* Clear all the static flags */ - __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS); - - - /* We have received response, retrieve it for analysis */ - responseR1 = SDIO_GetResponse(hsd->Instance, SDIO_RESP1); - - /* Find out card status */ - *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F); - - if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO) - { - return errorstate; - } - - if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE) - { - return(SD_ADDR_OUT_OF_RANGE); - } - - if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED) - { - return(SD_ADDR_MISALIGNED); - } - - if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR) - { - return(SD_BLOCK_LEN_ERR); - } - - if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR) - { - return(SD_ERASE_SEQ_ERR); - } - - if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM) - { - return(SD_BAD_ERASE_PARAM); - } - - if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION) - { - return(SD_WRITE_PROT_VIOLATION); - } - - if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED) - { - return(SD_LOCK_UNLOCK_FAILED); - } - - if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED) - { - return(SD_COM_CRC_FAILED); - } - - if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD) - { - return(SD_ILLEGAL_CMD); - } - - if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED) - { - return(SD_CARD_ECC_FAILED); - } - - if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR) - { - return(SD_CC_ERROR); - } - - if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR) - { - return(SD_GENERAL_UNKNOWN_ERROR); - } - - if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN) - { - return(SD_STREAM_READ_UNDERRUN); - } + uint32_t count = 0U; + uint32_t* tmp; + + tmp = (uint32_t*)hsd->pRxBuffPtr; - if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN) + /* Read data from SDIO Rx FIFO */ + for(count = 0U; count < 8U; count++) { - return(SD_STREAM_WRITE_OVERRUN); + *(tmp + count) = SDIO_ReadFIFO(hsd->Instance); } - if((responseR1 & SD_OCR_CID_CSD_OVERWRITE) == SD_OCR_CID_CSD_OVERWRITE) - { - return(SD_CID_CSD_OVERWRITE); - } + hsd->pRxBuffPtr += 8U; - if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP) - { - return(SD_WP_ERASE_SKIP); - } + return HAL_OK; +} + +/** + * @brief Wrap up writing in non-blocking mode. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval HAL status + */ +static HAL_StatusTypeDef SD_Write_IT(SD_HandleTypeDef *hsd) +{ + uint32_t count = 0U; + uint32_t* tmp; - if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED) - { - return(SD_CARD_ECC_DISABLED); - } + tmp = (uint32_t*)hsd->pTxBuffPtr; - if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET) + /* Write data to SDIO Tx FIFO */ + for(count = 0U; count < 8U; count++) { - return(SD_ERASE_RESET); + SDIO_WriteFIFO(hsd->Instance, (tmp + count)); } - if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR) - { - return(SD_AKE_SEQ_ERROR); - } + hsd->pTxBuffPtr += 8U; - return errorstate; -} + return HAL_OK; +} /** * @} */ - + #endif /* STM32F103xE || STM32F103xG */ #endif /* HAL_SD_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.h index a57a7a384b5..1084d683c41 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sd.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_hal_sd.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of SD HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -52,7 +52,8 @@ * @{ */ -/** @addtogroup SD +/** @defgroup SD SD + * @brief SD HAL module driver * @{ */ @@ -61,45 +62,116 @@ * @{ */ +/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure + * @{ + */ +typedef enum +{ + HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */ + HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */ + HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */ + HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */ + HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */ + HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receinving State */ + HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */ + HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */ +}HAL_SD_StateTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure + * @{ + */ +typedef enum +{ + HAL_SD_CARD_READY = 0x00000001U, /*!< Card state is ready */ + HAL_SD_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */ + HAL_SD_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */ + HAL_SD_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */ + HAL_SD_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */ + HAL_SD_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */ + HAL_SD_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */ + HAL_SD_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */ + HAL_SD_CARD_ERROR = 0x000000FFU /*!< Card response Error */ +}HAL_SD_CardStateTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition + * @{ + */ #define SD_InitTypeDef SDIO_InitTypeDef #define SD_TypeDef SDIO_TypeDef /** - * @brief SDIO Handle Structure definition + * @brief SD Card Information Structure definition */ typedef struct { - SD_TypeDef *Instance; /*!< SDIO register base address */ + uint32_t CardType; /*!< Specifies the card Type */ - SD_InitTypeDef Init; /*!< SD required parameters */ + uint32_t CardVersion; /*!< Specifies the card version */ + + uint32_t Class; /*!< Specifies the class of the card class */ + + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ - HAL_LockTypeDef Lock; /*!< SD locking object */ + uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ + + uint32_t BlockSize; /*!< Specifies one block size in bytes */ - uint32_t CardType; /*!< SD card type */ + uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ + + uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ + +}HAL_SD_CardInfoTypeDef; + +/** + * @brief SD handle Structure definition + */ +typedef struct +{ + SD_TypeDef *Instance; /*!< SD registers base address */ - uint32_t RCA; /*!< SD relative card address */ + SD_InitTypeDef Init; /*!< SD required parameters */ - uint32_t CSD[4]; /*!< SD card specific data table */ + HAL_LockTypeDef Lock; /*!< SD locking object */ - uint32_t CID[4]; /*!< SD card identification number table */ + uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< SD Tx Transfer size */ + + uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< SD Rx Transfer size */ - __IO uint32_t SdTransferCplt; /*!< SD transfer complete flag in non blocking mode */ + __IO uint32_t Context; /*!< SD transfer context */ + + __IO HAL_SD_StateTypeDef State; /*!< SD card State */ - __IO uint32_t SdTransferErr; /*!< SD transfer error flag in non blocking mode */ + __IO uint32_t ErrorCode; /*!< SD Card Error codes */ + + DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ - __IO uint32_t DmaTransferCplt; /*!< SD DMA transfer complete flag */ + DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ - __IO uint32_t SdOperation; /*!< SD transfer operation (read/write) */ + HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ - DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ + uint32_t CSD[4]; /*!< SD card specific data table */ - DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ + uint32_t CID[4]; /*!< SD card identification number table */ }SD_HandleTypeDef; /** - * @brief Card Specific Data: CSD Register - */ + * @} + */ + +/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register + * @{ + */ typedef struct { __IO uint8_t CSDStruct; /*!< CSD structure */ @@ -139,11 +211,14 @@ typedef struct __IO uint8_t ECC; /*!< ECC code */ __IO uint8_t CSD_CRC; /*!< CSD CRC */ __IO uint8_t Reserved4; /*!< Always 1 */ - -}HAL_SD_CSDTypedef; - + +}HAL_SD_CardCSDTypeDef; /** - * @brief Card Identification Data: CID Register + * @} + */ + +/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register + * @{ */ typedef struct { @@ -158,287 +233,160 @@ typedef struct __IO uint8_t CID_CRC; /*!< CID CRC */ __IO uint8_t Reserved2; /*!< Always 1 */ -}HAL_SD_CIDTypedef; - +}HAL_SD_CardCIDTypeDef; /** - * @brief SD Card Status returned by ACMD13 + * @} */ -typedef struct -{ - __IO uint8_t DAT_BUS_WIDTH; /*!< Shows the currently defined data bus width */ - __IO uint8_t SECURED_MODE; /*!< Card is in secured mode of operation */ - __IO uint16_t SD_CARD_TYPE; /*!< Carries information about card type */ - __IO uint32_t SIZE_OF_PROTECTED_AREA; /*!< Carries information about the capacity of protected area */ - __IO uint8_t SPEED_CLASS; /*!< Carries information about the speed class of the card */ - __IO uint8_t PERFORMANCE_MOVE; /*!< Carries information about the card's performance move */ - __IO uint8_t AU_SIZE; /*!< Carries information about the card's allocation unit size */ - __IO uint16_t ERASE_SIZE; /*!< Determines the number of AUs to be erased in one operation */ - __IO uint8_t ERASE_TIMEOUT; /*!< Determines the timeout for any number of AU erase */ - __IO uint8_t ERASE_OFFSET; /*!< Carries information about the erase offset */ - -}HAL_SD_CardStatusTypedef; -/** - * @brief SD Card information structure +/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 + * @{ */ typedef struct { - HAL_SD_CSDTypedef SD_csd; /*!< SD card specific data register */ - HAL_SD_CIDTypedef SD_cid; /*!< SD card identification number register */ - uint64_t CardCapacity; /*!< Card capacity */ - uint32_t CardBlockSize; /*!< Card block size */ - uint16_t RCA; /*!< SD relative card address */ - uint8_t CardType; /*!< SD card type */ - -}HAL_SD_CardInfoTypedef; - + __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */ + __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */ + __IO uint16_t CardType; /*!< Carries information about card type */ + __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */ + __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */ + __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */ + __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */ + __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */ + __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */ + __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */ + +}HAL_SD_CardStatusTypeDef; /** - * @brief SD Error status enumeration Structure definition + * @} */ -typedef enum -{ -/** - * @brief SD specific error defines - */ - SD_CMD_CRC_FAIL = (1), /*!< Command response received (but CRC check failed) */ - SD_DATA_CRC_FAIL = (2), /*!< Data block sent/received (CRC check failed) */ - SD_CMD_RSP_TIMEOUT = (3), /*!< Command response timeout */ - SD_DATA_TIMEOUT = (4), /*!< Data timeout */ - SD_TX_UNDERRUN = (5), /*!< Transmit FIFO underrun */ - SD_RX_OVERRUN = (6), /*!< Receive FIFO overrun */ - SD_START_BIT_ERR = (7), /*!< Start bit not detected on all data signals in wide bus mode */ - SD_CMD_OUT_OF_RANGE = (8), /*!< Command's argument was out of range. */ - SD_ADDR_MISALIGNED = (9), /*!< Misaligned address */ - SD_BLOCK_LEN_ERR = (10), /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */ - SD_ERASE_SEQ_ERR = (11), /*!< An error in the sequence of erase command occurs. */ - SD_BAD_ERASE_PARAM = (12), /*!< An invalid selection for erase groups */ - SD_WRITE_PROT_VIOLATION = (13), /*!< Attempt to program a write protect block */ - SD_LOCK_UNLOCK_FAILED = (14), /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */ - SD_COM_CRC_FAILED = (15), /*!< CRC check of the previous command failed */ - SD_ILLEGAL_CMD = (16), /*!< Command is not legal for the card state */ - SD_CARD_ECC_FAILED = (17), /*!< Card internal ECC was applied but failed to correct the data */ - SD_CC_ERROR = (18), /*!< Internal card controller error */ - SD_GENERAL_UNKNOWN_ERROR = (19), /*!< General or unknown error */ - SD_STREAM_READ_UNDERRUN = (20), /*!< The card could not sustain data transfer in stream read operation. */ - SD_STREAM_WRITE_OVERRUN = (21), /*!< The card could not sustain data programming in stream mode */ - SD_CID_CSD_OVERWRITE = (22), /*!< CID/CSD overwrite error */ - SD_WP_ERASE_SKIP = (23), /*!< Only partial address space was erased */ - SD_CARD_ECC_DISABLED = (24), /*!< Command has been executed without using internal ECC */ - SD_ERASE_RESET = (25), /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ - SD_AKE_SEQ_ERROR = (26), /*!< Error in sequence of authentication. */ - SD_INVALID_VOLTRANGE = (27), - SD_ADDR_OUT_OF_RANGE = (28), - SD_SWITCH_ERROR = (29), - SD_SDIO_DISABLED = (30), - SD_SDIO_FUNCTION_BUSY = (31), - SD_SDIO_FUNCTION_FAILED = (32), - SD_SDIO_UNKNOWN_FUNCTION = (33), - -/** - * @brief Standard error defines - */ - SD_INTERNAL_ERROR = (34), - SD_NOT_CONFIGURED = (35), - SD_REQUEST_PENDING = (36), - SD_REQUEST_NOT_APPLICABLE = (37), - SD_INVALID_PARAMETER = (38), - SD_UNSUPPORTED_FEATURE = (39), - SD_UNSUPPORTED_HW = (40), - SD_ERROR = (41), - SD_OK = (0) - -}HAL_SD_ErrorTypedef; /** - * @brief SD Transfer state enumeration structure - */ -typedef enum -{ - SD_TRANSFER_OK = 0, /*!< Transfer success */ - SD_TRANSFER_BUSY = 1, /*!< Transfer is occurring */ - SD_TRANSFER_ERROR = 2 /*!< Transfer failed */ + * @} + */ -}HAL_SD_TransferStateTypedef; +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SD_Exported_Constants Exported Constants + * @{ + */ -/** - * @brief SD Card State enumeration structure - */ -typedef enum -{ - SD_CARD_READY = ((uint32_t)0x00000001), /*!< Card state is ready */ - SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), /*!< Card is in identification state */ - SD_CARD_STANDBY = ((uint32_t)0x00000003), /*!< Card is in standby state */ - SD_CARD_TRANSFER = ((uint32_t)0x00000004), /*!< Card is in transfer state */ - SD_CARD_SENDING = ((uint32_t)0x00000005), /*!< Card is sending an operation */ - SD_CARD_RECEIVING = ((uint32_t)0x00000006), /*!< Card is receiving operation information */ - SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), /*!< Card is in programming state */ - SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), /*!< Card is disconnected */ - SD_CARD_ERROR = ((uint32_t)0x000000FF) /*!< Card is in error state */ - -}HAL_SD_CardStateTypedef; +#define BLOCKSIZE 512U /*!< Block size is 512 bytes */ +/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition + * @{ + */ +#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ + /** - * @brief SD Operation enumeration structure - */ -typedef enum -{ - SD_READ_SINGLE_BLOCK = 0, /*!< Read single block operation */ - SD_READ_MULTIPLE_BLOCK = 1, /*!< Read multiple blocks operation */ - SD_WRITE_SINGLE_BLOCK = 2, /*!< Write single block operation */ - SD_WRITE_MULTIPLE_BLOCK = 3 /*!< Write multiple blocks operation */ - -}HAL_SD_OperationTypedef; + * @} + */ + +/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration + * @{ + */ +#define SD_CONTEXT_NONE 0x00000000U /*!< None */ +#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */ +#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */ +#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */ +#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */ +#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */ +#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */ /** * @} */ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SD_Exported_Constants SD Exported Constants +/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards * @{ */ +#define CARD_SDSC 0x00000000U +#define CARD_SDHC_SDXC 0x00000001U +#define CARD_SECURED 0x00000003U + +/** + * @} + */ -/** - * @brief SD Commands Index - */ -#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */ -#define SD_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */ -#define SD_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ -#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */ -#define SD_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */ -#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its - operating condition register (OCR) content in the response on the CMD line. */ -#define SD_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ -#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information - and asks the card whether card supports voltage. */ -#define SD_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ -#define SD_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */ -#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */ -#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */ -#define SD_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */ -#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) -#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */ -#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands - (read, write, lock). Default block length is fixed to 512 Bytes. Not effective - for SDHS and SDXC. */ -#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ -#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by - STOP_TRANSMISSION command. */ -#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ -#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */ -#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */ -#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ -#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ -#define SD_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */ -#define SD_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */ -#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */ -#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */ -#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */ -#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */ -#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command - system set by switch function command (CMD6). */ -#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased. - Reserved for each command system set by switch function command (CMD6). */ -#define SD_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */ -#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */ -#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */ -#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by - the SET_BLOCK_LEN command. */ -#define SD_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather - than a standard command. */ -#define SD_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card - for general purpose/application specific commands. */ -#define SD_CMD_NO_CMD ((uint8_t)64) - -/** - * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus - widths are given in SCR register. */ -#define SD_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */ -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with - 32bit+CRC data block. */ -#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to - send its operating condition register (OCR) content in the response on the CMD line. */ -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */ -#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */ -#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */ -#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */ - -/** - * @brief Following commands are SD Card Specific security commands. - * SD_CMD_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD card only */ -#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD card only */ -#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD card only */ -#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD card only */ -#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD card only */ - -/** - * @brief Supported SD Memory Cards +/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version + * @{ */ -#define STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) -#define STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) -#define HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) -#define MULTIMEDIA_CARD ((uint32_t)0x00000003) -#define SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) -#define HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) -#define SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) -#define HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) +#define CARD_V1_X 0x00000000U +#define CARD_V2_X 0x00000001U +/** + * @} + */ + /** * @} */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup SD_Exported_macros SD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ /** * @brief Enable the SD device. - * @param __HANDLE__: SD Handle * @retval None */ -#define __HAL_SD_SDIO_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance) +#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance) /** * @brief Disable the SD device. - * @param __HANDLE__: SD Handle * @retval None */ -#define __HAL_SD_SDIO_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance) +#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance) /** - * @brief Enable the SDIO DMA transfer. - * @param __HANDLE__: SD Handle + * @brief Enable the SDMMC DMA transfer. * @retval None */ -#define __HAL_SD_SDIO_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance) +#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance) /** - * @brief Disable the SDIO DMA transfer. - * @param __HANDLE__: SD Handle + * @brief Disable the SDMMC DMA transfer. * @retval None */ -#define __HAL_SD_SDIO_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance) +#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance) /** * @brief Enable the SD device interrupt. * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDIO interrupt sources to be enabled. + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -449,8 +397,6 @@ typedef enum * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt * @arg SDIO_IT_TXACT: Data transmit in progress interrupt @@ -464,15 +410,14 @@ typedef enum * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt * @retval None */ -#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) +#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) /** * @brief Disable the SD device interrupt. * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDIO interrupt sources to be disabled. + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -483,8 +428,6 @@ typedef enum * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt * @arg SDIO_IT_TXACT: Data transmit in progress interrupt @@ -497,11 +440,10 @@ typedef enum * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt * @retval None */ -#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) +#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) /** * @brief Check whether the specified SD flag is set or not. @@ -517,7 +459,6 @@ typedef enum * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDIO_FLAG_CMDACT: Command transfer in progress * @arg SDIO_FLAG_TXACT: Data transmit in progress @@ -531,10 +472,9 @@ typedef enum * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 * @retval The new state of SD FLAG (SET or RESET). */ -#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) +#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) /** * @brief Clear the SD's pending flags. @@ -550,18 +490,16 @@ typedef enum * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 * @retval None */ -#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) +#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) /** * @brief Check whether the specified SD interrupt has occurred or not. * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDIO interrupt source to check. + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -572,8 +510,6 @@ typedef enum * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt * @arg SDIO_IT_TXACT: Data transmit in progress interrupt @@ -587,14 +523,13 @@ typedef enum * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt * @retval The new state of SD IT (SET or RESET). */ -#define __HAL_SD_SDIO_GET_IT (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT ((__HANDLE__)->Instance, __INTERRUPT__) +#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) /** * @brief Clear the SD's interrupt pending bits. - * @param __HANDLE__ : SD Handle + * @param __HANDLE__: SD Handle * @param __INTERRUPT__: specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt @@ -605,91 +540,161 @@ typedef enum * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 * @retval None */ -#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) +#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + /** * @} */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup SD_Exported_Functions +/** @defgroup SD_Exported_Functions SD Exported Functions * @{ */ - -/* Initialization and de-initialization functions **********************************/ -/** @addtogroup SD_Exported_Functions_Group1 + +/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ -HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo); -HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); void HAL_SD_MspInit(SD_HandleTypeDef *hsd); void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); /** * @} */ - -/* I/O operation functions *****************************************************/ -/** @addtogroup SD_Exported_Functions_Group2 + +/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions * @{ */ /* Blocking mode: Polling */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t Startaddr, uint64_t Endaddr); +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +/* Non-Blocking mode: IT */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -/* Non-Blocking mode: Interrupt */ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); /* Callback in non blocking modes (DMA) */ -void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma); -void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma); -void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd); -void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd); - -/* Non-Blocking mode: DMA */ -HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks); -HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout); -HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout); +void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd); +void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd); /** * @} */ -/* Peripheral Control functions ************************************************/ -/** @addtogroup SD_Exported_Functions_Group3 +/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions * @{ */ -HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo); -HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode); -HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd); -HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode); /** * @} */ - -/* Peripheral State functions **************************************************/ -/** @addtogroup SD_Exported_Functions_Group4 + +/** @defgroup SD_Exported_Functions_Group4 SD card related functions * @{ */ -HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); -HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus); -HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); +HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ +/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd); +uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); /** * @} */ - + +/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management + * @{ + */ +HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup SD_Private_Types SD Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SD_Private_Defines SD Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup SD_Private_Variables SD Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SD_Private_Constants SD Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SD_Private_Macros SD Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SD_Private_Functions SD Private Functions + * @{ + */ + +/** + * @} + */ + + /** * @} */ @@ -698,6 +703,9 @@ HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd); * @} */ +/** + * @} + */ #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c index d25afce9c43..bec0085ea28 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c @@ -2,16 +2,15 @@ ****************************************************************************** * @file stm32f1xx_hal_smartcard.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral State and Errors functions * + Peripheral Control functions - * + * + Peripheral State and Errors functions @verbatim ============================================================================== ##### How to use this driver ##### @@ -21,10 +20,10 @@ (#) Declare a SMARTCARD_HandleTypeDef handle structure. (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: - (##) Enable the interface clock of the USARTx associated to the SMARTCARD. + (##) Enable the USARTx interface clock. (##) SMARTCARD pins configuration: (+++) Enable the clock for the SMARTCARD GPIOs. - (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). + (+++) Configure the SMARTCARD pins as alternate function pull-up. (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() and HAL_SMARTCARD_Receive_IT() APIs): (+++) Configure the USARTx interrupt priority. @@ -35,75 +34,84 @@ (+++) Enable the DMAx interface clock. (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle. + (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle (used for last byte sending completion detection in DMA non circular mode) - (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure. (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_SMARTCARD_MspInit(&hsc) API. - - -@@- The specific SMARTCARD interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process. - - (#) Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() - (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT() - (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT() - (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback - (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() - (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() - (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback - (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback - - *** SMARTCARD HAL driver macros list *** - ======================================== - [..] - Below the list of most used macros in SMARTCARD HAL driver. - - (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral - (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral - (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not - (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag - (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt - (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt - (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether the specified SMARTCARD interrupt has occurred or not - + (++) These APIs configure also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SMARTCARD_MspInit() API. [..] - (@) You can refer to the SMARTCARD HAL driver header file for more useful macros + (@)The specific SMARTCARD interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process. + [..] + Three operation modes are available within this driver: + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() + (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive() + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT() + (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback + (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT() + (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback + (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() + (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback + (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() + (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback + (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback + + *** SMARTCARD HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in SMARTCARD HAL driver. + + (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral + (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral + (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not + (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag + (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt + (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt + + [..] + (@) You can refer to the SMARTCARD HAL driver header file for more useful macros + @endverbatim + [..] + (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible SMARTCARD frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | SMARTCARD frame | + |---------------------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -141,42 +149,50 @@ * @brief HAL SMARTCARD module driver * @{ */ - #ifdef HAL_SMARTCARD_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macros --------------------------------------------------------*/ +/** @addtogroup SMARTCARD_Private_Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup SMARTCARD_Private_Functions SMARTCARD Private Functions +/** @addtogroup SMARTCARD_Private_Functions * @{ */ +static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc); +static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc); +static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc); static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc); static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc); -static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc); static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); /** * @} */ - -/* Exported functions ---------------------------------------------------------*/ - +/* Exported functions --------------------------------------------------------*/ /** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions * @{ */ -/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions +/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim - ============================================================================== - ##### Initialization and Configuration functions ##### + ##### Initialization and Configuration functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART @@ -193,7 +209,7 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe (++) Baud Rate (++) Word Length => Should be 9 bits (8 bits + parity) (++) Stop Bit - (++) Parity: => Should be enabled + (++) Parity: => Should be enabled (++) USART polarity (++) USART phase (++) USART LastBit @@ -211,32 +227,23 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe [..] Please refer to the ISO 7816-3 specification for more details. - (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended - to use 1.5 stop bits for both transmitting and receiving to avoid switching - between the two configurations. [..] - The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration - procedure (details for the procedure are available in reference manuals - (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)). + (@) It is also possible to choose 0.5 stop bit for receiving but it is recommended + to use 1.5 stop bits for both transmitting and receiving to avoid switching + between the two configurations. + [..] + The HAL_SMARTCARD_Init() function follows the USART SmartCard configuration + procedure (details for the procedure are available in reference manual (RM0329)). @endverbatim * @{ */ -/* - Additionnal remark on the smartcard frame: - +-------------------------------------------------------------+ - | M bit | PCE bit | SMARTCARD frame | - |---------------------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ -*/ - /** - * @brief Initializes the SmartCard mode according to the specified - * parameters in the SMARTCARD_HandleTypeDef and create the associated handle. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Initializes the SmartCard mode according to the specified + * parameters in the SMARTCARD_InitTypeDef and create the associated handle. + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) @@ -247,38 +254,26 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) return HAL_ERROR; } - /* Check Wordlength, Parity and Stop bits parameters */ - if ( (!(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength))) - ||(!(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits))) - ||(!(IS_SMARTCARD_PARITY(hsc->Init.Parity))) ) - { - return HAL_ERROR; - } - /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); - assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState)); - assert_param(IS_SMARTCARD_PRESCALER(hsc->Init.Prescaler)); - if(hsc->State == HAL_SMARTCARD_STATE_RESET) + + if(hsc->gState == HAL_SMARTCARD_STATE_RESET) { /* Allocate lock resource and initialize it */ hsc->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_SMARTCARD_MspInit(hsc); } - - hsc->State = HAL_SMARTCARD_STATE_BUSY; - /* Disable the Peripheral */ - __HAL_SMARTCARD_DISABLE(hsc); - + hsc->gState = HAL_SMARTCARD_STATE_BUSY; + /* Set the Prescaler */ MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler); /* Set the Guard Time */ - MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8)); + MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8U)); /* Set the Smartcard Communication parameters */ SMARTCARD_SetConfig(hsc); @@ -289,26 +284,33 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN); CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); - /* Enable the Peripharal */ + /* Enable the SMARTCARD Parity Error Interrupt */ + SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE); + + /* Enable the SMARTCARD Framing Error Interrupt */ + SET_BIT(hsc->Instance->CR3, USART_CR3_EIE); + + /* Enable the Peripheral */ __HAL_SMARTCARD_ENABLE(hsc); /* Configure the Smartcard NACK state */ MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState); /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - SET_BIT(hsc->Instance->CR3, USART_CR3_SCEN); + hsc->Instance->CR3 |= (USART_CR3_SCEN); /* Initialize the SMARTCARD state*/ hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->State= HAL_SMARTCARD_STATE_READY; + hsc->gState= HAL_SMARTCARD_STATE_READY; + hsc->RxState= HAL_SMARTCARD_STATE_READY; return HAL_OK; } /** - * @brief DeInitializes the SMARTCARD peripheral - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief DeInitializes the USART SmartCard peripheral + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) @@ -322,22 +324,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); - hsc->State = HAL_SMARTCARD_STATE_BUSY; + hsc->gState = HAL_SMARTCARD_STATE_BUSY; - /* Disable the Peripheral */ - __HAL_SMARTCARD_DISABLE(hsc); - - hsc->Instance->CR1 = 0x0; - hsc->Instance->CR2 = 0x0; - hsc->Instance->CR3 = 0x0; - hsc->Instance->BRR = 0x0; - hsc->Instance->GTPR = 0x0; - /* DeInit the low level hardware */ HAL_SMARTCARD_MspDeInit(hsc); hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsc->State = HAL_SMARTCARD_STATE_RESET; + hsc->gState = HAL_SMARTCARD_STATE_RESET; + hsc->RxState = HAL_SMARTCARD_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hsc); @@ -346,33 +340,33 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) } /** - * @brief SMARTCARD MSP Init. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief SMARTCARD MSP Init. + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc) +__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsc); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_MspInit can be implemented in the user file - */ + the HAL_SMARTCARD_MspInit could be implemented in the user file + */ } /** - * @brief SMARTCARD MSP DeInit. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief SMARTCARD MSP DeInit + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval None */ - __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc) +__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsc); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_MspDeInit can be implemented in the user file - */ + the HAL_SMARTCARD_MspDeInit could be implemented in the user file + */ } /** @@ -383,33 +377,32 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) * @brief SMARTCARD Transmit and Receive functions * @verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. - [..] + [..] (#) Smartcard is a single wire half duplex communication protocol. The Smartcard interface is designed to support asynchronous protocol Smartcards as defined in the ISO 7816-3 standard. (#) The USART should be configured as: - (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register - (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. + (++) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register + (++) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, the relevant API's return the HAL status. - The end of the data processing will be indicated through the - dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks - will be executed respectively at the end of the Transmit or Receive process - The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication - error is detected. + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks + will be executed respectively at the end of the Transmit or Receive process + The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected (#) Blocking mode APIs are : (++) HAL_SMARTCARD_Transmit() @@ -434,22 +427,22 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) */ /** - * @brief Sends an amount of data in blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent - * @param Timeout: Specify timeout value + * @brief Send an amount of data in blocking mode + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tmp_state = 0; + uint16_t* tmp; + uint32_t tickstart = 0U; - tmp_state = hsc->State; - if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_RX)) + if(hsc->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -458,42 +451,33 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * __HAL_LOCK(hsc); hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - + hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX; + + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); + hsc->TxXferSize = Size; hsc->TxXferCount = Size; - while(hsc->TxXferCount > 0) + while(hsc->TxXferCount > 0U) { - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK) + hsc->TxXferCount--; + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - WRITE_REG(hsc->Instance->DR, (*pData++ & (uint8_t)0xFF)); - hsc->TxXferCount--; + tmp = (uint16_t*) pData; + hsc->Instance->DR = (*tmp & (uint16_t)0x01FF); + pData +=1U; } - - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK) + + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - /* Check if a non-blocking receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } + /* At end of Tx process, restore hsc->gState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsc); @@ -506,22 +490,22 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * } /** - * @brief Receive an amount of data in blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Specify timeout value + * @brief Receive an amount of data in blocking mode + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tmp_state = 0; + uint16_t* tmp; + uint32_t tickstart = 0U; - tmp_state = hsc->State; - if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX)) + if(hsc->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -530,40 +514,30 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p __HAL_LOCK(hsc); hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX; - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); hsc->RxXferSize = Size; hsc->RxXferCount = Size; + /* Check the remain data to be received */ - while(hsc->RxXferCount > 0) + while(hsc->RxXferCount > 0U) { - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK) + hsc->RxXferCount--; + if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF); - hsc->RxXferCount--; - } - - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; + tmp = (uint16_t*) pData; + *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF); + pData +=1U; } + /* At end of Rx process, restore hsc->RxState to Ready */ + hsc->RxState = HAL_SMARTCARD_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hsc); @@ -576,25 +550,22 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p } /** - * @brief Sends an amount of data in non-blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @brief Send an amount of data in non blocking mode + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { - uint32_t tmp_state = 0; - - tmp_state = hsc->State; - if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(hsc->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(hsc); @@ -603,24 +574,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ hsc->TxXferCount = Size; hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } + hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX; /* Process Unlocked */ __HAL_UNLOCK(hsc); + + /* Enable the SMARTCARD Parity Error Interrupt */ + SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE); - /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); /* Enable the SMARTCARD Transmit data register empty Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE); + SET_BIT(hsc->Instance->CR1, USART_CR1_TXEIE); return HAL_OK; } @@ -631,21 +597,19 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ } /** - * @brief Receives an amount of data in non-blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received + * @brief Receive an amount of data in non blocking mode + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { - uint32_t tmp_state = 0; - - tmp_state = hsc->State; - if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(hsc->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -658,27 +622,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t hsc->RxXferCount = Size; hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - + hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + /* Process Unlocked */ __HAL_UNLOCK(hsc); - /* Enable the SMARTCARD Data Register not empty Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE); - - /* Enable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE); + /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */ + SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE| USART_CR1_RXNEIE); /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR); + SET_BIT(hsc->Instance->CR3, USART_CR3_EIE); return HAL_OK; } @@ -689,22 +642,21 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t } /** - * @brief Sends an amount of data in non-blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be sent + * @brief Send an amount of data in non blocking mode + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { - uint32_t *tmp = 0; - uint32_t tmp_state = 0; + uint32_t *tmp; - tmp_state = hsc->State; - if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(hsc->gState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -717,15 +669,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 hsc->TxXferCount = Size; hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } + hsc->gState = HAL_SMARTCARD_STATE_BUSY_TX; /* Set the SMARTCARD DMA transfer complete callback */ hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; @@ -733,20 +677,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 /* Set the DMA error callback */ hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError; - /* Enable the SMARTCARD transmit DMA channel */ + /* Set the DMA abort callback */ + hsc->hdmatx->XferAbortCallback = NULL; + + /* Enable the SMARTCARD transmit DMA Channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size); - /* Clear the TC flag in the SR register by writing 0 to it */ + /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the SMARTCARD CR3 register */ - SET_BIT(hsc->Instance->CR3,USART_CR3_DMAT); - /* Process Unlocked */ __HAL_UNLOCK(hsc); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the SMARTCARD CR3 register */ + SET_BIT(hsc->Instance->CR3, USART_CR3_DMAT); + return HAL_OK; } else @@ -756,23 +703,22 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 } /** - * @brief Receive an amount of data in non-blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit. + * @brief Receive an amount of data in non blocking mode + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be received + * @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) { - uint32_t *tmp = 0; - uint32_t tmp_state = 0; + uint32_t *tmp; - tmp_state = hsc->State; - if((tmp_state == HAL_SMARTCARD_STATE_READY) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(hsc->RxState == HAL_SMARTCARD_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -784,15 +730,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_ hsc->RxXferSize = Size; hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } + hsc->RxState = HAL_SMARTCARD_STATE_BUSY_RX; /* Set the SMARTCARD DMA transfer complete callback */ hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; @@ -800,17 +738,29 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_ /* Set the DMA error callback */ hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError; - /* Enable the DMA channel */ + /* Set the DMA abort callback */ + hsc->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA Channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the SMARTCARD CR3 register */ - SET_BIT(hsc->Instance->CR3,USART_CR3_DMAR); + /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ + __HAL_SMARTCARD_CLEAR_OREFLAG(hsc); /* Process Unlocked */ __HAL_UNLOCK(hsc); + /* Enable the SMARTCARD Parity Error Interrupt */ + SET_BIT(hsc->Instance->CR1, USART_CR1_PEIE); + + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hsc->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the SMARTCARD CR3 register */ + SET_BIT(hsc->Instance->CR3, USART_CR3_DMAR); + return HAL_OK; } else @@ -820,342 +770,976 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_ } /** - * @brief This function handles SMARTCARD interrupt request. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) + * @brief Abort ongoing transfers (blocking mode). + * @param hsc SMARTCARD handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc) { - uint32_t tmp_flag = 0, tmp_it_source = 0; + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); - tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_PE); - tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE); - /* SMARTCARD parity error interrupt occurred -----------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + /* Disable the SMARTCARD DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT)) { - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE; - } + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT); - tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_FE); - tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR); - /* SMARTCARD frame error interrupt occurred ------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE; - } + /* Abort the SMARTCARD DMA Tx channel: use blocking DMA Abort API (no callback) */ + if(hsc->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsc->hdmatx->XferAbortCallback = NULL; - tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_NE); - /* SMARTCARD noise error interrupt occurred ------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE; + HAL_DMA_Abort(hsc->hdmatx); + } } - tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_ORE); - /* SMARTCARD Over-Run interrupt occurred ---------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; - } - - tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_RXNE); - tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE); - /* SMARTCARD in mode Receiver --------------------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + /* Disable the SMARTCARD DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) { - SMARTCARD_Receive_IT(hsc); - } + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); - tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TXE); - tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE); - /* SMARTCARD in mode Transmitter -----------------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - SMARTCARD_Transmit_IT(hsc); + /* Abort the SMARTCARD DMA Rx channel: use blocking DMA Abort API (no callback) */ + if(hsc->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsc->hdmarx->XferAbortCallback = NULL; + + HAL_DMA_Abort(hsc->hdmarx); + } } - - tmp_flag = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TC); - tmp_it_source = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC); - /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - SMARTCARD_EndTransmit_IT(hsc); - } - /* Call the Error call Back in case of Errors */ - if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE) - { - /* Clear all the error flag at once */ - __HAL_SMARTCARD_CLEAR_PEFLAG(hsc); + /* Reset Tx and Rx transfer counters */ + hsc->TxXferCount = 0x00U; + hsc->RxXferCount = 0x00U; - /* Set the SMARTCARD state ready to be able to start again the process */ - hsc->State= HAL_SMARTCARD_STATE_READY; - HAL_SMARTCARD_ErrorCallback(hsc); - } -} + /* Reset ErrorCode */ + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; -/** - * @brief Tx Transfer completed callback. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ - __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsc); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file - */ -} + /* Restore hsc->RxState and hsc->gState to Ready */ + hsc->RxState = HAL_SMARTCARD_STATE_READY; + hsc->gState = HAL_SMARTCARD_STATE_READY; -/** - * @brief Rx Transfer completed callback. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsc); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file - */ + return HAL_OK; } /** - * @brief SMARTCARD error callback. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ - __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc) + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param hsc SMARTCARD handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsc); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_ErrorCallback can be implemented in the user file - */ -} + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); -/** - * @} - */ + /* Disable the SMARTCARD DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT); -/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief SMARTCARD State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of SmartCard - communication process and also return Peripheral Errors occurred during communication process - (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state - of the SMARTCARD peripheral. - (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during - communication. + /* Abort the SMARTCARD DMA Tx channel: use blocking DMA Abort API (no callback) */ + if(hsc->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsc->hdmatx->XferAbortCallback = NULL; -@endverbatim - * @{ - */ + HAL_DMA_Abort(hsc->hdmatx); + } + } -/** - * @brief Returns the SMARTCARD state. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL state - */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) -{ - return hsc->State; + /* Reset Tx transfer counter */ + hsc->TxXferCount = 0x00U; + + /* Restore hsc->gState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; + + return HAL_OK; } /** - * @brief Return the SMARTCARD error code - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval SMARTCARD Error Code - */ -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc) + * @brief Abort ongoing Receive transfer (blocking mode). + * @param hsc SMARTCARD handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc) { - return hsc->ErrorCode; -} + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); -/** - * @} - */ - -/** - * @} - */ + /* Disable the SMARTCARD DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); -/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions - * @brief SMARTCARD Private functions - * @{ - */ -/** - * @brief DMA SMARTCARD transmit process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Abort the SMARTCARD DMA Rx channel: use blocking DMA Abort API (no callback) */ + if(hsc->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsc->hdmarx->XferAbortCallback = NULL; + + HAL_DMA_Abort(hsc->hdmarx); + } + } - hsc->TxXferCount = 0; + /* Reset Rx transfer counter */ + hsc->RxXferCount = 0x00U; - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the SMARTCARD CR3 register */ - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT); + /* Restore hsc->RxState to Ready */ + hsc->RxState = HAL_SMARTCARD_STATE_READY; - /* Enable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC); + return HAL_OK; } /** - * @brief DMA SMARTCARD receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief Abort ongoing transfers (Interrupt mode). + * @param hsc SMARTCARD handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc) +{ + uint32_t AbortCplt = 0x01U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if(hsc->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT)) + { + hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback; + } + else + { + hsc->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if(hsc->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) + { + hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback; + } + else + { + hsc->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the SMARTCARD DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at SMARTCARD level */ + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ + if(hsc->hdmatx != NULL) + { + /* SMARTCARD Tx DMA Abort callback has already been initialised : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK) + { + hsc->hdmatx->XferAbortCallback = NULL; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* Disable the SMARTCARD DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ + if(hsc->hdmarx != NULL) + { + /* SMARTCARD Rx DMA Abort callback has already been initialised : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK) + { + hsc->hdmarx->XferAbortCallback = NULL; + AbortCplt = 0x01U; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if(AbortCplt == 0x01U) + { + /* Reset Tx and Rx transfer counters */ + hsc->TxXferCount = 0x00U; + hsc->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Restore hsc->gState and hsc->RxState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; + hsc->RxState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SMARTCARD_AbortCpltCallback(hsc); + } + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param hsc SMARTCARD handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the SMARTCARD DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(hsc->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + hsc->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(hsc->hdmatx) != HAL_OK) + { + /* Call Directly hsc->hdmatx->XferAbortCallback function in case of error */ + hsc->hdmatx->XferAbortCallback(hsc->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + hsc->TxXferCount = 0x00U; + + /* Restore hsc->gState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SMARTCARD_AbortTransmitCpltCallback(hsc); + } + } + else + { + /* Reset Tx transfer counter */ + hsc->TxXferCount = 0x00U; + + /* Restore hsc->gState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SMARTCARD_AbortTransmitCpltCallback(hsc); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param hsc SMARTCARD handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); + + /* Disable the SMARTCARD DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(hsc->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + hsc->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK) + { + /* Call Directly hsc->hdmarx->XferAbortCallback function in case of error */ + hsc->hdmarx->XferAbortCallback(hsc->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + hsc->RxXferCount = 0x00U; + + /* Restore hsc->RxState to Ready */ + hsc->RxState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SMARTCARD_AbortReceiveCpltCallback(hsc); + } + } + else + { + /* Reset Rx transfer counter */ + hsc->RxXferCount = 0x00U; + + /* Restore hsc->RxState to Ready */ + hsc->RxState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SMARTCARD_AbortReceiveCpltCallback(hsc); + } + + return HAL_OK; +} + +/** + * @brief This function handles SMARTCARD interrupt request. + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval None */ -static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) { - SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + uint32_t isrflags = READ_REG(hsc->Instance->SR); + uint32_t cr1its = READ_REG(hsc->Instance->CR1); + uint32_t cr3its = READ_REG(hsc->Instance->CR3); + uint32_t dmarequest = 0x00U; + uint32_t errorflags = 0x00U; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); + if(errorflags == RESET) + { + /* SMARTCARD in mode Receiver -------------------------------------------------*/ + if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + SMARTCARD_Receive_IT(hsc); + return; + } + } - hsc->RxXferCount = 0; + /* If some errors occur */ + if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + { + /* SMARTCARD parity error interrupt occurred ---------------------------*/ + if(((isrflags & SMARTCARD_FLAG_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE; + } - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); + /* SMARTCARD noise error interrupt occurred ----------------------------*/ + if(((isrflags & SMARTCARD_FLAG_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE; + } + + /* SMARTCARD frame error interrupt occurred ----------------------------*/ + if(((isrflags & SMARTCARD_FLAG_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE; + } - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) + /* SMARTCARD Over-Run interrupt occurred -------------------------------*/ + if(((isrflags & SMARTCARD_FLAG_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; + } + + /* Call SMARTCARD Error Call back function if need be ------------------*/ + if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE) + { + /* SMARTCARD in mode Receiver ----------------------------------------*/ + if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + SMARTCARD_Receive_IT(hsc); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR); + if(((hsc->ErrorCode & HAL_SMARTCARD_ERROR_ORE) != RESET) || dmarequest) + { + /* Blocking error : transfer is aborted + Set the SMARTCARD state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + SMARTCARD_EndRxTransfer(hsc); + + /* Disable the SMARTCARD DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel */ + if(hsc->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + hsc->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError; + if(HAL_DMA_Abort_IT(hsc->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hsc->hdmarx->XferAbortCallback(hsc->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_SMARTCARD_ErrorCallback(hsc); + } + } + else + { + /* Call user error callback */ + HAL_SMARTCARD_ErrorCallback(hsc); + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ + HAL_SMARTCARD_ErrorCallback(hsc); + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + } + } + return; + } /* End if some error occurs */ + + /* SMARTCARD in mode Transmitter -------------------------------------------*/ + if(((isrflags & SMARTCARD_FLAG_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; + SMARTCARD_Transmit_IT(hsc); + return; } - else + + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ + if(((isrflags & SMARTCARD_FLAG_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { - hsc->State = HAL_SMARTCARD_STATE_READY; + SMARTCARD_EndTransmit_IT(hsc); + return; } +} + +/** + * @brief Tx Transfer completed callbacks + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SMARTCARD_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SMARTCARD_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief SMARTCARD error callbacks + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SMARTCARD_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief SMARTCARD Abort Complete callback. + * @param hsc SMARTCARD handle. + * @retval None + */ +__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD Abort Transmit Complete callback. + * @param hsc SMARTCARD handle. + * @retval None + */ +__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD Abort ReceiveComplete callback. + * @param hsc SMARTCARD handle. + * @retval None + */ +__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file. + */ +} +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SMARTCARD State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SmartCard. + (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state of the SmartCard peripheral. + (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during communication. +@endverbatim + * @{ + */ + +/** + * @brief return the SMARTCARD state + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. + * @retval HAL state + */ +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) +{ + uint32_t temp1= 0x00U, temp2 = 0x00U; + temp1 = hsc->gState; + temp2 = hsc->RxState; + + return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the SMARTCARD error code + * @param hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD. + * @retval SMARTCARD Error Code + */ +uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc) +{ + return hsc->ErrorCode; +} + +/** + * @} + */ + +/** + * @brief DMA SMARTCARD transmit process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hsc->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE); +} + +/** + * @brief DMA SMARTCARD receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hsc->RxXferCount = 0U; + + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore hsc->RxState to Ready */ + hsc->RxState = HAL_SMARTCARD_STATE_READY; + HAL_SMARTCARD_RxCpltCallback(hsc); } /** - * @brief DMA SMARTCARD communication error callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief DMA SMARTCARD communication error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) { + uint32_t dmarequest = 0x00U; SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hsc->RxXferCount = 0U; + hsc->TxXferCount = 0U; + hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - hsc->RxXferCount = 0; - hsc->TxXferCount = 0; - hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - hsc->State= HAL_SMARTCARD_STATE_READY; - + /* Stop SMARTCARD DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAT); + if((hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) && dmarequest) + { + SMARTCARD_EndTxTransfer(hsc); + } + + /* Stop SMARTCARD DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(hsc->Instance->CR3, USART_CR3_DMAR); + if((hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) && dmarequest) + { + SMARTCARD_EndRxTransfer(hsc); + } + HAL_SMARTCARD_ErrorCallback(hsc); } /** * @brief This function handles SMARTCARD Communication Timeout. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @param hsc: SMARTCARD handle * @param Flag: specifies the SMARTCARD flag to check. * @param Status: The new Flag status (SET or RESET). * @param Timeout: Timeout duration + * @param Tickstart: tick start value * @retval HAL status */ -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait until flag is set */ - if(Status == RESET) + while((__HAL_SMARTCARD_GET_FLAG(hsc, Flag) ? SET : RESET) == Status) { - while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE and RXNE interrupts for the interrupt process */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); - - hsc->State= HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_TIMEOUT; - } + /* Disable TXE and RXNE interrupts for the interrupt process */ + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE); + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE); + + hsc->gState= HAL_SMARTCARD_STATE_READY; + hsc->RxState= HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsc); + + return HAL_TIMEOUT; } } } - else + return HAL_OK; +} + +/** + * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). + * @param hsc: SMARTCARD handle. + * @retval None + */ +static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc) +{ + /* At end of Tx process, restore hsc->gState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; + + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); +} + + +/** + * @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion). + * @param hsc: SMARTCARD handle. + * @retval None + */ +static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc) +{ + /* At end of Rx process, restore hsc->RxState to Ready */ + hsc->RxState = HAL_SMARTCARD_STATE_READY; + + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); +} + + + +/** + * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsc = (SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hsc->RxXferCount = 0x00U; + hsc->TxXferCount = 0x00U; + + HAL_SMARTCARD_ErrorCallback(hsc); +} + +/** + * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hsc->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(hsc->hdmarx != NULL) { - while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET) + if(hsc->hdmarx->XferAbortCallback != NULL) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE and RXNE interrupts for the interrupt process */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hsc->TxXferCount = 0x00U; + hsc->RxXferCount = 0x00U; - hsc->State= HAL_SMARTCARD_STATE_READY; + /* Reset ErrorCode */ + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hsc); - - return HAL_TIMEOUT; - } - } + /* Restore hsc->gState and hsc->RxState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; + hsc->RxState = HAL_SMARTCARD_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SMARTCARD_AbortCpltCallback(hsc); +} + +/** + * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hsc->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(hsc->hdmatx != NULL) + { + if(hsc->hdmatx->XferAbortCallback != NULL) + { + return; } } - return HAL_OK; + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hsc->TxXferCount = 0x00U; + hsc->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Restore hsc->gState and hsc->RxState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; + hsc->RxState = HAL_SMARTCARD_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SMARTCARD_AbortCpltCallback(hsc); } /** - * @brief Send an amount of data in non-blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * Function called under interruption only, once - * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() + * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to + * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hsc->TxXferCount = 0x00U; + + /* Restore hsc->gState to Ready */ + hsc->gState = HAL_SMARTCARD_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SMARTCARD_AbortTransmitCpltCallback(hsc); +} + +/** + * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to + * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hsc->RxXferCount = 0x00U; + + /* Restore hsc->RxState to Ready */ + hsc->RxState = HAL_SMARTCARD_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SMARTCARD_AbortReceiveCpltCallback(hsc); +} + +/** + * @brief Send an amount of data in non blocking mode + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval HAL status */ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) { - uint32_t tmp_state = 0; - - tmp_state = hsc->State; - if((tmp_state == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + uint16_t* tmp; + + /* Check that a Tx process is ongoing */ + if(hsc->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - WRITE_REG(hsc->Instance->DR, (*hsc->pTxBuffPtr++ & (uint8_t)0xFF)); + tmp = (uint16_t*) hsc->pTxBuffPtr; + hsc->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); + hsc->pTxBuffPtr += 1U; - if(--hsc->TxXferCount == 0) + if(--hsc->TxXferCount == 0U) { - /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE); + /* Disable the SMARTCARD Transmit data register empty Interrupt */ + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_TXEIE); - /* Enable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC); + /* Enable the SMARTCARD Transmit Complete Interrupt */ + SET_BIT(hsc->Instance->CR1, USART_CR1_TCIE); } - + return HAL_OK; } else @@ -1164,7 +1748,6 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) } } - /** * @brief Wraps up transmission in non blocking mode. * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains @@ -1173,62 +1756,49 @@ static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc) */ static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Disable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC); - - /* Check if a receive process is ongoing or not */ - if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else - { - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR); - - hsmartcard->State = HAL_SMARTCARD_STATE_READY; - } + /* Disable the SMARTCARD Transmit Complete Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TCIE); + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Tx process is ended, restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + HAL_SMARTCARD_TxCpltCallback(hsmartcard); return HAL_OK; } - /** - * @brief Receive an amount of data in non-blocking mode. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Receive an amount of data in non blocking mode + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval HAL status */ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) { - uint32_t tmp_state = 0; - - tmp_state = hsc->State; - if((tmp_state == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp_state == HAL_SMARTCARD_STATE_BUSY_TX_RX)) + uint16_t* tmp; + + /* Check that a Rx process is ongoing */ + if(hsc->RxState == HAL_SMARTCARD_STATE_BUSY_RX) { - *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF); + tmp = (uint16_t*) hsc->pRxBuffPtr; + *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF); + hsc->pRxBuffPtr += 1U; - if(--hsc->RxXferCount == 0) + if(--hsc->RxXferCount == 0U) { - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE); + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_RXNEIE); /* Disable the SMARTCARD Parity Error Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE); - + CLEAR_BIT(hsc->Instance->CR1, USART_CR1_PEIE); + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR); + CLEAR_BIT(hsc->Instance->CR3, USART_CR3_EIE); - /* Check if a non-blocking transmit process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_TX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } + /* Rx process is completed, restore hsc->RxState to Ready */ + hsc->RxState = HAL_SMARTCARD_STATE_READY; HAL_SMARTCARD_RxCpltCallback(hsc); @@ -1238,19 +1808,22 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc) } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Configures the SMARTCARD peripheral. - * @param hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. + * @brief Configure the SMARTCARD peripheral + * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for SMARTCARD module. * @retval None */ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) { + uint32_t tmpreg = 0x00U; + /* Check the parameters */ + assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity)); assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase)); assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit)); @@ -1261,38 +1834,58 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode)); assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState)); + /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */ - CLEAR_BIT(hsc->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE)); + CLEAR_BIT(hsc->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - /*------ SMARTCARD-associated USART registers setting : CR2 Configuration ------*/ + /*---------------------------- USART CR2 Configuration ---------------------*/ + tmpreg = hsc->Instance->CR2; /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL)); /* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/ /* Set CPOL bit according to hsc->Init.CLKPolarity value */ /* Set CPHA bit according to hsc->Init.CLKPhase value */ /* Set LBCL bit according to hsc->Init.CLKLastBit value */ - MODIFY_REG(hsc->Instance->CR2, - ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL)), - ((uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity | hsc->Init.CLKPhase| hsc->Init.CLKLastBit)) ); + /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */ + tmpreg |= (uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity | + hsc->Init.CLKPhase| hsc->Init.CLKLastBit | hsc->Init.StopBits); + /* Write to USART CR2 */ + WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg); + tmpreg = hsc->Instance->CR2; + + /* Clear STOP[13:12] bits */ + tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); + /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */ - MODIFY_REG(hsc->Instance->CR2, USART_CR2_STOP,(uint32_t)(hsc->Init.StopBits)); + tmpreg |= (uint32_t)(hsc->Init.StopBits); + + /* Write to USART CR2 */ + WRITE_REG(hsc->Instance->CR2, (uint32_t)tmpreg); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = hsc->Instance->CR1; - /*------ SMARTCARD-associated USART registers setting : CR1 Configuration ------*/ /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE)); + /* Configure the SMARTCARD Word Length, Parity and mode: - Set the M according to hsc->Init.WordLength value (forced to 1 as 9B data frame should be selected) - Set PCE and PS bits according to hsc->Init.Parity value (PCE bit forced to 1 as parity control should always be enabled) + Set the M bits according to hsc->Init.WordLength value + Set PCE and PS bits according to hsc->Init.Parity value Set TE and RE bits according to hsc->Init.Mode value */ - MODIFY_REG(hsc->Instance->CR1, - ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)), - ((uint32_t)(USART_CR1_M | USART_CR1_PCE | hsc->Init.Parity | hsc->Init.Mode)) ); + tmpreg |= (uint32_t)hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode; + + /* Write to USART CR1 */ + WRITE_REG(hsc->Instance->CR1, (uint32_t)tmpreg); - /*------ SMARTCARD-associated USART registers setting : CR3 Configuration ------*/ + /*-------------------------- USART CR3 Configuration -----------------------*/ /* Clear CTSE and RTSE bits */ CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE)); - /*------ SMARTCARD-associated USART registers setting : BRR Configuration ------*/ + /*-------------------------- USART BRR Configuration -----------------------*/ + if(hsc->Instance == USART1) { hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate); diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.h index d139575ddcd..0e6a1dde19d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_hal_smartcard.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -57,10 +57,9 @@ /* Exported types ------------------------------------------------------------*/ /** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types * @{ - */ - + */ -/** +/** * @brief SMARTCARD Init Structure definition */ typedef struct @@ -108,21 +107,65 @@ typedef struct }SMARTCARD_InitTypeDef; /** - * @brief HAL State structures definition + * @brief HAL SMARTCARD State structures definition + * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState. + * - gState contains SMARTCARD state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. */ typedef enum { - HAL_SMARTCARD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */ - HAL_SMARTCARD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_SMARTCARD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_SMARTCARD_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_SMARTCARD_STATE_ERROR = 0x04 /*!< Error */ + HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ }HAL_SMARTCARD_StateTypeDef; - /** * @brief SMARTCARD handle Structure definition */ @@ -136,13 +179,13 @@ typedef struct uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ - uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ - uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ @@ -150,9 +193,14 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SMARTCARD_StateTypeDef State; /*!< SmartCard communication state */ + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + + __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. + This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ - __IO uint32_t ErrorCode; /*!< SmartCard Error code */ + __IO uint32_t ErrorCode; /*!< SmartCard Error code */ }SMARTCARD_HandleTypeDef; /** @@ -164,26 +212,23 @@ typedef struct * @{ */ -/** @defgroup SMARTCARD_Error_Codes SMARTCARD Error Codes +/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code * @{ */ -#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ -#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ -#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04) /*!< frame error */ -#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ -#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ - +#define HAL_SMARTCARD_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE 0x00000001U /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE 0x00000002U /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE 0x00000004U /*!< Frame error */ +#define HAL_SMARTCARD_ERROR_ORE 0x00000008U /*!< OverRun error */ +#define HAL_SMARTCARD_ERROR_DMA 0x00000010U /*!< DMA transfer error */ /** * @} */ - /** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length * @{ */ #define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M) - /** * @} */ @@ -219,16 +264,16 @@ typedef struct /** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity * @{ */ -#define SMARTCARD_POLARITY_LOW ((uint32_t)0x00000000) +#define SMARTCARD_POLARITY_LOW 0x00000000U #define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /** * @} */ -/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase +/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase * @{ */ -#define SMARTCARD_PHASE_1EDGE ((uint32_t)0x00000000) +#define SMARTCARD_PHASE_1EDGE 0x00000000U #define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /** * @} @@ -237,78 +282,73 @@ typedef struct /** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit * @{ */ -#define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_LASTBIT_DISABLE 0x00000000U #define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /** * @} */ -/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State +/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State * @{ */ -#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) -#define SMARTCARD_NACK_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) +#define SMARTCARD_NACK_DISABLE 0x00000000U /** * @} */ -/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests +/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests * @{ */ - -#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT) -#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR) - +#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT) +#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR) /** * @} */ -/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler +/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler * @{ */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV2 ((uint32_t)0x00000001) /*!< SYSCLK divided by 2 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV4 ((uint32_t)0x00000002) /*!< SYSCLK divided by 4 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV6 ((uint32_t)0x00000003) /*!< SYSCLK divided by 6 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV8 ((uint32_t)0x00000004) /*!< SYSCLK divided by 8 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV10 ((uint32_t)0x00000005) /*!< SYSCLK divided by 10 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV12 ((uint32_t)0x00000006) /*!< SYSCLK divided by 12 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV14 ((uint32_t)0x00000007) /*!< SYSCLK divided by 14 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV16 ((uint32_t)0x00000008) /*!< SYSCLK divided by 16 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV18 ((uint32_t)0x00000009) /*!< SYSCLK divided by 18 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV20 ((uint32_t)0x0000000A) /*!< SYSCLK divided by 20 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV22 ((uint32_t)0x0000000B) /*!< SYSCLK divided by 22 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV24 ((uint32_t)0x0000000C) /*!< SYSCLK divided by 24 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV26 ((uint32_t)0x0000000D) /*!< SYSCLK divided by 26 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV28 ((uint32_t)0x0000000E) /*!< SYSCLK divided by 28 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV30 ((uint32_t)0x0000000F) /*!< SYSCLK divided by 30 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV32 ((uint32_t)0x00000010) /*!< SYSCLK divided by 32 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV34 ((uint32_t)0x00000011) /*!< SYSCLK divided by 34 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV36 ((uint32_t)0x00000012) /*!< SYSCLK divided by 36 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV38 ((uint32_t)0x00000013) /*!< SYSCLK divided by 38 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV40 ((uint32_t)0x00000014) /*!< SYSCLK divided by 40 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV42 ((uint32_t)0x00000015) /*!< SYSCLK divided by 42 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV44 ((uint32_t)0x00000016) /*!< SYSCLK divided by 44 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV46 ((uint32_t)0x00000017) /*!< SYSCLK divided by 46 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV48 ((uint32_t)0x00000018) /*!< SYSCLK divided by 48 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV50 ((uint32_t)0x00000019) /*!< SYSCLK divided by 50 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV52 ((uint32_t)0x0000001A) /*!< SYSCLK divided by 52 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV54 ((uint32_t)0x0000001B) /*!< SYSCLK divided by 54 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV56 ((uint32_t)0x0000001C) /*!< SYSCLK divided by 56 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV58 ((uint32_t)0x0000001D) /*!< SYSCLK divided by 58 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV60 ((uint32_t)0x0000001E) /*!< SYSCLK divided by 60 */ -#define SMARTCARD_PRESCALER_SYSCLK_DIV62 ((uint32_t)0x0000001F) /*!< SYSCLK divided by 62 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U /*!< SYSCLK divided by 2 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U /*!< SYSCLK divided by 4 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U /*!< SYSCLK divided by 6 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U /*!< SYSCLK divided by 8 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U /*!< SYSCLK divided by 10 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U /*!< SYSCLK divided by 12 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U /*!< SYSCLK divided by 14 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U /*!< SYSCLK divided by 16 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U /*!< SYSCLK divided by 18 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU /*!< SYSCLK divided by 20 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU /*!< SYSCLK divided by 22 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU /*!< SYSCLK divided by 24 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU /*!< SYSCLK divided by 26 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU /*!< SYSCLK divided by 28 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU /*!< SYSCLK divided by 30 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U /*!< SYSCLK divided by 32 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U /*!< SYSCLK divided by 34 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U /*!< SYSCLK divided by 36 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U /*!< SYSCLK divided by 38 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U /*!< SYSCLK divided by 40 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U /*!< SYSCLK divided by 42 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U /*!< SYSCLK divided by 44 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U /*!< SYSCLK divided by 46 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U /*!< SYSCLK divided by 48 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U /*!< SYSCLK divided by 50 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU /*!< SYSCLK divided by 52 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU /*!< SYSCLK divided by 54 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU /*!< SYSCLK divided by 56 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU /*!< SYSCLK divided by 58 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU /*!< SYSCLK divided by 60 */ +#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU /*!< SYSCLK divided by 62 */ /** * @} */ - - -/** @defgroup SMARTCARD_Flags SMARTCARD Flags +/** @defgroup SmartCard_Flags SMARTCARD Flags * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the SR register * @{ */ - #define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE) #define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC) #define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE) @@ -321,24 +361,20 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupts Definition +/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask (16 bits) in the Y register - * - Y : Interrupt source register (4 bits) - * - 0001: CR1 register - * - 0010: CR3 register - - * + * - XXXX : Interrupt mask in the XX register + * - Y : Interrupt source register (2bits) + * - 01: CR1 register + * - 11: CR3 register * @{ */ - -#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_PEIE)) -#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TXEIE)) -#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_TCIE)) -#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE)) -#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE)) -#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28 | USART_CR3_EIE)) - +#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) +#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) +#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) +#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) +#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) +#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE)) /** * @} */ @@ -347,27 +383,26 @@ typedef struct * @} */ - /* Exported macro ------------------------------------------------------------*/ -/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros +/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros * @{ */ - -/** @brief Reset SMARTCARD handle state +/** @brief Reset SMARTCARD handle gstate & RxState * @param __HANDLE__: specifies the SMARTCARD Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ -#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET) +#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + } while(0U) /** @brief Flush the Smartcard DR register * @param __HANDLE__: specifies the SMARTCARD Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) - + /** @brief Check whether the specified Smartcard flag is set or not. * @param __HANDLE__: specifies the SMARTCARD Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). @@ -392,7 +427,6 @@ typedef struct * This parameter can be any combination of the following values: * @arg SMARTCARD_FLAG_TC: Transmission Complete flag. * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag. - * @retval None * * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun * error) flags are cleared by software sequence: a read operation to @@ -401,51 +435,42 @@ typedef struct * @note TC flag can be also cleared by software sequence: a read operation to * USART_SR register followed by a write operation to USART_DR register. * @note TXE flag is cleared only by a write to the USART_DR register. - * - * @retval None */ #define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** @brief Clear the SMARTCARD PE pending flag. * @param __HANDLE__: specifies the USART Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ -#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \ -do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - tmpreg = (__HANDLE__)->Instance->DR; \ - UNUSED(tmpreg); \ -}while(0) - - +#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ + } while(0U) /** @brief Clear the SMARTCARD FE pending flag. * @param __HANDLE__: specifies the USART Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the SMARTCARD NE pending flag. * @param __HANDLE__: specifies the USART Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the SMARTCARD ORE pending flag. * @param __HANDLE__: specifies the USART Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the SMARTCARD IDLE pending flag. * @param __HANDLE__: specifies the USART Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) @@ -459,13 +484,12 @@ do{ \ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt * @arg SMARTCARD_IT_PE: Parity Error interrupt - * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None + * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overRun error) */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK))) +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK))) -/** @brief Disable the specified SmartCard interrupts. +/** @brief Disable the specified SmartCard interrupt. * @param __HANDLE__: specifies the SMARTCARD Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable. @@ -475,14 +499,13 @@ do{ \ * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt * @arg SMARTCARD_IT_PE: Parity Error interrupt - * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overRun error) */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK))) +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK))) -/** @brief Check whether the specified SmartCard interrupt has occurred or not. - * @param __HANDLE__: specifies the SMARTCARD Handle. - * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). +/** @brief Checks whether the specified SmartCard interrupt has occurred or not. + * @param __HANDLE__: specifies the SmartCard Handle. * @param __IT__: specifies the SMARTCARD interrupt source to check. * This parameter can be one of the following values: * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt @@ -493,135 +516,62 @@ do{ \ * @arg SMARTCARD_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK)) +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK)) /** @brief Enable the USART associated to the SMARTCARD Handle * @param __HANDLE__: specifies the SMARTCARD Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None - */ -#define __HAL_SMARTCARD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) + */ +#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable the USART associated to the SMARTCARD Handle * @param __HANDLE__: specifies the SMARTCARD Handle. * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None - */ -#define __HAL_SMARTCARD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE)) + */ +#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) -/** @brief Enable the SmartCard DMA request. +/** @brief Macros to enable the SmartCard DMA request. * @param __HANDLE__: specifies the SmartCard Handle. - * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __REQUEST__: specifies the SmartCard DMA request. - * This parameter can be one of the following values: + * This parameter can be one of the following values: * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request - * @retval None */ -#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) (SET_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__))) +#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__)) -/** @brief Disable the SmartCard DMA request. +/** @brief Macros to disable the SmartCard DMA request. * @param __HANDLE__: specifies the SmartCard Handle. - * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __REQUEST__: specifies the SmartCard DMA request. - * This parameter can be one of the following values: + * This parameter can be one of the following values: * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request - * @retval None */ -#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) (CLEAR_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__))) - +#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__)) /** * @} */ - - -/* Private macros --------------------------------------------------------*/ -/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros - * @{ - */ - -#define SMARTCARD_CR1_REG_INDEX 1 -#define SMARTCARD_CR3_REG_INDEX 3 - -#define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) -#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100) -#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) -/* UART BRR = mantissa + overflow + fraction - = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */ -#define SMARTCARD_BRR(_PCLK_, _BAUD_) (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4) + \ - (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0)) + \ - (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F)) - -/** Check the Baud rate range. - * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz) - * divided by the smallest oversampling used on the USART (i.e. 16) - * __BAUDRATE__: Baud rate set by the configuration function. - * Return : TRUE or FALSE - */ -#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001) - -#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B) - -#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \ - ((STOPBITS) == SMARTCARD_STOPBITS_1_5)) - -#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \ - ((PARITY) == SMARTCARD_PARITY_ODD)) - -#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (~((uint32_t)SMARTCARD_MODE_TX_RX))) == 0x00) && \ - ((MODE) != (uint32_t)0x00000000)) - -#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH)) - -#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE)) - -#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \ - ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE)) - -#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \ - ((NACK) == SMARTCARD_NACK_DISABLE)) - -#define IS_SMARTCARD_PRESCALER(PRESCALER) (((PRESCALER) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \ - ((PRESCALER) <= SMARTCARD_PRESCALER_SYSCLK_DIV62) ) - -/** SMARTCARD interruptions flag mask - * - */ -#define SMARTCARD_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ - USART_CR1_IDLEIE | USART_CR3_EIE ) - - -/** - * @} - */ - - /* Exported functions --------------------------------------------------------*/ - -/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions +/** @addtogroup SMARTCARD_Exported_Functions * @{ */ - -/** @addtogroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup SMARTCARD_Exported_Functions_Group1 * @{ */ - /* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc); +HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc); HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc); void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc); void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc); - /** * @} */ -/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions +/** @addtogroup SMARTCARD_Exported_Functions_Group2 * @{ */ - /* IO operation functions *******************************************************/ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); @@ -629,27 +579,91 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc); +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc); +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc); +HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc); +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc); +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc); + void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc); void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc); void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc); void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc); +void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc); +void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc); +void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc); +/** + * @} + */ +/** @addtogroup SMARTCARD_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc); +uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); /** * @} */ -/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants * @{ */ -/* Peripheral State and Errors functions functions *****************************/ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc); -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); +/** @brief SMARTCARD interruptions flag mask + * + */ +#define SMARTCARD_IT_MASK 0x0000FFFFU + +#define SMARTCARD_CR1_REG_INDEX 1U +#define SMARTCARD_CR3_REG_INDEX 3U +/** + * @} + */ +/* Private macros --------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros + * @{ + */ +#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B) +#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \ + ((STOPBITS) == SMARTCARD_STOPBITS_1_5)) +#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \ + ((PARITY) == SMARTCARD_PARITY_ODD)) +#define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U)) +#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH)) +#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE)) +#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \ + ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE)) +#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \ + ((NACK) == SMARTCARD_NACK_DISABLE)) +#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U) + +#define SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_))) +#define SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U) +#define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U) +/* SMARTCARD BRR = mantissa + overflow + fraction + = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */ +#define SMARTCARD_BRR(_PCLK_, _BAUD_) (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \ + (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \ + (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU)) /** * @} */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions + * @{ + */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.c index 6e8607150a1..798545eee1c 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.c @@ -2,16 +2,16 @@ ****************************************************************************** * @file stm32f1xx_hal_spi.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief SPI HAL module driver. - * - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions + * @verbatim ============================================================================== ##### How to use this driver ##### @@ -20,12 +20,12 @@ The SPI HAL driver can be used as follows: (#) Declare a SPI_HandleTypeDef handle structure, for example: - SPI_HandleTypeDef hspi; + SPI_HandleTypeDef hspi; - (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: - (##) Enable the SPIx interface clock + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock (##) SPI pins configuration - (+++) Enable the clock for the SPI GPIOs + (+++) Enable the clock for the SPI GPIOs (+++) Configure these SPI pins as alternate function push-pull (##) NVIC configuration if you need to use interrupt process (+++) Configure the SPIx interrupt priority @@ -38,117 +38,119 @@ (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel - (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_SPI_MspInit() API. + by calling the customized HAL_SPI_MspInit() API. [..] Circular mode restriction: (#) The DMA circular mode cannot be used when the SPI is configured in these modes: (##) Master 2Lines RxOnly (##) Master 1Line Rx (#) The CRC feature is not managed when the DMA circular mode is enabled - (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + [..] + Master Receive mode restriction: + (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=0) or + bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI + does not initiate a new transfer the following procedure has to be respected: + (##) HAL_SPI_DeInit() + (##) HAL_SPI_Init() @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -/* Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, - the following table resume the max SPI frequency reached with data size 8bits/16bits, + the following tables resume the max SPI frequency reached with data size 8bits/16bits, according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : - - For 8 bits SPI data size transfers : + + DataSize = SPI_DATASIZE_8BIT: +--------------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | Process | Tranfert mode |-----------------------|-----------------------|-----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==================================================================================================| - | T | Polling | fPCLK/8 | fPCLK/8 | NA | NA | NA | NA | + | T | Polling | fPCLK/2 | fPCLK/16 | NA | NA | NA | NA | | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| - | / | Interrupt | fPCLK/32 | fPCLK/32 | NA | NA | NA | NA | + | / | Interrupt | fPCLK/8 | fPCLK/32 | NA | NA | NA | NA | | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | |=========|================|===========|===========|===========|===========|===========|===========| - | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/8 | + | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/8 | fPCLK/16 | fPCLK/64 | fPCLK/2 | | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| - | R | Interrupt | fPCLK/32 | fPCLK/16 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/16 | + | R | Interrupt | fPCLK/8 | fPCLK/16 | fPCLK/32 | fPCLK/16 | fPCLK/64 | fPCLK/4 | | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| - | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/16 | fPCLK/128 | fPCLK/2 | + | | DMA | fPCLK/2 | fPCLK/16 | fPCLK/8 | fPCLK/16 | fPCLK/64 | fPCLK/2 | |=========|================|===========|===========|===========|===========|===========|===========| - | | Polling | fPCLK/4 | fPCLK/4 | NA | NA | fPCLK/4 | fPCLK/64 | + | | Polling | fPCLK/2 | fPCLK/2 | NA | NA | fPCLK/2 | fPCLK/32 | | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| - | T | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | fPCLK/8 | fPCLK/128 | + | T | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | fPCLK/2 | fPCLK/64 | | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| - | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 | + | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 | +--------------------------------------------------------------------------------------------------+ - For 16 bits SPI data size transfers : + DataSize = SPI_DATASIZE_16BIT: +--------------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | | Process | Tranfert mode |-----------------------|-----------------------|-----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==================================================================================================| - | T | Polling | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | + | T | Polling | fPCLK/4 | fPCLK/4 | NA | NA | NA | NA | | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| - | / | Interrupt | fPCLK/16 | fPCLK/16 | NA | NA | NA | NA | + | / | Interrupt | fPCLK/8 | fPCLK/16 | NA | NA | NA | NA | | R |----------------|-----------|-----------|-----------|-----------|-----------|-----------| | X | DMA | fPCLK/2 | fPCLK/4 | NA | NA | NA | NA | |=========|================|===========|===========|===========|===========|===========|===========| - | | Polling | fPCLK/2 | fPCLK/4 | fPCLK/64 | fPCLK/8 | fPCLK/64 | fPCLK/4 | + | | Polling | fPCLK/4 | fPCLK/8 | fPCLK/4 | fPCLK/8 | fPCLK/64 | fPCLK/2 | | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| - | R | Interrupt | fPCLK/16 | fPCLK/8 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/8 | + | R | Interrupt | fPCLK/8 | fPCLK/8 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/4 | | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| - | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/8 | fPCLK/128 | fPCLK/2 | + | | DMA | fPCLK/2 | fPCLK/2 | fPCLK/128 | fPCLK/16 | fPCLK/64 | fPCLK/2 | |=========|================|===========|===========|===========|===========|===========|===========| - | | Polling | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/64 | + | | Polling | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/4 | fPCLK/8 | | |----------------|-----------|-----------|-----------|-----------|-----------|-----------| - | T | Interrupt | fPCLK/4 | fPCLK/8 | NA | NA | fPCLK/4 | fPCLK/256 | + | T | Interrupt | fPCLK/4 | fPCLK/8 | NA | NA | fPCLK/4 | fPCLK/4 | | X |----------------|-----------|-----------|-----------|-----------|-----------|-----------| - | | DMA | fPCLK/2 | fPCLK/4 | NA | NA | fPCLK/2 | fPCLK/32 | + | | DMA | fPCLK/2 | fPCLK/2 | NA | NA | fPCLK/4 | fPCLK/8 | +--------------------------------------------------------------------------------------------------+ - - note: - The max SPI frequency depend on SPI data size (8bits, 16bits), - SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). - - note: - TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() - RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() - TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() - -*/ + [..] + (@) The max SPI frequency depend on SPI data size (8bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + (@) + (+@) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (+@) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (+@) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -156,35 +158,28 @@ /** @addtogroup STM32F1xx_HAL_Driver * @{ */ - /** @defgroup SPI SPI * @brief SPI HAL module driver * @{ */ - #ifdef HAL_SPI_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /** @defgroup SPI_Private_Constants SPI Private Constants * @{ */ -#define SPI_TIMEOUT_VALUE 10 +#define SPI_DEFAULT_TIMEOUT 100U /** * @} */ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup SPI_Private_Functions SPI Private Functions +/** @addtogroup SPI_Private_Functions * @{ */ -static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi); -static void SPI_TxISR(SPI_HandleTypeDef *hspi); -static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi); -static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi); -static void SPI_RxISR(SPI_HandleTypeDef *hspi); static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); @@ -192,34 +187,56 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +#if (USE_SPI_CRC != 0U) +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +#endif /* USE_SPI_CRC */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); +static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); /** * @} */ -/* Exported functions ---------------------------------------------------------*/ - +/* Exported functions --------------------------------------------------------*/ /** @defgroup SPI_Exported_Functions SPI Exported Functions * @{ */ -/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialiaze the SPIx peripheral: + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: - (+) User must implement HAL_SPI_MspInit() function in which he configures + (+) User must implement HAL_SPI_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - (+) Call the function HAL_SPI_Init() to configure the selected device with + (+) Call the function HAL_SPI_Init() to configure the selected device with the selected configuration: (++) Mode - (++) Direction + (++) Direction (++) Data Size (++) Clock Polarity and Phase (++) NSS Management @@ -229,18 +246,18 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin (++) CRC Calculation (++) CRC Polynomial if CRC enabled - (+) Call the function HAL_SPI_DeInit() to restore the default configuration - of the selected SPIx periperal. + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. @endverbatim * @{ */ /** - * @brief Initializes the SPI according to the specified parameters - * in the SPI_InitTypeDef and create the associated handle. + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) @@ -254,29 +271,36 @@ __weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /* Check the parameters */ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); assert_param(IS_SPI_MODE(hspi->Init.Mode)); - assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); - assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + +#if (USE_SPI_CRC != 0U) assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); - assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ if(hspi->State == HAL_SPI_STATE_RESET) { /* Allocate lock resource and initialize it */ hspi->Lock = HAL_UNLOCKED; - + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ HAL_SPI_MspInit(hspi); } - + hspi->State = HAL_SPI_STATE_BUSY; - /* Disble the selected SPI peripheral */ + /* Disable the selected SPI peripheral */ __HAL_SPI_DISABLE(hspi); /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ @@ -287,22 +311,32 @@ __weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); /* Configure : NSS management */ - WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode)); +#if (USE_SPI_CRC != 0U) /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ /* Configure : CRC Polynomial */ - WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->State = HAL_SPI_STATE_READY; - + hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } /** - * @brief DeInitializes the SPI peripheral + * @brief De Initialize the SPI peripheral. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) @@ -313,6 +347,9 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) return HAL_ERROR; } + /* Check SPI Instance parameter */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + hspi->State = HAL_SPI_STATE_BUSY; /* Disable the SPI Peripheral Clock */ @@ -331,33 +368,33 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) } /** - * @brief SPI MSP Init + * @brief Initialize the SPI MSP. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ - __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) - { +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_MspInit could be implenetd in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ } /** - * @brief SPI MSP DeInit + * @brief De-Initialize the SPI MSP. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. * @retval None */ - __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_MspDeInit could be implenetd in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file + */ } /** @@ -371,6 +408,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) ============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the SPI data transfers. @@ -382,11 +420,11 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) after finishing transfer. (++) No-Blocking mode: The communication is performed using Interrupts or DMA, These APIs return the HAL status. - The end of the data processing will be indicated through the - dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or Receive process + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) @@ -397,9 +435,9 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) */ /** - * @brief Transmit an amount of data in blocking mode + * @brief Transmit an amount of data in blocking mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @param Timeout: Timeout duration @@ -407,293 +445,345 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { + uint32_t tickstart = 0U; + HAL_StatusTypeDef errorcode = HAL_OK; - if(hspi->State == HAL_SPI_STATE_READY) - { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Check the parameters */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + /* Process Locked */ + __HAL_LOCK(hspi); - /* Process Locked */ - __HAL_LOCK(hspi); + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; + if(hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } - hspi->pTxBuffPtr = pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; + if((pData == NULL ) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } - /*Init field not used in handle to zero */ - hspi->TxISR = 0; - hspi->RxISR = 0; - hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - /* Configure communication direction : 1Line */ - SPI_1LINE_TX(hspi); - } + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + /* Transmit data in 16 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); + hspi->Instance->DR = *((uint16_t *)pData); + pData += sizeof(uint16_t); + hspi->TxXferCount--; } - - /* Transmit data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) { - if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) + /* Wait until TXE flag is set to send data */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; + hspi->Instance->DR = *((uint16_t *)pData); + pData += sizeof(uint16_t); + hspi->TxXferCount--; } - - while(hspi->TxXferCount > 0) + else { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; + /* Timeout management */ + if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + { + errorcode = HAL_TIMEOUT; + goto error; } - hspi->Instance->DR = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; - } - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } } - /* Transmit data in 16 Bit mode */ - else + } + /* Transmit data in 8 Bit mode */ + else + { + if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) + { + *((__IO uint8_t*)&hspi->Instance->DR) = (*pData); + pData += sizeof(uint8_t); + hspi->TxXferCount--; + } + while (hspi->TxXferCount > 0U) { - if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01)) + /* Wait until TXE flag is set to send data */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; + *((__IO uint8_t*)&hspi->Instance->DR) = (*pData); + pData += sizeof(uint8_t); hspi->TxXferCount--; } - - while(hspi->TxXferCount > 0) + else { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; + /* Timeout management */ + if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + { + errorcode = HAL_TIMEOUT; + goto error; } - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; - hspi->TxXferCount--; - } - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } } + } - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } - - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } - - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - - hspi->State = HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Wait until TXE flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK) + { + errorcode = HAL_TIMEOUT; + goto error; + } + + /* Check Busy flag */ + if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK) + { + errorcode = HAL_ERROR; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + goto error; + } - return HAL_OK; + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); } - else +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - return HAL_BUSY; + errorcode = HAL_ERROR; } + +error: + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Receive an amount of data in blocking mode + * @brief Receive an amount of data in blocking mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @param pData: pointer to data buffer - * @param Size: amount of data to be sent + * @param Size: amount of data to be received * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - __IO uint16_t tmpreg = 0; +#if (USE_SPI_CRC != 0U) + __IO uint16_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + uint32_t tickstart = 0U; + HAL_StatusTypeDef errorcode = HAL_OK; - if(hspi->State == HAL_SPI_STATE_READY) + if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { - if((pData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hspi); + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout); + } - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; + /* Process Locked */ + __HAL_LOCK(hspi); - hspi->pRxBuffPtr = pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; - hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; + if(hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } + if((pData == NULL ) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + /* this is done to handle the CRCNEXT before the latest data */ + hspi->RxXferCount--; + } +#endif /* USE_SPI_CRC */ - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); - } + /* Configure communication direction: 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } /* Receive data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + { + /* Transfer loop */ + while(hspi->RxXferCount > 0U) { - while(hspi->RxXferCount > 1) + /* Check the RXNE flag */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) { - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + /* read the received data */ + (* (uint8_t *)pData)= *(__IO uint8_t *)&hspi->Instance->DR; + pData += sizeof(uint8_t); hspi->RxXferCount--; } - /* Enable CRC Reception */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + else { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Timeout management */ + if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + { + errorcode = HAL_TIMEOUT; + goto error; + } } } - /* Receive data in 16 Bit mode */ - else + } + else + { + /* Transfer loop */ + while(hspi->RxXferCount > 0U) { - while(hspi->RxXferCount > 1) + /* Check the RXNE flag */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) { - /* Wait until RXNE flag is set to read data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; + *((uint16_t*)pData) = hspi->Instance->DR; + pData += sizeof(uint16_t); hspi->RxXferCount--; } - /* Enable CRC Reception */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + else { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Timeout management */ + if((Timeout == 0U) || ((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout))) + { + errorcode = HAL_TIMEOUT; + goto error; + } } } + } - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } +#if (USE_SPI_CRC != 0U) + /* Handle the CRC Transmission */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* freeze the CRC before the latest data */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - /* Receive last data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) + /* Read the latest data */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + /* the latest data has not been received */ + errorcode = HAL_TIMEOUT; + goto error; } + /* Receive last data in 16 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + *((uint16_t*)pData) = hspi->Instance->DR; + } + /* Receive last data in 8 Bit mode */ else { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; + (*(uint8_t *)pData) = *(__IO uint8_t *)&hspi->Instance->DR; } - hspi->RxXferCount--; - /* If CRC computation is enabled */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + /* Wait the CRC data */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { - /* Wait until RXNE flag is set: CRC Received */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - return HAL_TIMEOUT; - } - - /* Read CRC to clear RXNE flag */ - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); - } - - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; } - hspi->State = HAL_SPI_STATE_READY; + /* Read CRC to Flush DR and RXNE flag */ + tmpreg = hspi->Instance->DR; + /* To avoid GCC warning */ + UNUSED(tmpreg); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ - if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) - { + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { /* Check if CRC error is valid or not (workaround to be applied or not) */ if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) { @@ -701,838 +791,1126 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Reset CRC Calculation */ SPI_RESET_CRC(hspi); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_ERROR; } else { __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } } +#endif /* USE_SPI_CRC */ - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; - } - else + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - return HAL_BUSY; + errorcode = HAL_ERROR; } + +error : + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Transmit and Receive an amount of data in blocking mode + * @brief Transmit and Receive an amount of data in blocking mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer to be - * @param Size: amount of data to be sent + * @param pRxData: pointer to reception data buffer + * @param Size: amount of data to be sent and received * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - __IO uint16_t tmpreg = 0; + uint32_t tmp = 0U, tmp1 = 0U; +#if (USE_SPI_CRC != 0U) + __IO uint16_t tmpreg1 = 0U; +#endif /* USE_SPI_CRC */ + uint32_t tickstart = 0U; + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX)) - { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + /* Process Locked */ + __HAL_LOCK(hspi); - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if(hspi->State == HAL_SPI_STATE_READY) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + tmp = hspi->State; + tmp1 = hspi->Init.Mode; + + if(!((tmp == HAL_SPI_STATE_READY) || \ + ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } - /* Configure communication */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } - hspi->pRxBuffPtr = pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - hspi->pTxBuffPtr = pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State == HAL_SPI_STATE_READY) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } - /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + /* Transmit and Receive data in 16 Bit mode */ + if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); + hspi->Instance->DR = *((uint16_t *)pTxData); + pTxData += sizeof(uint16_t); + hspi->TxXferCount--; } - - /* Transmit and Receive data in 16 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_16BIT) + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { - if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + /* Check TXE flag */ + if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) { - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; + hspi->Instance->DR = *((uint16_t *)pTxData); + pTxData += sizeof(uint16_t); hspi->TxXferCount--; - } - if(hspi->TxXferCount == 0) - { + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } +#endif /* USE_SPI_CRC */ + } - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; + /* Check RXNE flag */ + if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) + { + *((uint16_t *)pRxData) = hspi->Instance->DR; + pRxData += sizeof(uint16_t); hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; } - else + if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) { - while(hspi->TxXferCount > 0) - { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; - hspi->TxXferCount--; - - /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; - hspi->RxXferCount--; - } - /* Receive the last byte */ - if(hspi->Init.Mode == SPI_MODE_SLAVE) - { - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; - hspi->RxXferCount--; - } + errorcode = HAL_TIMEOUT; + goto error; } } - /* Transmit and Receive data in 8 Bit mode */ - else + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01U)) + { + *((__IO uint8_t*)&hspi->Instance->DR) = (*pTxData); + pTxData += sizeof(uint8_t); + hspi->TxXferCount--; + } + while((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) { - if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01))) + /* check TXE flag */ + if(txallowed && (hspi->TxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))) { - hspi->Instance->DR = (*hspi->pTxBuffPtr++); + *(__IO uint8_t *)&hspi->Instance->DR = (*pTxData++); hspi->TxXferCount--; - } - if(hspi->TxXferCount == 0) - { + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + if((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } - - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->RxXferCount--; +#endif /* USE_SPI_CRC */ } - else - { - while(hspi->TxXferCount > 0) - { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - hspi->Instance->DR = (*hspi->pTxBuffPtr++); - hspi->TxXferCount--; - - /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - hspi->RxXferCount--; - } - if(hspi->Init.Mode == SPI_MODE_SLAVE) - { - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - hspi->RxXferCount--; - } + /* Wait until RXNE flag is reset */ + if((hspi->RxXferCount > 0U) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))) + { + (*(uint8_t *)pRxData++) = hspi->Instance->DR; + hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; } - } - - /* Read CRC from DR to close CRC calculation process */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if((Timeout != HAL_MAX_DELAY) && ((HAL_GetTick()-tickstart) >= Timeout)) { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - return HAL_TIMEOUT; + errorcode = HAL_TIMEOUT; + goto error; } - /* Read CRC */ - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); } + } - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) +#if (USE_SPI_CRC != 0U) + /* Read CRC from DR to close CRC calculation process */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until TXE flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + errorcode = HAL_TIMEOUT; + goto error; } - - hspi->State = HAL_SPI_STATE_READY; + /* Read CRC */ + tmpreg1 = hspi->Instance->DR; + /* To avoid GCC warning */ + UNUSED(tmpreg1); + } - /* Check if CRC error occurred */ - if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + /* Reset CRC Calculation */ SPI_RESET_CRC(hspi); - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_ERROR; + errorcode = HAL_ERROR; } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } +#endif /* USE_SPI_CRC */ - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; + /* Wait until TXE flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_TXE, SET, Timeout, tickstart) != HAL_OK) + { + errorcode = HAL_TIMEOUT; + goto error; } - else + + /* Check Busy flag */ + if(SPI_CheckFlag_BSY(hspi, Timeout, tickstart) != HAL_OK) { - return HAL_BUSY; + errorcode = HAL_ERROR; + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + goto error; } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +error : + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Transmit an amount of data in no-blocking mode with Interrupt + * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - if(hspi->State == HAL_SPI_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + HAL_StatusTypeDef errorcode = HAL_OK; - /* Process Locked */ - __HAL_LOCK(hspi); + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - - hspi->TxISR = &SPI_TxISR; - hspi->pTxBuffPtr = pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; + /* Process Locked */ + __HAL_LOCK(hspi); - /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + if((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_TX(hspi); - } + if(hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->RxISR = NULL; + + /* Set the function for IT treatment */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } - if (hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); - } - else - { - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - } - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ - return HAL_OK; + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + /* Enable TXE interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); } else { - return HAL_BUSY; + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + } + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); } + +error : + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Receive an amount of data in no-blocking mode with Interrupt + * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @param pData: pointer to data buffer * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - if(hspi->State == HAL_SPI_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } + HAL_StatusTypeDef errorcode = HAL_OK; - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - - hspi->RxISR = &SPI_RxISR; - hspi->pRxBuffPtr = pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size ; + if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } - /*Init field not used in handle to zero */ - hspi->TxISR = 0; - hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; + /* Process Locked */ + __HAL_LOCK(hspi); - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + if(hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); - } + if((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->TxISR = NULL; + + /* Set the function for IT treatment */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + { + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + } - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } - /* Process Unlocked */ - __HAL_UNLOCK(hspi); +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ - /* Note : The SPI must be enabled after unlocking current process - to avoid the risk of SPI interrupt handle execution before current - process unlock */ + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ - return HAL_OK; - } - else + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { - return HAL_BUSY; + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); } + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer to be - * @param Size: amount of data to be sent + * @param pRxData: pointer to reception data buffer + * @param Size: amount of data to be sent and received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { + uint32_t tmp = 0U, tmp1 = 0U; + HAL_StatusTypeDef errorcode = HAL_OK; - if((hspi->State == HAL_SPI_STATE_READY) || \ - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) - { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Process locked */ - __HAL_LOCK(hspi); - - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if(hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - - /* Configure communication */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - hspi->TxISR = &SPI_TxISR; - hspi->pTxBuffPtr = pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - hspi->RxISR = &SPI_2LinesRxISR; - hspi->pRxBuffPtr = pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } + /* Process locked */ + __HAL_LOCK(hspi); - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + tmp = hspi->State; + tmp1 = hspi->Init.Mode; + + if(!((tmp == HAL_SPI_STATE_READY) || \ + ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) + { + errorcode = HAL_BUSY; + goto error; + } - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State == HAL_SPI_STATE_READY) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } - return HAL_OK; + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Set the function for IT treatment */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + { + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; } else { - return HAL_BUSY; + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; } -} -/** - * @brief Transmit an amount of data in no-blocking mode with DMA - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size: amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - if(hspi->State == HAL_SPI_STATE_READY) +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ - /* Check the parameters */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - /* Process Locked */ - __HAL_LOCK(hspi); + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} - hspi->pTxBuffPtr = pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size: amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef errorcode = HAL_OK; - /*Init field not used in handle to zero */ - hspi->TxISR = 0; - hspi->RxISR = 0; - hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_TX(hspi); - } + /* Process Locked */ + __HAL_LOCK(hspi); - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } + if(hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } - /* Set the SPI TxDMA Half transfer complete callback */ - hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + if((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } - /* Set the SPI TxDMA transfer complete callback */ - hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ - /* Enable the Tx DMA Channel */ - HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; - /* Enable Tx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; - return HAL_OK; - } - else + /* Enable the Tx DMA Stream */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { - return HAL_BUSY; + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); } + + /* Enable the SPI Error Interrupt Bit */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Receive an amount of data in no-blocking mode with DMA + * @brief Receive an amount of data in non-blocking mode with DMA. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @param pData: pointer to data buffer - * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @note When the CRC feature is enabled the pData Length must be Size + 1. * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - if(hspi->State == HAL_SPI_STATE_READY) - { - if((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } + HAL_StatusTypeDef errorcode = HAL_OK; - /* Process Locked */ - __HAL_LOCK(hspi); + if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } - /* Configure communication */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; + /* Process Locked */ + __HAL_LOCK(hspi); - hspi->pRxBuffPtr = pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; + if(hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } - /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; - hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; + if((pData == NULL) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } - /* Configure communication direction : 1Line */ - if(hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if(hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); - } +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - /* Set the SPI RxDMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - /* Set the SPI Rx DMA transfer complete callback */ - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; - /* Set the DMA error callback */ - hspi->hdmarx->XferErrorCallback = SPI_DMAError; + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; - /* Enable the Rx DMA Channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + /* Enable the Rx DMA Stream */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); - /* Enable Rx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - return HAL_OK; - } - else - { - return HAL_BUSY; - } +error: + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; } /** - * @brief Transmit and Receive an amount of data in no-blocking mode with DMA + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @param pTxData: pointer to transmission data buffer * @param pRxData: pointer to reception data buffer - * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 * @param Size: amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - if((hspi->State == HAL_SPI_STATE_READY) || \ - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) + uint32_t tmp = 0U, tmp1 = 0U; + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Process locked */ + __HAL_LOCK(hspi); + + tmp = hspi->State; + tmp1 = hspi->Init.Mode; + if(!((tmp == HAL_SPI_STATE_READY) || + ((tmp1 == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp == HAL_SPI_STATE_BUSY_RX)))) { - if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) - { - return HAL_ERROR; - } + errorcode = HAL_BUSY; + goto error; + } - /* Check the parameters */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Process locked */ - __HAL_LOCK(hspi); + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0U)) + { + errorcode = HAL_ERROR; + goto error; + } - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if(hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if(hspi->State == HAL_SPI_STATE_READY) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (uint8_t*)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t*)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if(hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } - /* Configure communication */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; - hspi->pTxBuffPtr = (uint8_t*)pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; - hspi->pRxBuffPtr = (uint8_t*)pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; + /* Enable the Rx DMA Stream */ + HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); - /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferErrorCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream */ + HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); + + /* Check if the SPI is already enabled */ + if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + /* Enable the SPI Error Interrupt Bit */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + +error : + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application + * before starting new SPI receive process. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + } + + if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + } + + /* Clear ERRIE interrupts in case of DMA Mode */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); - /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ - if(hspi->State == HAL_SPI_STATE_BUSY_RX) + /* Disable the SPI DMA Tx or SPI DMA Rx request if enabled */ + if ((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) + { + /* Abort the SPI DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(hspi->hdmatx != NULL) { - /* Set the SPI Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = NULL; - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + /* Abort DMA Tx Handle linked to SPI Peripheral */ + HAL_DMA_Abort(hspi->hdmatx); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); + + /* Wait until TXE flag is set */ + do + { + if(count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + } + while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); } - else + /* Abort the SPI DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(hspi->hdmarx != NULL) { - /* Set the SPI Tx/Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; - - hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + HAL_DMA_Abort(hspi->hdmarx); + + /* Disable peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); + } + } + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); - /* Set the DMA error callback */ - hspi->hdmarx->XferErrorCallback = SPI_DMAError; + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @note Once transfer is aborted, the __HAL_SPI_CLEAR_OVRFLAG() macro must be called in user application + * before starting new SPI receive process. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + uint32_t abortcplt; + + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ + if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + } - /* Enable the Rx DMA Channel */ - HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); + if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + } - /* Enable Rx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + /* Clear ERRIE interrupts in case of DMA Mode */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); - /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing - is performed in DMA reception complete callback */ - if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + abortcplt = 1U; + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if(hspi->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) { - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; } else { - hspi->hdmatx->XferErrorCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; } - - /* Enable the Tx DMA Channel */ - HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); - - /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + } + /* DMA Rx Handle is valid */ + if(hspi->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } - /* Enable Tx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + if((HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) && (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))) + { + /* Abort the SPI DMA Tx channel */ + if(hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + /* Abort the SPI DMA Rx channel */ + if(hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } - return HAL_OK; + /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx channel */ + if(hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if(HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } } - else + /* Disable the SPI DMA Tx or the SPI Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) { - return HAL_BUSY; + /* Abort the SPI DMA Rx channel */ + if(hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if(HAL_DMA_Abort_IT(hspi->hdmarx)!= HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } } -} + if(abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_SPI_AbortCpltCallback(hspi); + } + return HAL_OK; +} /** - * @brief Pauses the DMA Transfer. + * @brief Pause the DMA Transfer. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. + * the configuration information for the specified SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) { /* Process Locked */ __HAL_LOCK(hspi); - + /* Disable the SPI DMA Tx & Rx requests */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + /* Process Unlocked */ __HAL_UNLOCK(hspi); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Resumes the DMA Transfer. + * @brief Resume the DMA Transfer. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. + * the configuration information for the specified SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) { /* Process Locked */ __HAL_LOCK(hspi); - + /* Enable the SPI DMA Tx & Rx requests */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + /* Process Unlocked */ __HAL_UNLOCK(hspi); - + return HAL_OK; } /** - * @brief Stops the DMA Transfer. + * @brief Stop the DMA Transfer. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. + * the configuration information for the specified SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) @@ -1542,188 +1920,233 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() */ - - /* Abort the SPI DMA tx Channel */ + + /* Abort the SPI DMA tx Stream */ if(hspi->hdmatx != NULL) { HAL_DMA_Abort(hspi->hdmatx); } - /* Abort the SPI DMA rx Channel */ + /* Abort the SPI DMA rx Stream */ if(hspi->hdmarx != NULL) { HAL_DMA_Abort(hspi->hdmarx); } - + /* Disable the SPI DMA Tx & Rx requests */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); hspi->State = HAL_SPI_STATE_READY; - return HAL_OK; } /** - * @brief This function handles SPI interrupt request. + * @brief Handle SPI interrupt request. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for the specified SPI module. * @retval None */ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) { - /* SPI in mode Receiver and Overrun not occurred ---------------------------*/ - if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET)) + uint32_t itsource = hspi->Instance->CR2; + uint32_t itflag = hspi->Instance->SR; + + /* SPI in mode Receiver ----------------------------------------------------*/ + if(((itflag & SPI_FLAG_OVR) == RESET) && + ((itflag & SPI_FLAG_RXNE) != RESET) && ((itsource & SPI_IT_RXNE) != RESET)) { hspi->RxISR(hspi); return; } - /* SPI in mode Tramitter ---------------------------------------------------*/ - if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET)) + /* SPI in mode Transmitter -------------------------------------------------*/ + if(((itflag & SPI_FLAG_TXE) != RESET) && ((itsource & SPI_IT_TXE) != RESET)) { hspi->TxISR(hspi); return; } - if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET) + /* SPI in Error Treatment --------------------------------------------------*/ + if(((itflag & (SPI_FLAG_MODF | SPI_FLAG_OVR)) != RESET) && ((itsource & SPI_IT_ERR) != RESET)) { - /* SPI CRC error interrupt occurred ---------------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } - /* SPI Mode Fault error interrupt occurred --------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); - __HAL_SPI_CLEAR_MODFFLAG(hspi); - } - - /* SPI Overrun error interrupt occurred -----------------------------------*/ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if((itflag & SPI_FLAG_OVR) != RESET) { if(hspi->State != HAL_SPI_STATE_BUSY_TX) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); - __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + else + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + return; } } - /* Call the Error call Back in case of Errors */ - if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE) + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if((itflag & SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { + /* Disable all interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_ErrorCallback(hspi); + /* Disable the SPI DMA requests if enabled */ + if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN))||(HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) + { + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + + /* Abort the SPI DMA Rx channel */ + if(hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + HAL_DMA_Abort_IT(hspi->hdmarx); + } + /* Abort the SPI DMA Tx channel */ + if(hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + HAL_DMA_Abort_IT(hspi->hdmatx); + } + } + else + { + /* Call user error callback */ + HAL_SPI_ErrorCallback(hspi); + } } + return; } } /** - * @brief Tx Transfer completed callbacks + * @brief Tx Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_TxCpltCallback could be implenetd in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ } /** - * @brief Rx Transfer completed callbacks + * @brief Rx Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_RxCpltCallback() could be implenetd in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ } /** - * @brief Tx and Rx Transfer completed callbacks + * @brief Tx and Rx Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ } /** - * @brief Tx Half Transfer completed callbacks + * @brief Tx Half Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ } /** - * @brief Rx Half Transfer completed callbacks + * @brief Rx Half Transfer completed callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ } /** - * @brief Tx and Rx Transfer completed callbacks + * @brief Tx and Rx Half Transfer callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file - */ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ } /** - * @brief SPI error callbacks + * @brief SPI error callback. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) { /* Prevent unused argument(s) compilation warning */ UNUSED(hspi); - /* NOTE : - This function Should not be modified, when the callback is needed, - the HAL_SPI_ErrorCallback() could be implenetd in the user file. - - The ErrorCode parameter in the hspi handle is updated by the SPI processes - and user can use HAL_SPI_GetError() API to check the latest error occurred. + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. */ } @@ -1731,13 +2154,13 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) * @} */ -/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief SPI control functions +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides a set of functions allowing to control the SPI. (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral @@ -1747,640 +2170,1071 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) */ /** - * @brief Return the SPI state + * @brief Return the SPI handle state. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @retval SPI state */ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) { + /* Return SPI handle state */ return hspi->State; } /** - * @brief Return the SPI error code + * @brief Return the SPI error code. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval SPI Error Code + * the configuration information for SPI module. + * @retval SPI error code in bitmap format */ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) { + /* Return SPI ErrorCode */ return hspi->ErrorCode; } /** * @} */ - -/** - * @} - */ - +/** + * @} + */ /** @addtogroup SPI_Private_Functions - * @{ - */ - + * @brief Private functions + * @{ + */ - /** - * @brief Interrupt Handler to close Tx transfer - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ -static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi) +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + uint32_t tickstart = 0U; - /* Disable TXE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); - /* Disable ERR interrupt if Receive process is finished */ - if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET) + /* DMA Normal Mode */ + if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) { - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + /* Check the end of the transaction */ + if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ + /* Clear overrun flag in 2 Lines communication mode because received data is not read */ if(hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_CLEAR_OVRFLAG(hspi); } - - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - /* Check if we are in Tx or in Rx/Tx Mode */ - if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_TxRxCpltCallback(hspi); - } - else - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_TxCpltCallback(hspi); - } - } - else + + hspi->TxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - /* Call Error call back in case of Error */ HAL_SPI_ErrorCallback(hspi); + return; } } + HAL_SPI_TxCpltCallback(hspi); } /** - * @brief Interrupt Handler to transmit amount of data in no-blocking mode - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * @brief DMA SPI receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ -static void SPI_TxISR(SPI_HandleTypeDef *hspi) +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - /* Transmit data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) - { - hspi->Instance->DR = (*hspi->pTxBuffPtr++); - } - /* Transmit data in 16 Bit mode */ - else - { - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2; - } - hspi->TxXferCount--; + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; +#if (USE_SPI_CRC != 0U) + uint32_t tickstart = 0U; + __IO uint16_t tmpreg = 0U; - if(hspi->TxXferCount == 0) + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); +#endif /* USE_SPI_CRC */ + + if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) { +#if (USE_SPI_CRC != 0U) + /* CRC handling */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - /* calculate and transfer CRC on Tx line */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Wait until RXNE flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC */ + tmpreg = hspi->Instance->DR; + /* To avoid GCC warning */ + UNUSED(tmpreg); } - SPI_TxCloseIRQHandler(hspi); - } -} +#endif /* USE_SPI_CRC */ -/** - * @brief Interrupt Handler to close Rx transfer - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi) -{ - __IO uint16_t tmpreg = 0; + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Wait until RXNE flag is set to read CRC data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + /* Check the end of the transaction */ + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); } - /* Read CRC to reset RXNE flag */ - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); - - /* Wait until RXNE flag is reset */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; +#if (USE_SPI_CRC != 0U) /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { /* Check if CRC error is valid or not (workaround to be applied or not) */ - if ( (hspi->State != HAL_SPI_STATE_BUSY_RX) - || (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) ) + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Reset CRC Calculation */ SPI_RESET_CRC(hspi); - } + } else { __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } } +#endif /* USE_SPI_CRC */ + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + return; + } } + HAL_SPI_RxCpltCallback(hspi); +} - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE)); +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + uint32_t tickstart = 0U; +#if (USE_SPI_CRC != 0U) + __IO int16_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); - /* if Transmit process is finished */ - if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET) + if((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) { - /* Disable ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); - - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); + /* Wait the CRC data */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC to Flush DR and RXNE flag */ + tmpreg = hspi->Instance->DR; + /* To avoid GCC warning */ + UNUSED(tmpreg); } - - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) +#endif /* USE_SPI_CRC */ + /* Check the end of the transaction */ + if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx/Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0U; + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { - /* Check if we are in Rx or in Rx/Tx Mode */ - if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_TxRxCpltCallback(hspi); - } + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + } else { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_RxCpltCallback(hspi); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } } - else +#endif /* USE_SPI_CRC */ + + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - /* Call Error call back in case of Error */ HAL_SPI_ErrorCallback(hspi); + return; } } + HAL_SPI_TxRxCpltCallback(hspi); } /** - * @brief Interrupt Handler to receive amount of data in 2Lines mode - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * @brief DMA SPI half transmit process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ -static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi) +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - /* Receive data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) - { - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - } - /* Receive data in 16 Bit mode */ - else - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; - } - hspi->RxXferCount--; + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - if(hspi->RxXferCount==0) - { - SPI_RxCloseIRQHandler(hspi); - } + HAL_SPI_TxHalfCpltCallback(hspi); } /** - * @brief Interrupt Handler to receive amount of data in no-blocking mode - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * @brief DMA SPI half receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ -static void SPI_RxISR(SPI_HandleTypeDef *hspi) +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - /* Receive data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) - { - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - } - /* Receive data in 16 Bit mode */ - else - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2; - } - hspi->RxXferCount--; - - /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - /* Set CRC Next to calculate CRC on Rx side */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - if(hspi->RxXferCount == 0) - { - SPI_RxCloseIRQHandler(hspi); - } + HAL_SPI_RxHalfCpltCallback(hspi); } /** - * @brief DMA SPI transmit process complete callback + * @brief DMA SPI half transmit receive process complete callback. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * the configuration information for the specified DMA module. * @retval None */ -static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* DMA Normal Mode */ - if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) - { - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } + HAL_SPI_TxRxHalfCpltCallback(hspi); +} - /* Disable Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +/** + * @brief DMA SPI communication error callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } +/* Stop the disable DMA transfer on SPI side */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - hspi->TxXferCount = 0; - hspi->State = HAL_SPI_STATE_READY; - } + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_ErrorCallback(hspi); +} - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + HAL_SPI_ErrorCallback(hspi); +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + hspi->hdmatx->XferAbortCallback = NULL; + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN ); + + /* Wait until TXE flag is set */ + do { - HAL_SPI_ErrorCallback(hspi); + if(count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } } - else + while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Check if an Abort process is still ongoing */ + if(hspi->hdmarx != NULL) { - HAL_SPI_TxCpltCallback(hspi); + if(hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ + HAL_SPI_AbortCpltCallback(hspi); } /** - * @brief DMA SPI receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. * @retval None */ -static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - __IO uint16_t tmpreg = 0; SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) - { - /* Disable Rx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); - /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + hspi->hdmarx->XferAbortCallback = NULL; - /* CRC Calculation handling */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Check if an Abort process is still ongoing */ + if(hspi->hdmatx != NULL) + { + if(hspi->hdmatx->XferAbortCallback != NULL) { - /* Wait until RXNE flag is set (CRC ready) */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } + return; + } + } - /* Read CRC */ - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; - /* Wait until RXNE flag is reset */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - /* Check if CRC error is valid or not (workaround to be applied or not) */ - if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - - /* Reset CRC Calculation */ - SPI_RESET_CRC(hspi); - } - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } - } + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; - hspi->RxXferCount = 0; - hspi->State = HAL_SPI_STATE_READY; + /* Call user Abort complete callback */ + HAL_SPI_AbortCpltCallback(hspi); +} - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8bit mode */ + *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->RxXferCount--; + + /* check end of the reception */ + if(hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - HAL_SPI_ErrorCallback(hspi); + hspi->RxISR = SPI_2linesRxISR_8BITCRC; + return; } - else +#endif /* USE_SPI_CRC */ + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if(hspi->TxXferCount == 0U) { - HAL_SPI_RxCpltCallback(hspi); + SPI_CloseRxTx_ISR(hspi); } } - else +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t tmpreg = 0U; + + /* Read data register to flush CRC */ + tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); + + /* To avoid GCC warning */ + + UNUSED(tmpreg); + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if(hspi->TxXferCount == 0U) { - HAL_SPI_RxCpltCallback(hspi); + SPI_CloseRxTx_ISR(hspi); } } +#endif /* USE_SPI_CRC */ /** - * @brief DMA SPI transmit receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval None */ -static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - __IO uint16_t tmpreg = 0; - - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; - if((hdma->Instance->CCR & DMA_CIRCULAR) == 0) + /* check the end of the transmission */ + if(hspi->TxXferCount == 0U) { - /* CRC Calculation handling */ +#if (USE_SPI_CRC != 0U) if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - /* Check if CRC is done on going (RXNE flag set) */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) - { - /* Wait until RXNE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - } - /* Read CRC */ - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if(hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); } + } +} + +/** + * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) + if(hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + hspi->RxISR = SPI_2linesRxISR_16BITCRC; + return; } - - /* Disable Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); +#endif /* USE_SPI_CRC */ - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + if(hspi->TxXferCount == 0U) { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + SPI_CloseRxTx_ISR(hspi); } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ + __IO uint16_t tmpreg = 0U; - /* Disable Rx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + /* Read data register to flush CRC */ + tmpreg = hspi->Instance->DR; - hspi->TxXferCount = 0; - hspi->RxXferCount = 0; + /* To avoid GCC warning */ + UNUSED(tmpreg); - hspi->State = HAL_SPI_STATE_READY; + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + SPI_CloseRxTx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if(hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - HAL_SPI_ErrorCallback(hspi); + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; } - else +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if(hspi->RxXferCount == 0U) { - HAL_SPI_TxRxCpltCallback(hspi); + SPI_CloseRxTx_ISR(hspi); } } - else - { - HAL_SPI_TxRxCpltCallback(hspi); - } } +#if (USE_SPI_CRC != 0U) /** - * @brief DMA SPI half transmit process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief Manage the CRC 8-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval None */ -static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + __IO uint8_t tmpreg = 0U; - HAL_SPI_TxHalfCpltCallback(hspi); + /* Read data register to flush CRC */ + tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); + + /* To avoid GCC warning */ + UNUSED(tmpreg); + + SPI_CloseRx_ISR(hspi); } +#endif /* USE_SPI_CRC */ /** - * @brief DMA SPI half receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval None */ -static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); + hspi->RxXferCount--; - HAL_SPI_RxHalfCpltCallback(hspi); +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if(hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } } +#if (USE_SPI_CRC != 0U) /** - * @brief DMA SPI Half transmit receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief Manage the CRC 16-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval None */ -static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { - SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + __IO uint16_t tmpreg = 0U; - HAL_SPI_TxRxHalfCpltCallback(hspi); + /* Read data register to flush CRC */ + tmpreg = hspi->Instance->DR; + + /* To avoid GCC warning */ + UNUSED(tmpreg); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + SPI_CloseRx_ISR(hspi); } +#endif /* USE_SPI_CRC */ /** - * @brief DMA SPI communication error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval None */ -static void SPI_DMAError(DMA_HandleTypeDef *hdma) +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { - SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hspi->TxXferCount = 0; - hspi->RxXferCount = 0; - hspi->State= HAL_SPI_STATE_READY; - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - HAL_SPI_ErrorCallback(hspi); + *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if(hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } } /** - * @brief This function handles SPI Communication Timeout. + * @brief Handle the data 8-bit transmit in Interrupt mode. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Flag: SPI flag to check - * @param Status: Flag status to check: RESET or set - * @param Timeout: Timeout duration - * @retval HAL status + * the configuration information for SPI module. + * @retval None */ -static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - uint32_t tickstart = 0; + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; - /* Get tick */ - tickstart = HAL_GetTick(); + if(hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} - /* Wait until flag is set */ - if(Status == RESET) +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + if(hspi->TxXferCount == 0U) { - while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET) +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - if(Timeout != HAL_MAX_DELAY) + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param State: flag state to check + * @param Timeout: Timeout duration + * @param Tickstart: tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart) +{ + while((((hspi->Instance->SR & Flag) == (Flag)) ? SET : RESET) != State) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout)) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ - /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { /* Disable SPI peripheral */ __HAL_SPI_DISABLE(hspi); + } - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } - hspi->State= HAL_SPI_STATE_READY; + hspi->State= HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } } + + return HAL_OK; +} +/** + * @brief Handle to check BSY flag before start a new transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Timeout: Timeout duration + * @param Tickstart: tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + /* Control the BSY flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + return HAL_OK; +} + +/** + * @brief Handle the end of the RXTX transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart = 0U; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Wait until TXE flag is set */ + do + { + if(count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + } + while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Check the end of the transaction */ + if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); + + HAL_SPI_ErrorCallback(hspi); + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } else { - while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET) +#endif /* USE_SPI_CRC */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) { - if(Timeout != HAL_MAX_DELAY) + if(hspi->State == HAL_SPI_STATE_BUSY_RX) { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_RxCpltCallback(hspi); + } + else + { + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + } + else + { + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_ErrorCallback(hspi); + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} - /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); +/** + * @brief Handle the end of the RX transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); + /* Check the end of the transaction */ + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + hspi->State = HAL_SPI_STATE_READY; - hspi->State= HAL_SPI_STATE_READY; +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + /* Check if CRC error is valid or not (workaround to be applied or not) */ + if (SPI_ISCRCErrorValid(hspi) == SPI_VALID_CRC_ERROR) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Reset CRC Calculation */ + SPI_RESET_CRC(hspi); - return HAL_TIMEOUT; - } + HAL_SPI_ErrorCallback(hspi); + } + else + { + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } + else + { +#endif /* USE_SPI_CRC */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + HAL_SPI_RxCpltCallback(hspi); + } + else + { + HAL_SPI_ErrorCallback(hspi); } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the TX transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart = 0U; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Wait until TXE flag is set */ + do + { + if(count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; } } - return HAL_OK; + while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Disable TXE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + /* Check Busy flag */ + if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxCpltCallback(hspi); + } } /** * @} */ -/** @addtogroup SPI_Private_Functions - * @{ +/** + * @brief Handle abort a Tx or Rx transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg = 0U; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Wait until TXE flag is set */ + do + { + if(count-- == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + } + while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + + /* Flush DR Register */ + tmpreg = (*(__IO uint32_t *)&hspi->Instance->DR); + + /* To avoid GCC warning */ + UNUSED(tmpreg); +} + +/** + * @brief Handle abort a Tx or Rx transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE)); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); +} /** * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors @@ -2391,14 +3245,16 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin */ __weak uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + return (SPI_VALID_CRC_ERROR); } /** * @} */ - - #endif /* HAL_SPI_MODULE_ENABLED */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.h index 1bc59de0b60..d152d74affd 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_hal_spi.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_SPI_H @@ -59,19 +59,19 @@ * @{ */ -/** - * @brief SPI Configuration Structure definition +/** + * @brief SPI Configuration Structure definition */ typedef struct { uint32_t Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ + This parameter can be a value of @ref SPI_Mode */ uint32_t Direction; /*!< Specifies the SPI Directional mode state. - This parameter can be a value of @ref SPI_Direction_mode */ + This parameter can be a value of @ref SPI_Direction */ uint32_t DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ + This parameter can be a value of @ref SPI_Data_Size */ uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_Clock_Polarity */ @@ -87,7 +87,7 @@ typedef struct used to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_BaudRate_Prescaler @note The communication clock is derived from the master - clock. The slave clock does not need to be set */ + clock. The slave clock does not need to be set. */ uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_MSB_LSB_transmission */ @@ -100,7 +100,6 @@ typedef struct uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */ - }SPI_InitTypeDef; /** @@ -108,18 +107,16 @@ typedef struct */ typedef enum { - HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */ - HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */ - HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */ - HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */ - + HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */ }HAL_SPI_StateTypeDef; - -/** +/** * @brief SPI handle Structure definition */ typedef struct __SPI_HandleTypeDef @@ -130,95 +127,88 @@ typedef struct __SPI_HandleTypeDef uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ - uint16_t TxXferSize; /*!< SPI Tx transfer size */ - - uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ - uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< SPI Rx transfer size */ + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ - uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ - DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */ + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ - DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */ + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */ void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */ - HAL_LockTypeDef Lock; /*!< SPI locking object */ + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ - __IO uint32_t ErrorCode; /*!< SPI Error code */ + __IO uint32_t ErrorCode; /*!< SPI Error code */ }SPI_HandleTypeDef; + /** * @} */ - /* Exported constants --------------------------------------------------------*/ - /** @defgroup SPI_Exported_Constants SPI Exported Constants * @{ */ -/** @defgroup SPI_Error_Codes SPI Error Codes +/** @defgroup SPI_Error_Code SPI Error Code * @{ - */ -#define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */ -#define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */ -#define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */ -#define HAL_SPI_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */ -#define HAL_SPI_ERROR_FLAG ((uint32_t)0x10) /*!< Flag: RXNE,TXE, BSY */ + */ +#define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */ +#define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */ +#define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */ +#define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */ +#define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */ /** * @} */ - - - -/** @defgroup SPI_mode SPI mode +/** @defgroup SPI_Mode SPI Mode * @{ */ -#define SPI_MODE_SLAVE ((uint32_t)0x00000000) +#define SPI_MODE_SLAVE 0x00000000U #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) - /** * @} */ -/** @defgroup SPI_Direction_mode SPI Direction mode +/** @defgroup SPI_Direction SPI Direction Mode * @{ */ -#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES 0x00000000U #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE - /** * @} */ -/** @defgroup SPI_data_size SPI data size +/** @defgroup SPI_Data_Size SPI Data Size * @{ */ -#define SPI_DATASIZE_8BIT ((uint32_t)0x00000000) +#define SPI_DATASIZE_8BIT 0x00000000U #define SPI_DATASIZE_16BIT SPI_CR1_DFF - /** * @} - */ + */ /** @defgroup SPI_Clock_Polarity SPI Clock Polarity * @{ */ -#define SPI_POLARITY_LOW ((uint32_t)0x00000000) +#define SPI_POLARITY_LOW 0x00000000U #define SPI_POLARITY_HIGH SPI_CR1_CPOL - /** * @} */ @@ -226,71 +216,65 @@ typedef struct __SPI_HandleTypeDef /** @defgroup SPI_Clock_Phase SPI Clock Phase * @{ */ -#define SPI_PHASE_1EDGE ((uint32_t)0x00000000) +#define SPI_PHASE_1EDGE 0x00000000U #define SPI_PHASE_2EDGE SPI_CR1_CPHA - /** * @} */ -/** @defgroup SPI_Slave_Select_management SPI Slave Select management +/** @defgroup SPI_Slave_Select_management SPI Slave Select Management * @{ */ #define SPI_NSS_SOFT SPI_CR1_SSM -#define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) +#define SPI_NSS_HARD_INPUT 0x00000000U #define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16)) - /** * @} - */ + */ /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler * @{ */ -#define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) -#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) -#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) -#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) -#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) -#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) -#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) -#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_2 0x00000000U +#define SPI_BAUDRATEPRESCALER_4 SPI_CR1_BR_0 +#define SPI_BAUDRATEPRESCALER_8 SPI_CR1_BR_1 +#define SPI_BAUDRATEPRESCALER_16 (uint32_t)(SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 SPI_CR1_BR_2 +#define SPI_BAUDRATEPRESCALER_64 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /** * @} - */ + */ -/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission * @{ */ -#define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) +#define SPI_FIRSTBIT_MSB 0x00000000U #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST - /** * @} */ -/** @defgroup SPI_TI_mode SPI TI mode disable - * @brief SPI TI Mode not supported for STM32F1xx family +/** @defgroup SPI_TI_mode SPI TI Mode * @{ */ -#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) - +#define SPI_TIMODE_DISABLE 0x00000000U /** * @} */ - + /** @defgroup SPI_CRC_Calculation SPI CRC Calculation * @{ */ -#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) -#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN - +#define SPI_CRCCALCULATION_DISABLE 0x00000000U +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN /** * @} */ -/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition * @{ */ #define SPI_IT_TXE SPI_CR2_TXEIE @@ -300,16 +284,15 @@ typedef struct __SPI_HandleTypeDef * @} */ -/** @defgroup SPI_Flag_definition SPI Flag definition +/** @defgroup SPI_Flags_definition SPI Flags Definition * @{ */ -#define SPI_FLAG_RXNE SPI_SR_RXNE -#define SPI_FLAG_TXE SPI_SR_TXE -#define SPI_FLAG_CRCERR SPI_SR_CRCERR -#define SPI_FLAG_MODF SPI_SR_MODF -#define SPI_FLAG_OVR SPI_SR_OVR -#define SPI_FLAG_BSY SPI_SR_BSY - +#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ +#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ +#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ /** * @} */ @@ -318,25 +301,13 @@ typedef struct __SPI_HandleTypeDef * @} */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SPI_Private_Constants SPI Private Constants - * @{ - */ -#define SPI_INVALID_CRC_ERROR 0 /* CRC error wrongly detected */ -#define SPI_VALID_CRC_ERROR 1 /* CRC error is true */ -/** - * @} - */ - - /* Exported macro ------------------------------------------------------------*/ /** @defgroup SPI_Exported_Macros SPI Exported Macros * @{ */ -/** @brief Reset SPI handle state - * @param __HANDLE__: specifies the SPI handle. +/** @brief Reset SPI handle state. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -352,7 +323,7 @@ typedef struct __SPI_HandleTypeDef * @arg SPI_IT_ERR: Error interrupt enable * @retval None */ -#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) /** @brief Disable the specified SPI interrupts. * @param __HANDLE__: specifies the SPI handle. @@ -364,10 +335,10 @@ typedef struct __SPI_HandleTypeDef * @arg SPI_IT_ERR: Error interrupt enable * @retval None */ -#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) -/** @brief Check if the specified SPI interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the SPI handle. +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @param __INTERRUPT__: specifies the SPI interrupt source to check. * This parameter can be one of the following values: @@ -379,7 +350,7 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI handle. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: @@ -394,191 +365,52 @@ typedef struct __SPI_HandleTypeDef #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI handle. + * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ -do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - tmpreg = CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ - UNUSED(tmpreg); \ -}while(0) +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg_modf = 0x00U; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ + (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ + UNUSED(tmpreg_modf); \ + } while(0U) /** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ -do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->DR; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg); \ -}while(0) - - -/** @brief Enables the SPI. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None - */ -#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) - -/** @brief Disables the SPI. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) - -/** - * @} - */ - - -/* Private macros -----------------------------------------------------------*/ -/** @defgroup SPI_Private_Macros SPI Private Macros - * @{ - */ - -/** @brief Checks if SPI Mode parameter is in allowed range. - * @param __MODE__: specifies the SPI Mode. - * This parameter can be a value of @ref SPI_mode - * @retval None - */ -#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER)) - -/** @brief Checks if SPI Direction Mode parameter is in allowed range. - * @param __MODE__: specifies the SPI Direction Mode. - * This parameter can be a value of @ref SPI_Direction_mode - * @retval None - */ -#define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ - ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((__MODE__) == SPI_DIRECTION_1LINE)) - -/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. - * @param __MODE__: specifies the SPI Direction Mode. - * @retval None - */ -#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ - ((__MODE__) == SPI_DIRECTION_1LINE)) - -/** @brief Checks if SPI Direction Mode parameter is 2 lines. - * @param __MODE__: specifies the SPI Direction Mode. - * @retval None - */ -#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) - -/** @brief Checks if SPI Data Size parameter is in allowed range. - * @param __DATASIZE__: specifies the SPI Data Size. - * This parameter can be a value of @ref SPI_data_size - * @retval None - */ -#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_8BIT)) - -/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. - * @param __CPOL__: specifies the SPI serial clock steady state. - * This parameter can be a value of @ref SPI_Clock_Polarity - * @retval None - */ -#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ - ((__CPOL__) == SPI_POLARITY_HIGH)) - -/** @brief Checks if SPI Clock Phase parameter is in allowed range. - * @param __CPHA__: specifies the SPI Clock Phase. - * This parameter can be a value of @ref SPI_Clock_Phase - * @retval None - */ -#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ - ((__CPHA__) == SPI_PHASE_2EDGE)) - -/** @brief Checks if SPI Slave select parameter is in allowed range. - * @param __NSS__: specifies the SPI Slave Slelect management parameter. - * This parameter can be a value of @ref SPI_Slave_Select_management - * @retval None - */ -#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ - ((__NSS__) == SPI_NSS_HARD_INPUT) || \ - ((__NSS__) == SPI_NSS_HARD_OUTPUT)) - -/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. - * @param __PRESCALER__: specifies the SPI Baudrate prescaler. - * This parameter can be a value of @ref SPI_BaudRate_Prescaler - * @retval None - */ -#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) - -/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. - * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). - * This parameter can be a value of @ref SPI_MSB_LSB_transmission - * @retval None - */ -#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ - ((__BIT__) == SPI_FIRSTBIT_LSB)) - -/** @brief Checks if SPI TI mode parameter is in allowed range. - * @param __MODE__: specifies the SPI TI mode. - * This parameter can be a value of @ref SPI_TI_mode - * @retval None - */ -#define IS_SPI_TIMODE(__MODE__) ((__MODE__) == SPI_TIMODE_DISABLE) - -/** @brief Checks if SPI CRC calculation enabled state is in allowed range. - * @param __CALCULATION__: specifies the SPI CRC calculation enable state. - * This parameter can be a value of @ref SPI_CRC_Calculation - * @retval None */ -#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ - ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ +do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + } while(0U) -/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. - * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation. - * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 - * @retval None - */ -#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF)) -/** @brief Sets the SPI transmit-only mode. +/** @brief Enable the SPI peripheral. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) - -/** @brief Sets the SPI receive-only mode. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) +#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) -/** @brief Resets the CRC calculation of the SPI. +/** @brief Disable the SPI peripheral. * @param __HANDLE__: specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) - +#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE)) /** * @} */ @@ -588,10 +420,10 @@ do{ \ * @{ */ -/* Initialization/de-initialization functions **********************************/ /** @addtogroup SPI_Exported_Functions_Group1 * @{ */ +/* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); @@ -600,10 +432,10 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); * @} */ -/* I/O operation functions *****************************************************/ /** @addtogroup SPI_Exported_Functions_Group2 * @{ */ +/* I/O operation functions *****************************************************/ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); @@ -616,55 +448,138 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); /** * @} */ - -/* Peripheral State and Control functions **************************************/ /** @addtogroup SPI_Exported_Functions_Group3 * @{ */ +/* Peripheral State and Error functions ***************************************/ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +/** + * @} + */ /** * @} */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */ +#define SPI_VALID_CRC_ERROR 1U /* CRC error is true */ /** * @} */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) +/** @brief Set the SPI receive-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) -/* Private functions --------------------------------------------------------*/ -/** @addtogroup SPI_Private_Functions - * @{ +/** @brief Reset the CRC calculation of the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None */ -uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi); +#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\ + (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U) + +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ + ((MODE) == SPI_MODE_MASTER)) + +#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((MODE) == SPI_DIRECTION_1LINE)) + +#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) + +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_1LINE)) + +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ + ((DATASIZE) == SPI_DATASIZE_8BIT)) + +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ + ((CPOL) == SPI_POLARITY_HIGH)) + +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ + ((CPHA) == SPI_PHASE_2EDGE)) + +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ + ((NSS) == SPI_NSS_HARD_INPUT) || \ + ((NSS) == SPI_NSS_HARD_OUTPUT)) + +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) + +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ + ((BIT) == SPI_FIRSTBIT_LSB)) + +#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ + ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU)) /** * @} */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi); +/** + * @} + */ /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi_ex.c index 7659fc4c87b..8ae2f75b434 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_spi_ex.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Extended SPI HAL module driver. * * This file provides firmware functions to manage the following @@ -53,8 +53,9 @@ #ifdef HAL_SPI_MODULE_ENABLED /** @defgroup SPI_Private_Variables SPI Private Variables - * @{ - */ + * @{ + */ +#if (USE_SPI_CRC != 0U) /* Variable used to determine if device is impacted by implementation of workaround related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are: - STM32F101CDE/STM32F103CDE @@ -66,7 +67,8 @@ + Otherwise, one or more errors have been detected during the data transfer by CPU or DMA. If CRCERR is found reset, the complete data transfer is considered successful. */ -uint8_t uCRCErrorWorkaroundCheck = 0; +uint8_t uCRCErrorWorkaroundCheck = 0U; +#endif /* USE_SPI_CRC */ /** * @} */ @@ -84,7 +86,7 @@ uint8_t uCRCErrorWorkaroundCheck = 0; */ /** @addtogroup SPI_Exported_Functions_Group1 - * + * * @{ */ @@ -106,16 +108,23 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /* Check the parameters */ assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); assert_param(IS_SPI_MODE(hspi->Init.Mode)); - assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); assert_param(IS_SPI_NSS(hspi->Init.NSS)); assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); - assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + +#if (USE_SPI_CRC != 0U) assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); - assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ if(hspi->State == HAL_SPI_STATE_RESET) { @@ -136,17 +145,18 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); /* Configure : NSS management */ - WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode)); + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode)); /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ /* Configure : CRC Polynomial */ WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); -#if defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) +#if defined(SPI_I2SCFGR_I2SMOD) /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); -#endif +#endif /* SPI_I2SCFGR_I2SMOD */ +#if (USE_SPI_CRC != 0U) #if defined (STM32F101xE) || defined (STM32F103xE) /* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for CRC errors wrongly detected */ @@ -154,10 +164,11 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) Revision ID information is only available in Debug mode, so Workaround could not be implemented to distinguish Rev Z devices (issue present) from more recent version (issue fixed). So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */ - uCRCErrorWorkaroundCheck = 0; + uCRCErrorWorkaroundCheck = 0U; #else - uCRCErrorWorkaroundCheck = 0; -#endif + uCRCErrorWorkaroundCheck = 0U; +#endif /* STM32F101xE || STM32F103xE */ +#endif /* USE_SPI_CRC */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->State = HAL_SPI_STATE_READY; @@ -176,7 +187,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /** @addtogroup SPI_Private_Functions * @{ */ - +#if (USE_SPI_CRC != 0U) /** * @brief Checks if encountered CRC error could be corresponding to wrongly detected errors * according to SPI instance, Device type, and revision ID. @@ -186,21 +197,26 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) */ uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi) { -#if defined (STM32F101xE) || defined (STM32F103xE) +#if defined(STM32F101xE) || defined(STM32F103xE) /* Check how to handle this CRC error (workaround to be applied or not) */ /* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */ - if ( (uCRCErrorWorkaroundCheck != 0) && (hspi->Instance == SPI2) ) + if((uCRCErrorWorkaroundCheck != 0U) && (hspi->Instance == SPI2)) { - if (hspi->Instance->RXCRCR == 0) + if(hspi->Instance->RXCRCR == 0U) { return (SPI_INVALID_CRC_ERROR); } } return (SPI_VALID_CRC_ERROR); #else + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + return (SPI_VALID_CRC_ERROR); #endif } +#endif /* USE_SPI_CRC */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.c index c94bf7a41ed..156faaf03a9 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_sram.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. @@ -291,7 +291,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress hsram->State = HAL_SRAM_STATE_BUSY; /* Read data from memory */ - for(; BufferSize != 0; BufferSize--) + for(; BufferSize != 0U; BufferSize--) { *pDstBuffer = *(__IO uint8_t *)psramaddress; pDstBuffer++; @@ -333,7 +333,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres hsram->State = HAL_SRAM_STATE_BUSY; /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) + for(; BufferSize != 0U; BufferSize--) { *(__IO uint8_t *)psramaddress = *pSrcBuffer; pSrcBuffer++; @@ -369,7 +369,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres hsram->State = HAL_SRAM_STATE_BUSY; /* Read data from memory */ - for(; BufferSize != 0; BufferSize--) + for(; BufferSize != 0U; BufferSize--) { *pDstBuffer = *(__IO uint16_t *)psramaddress; pDstBuffer++; @@ -411,7 +411,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre hsram->State = HAL_SRAM_STATE_BUSY; /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) + for(; BufferSize != 0U; BufferSize--) { *(__IO uint16_t *)psramaddress = *pSrcBuffer; pSrcBuffer++; @@ -445,7 +445,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres hsram->State = HAL_SRAM_STATE_BUSY; /* Read data from memory */ - for(; BufferSize != 0; BufferSize--) + for(; BufferSize != 0U; BufferSize--) { *pDstBuffer = *(__IO uint32_t *)pAddress; pDstBuffer++; @@ -485,7 +485,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre hsram->State = HAL_SRAM_STATE_BUSY; /* Write data to memory */ - for(; BufferSize != 0; BufferSize--) + for(; BufferSize != 0U; BufferSize--) { *(__IO uint32_t *)pAddress = *pSrcBuffer; pSrcBuffer++; diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.h index ba2891aa6ec..c096f1b9df2 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_sram.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_sram.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention @@ -66,11 +66,11 @@ */ typedef enum { - HAL_SRAM_STATE_RESET = 0x00, /*!< SRAM not yet initialized or disabled */ - HAL_SRAM_STATE_READY = 0x01, /*!< SRAM initialized and ready for use */ - HAL_SRAM_STATE_BUSY = 0x02, /*!< SRAM internal process is ongoing */ - HAL_SRAM_STATE_ERROR = 0x03, /*!< SRAM error state */ - HAL_SRAM_STATE_PROTECTED = 0x04 /*!< SRAM peripheral NORSRAM device write protected */ + HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ + HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ + HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ + HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ + HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ }HAL_SRAM_StateTypeDef; diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.c index e47d6797ba5..3e6bd1bbe74 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_tim.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief TIM HAL module driver * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -215,6 +215,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -396,7 +397,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else if((htim->State == HAL_TIM_STATE_READY)) { - if((pData == 0 ) && (Length > 0)) + if((pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -490,6 +491,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -787,7 +789,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -994,6 +996,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -1141,7 +1144,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Starts the PWM signal generation in interrupt mode. * @param htim : TIM handle - * @param Channel : TIM Channel to be disabled + * @param Channel : TIM Channel to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1294,7 +1297,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -1501,6 +1504,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -1774,7 +1778,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else if((htim->State == HAL_TIM_STATE_READY)) { - if((pData == 0 ) && (Length > 0)) + if((pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -1974,6 +1978,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_OPM_MODE(OnePulseMode)); if(htim->State == HAL_TIM_STATE_RESET) @@ -2069,6 +2074,9 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2102,6 +2110,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2135,6 +2146,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and @@ -2174,6 +2188,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); @@ -2234,9 +2251,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) { - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpsmcr = 0U; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Check the TIM handle allocation */ if(htim == NULL) @@ -2246,6 +2263,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); @@ -2288,18 +2308,18 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); - tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; @@ -2581,7 +2601,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch } else if((htim->State == HAL_TIM_STATE_READY)) { - if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) + if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U)) { return HAL_ERROR; } @@ -2761,7 +2781,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) + if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) { HAL_TIM_IC_CaptureCallback(htim); } @@ -2783,7 +2803,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) + if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) { HAL_TIM_IC_CaptureCallback(htim); } @@ -2804,7 +2824,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) + if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) { HAL_TIM_IC_CaptureCallback(htim); } @@ -2825,7 +2845,7 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) + if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) { HAL_TIM_IC_CaptureCallback(htim); } @@ -3022,7 +3042,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); } else if (Channel == TIM_CHANNEL_3) { @@ -3054,7 +3074,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } htim->State = HAL_TIM_STATE_READY; @@ -3328,7 +3348,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t } else if((htim->State == HAL_TIM_STATE_READY)) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if((BurstBuffer == 0U) && (BurstLength > 0U)) { return HAL_ERROR; } @@ -3348,7 +3368,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC1: @@ -3360,7 +3380,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC2: @@ -3372,7 +3392,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC3: @@ -3384,7 +3404,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC4: @@ -3396,7 +3416,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_COM: @@ -3408,7 +3428,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_TRIGGER: @@ -3420,7 +3440,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U); } break; default: @@ -3551,7 +3571,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B } else if((htim->State == HAL_TIM_STATE_READY)) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if((BurstBuffer == 0U) && (BurstLength > 0U)) { return HAL_ERROR; } @@ -3571,7 +3591,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC1: @@ -3583,7 +3603,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC2: @@ -3595,7 +3615,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC3: @@ -3607,7 +3627,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_CC4: @@ -3619,7 +3639,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_COM: @@ -3631,7 +3651,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; case TIM_DMA_TRIGGER: @@ -3643,7 +3663,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA channel */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U); } break; default: @@ -3779,7 +3799,7 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr = 0U; /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); @@ -3797,8 +3817,6 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp { case TIM_CLEARINPUTSOURCE_NONE: { - /* Clear the OCREF clear selection bit */ - tmpsmcr &= ~TIM_SMCR_OCCS; /* Clear the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); @@ -3815,8 +3833,6 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp sClearInputConfig->ClearInputPolarity, sClearInputConfig->ClearInputFilter); - /* Set the OCREF clear selection bit */ - htim->Instance->SMCR |= TIM_SMCR_OCCS; } break; default: @@ -3904,7 +3920,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr = 0U; /* Process Locked */ __HAL_LOCK(htim); @@ -4078,7 +4094,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo */ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) { - uint32_t tmpcr2 = 0; + uint32_t tmpcr2 = 0U; /* Check the parameters */ assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); @@ -4183,7 +4199,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, */ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpreg = 0; + uint32_t tmpreg = 0U; __HAL_LOCK(htim); @@ -4552,7 +4568,7 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { - uint32_t tmpcr1 = 0; + uint32_t tmpcr1 = 0U; tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ @@ -4570,6 +4586,10 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) tmpcr1 |= (uint32_t)Structure->ClockDivision; } + /* Set the auto-reload preload */ + tmpcr1 &= ~TIM_CR1_ARPE; + tmpcr1 |= (uint32_t)Structure->AutoReloadPreload; + TIMx->CR1 = tmpcr1; /* Set the Autoreload value */ @@ -4597,9 +4617,9 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; @@ -4671,9 +4691,9 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -4691,12 +4711,12 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccmrx &= ~TIM_CCMR1_CC2S; /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4); + tmpccer |= (OC_Config->OCPolarity << 4U); if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) { @@ -4705,7 +4725,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4); + tmpccer |= (OC_Config->OCNPolarity << 4U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; @@ -4747,9 +4767,9 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; @@ -4771,7 +4791,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8); + tmpccer |= (OC_Config->OCPolarity << 8U); if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) { @@ -4780,7 +4800,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8); + tmpccer |= (OC_Config->OCNPolarity << 8U); /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; } @@ -4795,9 +4815,9 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpcr2 &= ~TIM_CR2_OIS3; tmpcr2 &= ~TIM_CR2_OIS3N; /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4); + tmpcr2 |= (OC_Config->OCIdleState << 4U); /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4); + tmpcr2 |= (OC_Config->OCNIdleState << 4U); } /* Write to TIMx CR2 */ @@ -4821,9 +4841,9 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) { - uint32_t tmpccmrx = 0; - uint32_t tmpccer = 0; - uint32_t tmpcr2 = 0; + uint32_t tmpccmrx = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; @@ -4841,12 +4861,12 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) tmpccmrx &= ~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8); + tmpccmrx |= (OC_Config->OCMode << 8U); /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12); + tmpccer |= (OC_Config->OCPolarity << 12U); if(IS_TIM_BREAK_INSTANCE(TIMx)) { @@ -4882,9 +4902,9 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) { - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpsmcr = 0U; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; @@ -4933,7 +4953,7 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); /* Write to TIMx CCMR1 and CCER registers */ htim->Instance->CCMR1 = tmpccmr1; @@ -5010,7 +5030,6 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. @@ -5026,8 +5045,8 @@ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; @@ -5047,7 +5066,7 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); @@ -5064,16 +5083,15 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE + * @arg TIM_ICPOLARITY_FALLING * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; @@ -5082,7 +5100,7 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4); + tmpccmr1 |= (TIM_ICFilter << 4U); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); @@ -5099,8 +5117,7 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE + * @arg TIM_ICPOLARITY_FALLING * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. @@ -5116,8 +5133,8 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -5126,15 +5143,15 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Select the Input */ tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8); + tmpccmr1 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; @@ -5147,16 +5164,15 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE + * @arg TIM_ICPOLARITY_FALLING * @param TIM_ICFilter : Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; @@ -5165,11 +5181,11 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12); + tmpccmr1 |= (TIM_ICFilter << 12U); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4); + tmpccer |= (TIM_ICPolarity << 4U); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; @@ -5182,8 +5198,7 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE + * @arg TIM_ICPOLARITY_FALLING * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. @@ -5199,8 +5214,8 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; @@ -5213,11 +5228,11 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -5230,8 +5245,7 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE + * @arg TIM_ICPOLARITY_FALLING * @param TIM_ICSelection : specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. @@ -5247,8 +5261,8 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter) { - uint32_t tmpccmr2 = 0; - uint32_t tmpccer = 0; + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; @@ -5257,15 +5271,15 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Select the Input */ tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8); + tmpccmr2 |= (TIM_ICSelection << 8U); /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); /* Select the Polarity and set the CC4E Bit */ - tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + tmpccer &= ~TIM_CCER_CC4P; + tmpccer |= ((TIM_ICPolarity << 12U) & TIM_CCER_CC4P); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -5289,7 +5303,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr = 0U; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; @@ -5320,7 +5334,7 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { - uint32_t tmpsmcr = 0; + uint32_t tmpsmcr = 0U; tmpsmcr = TIMx->SMCR; @@ -5328,7 +5342,7 @@ static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; @@ -5349,7 +5363,7 @@ static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, */ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) { - uint32_t tmp = 0; + uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.h index 91d0a07aa81..ad4d8853321 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_tim.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention @@ -84,6 +84,9 @@ typedef struct - the number of half PWM period in center-aligned mode This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ } TIM_Base_InitTypeDef; /** @@ -261,11 +264,11 @@ typedef struct { */ typedef enum { - HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ }HAL_TIM_StateTypeDef; /** @@ -273,11 +276,11 @@ typedef enum */ typedef enum { - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ }HAL_TIM_ActiveChannel; /** @@ -285,12 +288,12 @@ typedef enum */ typedef struct { - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref TIM_DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7U]; /*!< DMA Handlers array + This array is accessed by a @ref TIM_DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ }TIM_HandleTypeDef; @@ -306,7 +309,7 @@ typedef struct /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity * @{ */ -#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ /** @@ -317,7 +320,7 @@ typedef struct * @{ */ #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ /** * @} */ @@ -325,7 +328,7 @@ typedef struct /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler * @{ */ -#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ @@ -336,7 +339,7 @@ typedef struct /** @defgroup TIM_Counter_Mode TIM Counter Mode * @{ */ -#define TIM_COUNTERMODE_UP ((uint32_t)0x0000) +#define TIM_COUNTERMODE_UP 0x00000000U #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 @@ -348,17 +351,26 @@ typedef struct /** @defgroup TIM_ClockDivision TIM ClockDivision * @{ */ -#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) +#define TIM_CLOCKDIVISION_DIV1 0x00000000U #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) /** * @} */ +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */ +/** + * @} + */ + /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes * @{ */ -#define TIM_OCMODE_TIMING ((uint32_t)0x0000) +#define TIM_OCMODE_TIMING 0x00000000U #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) @@ -373,7 +385,7 @@ typedef struct /** @defgroup TIM_Output_Compare_State TIM Output Compare State * @{ */ -#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) /** * @} @@ -382,7 +394,7 @@ typedef struct /** @defgroup TIM_Output_Fast_State TIM Output Fast State * @{ */ -#define TIM_OCFAST_DISABLE ((uint32_t)0x0000) +#define TIM_OCFAST_DISABLE 0x00000000U #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) /** * @} @@ -391,7 +403,7 @@ typedef struct /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State * @{ */ -#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) /** * @} @@ -400,7 +412,7 @@ typedef struct /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity * @{ */ -#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCPOLARITY_HIGH 0x00000000U #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) /** * @} @@ -409,7 +421,7 @@ typedef struct /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity * @{ */ -#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000) +#define TIM_OCNPOLARITY_HIGH 0x00000000U #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP) /** * @} @@ -419,7 +431,7 @@ typedef struct * @{ */ #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1) -#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000) +#define TIM_OCIDLESTATE_RESET 0x00000000U /** * @} */ @@ -428,7 +440,7 @@ typedef struct * @{ */ #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N) -#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000) +#define TIM_OCNIDLESTATE_RESET 0x00000000U /** * @} */ @@ -436,11 +448,11 @@ typedef struct /** @defgroup TIM_Channel TIM Channel * @{ */ -#define TIM_CHANNEL_1 ((uint32_t)0x0000) -#define TIM_CHANNEL_2 ((uint32_t)0x0004) -#define TIM_CHANNEL_3 ((uint32_t)0x0008) -#define TIM_CHANNEL_4 ((uint32_t)0x000C) -#define TIM_CHANNEL_ALL ((uint32_t)0x0018) +#define TIM_CHANNEL_1 0x00000000U +#define TIM_CHANNEL_2 0x00000004U +#define TIM_CHANNEL_3 0x00000008U +#define TIM_CHANNEL_4 0x0000000CU +#define TIM_CHANNEL_ALL 0x00000018U /** * @} */ @@ -450,7 +462,6 @@ typedef struct */ #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /** * @} */ @@ -470,7 +481,7 @@ typedef struct /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler * @{ */ -#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ @@ -482,7 +493,7 @@ typedef struct * @{ */ #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) -#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) +#define TIM_OPMODE_REPETITIVE 0x00000000U /** * @} */ @@ -516,7 +527,7 @@ typedef struct * @{ */ #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS) -#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000) +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /** * @} @@ -590,9 +601,9 @@ typedef struct /** @defgroup TIM_Clock_Polarity TIM Clock Polarity * @{ */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ /** @@ -613,9 +624,8 @@ typedef struct /** @defgroup TIM_ClearInput_Source TIM ClearInput Source * @{ */ -#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) -#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002) -#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /** * @} */ @@ -624,7 +634,7 @@ typedef struct * @{ */ #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ /** * @} */ @@ -644,7 +654,7 @@ typedef struct * @{ */ #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR) -#define TIM_OSSR_DISABLE ((uint32_t)0x0000) +#define TIM_OSSR_DISABLE 0x00000000U /** * @} */ @@ -653,7 +663,7 @@ typedef struct * @{ */ #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI) -#define TIM_OSSI_DISABLE ((uint32_t)0x0000) +#define TIM_OSSI_DISABLE 0x00000000U /** * @} */ @@ -661,7 +671,7 @@ typedef struct /** @defgroup TIM_Lock_level TIM Lock level * @{ */ -#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000) +#define TIM_LOCKLEVEL_OFF 0x00000000U #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0) #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1) #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK) @@ -673,7 +683,7 @@ typedef struct * @{ */ #define TIM_BREAK_ENABLE (TIM_BDTR_BKE) -#define TIM_BREAK_DISABLE ((uint32_t)0x0000) +#define TIM_BREAK_DISABLE 0x00000000U /** * @} */ @@ -681,7 +691,7 @@ typedef struct /** @defgroup TIM_Break_Polarity TIM Break Input Polarity * @{ */ -#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000) +#define TIM_BREAKPOLARITY_LOW 0x00000000U #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP) /** * @} @@ -690,7 +700,7 @@ typedef struct * @{ */ #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE) -#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000) +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /** * @} */ @@ -698,7 +708,7 @@ typedef struct /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_RESET 0x00000000U #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) @@ -713,11 +723,11 @@ typedef struct /** @defgroup TIM_Slave_Mode TIM Slave Mode * @{ */ -#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) -#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004) -#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) -#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) -#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) +#define TIM_SLAVEMODE_DISABLE 0x00000000U +#define TIM_SLAVEMODE_RESET 0x00000004U +#define TIM_SLAVEMODE_GATED 0x00000005U +#define TIM_SLAVEMODE_TRIGGER 0x00000006U +#define TIM_SLAVEMODE_EXTERNAL1 0x00000007U /** * @} */ @@ -725,8 +735,8 @@ typedef struct /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode * @{ */ -#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) -#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) +#define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /** * @} */ @@ -734,15 +744,15 @@ typedef struct /** @defgroup TIM_Trigger_Selection TIM Trigger Selection * @{ */ -#define TIM_TS_ITR0 ((uint32_t)0x0000) -#define TIM_TS_ITR1 ((uint32_t)0x0010) -#define TIM_TS_ITR2 ((uint32_t)0x0020) -#define TIM_TS_ITR3 ((uint32_t)0x0030) -#define TIM_TS_TI1F_ED ((uint32_t)0x0040) -#define TIM_TS_TI1FP1 ((uint32_t)0x0050) -#define TIM_TS_TI2FP2 ((uint32_t)0x0060) -#define TIM_TS_ETRF ((uint32_t)0x0070) -#define TIM_TS_NONE ((uint32_t)0xFFFF) +#define TIM_TS_ITR0 0x00000000U +#define TIM_TS_ITR1 0x00000010U +#define TIM_TS_ITR2 0x00000020U +#define TIM_TS_ITR3 0x00000030U +#define TIM_TS_TI1F_ED 0x00000040U +#define TIM_TS_TI1FP1 0x00000050U +#define TIM_TS_TI2FP2 0x00000060U +#define TIM_TS_ETRF 0x00000070U +#define TIM_TS_NONE 0x0000FFFFU /** * @} */ @@ -773,7 +783,7 @@ typedef struct /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection * @{ */ -#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) +#define TIM_TI1SELECTION_CH1 0x00000000U #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) /** * @} @@ -782,25 +792,25 @@ typedef struct /** @defgroup TIM_DMA_Base_address TIM DMA Base Address * @{ */ -#define TIM_DMABASE_CR1 (0x00000000) -#define TIM_DMABASE_CR2 (0x00000001) -#define TIM_DMABASE_SMCR (0x00000002) -#define TIM_DMABASE_DIER (0x00000003) -#define TIM_DMABASE_SR (0x00000004) -#define TIM_DMABASE_EGR (0x00000005) -#define TIM_DMABASE_CCMR1 (0x00000006) -#define TIM_DMABASE_CCMR2 (0x00000007) -#define TIM_DMABASE_CCER (0x00000008) -#define TIM_DMABASE_CNT (0x00000009) -#define TIM_DMABASE_PSC (0x0000000A) -#define TIM_DMABASE_ARR (0x0000000B) -#define TIM_DMABASE_RCR (0x0000000C) -#define TIM_DMABASE_CCR1 (0x0000000D) -#define TIM_DMABASE_CCR2 (0x0000000E) -#define TIM_DMABASE_CCR3 (0x0000000F) -#define TIM_DMABASE_CCR4 (0x00000010) -#define TIM_DMABASE_BDTR (0x00000011) -#define TIM_DMABASE_DCR (0x00000012) +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U /** * @} */ @@ -808,24 +818,24 @@ typedef struct /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) -#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) -#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) -#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) -#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) -#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) -#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) -#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) -#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) -#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) -#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) -#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) -#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) -#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) -#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) -#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) -#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) -#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /** * @} */ @@ -833,13 +843,13 @@ typedef struct /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index * @{ */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ +#define TIM_DMA_ID_UPDATE ((uint16_t)0x0) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t)0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t)0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t)0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t)0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t)0x5) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t)0x6) /*!< Index of the DMA handle used for Trigger DMA requests */ /** * @} */ @@ -847,10 +857,10 @@ typedef struct /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State * @{ */ -#define TIM_CCx_ENABLE ((uint32_t)0x0001) -#define TIM_CCx_DISABLE ((uint32_t)0x0000) -#define TIM_CCxN_ENABLE ((uint32_t)0x0004) -#define TIM_CCxN_DISABLE ((uint32_t)0x0000) +#define TIM_CCx_ENABLE 0x00000001U +#define TIM_CCx_DISABLE 0x00000000U +#define TIM_CCxN_ENABLE 0x00000004U +#define TIM_CCxN_DISABLE 0x00000000U /** * @} */ @@ -888,6 +898,9 @@ typedef struct ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ ((DIV) == TIM_CLOCKDIVISION_DIV4)) +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ ((MODE) == TIM_OCMODE_PWM2)) @@ -918,17 +931,16 @@ typedef struct ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4) || \ ((CHANNEL) == TIM_CHANNEL_ALL)) - + #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - + ((CHANNEL) == TIM_CHANNEL_2)) + #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3)) #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ - ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ - ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) + ((POLARITY) == TIM_ICPOLARITY_FALLING)) #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ @@ -946,9 +958,9 @@ typedef struct ((MODE) == TIM_ENCODERMODE_TI2) || \ ((MODE) == TIM_ENCODERMODE_TI12)) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U)) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U)) #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ @@ -972,10 +984,9 @@ typedef struct ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \ ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE)) #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ @@ -986,7 +997,7 @@ typedef struct ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) -#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \ ((STATE) == TIM_OSSR_DISABLE)) @@ -1052,7 +1063,7 @@ typedef struct ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) -#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU) #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) @@ -1096,7 +1107,7 @@ typedef struct ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS)) -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU) /** @brief Set TIM IC prescaler * @param __HANDLE__: TIM handle @@ -1106,9 +1117,9 @@ typedef struct */ #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) /** @brief Reset TIM IC prescaler * @param __HANDLE__: TIM handle @@ -1130,9 +1141,9 @@ typedef struct */ #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P))) /** @brief Reset TIM IC polarity * @param __HANDLE__: TIM handle @@ -1196,14 +1207,14 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat */ #define __HAL_TIM_DISABLE(__HANDLE__) \ do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \ { \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ } \ } \ - } while(0) + } while(0U) /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ /** @@ -1214,14 +1225,22 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \ { \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ } \ } \ - } while(0) + } while(0U) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__: TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) /** * @brief Enables the specified TIM interrupt. @@ -1229,11 +1248,11 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat * @param __INTERRUPT__: specifies the TIM interrupt source to enable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval None @@ -1246,11 +1265,11 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat * @param __INTERRUPT__: specifies the TIM interrupt source to disable. * This parameter can be one of the following values: * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt * @arg TIM_IT_CC2: Capture/Compare 2 interrupt * @arg TIM_IT_CC3: Capture/Compare 3 interrupt * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_COM: Commutation interrupt * @arg TIM_IT_TRIGGER: Trigger interrupt * @arg TIM_IT_BREAK: Break interrupt * @retval None @@ -1263,11 +1282,11 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat * @param __DMA__: specifies the TIM DMA request to enable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ @@ -1279,11 +1298,11 @@ void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelStat * @param __DMA__: specifies the TIM DMA request to disable. * This parameter can be one of the following values: * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_COM: Commutation DMA request * @arg TIM_DMA_TRIGGER: Trigger DMA request * @retval None */ @@ -1378,7 +1397,7 @@ mode. * @retval None */ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ -(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) +(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) /** * @brief Gets the TIM Capture Compare Register value on runtime @@ -1389,10 +1408,10 @@ mode. * @arg TIM_CHANNEL_2: get capture/compare 2 register value * @arg TIM_CHANNEL_3: get capture/compare 3 register value * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @retval None + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) */ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ - (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) + (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) /** * @brief Sets the TIM Counter Register value on runtime. @@ -1405,7 +1424,7 @@ mode. /** * @brief Gets the TIM Counter Register value on runtime. * @param __HANDLE__: TIM handle. - * @retval None + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) */ #define __HAL_TIM_GET_COUNTER(__HANDLE__) \ ((__HANDLE__)->Instance->CNT) @@ -1421,12 +1440,12 @@ mode. do{ \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) + } while(0U) /** * @brief Gets the TIM Autoreload Register value on runtime * @param __HANDLE__: TIM handle. - * @retval None + * @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) */ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ ((__HANDLE__)->Instance->ARR) @@ -1437,22 +1456,25 @@ mode. * @param __HANDLE__: TIM handle. * @param __CKD__: specifies the clock division value. * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1 - * @arg TIM_CLOCKDIVISION_DIV2 - * @arg TIM_CLOCKDIVISION_DIV4 + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @retval None */ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ + do{ \ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) + } while(0U) /** * @brief Gets the TIM Clock Division value on runtime * @param __HANDLE__: TIM handle. - * @retval None + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT */ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) @@ -1479,7 +1501,7 @@ mode. do{ \ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) + } while(0U) /** * @brief Gets the TIM Input Capture prescaler on runtime @@ -1490,13 +1512,17 @@ mode. * @arg TIM_CHANNEL_2: get input capture 2 prescaler value * @arg TIM_CHANNEL_3: get input capture 3 prescaler value * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval None + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events */ #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register @@ -1543,7 +1569,7 @@ mode. do{ \ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) + }while(0U) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.c index 1a0daa6696f..9fae96da0d3 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer Extended peripheral: @@ -177,6 +177,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); @@ -400,7 +401,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -625,7 +626,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpccer = 0; + uint32_t tmpccer = 0U; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -709,7 +710,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -1041,7 +1042,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) { - uint32_t tmpccer = 0; + uint32_t tmpccer = 0U; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1125,7 +1126,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0U) && (Length > 0U)) { return HAL_ERROR; } @@ -1625,6 +1626,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { + uint32_t tmpbdtr = 0U; + /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); @@ -1638,21 +1641,22 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ - htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode | - sBreakDeadTimeConfig->OffStateIDLEMode | - sBreakDeadTimeConfig->LockLevel | - sBreakDeadTimeConfig->DeadTime | - sBreakDeadTimeConfig->BreakState | - sBreakDeadTimeConfig->BreakPolarity | - sBreakDeadTimeConfig->AutomaticOutput; - - - htim->State = HAL_TIM_STATE_READY; - + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput); + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + __HAL_UNLOCK(htim); return HAL_OK; @@ -1826,7 +1830,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) */ static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState) { - uint32_t tmp = 0; + uint32_t tmp = 0U; tmp = TIM_CCER_CC1NE << Channel; diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.h index 29380e8f6a8..1e2d4a54634 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention @@ -66,17 +66,17 @@ typedef struct { - + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - + uint32_t IC1Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ } TIM_HallSensor_InitTypeDef; @@ -134,7 +134,7 @@ typedef struct { /** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter * @{ */ -#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF) /*!< BreakDead Time */ +#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /*!< BreakDead Time */ /** * @} */ @@ -147,6 +147,39 @@ typedef struct { /* defined(STM32F105xC) || defined(STM32F107xC) */ /* Exported macro ------------------------------------------------------------*/ +/** + * @brief Sets the TIM Output compare preload. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__: TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) + +/** + * @brief Resets the TIM Output compare preload. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__: TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ + ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE)) /* Exported functions --------------------------------------------------------*/ /** @addtogroup TIMEx_Exported_Functions diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.c index b437ce83934..0e3e8603e72 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.c @@ -2,29 +2,28 @@ ****************************************************************************** * @file stm32f1xx_hal_uart.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions + * + Peripheral Control functions + * + Peripheral State and Errors functions @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] The UART HAL driver can be used as follows: - - (#) Declare a UART_HandleTypeDef handle structure. + (#) Declare a UART_HandleTypeDef handle structure. (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: (##) Enable the USARTx interface clock. (##) UART pins configuration: (+++) Enable the clock for the UART GPIOs. - (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). + (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input). (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() and HAL_UART_Receive_IT() APIs): (+++) Configure the USARTx interrupt priority. @@ -64,18 +63,18 @@ [..] (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the - low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed + low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized HAL_UART_MspInit() API. - [..] - Three operation modes are available within this driver : + [..] + Three operation modes are available within this driver: *** Polling mode IO operation *** ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_UART_Transmit() + [..] + (+) Send an amount of data in blocking mode using HAL_UART_Transmit() (+) Receive an amount of data in blocking mode using HAL_UART_Receive() - + *** Interrupt mode IO operation *** =================================== [..] @@ -122,12 +121,27 @@ [..] (@) You can refer to the UART HAL driver header file for more useful macros - @endverbatim + [..] + (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible UART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | UART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -166,31 +180,42 @@ * @{ */ #ifdef HAL_UART_MODULE_ENABLED - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UART_Private_Constants + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup UART_Private_Functions UART Private Functions +/** @addtogroup UART_Private_Functions * @{ */ -static void UART_SetConfig (UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static void UART_SetConfig (UART_HandleTypeDef *huart); /** * @} */ - /* Exported functions ---------------------------------------------------------*/ - /** @defgroup UART_Exported_Functions UART Exported Functions * @{ */ @@ -199,9 +224,9 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, * @brief Initialization and Configuration functions * @verbatim -=============================================================================== + ============================================================================== ##### Initialization and Configuration functions ##### - =============================================================================== + ============================================================================== [..] This subsection provides a set of functions allowing to initialize the USARTx or the UARTy in asynchronous mode. @@ -209,42 +234,27 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, (++) Baud Rate (++) Word Length (++) Stop Bit - (++) Parity + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + please refer to Reference manual for possible UART frame formats. (++) Hardware flow control (++) Receiver/transmitter modes + (++) Over Sampling Method [..] The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration procedures (details for the procedures are available in reference manuals (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)). - @endverbatim * @{ */ -/* - Additionnal remark: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible UART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | UART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ -*/ - /** * @brief Initializes the UART mode according to the specified parameters in * the UART_InitTypeDef and create the associated handle. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -268,18 +278,20 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ - if(huart->State == HAL_UART_STATE_RESET) + if(huart->gState == HAL_UART_STATE_RESET) { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - + /* Init the low level hardware */ HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the peripheral */ __HAL_UART_DISABLE(huart); @@ -298,7 +310,8 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State= HAL_UART_STATE_READY; + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; return HAL_OK; } @@ -306,7 +319,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) /** * @brief Initializes the half-duplex mode according to the specified * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -317,22 +330,22 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) { return HAL_ERROR; } - - /* Check UART instance */ + + /* Check the parameters */ assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); - - if(huart->State == HAL_UART_STATE_RESET) - { +#endif /* USART_CR1_OVER8 */ + if(huart->gState == HAL_UART_STATE_RESET) + { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the peripheral */ __HAL_UART_DISABLE(huart); @@ -340,7 +353,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* Set the UART Communication parameters */ UART_SetConfig(huart); - /* In half-duplex mode, the following bits must be kept cleared: + /* In half-duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); @@ -354,7 +367,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* Initialize the UART state*/ huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State= HAL_UART_STATE_READY; + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; return HAL_OK; } @@ -362,7 +376,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /** * @brief Initializes the LIN mode according to the specified * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @param BreakDetectLength: Specifies the LIN break detection length. * This parameter can be one of the following values: @@ -383,18 +397,19 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /* Check the Break detection length parameter */ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ - if(huart->State == HAL_UART_STATE_RESET) - { + if(huart->gState == HAL_UART_STATE_RESET) + { /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - + huart->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the peripheral */ __HAL_UART_DISABLE(huart); @@ -419,7 +434,8 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /* Initialize the UART state*/ huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State= HAL_UART_STATE_READY; + huart->gState= HAL_UART_STATE_READY; + huart->RxState= HAL_UART_STATE_READY; return HAL_OK; } @@ -427,13 +443,13 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /** * @brief Initializes the Multi-Processor mode according to the specified * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. - * @param Address: UART node address - * @param WakeUpMethod: specifies the UART wakeup method. + * @param Address: USART address + * @param WakeUpMethod: specifies the USART wake-up method. * This parameter can be one of the following values: - * @arg UART_WAKEUPMETHOD_IDLELINE: Wakeup by an idle line detection - * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wakeup by an address mark + * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection + * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) @@ -451,18 +467,19 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); assert_param(IS_UART_ADDRESS(Address)); assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); +#if defined(USART_CR1_OVER8) assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); +#endif /* USART_CR1_OVER8 */ - if(huart->State == HAL_UART_STATE_RESET) - { + if(huart->gState == HAL_UART_STATE_RESET) + { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ HAL_UART_MspInit(huart); } - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the peripheral */ __HAL_UART_DISABLE(huart); @@ -487,14 +504,15 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State= HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; return HAL_OK; } /** * @brief DeInitializes the UART peripheral. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -505,24 +523,18 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); - huart->State = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - huart->Instance->CR1 = 0x0; - huart->Instance->CR2 = 0x0; - huart->Instance->CR3 = 0x0; - + huart->gState = HAL_UART_STATE_BUSY; + /* DeInit the low level hardware */ HAL_UART_MspDeInit(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->State = HAL_UART_STATE_RESET; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; /* Process Unlock */ __HAL_UNLOCK(huart); @@ -532,32 +544,32 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) /** * @brief UART MSP Init. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ - __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_MspInit can be implemented in the user file - */ + the HAL_UART_MspInit could be implemented in the user file + */ } /** * @brief UART MSP DeInit. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ - __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_MspDeInit can be implemented in the user file - */ + the HAL_UART_MspDeInit could be implemented in the user file + */ } /** @@ -570,7 +582,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) @verbatim ============================================================================== ##### IO operation functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides a set of functions allowing to manage the UART asynchronous and Half duplex data transfers. @@ -612,18 +624,18 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) (++) HAL_UART_RxCpltCallback() (++) HAL_UART_ErrorCallback() - [..] + [..] (@) In the Half duplex communication, it is forbidden to run the transmit - and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. - + @endverbatim * @{ */ /** - * @brief Sends an amount of data in blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @brief Sends an amount of data in blocking mode. + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -633,12 +645,12 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; - uint32_t tmp_state = 0; + uint32_t tickstart = 0U; - tmp_state = huart->State; - if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -647,24 +659,19 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a non-blocking receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); huart->TxXferSize = Size; huart->TxXferCount = Size; - while(huart->TxXferCount > 0) + while(huart->TxXferCount > 0U) { huart->TxXferCount--; if(huart->Init.WordLength == UART_WORDLENGTH_9B) { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -672,16 +679,16 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->Instance->DR = (*tmp & (uint16_t)0x01FF); if(huart->Init.Parity == UART_PARITY_NONE) { - pData +=2; + pData +=2U; } else - { - pData +=1; + { + pData +=1U; } - } + } else { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -689,20 +696,13 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u } } - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK) - { + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { return HAL_TIMEOUT; } - /* Check if a non-blocking receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -716,8 +716,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u } /** - * @brief Receives an amount of data in blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @brief Receive an amount of data in blocking mode. + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received @@ -727,59 +727,54 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint16_t* tmp; - uint32_t tmp_state = 0; - - tmp_state = huart->State; - if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_TX)) + uint32_t tickstart = 0U; + + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(huart); - + huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a non-blocking transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); huart->RxXferSize = Size; huart->RxXferCount = Size; /* Check the remain data to be received */ - while(huart->RxXferCount > 0) + while(huart->RxXferCount > 0U) { huart->RxXferCount--; if(huart->Init.WordLength == UART_WORDLENGTH_9B) { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - tmp = (uint16_t*) pData ; + tmp = (uint16_t*)pData; if(huart->Init.Parity == UART_PARITY_NONE) { *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); - pData +=2; + pData +=2U; } else { *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); - pData +=1; + pData +=1U; } - } + } else { - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -795,15 +790,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui } } - /* Check if a non-blocking transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -817,7 +806,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Sends an amount of data in non blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -825,40 +814,29 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - uint32_t tmp_state = 0; - - tmp_state = huart->State; - if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_RX)) + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); - + huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } + huart->gState = HAL_UART_STATE_BUSY_TX; /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Transmit data register empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); - + return HAL_OK; } else @@ -868,8 +846,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData } /** - * @brief Receives an amount of data in non blocking mode - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @brief Receives an amount of data in non blocking mode. + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received @@ -877,12 +855,10 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { - uint32_t tmp_state = 0; - - tmp_state = huart->State; - if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_TX)) + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -895,16 +871,8 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, huart->RxXferCount = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - + huart->RxState = HAL_UART_STATE_BUSY_RX; + /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -927,7 +895,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Sends an amount of data in non blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -936,12 +904,11 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - uint32_t tmp_state = 0; - - tmp_state = huart->State; - if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_RX)) + + /* Check that a Tx process is not already ongoing */ + if(huart->gState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -954,15 +921,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat huart->TxXferCount = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_TX; - } + huart->gState = HAL_UART_STATE_BUSY_TX; /* Set the UART DMA transfer complete callback */ huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; @@ -973,6 +932,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Set the DMA error callback */ huart->hdmatx->XferErrorCallback = UART_DMAError; + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + /* Enable the UART transmit DMA channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size); @@ -980,13 +942,13 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); + /* Process Unlocked */ + __HAL_UNLOCK(huart); + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } else @@ -997,23 +959,21 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /** * @brief Receives an amount of data in non blocking mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @param pData: Pointer to data buffer * @param Size: Amount of data to be received - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position) + * @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { uint32_t *tmp; - uint32_t tmp_state = 0; - - tmp_state = huart->State; - if((tmp_state == HAL_UART_STATE_READY) || (tmp_state == HAL_UART_STATE_BUSY_TX)) + + /* Check that a Rx process is not already ongoing */ + if(huart->RxState == HAL_UART_STATE_READY) { - if((pData == NULL ) || (Size == 0)) + if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1025,15 +985,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData huart->RxXferSize = Size; huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX) - { - huart->State = HAL_UART_STATE_BUSY_TX_RX; - } - else - { - huart->State = HAL_UART_STATE_BUSY_RX; - } + huart->RxState = HAL_UART_STATE_BUSY_RX; /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; @@ -1044,17 +996,29 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + /* Enable the DMA channel */ tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size); - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ + __HAL_UART_CLEAR_OREFLAG(huart); /* Process Unlocked */ __HAL_UNLOCK(huart); + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + return HAL_OK; } else @@ -1062,50 +1026,47 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_BUSY; } } - + /** * @brief Pauses the DMA Transfer. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { + uint32_t dmarequest = 0x00U; + /* Process Locked */ __HAL_LOCK(huart); - - if(huart->State == HAL_UART_STATE_BUSY_TX) + + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) { /* Disable the UART DMA Tx request */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } - else if(huart->State == HAL_UART_STATE_BUSY_RX) + + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Disable the UART DMA Rx request */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - else if (huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - /* Disable the UART DMA Tx & Rx requests */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_ERROR; - } - + /* Process Unlocked */ __HAL_UNLOCK(huart); - - return HAL_OK; + + return HAL_OK; } /** * @brief Resumes the DMA Transfer. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1113,152 +1074,610 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { /* Process Locked */ __HAL_LOCK(huart); - - if(huart->State == HAL_UART_STATE_BUSY_TX) + + if(huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } - else if(huart->State == HAL_UART_STATE_BUSY_RX) + + if(huart->RxState == HAL_UART_STATE_BUSY_RX) { - /* Clear the Overrun flag before resumming the Rx transfer*/ + /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_UART_CLEAR_OREFLAG(huart); + + /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Enable the UART DMA Rx request */ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - else if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - /* Clear the Overrun flag before resumming the Rx transfer*/ - __HAL_UART_CLEAR_OREFLAG(huart); - /* Enable the UART DMA Tx & Rx request */ - SET_BIT(huart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_ERROR; - } /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_OK; } /** * @brief Stops the DMA Transfer. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) { + uint32_t dmarequest = 0x00U; /* The Lock is not implemented on this API to allow the user application to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() */ - - /* Disable the UART Tx/Rx DMA requests */ - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); - - /* Abort the UART DMA tx channel */ - if(huart->hdmatx != NULL) + + /* Stop UART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) { - HAL_DMA_Abort(huart->hdmatx); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if(huart->hdmatx != NULL) + { + HAL_DMA_Abort(huart->hdmatx); + } + UART_EndTxTransfer(huart); } - /* Abort the UART DMA rx channel */ - if(huart->hdmarx != NULL) + + /* Stop UART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) { - HAL_DMA_Abort(huart->hdmarx); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if(huart->hdmarx != NULL) + { + HAL_DMA_Abort(huart->hdmarx); + } + UART_EndRxTransfer(huart); } - - huart->State = HAL_UART_STATE_READY; - + return HAL_OK; } /** - * @brief This function handles UART interrupt request. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { - uint32_t tmp_flag = 0, tmp_it_source = 0; - - tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_PE); - tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE); - /* UART parity error interrupt occurred ------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - huart->ErrorCode |= HAL_UART_ERROR_PE; - } + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_FE); - tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR); - /* UART frame error interrupt occurred -------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - huart->ErrorCode |= HAL_UART_ERROR_FE; + /* Disable the UART DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */ + if(huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + HAL_DMA_Abort(huart->hdmatx); + } } - - tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_NE); - /* UART noise error interrupt occurred -------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - huart->ErrorCode |= HAL_UART_ERROR_NE; + + /* Disable the UART DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */ + if(huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + HAL_DMA_Abort(huart->hdmarx); + } } - - tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_ORE); - /* UART Over-Run interrupt occurred ----------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - huart->ErrorCode |= HAL_UART_ERROR_ORE; + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->RxState and huart->gState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + HAL_DMA_Abort(huart->hdmatx); + } } - - tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE); - tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE); - /* UART in mode Receiver ---------------------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) - { - UART_Receive_IT(huart); + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + HAL_DMA_Abort(huart->hdmarx); + } } - - tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE); - tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE); + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t AbortCplt = 0x01U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if(huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if(huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the UART DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if(huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* Disable the UART DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if(huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + AbortCplt = 0x01U; + } + else + { + AbortCplt = 0x00U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if(AbortCplt == 0x01U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Disable the UART DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_UART_AbortTransmitCpltCallback(huart); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_UART_AbortTransmitCpltCallback(huart); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_UART_AbortReceiveCpltCallback(huart); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_UART_AbortReceiveCpltCallback(huart); + } + + return HAL_OK; +} + +/** + * @brief This function handles UART interrupt request. + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->SR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + uint32_t errorflags = 0x00U; + uint32_t dmarequest = 0x00U; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); + if(errorflags == RESET) + { + /* UART in mode Receiver -------------------------------------------------*/ + if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + return; + } + } + + /* If some errors occur */ + if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + { + /* UART parity error interrupt occurred ----------------------------------*/ + if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART noise error interrupt occurred -----------------------------------*/ + if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART frame error interrupt occurred -----------------------------------*/ + if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART Over-Run interrupt occurred --------------------------------------*/ + if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* Call UART Error Call back function if need be --------------------------*/ + if(huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver -----------------------------------------------*/ + if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + UART_Receive_IT(huart); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if(((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Disable the UART DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if(huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + if(HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_UART_ErrorCallback(huart); + } + } + else + { + /* Call user error callback */ + HAL_UART_ErrorCallback(huart); + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ + HAL_UART_ErrorCallback(huart); + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + } /* End if some error occurs */ + /* UART in mode Transmitter ------------------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) { UART_Transmit_IT(huart); + return; } - - tmp_flag = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC); - tmp_it_source = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC); + /* UART in mode Transmitter end --------------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { UART_EndTransmit_IT(huart); - } - - if(huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* Clear all the error flag at once */ - __HAL_UART_CLEAR_PEFLAG(huart); - - /* Set the UART state ready to be able to start again the process */ - huart->State = HAL_UART_STATE_READY; - - HAL_UART_ErrorCallback(huart); - } + return; + } } /** * @brief Tx Transfer completed callbacks. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1266,14 +1685,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback can be implemented in the user file + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback could be implemented in the user file */ } /** * @brief Tx Half Transfer completed callbacks. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1281,14 +1700,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxHalfCpltCallback can be implemented in the user file + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback could be implemented in the user file */ } /** * @brief Rx Transfer completed callbacks. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1296,14 +1715,14 @@ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback can be implemented in the user file + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback could be implemented in the user file */ } /** * @brief Rx Half Transfer completed callbacks. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ @@ -1311,26 +1730,70 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxHalfCpltCallback can be implemented in the user file + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback could be implemented in the user file */ } /** * @brief UART error callbacks. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback can be implemented in the user file + UNUSED(huart); + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback could be implemented in the user file */ } +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + /** * @} */ @@ -1356,7 +1819,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) /** * @brief Transmits break characters. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1368,12 +1831,12 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Send break characters */ SET_BIT(huart->Instance->CR1, USART_CR1_SBK); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1383,7 +1846,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /** * @brief Enters the UART in mute mode. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1395,12 +1858,12 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ SET_BIT(huart->Instance->CR1, USART_CR1_RWU); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1410,7 +1873,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) /** * @brief Exits the UART mute mode: wake up software. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1422,12 +1885,12 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1437,23 +1900,32 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) /** * @brief Enables the UART transmitter and disables the UART receiver. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { + uint32_t tmpreg = 0x00U; + /* Process Locked */ __HAL_LOCK(huart); - huart->State = HAL_UART_STATE_BUSY; + huart->gState = HAL_UART_STATE_BUSY; /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE), USART_CR1_TE); - - huart->State = HAL_UART_STATE_READY; + tmpreg |= (uint32_t)USART_CR1_TE; + + /* Write to USART CR1 */ + WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); + + huart->gState = HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1463,24 +1935,33 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) /** * @brief Enables the UART receiver and disables the UART transmitter. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { + uint32_t tmpreg = 0x00U; + /* Process Locked */ __HAL_LOCK(huart); - - huart->State = HAL_UART_STATE_BUSY; + + huart->gState = HAL_UART_STATE_BUSY; /*-------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = huart->Instance->CR1; + /* Clear TE and RE bits */ + tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE), USART_CR1_RE); - - huart->State = HAL_UART_STATE_READY; - + tmpreg |= (uint32_t)USART_CR1_RE; + + /* Write to USART CR1 */ + WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); + + huart->gState = HAL_UART_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1511,21 +1992,25 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) /** * @brief Returns the UART state. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - return huart->State; + uint32_t temp1= 0x00U, temp2 = 0x00U; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); } /** -* @brief Return the UART error code -* @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @brief Return the UART error code + * @param huart : pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. -* @retval UART Error Code -*/ + * @retval UART Error Code + */ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) { return huart->ErrorCode; @@ -1535,34 +2020,26 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) * @} */ -/** - * @} - */ - -/** @defgroup UART_Private_Functions UART Private Functions - * @brief UART Private functions - * @{ - */ /** * @brief DMA UART transmit process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @param hdma: DMA handle * @retval None */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode*/ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - huart->TxXferCount = 0; + huart->TxXferCount = 0U; /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - /* Enable the UART Transmit Complete Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + /* Enable the UART Transmit Complete Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } /* DMA Circular mode */ else @@ -1573,8 +2050,8 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART transmit process half complete callback - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1586,132 +2063,271 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA UART receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @param hdma: DMA handle * @retval None */ -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; /* DMA Normal mode*/ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) { - huart->RxXferCount = 0; + huart->RxXferCount = 0U; + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; } HAL_UART_RxCpltCallback(huart); } /** * @brief DMA UART receive process half complete callback - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - HAL_UART_RxHalfCpltCallback(huart); } /** * @brief DMA UART communication error callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @param hdma: DMA handle * @retval None */ -static void UART_DMAError(DMA_HandleTypeDef *hdma) +static void UART_DMAError(DMA_HandleTypeDef *hdma) { + uint32_t dmarequest = 0x00U; UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->RxXferCount = 0; - huart->TxXferCount = 0; - huart->State= HAL_UART_STATE_READY; + + /* Stop UART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); + if((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) + { + huart->TxXferCount = 0U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); + if((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) + { + huart->RxXferCount = 0U; + UART_EndRxTransfer(huart); + } + huart->ErrorCode |= HAL_UART_ERROR_DMA; HAL_UART_ErrorCallback(huart); } /** * @brief This function handles UART Communication Timeout. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @param Flag: specifies the UART flag to check. * @param Status: The new Flag status (SET or RESET). + * @param Tickstart Tick start value * @param Timeout: Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait until flag is set */ - if(Status == RESET) + while((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) { - while(__HAL_UART_GET_FLAG(huart, Flag) == RESET) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State= HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; } } } - else + + return HAL_OK; +} + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart: UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart: UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + huart->RxXferCount = 0x00U; + huart->TxXferCount = 0x00U; + + HAL_UART_ErrorCallback(huart); +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(huart->hdmarx != NULL) { - while(__HAL_UART_GET_FLAG(huart, Flag) != RESET) + if(huart->hdmarx->XferAbortCallback != NULL) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + return; + } + } - huart->State= HAL_UART_STATE_READY; + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; - /* Process Unlocked */ - __HAL_UNLOCK(huart); + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; - return HAL_TIMEOUT; - } - } + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(huart->hdmatx != NULL) + { + if(huart->hdmatx->XferAbortCallback != NULL) + { + return; } } - return HAL_OK; + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0x00U; + huart->RxXferCount = 0x00U; + + /* Reset ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + huart->TxXferCount = 0x00U; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + huart->RxXferCount = 0x00U; + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ + HAL_UART_AbortReceiveCpltCallback(huart); } /** @@ -1723,10 +2339,9 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { uint16_t* tmp; - uint32_t tmp_state = 0; - tmp_state = huart->State; - if((tmp_state == HAL_UART_STATE_BUSY_TX) || (tmp_state == HAL_UART_STATE_BUSY_TX_RX)) + /* Check that a Tx process is ongoing */ + if(huart->gState == HAL_UART_STATE_BUSY_TX) { if(huart->Init.WordLength == UART_WORDLENGTH_9B) { @@ -1734,11 +2349,11 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); if(huart->Init.Parity == UART_PARITY_NONE) { - huart->pTxBuffPtr += 2; + huart->pTxBuffPtr += 2U; } else { - huart->pTxBuffPtr += 1; + huart->pTxBuffPtr += 1U; } } else @@ -1746,7 +2361,7 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); } - if(--huart->TxXferCount == 0) + if(--huart->TxXferCount == 0U) { /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); @@ -1762,7 +2377,6 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) } } - /** * @brief Wraps up transmission in non blocking mode. * @param huart: pointer to a UART_HandleTypeDef structure that contains @@ -1774,16 +2388,8 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) /* Disable the UART Transmit Complete Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TC); - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } - + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; HAL_UART_TxCpltCallback(huart); return HAL_OK; @@ -1791,17 +2397,16 @@ static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) /** * @brief Receives an amount of data in non blocking mode - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) { uint16_t* tmp; - uint32_t tmp_state = 0; - tmp_state = huart->State; - if((tmp_state == HAL_UART_STATE_BUSY_RX) || (tmp_state == HAL_UART_STATE_BUSY_TX_RX)) + /* Check that a Rx process is ongoing */ + if(huart->RxState == HAL_UART_STATE_BUSY_RX) { if(huart->Init.WordLength == UART_WORDLENGTH_9B) { @@ -1809,12 +2414,12 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) if(huart->Init.Parity == UART_PARITY_NONE) { *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); - huart->pRxBuffPtr += 2; + huart->pRxBuffPtr += 2U; } else { *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); - huart->pRxBuffPtr += 1; + huart->pRxBuffPtr += 1U; } } else @@ -1829,25 +2434,19 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) } } - if(--huart->RxXferCount == 0) + if(--huart->RxXferCount == 0U) { + /* Disable the IRDA Data Register not empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - /* Check if a transmit process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - + /* Disable the UART Parity Error Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_PE); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - huart->State = HAL_UART_STATE_READY; - } + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + HAL_UART_RxCpltCallback(huart); return HAL_OK; @@ -1856,22 +2455,22 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) } else { - return HAL_BUSY; + return HAL_BUSY; } } /** * @brief Configures the UART peripheral. - * @param huart: Pointer to a UART_HandleTypeDef structure that contains + * @param huart: pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { - uint32_t tmpreg = 0x00; - + uint32_t tmpreg = 0x00U; + /* Check the parameters */ - assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); assert_param(IS_UART_PARITY(huart->Init.Parity)); assert_param(IS_UART_MODE(huart->Init.Mode)); @@ -1885,18 +2484,54 @@ static void UART_SetConfig(UART_HandleTypeDef *huart) /* Configure the UART Word Length, Parity and mode: Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value - Set TE and RE bits according to huart->Init.Mode value */ - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode ; + Set TE and RE bits according to huart->Init.Mode value + Set OVER8 bit according to huart->Init.OverSampling value */ + +#if defined(USART_CR1_OVER8) + tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; + MODIFY_REG(huart->Instance->CR1, + (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + tmpreg); +#else + tmpreg |= (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), tmpreg); - +#endif /* USART_CR1_OVER8 */ + /*------- UART-associated USART registers setting : CR3 Configuration ------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); - - /*------- UART-associated USART registers setting : BRR Configuration ------*/ - if((huart->Instance == USART1)) + +#if defined(USART_CR1_OVER8) + /* Check the Over Sampling */ + if(huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + /*-------------------------- USART BRR Configuration ---------------------*/ + if(huart->Instance == USART1) + { + huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); + } + else + { + huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); + } + } + else + { + /*-------------------------- USART BRR Configuration ---------------------*/ + if(huart->Instance == USART1) + { + huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); + } + else + { + huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); + } + } +#else + /*-------------------------- USART BRR Configuration ---------------------*/ + if(huart->Instance == USART1) { huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); } @@ -1904,7 +2539,9 @@ static void UART_SetConfig(UART_HandleTypeDef *huart) { huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); } +#endif /* USART_CR1_OVER8 */ } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.h index 03c2d80b532..a8639814cbc 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_uart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_uart.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_UART_H @@ -52,17 +52,16 @@ /** @addtogroup UART * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup UART_Exported_Types UART Exported Types * @{ - */ - + */ -/** +/** * @brief UART Init Structure definition - */ + */ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. @@ -82,38 +81,81 @@ typedef struct at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref UART_Mode */ - uint32_t HwFlowCtl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref UART_Hardware_Flow_Control */ - + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. This feature is not available - on STM32F1xx family, so OverSampling parameter should always be set to 16. */ + This parameter can be a value of @ref UART_Over_Sampling. This feature is only available + on STM32F100xx family, so OverSampling parameter should always be set to 16. */ }UART_InitTypeDef; /** - * @brief HAL UART State structures definition - */ + * @brief HAL UART State structures definition + * @note HAL UART State value is a combination of 2 different substates: gState and RxState. + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (IP busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 IP initilisation status + * 0 : Reset (IP not initialized) + * 1 : Init done (IP not initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ typedef enum { - HAL_UART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_UART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_UART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_UART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_UART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_UART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */ - HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_UART_STATE_ERROR = 0x04 /*!< Error */ + HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized + Value is allowed for gState and RxState */ + HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ + HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing + Value is allowed for gState only */ + HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing + Value is allowed for RxState only */ + HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between gState and RxState values */ + HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state + Value is allowed for gState only */ + HAL_UART_STATE_ERROR = 0xE0U /*!< Error + Value is allowed for gState only */ }HAL_UART_StateTypeDef; - /** - * @brief UART handle Structure definition - */ + * @brief UART handle Structure definition + */ typedef struct { USART_TypeDef *Instance; /*!< UART registers base address */ @@ -124,13 +166,13 @@ typedef struct uint16_t TxXferSize; /*!< UART Tx Transfer size */ - uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ uint16_t RxXferSize; /*!< UART Rx Transfer size */ - uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ @@ -138,10 +180,14 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_UART_StateTypeDef State; /*!< UART communication state */ + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ - __IO uint32_t ErrorCode; /*!< UART Error code */ + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. + This parameter can be a value of @ref HAL_UART_StateTypeDef */ + __IO uint32_t ErrorCode; /*!< UART Error code */ }UART_HandleTypeDef; /** @@ -153,56 +199,51 @@ typedef struct * @{ */ -/** @defgroup UART_Error_Codes UART Error Codes +/** @defgroup UART_Error_Code UART Error Code * @{ */ - -#define HAL_UART_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x04) /*!< frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ - +#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */ +#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */ +#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */ +#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */ +#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ /** * @} */ - - - -/** @defgroup UART_Word_Length UART Word Length +/** @defgroup UART_Word_Length UART Word Length * @{ */ -#define UART_WORDLENGTH_8B ((uint32_t)0x00000000) +#define UART_WORDLENGTH_8B 0x00000000U #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /** * @} */ -/** @defgroup UART_Stop_Bits UART Number of Stop Bits +/** @defgroup UART_Stop_Bits UART Number of Stop Bits * @{ */ -#define UART_STOPBITS_1 ((uint32_t)0x00000000) +#define UART_STOPBITS_1 0x00000000U #define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /** * @} - */ + */ /** @defgroup UART_Parity UART Parity * @{ - */ -#define UART_PARITY_NONE ((uint32_t)0x00000000) + */ +#define UART_PARITY_NONE 0x00000000U #define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) #define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /** * @} - */ + */ /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control * @{ - */ -#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) + */ +#define UART_HWCONTROL_NONE 0x00000000U #define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) #define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) #define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) @@ -216,41 +257,44 @@ typedef struct #define UART_MODE_RX ((uint32_t)USART_CR1_RE) #define UART_MODE_TX ((uint32_t)USART_CR1_TE) #define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) - /** * @} */ - - /** @defgroup UART_State UART State + +/** @defgroup UART_State UART State * @{ - */ -#define UART_STATE_DISABLE ((uint32_t)0x00000000) + */ +#define UART_STATE_DISABLE 0x00000000U #define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /** * @} */ + /** @defgroup UART_Over_Sampling UART Over Sampling * @{ */ -#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) +#define UART_OVERSAMPLING_16 0x00000000U +#if defined(USART_CR1_OVER8) +#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) +#endif /* USART_CR1_OVER8 */ /** * @} */ + /** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length * @{ */ -#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U #define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /** * @} */ - -/** @defgroup UART_WakeUp_functions UART Wakeup Functions +/** @defgroup UART_WakeUp_functions UART Wakeup Functions * @{ */ -#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U #define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /** * @} @@ -279,24 +323,22 @@ typedef struct * Elements values convention: 0xY000XXXX * - XXXX : Interrupt mask (16 bits) in the Y register * - Y : Interrupt source register (2bits) - * - 0001: CR1 register - * - 0010: CR2 register - * - 0011: CR3 register - * + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register * @{ - */ - -#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_PEIE)) -#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE)) -#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_TCIE)) -#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE)) -#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE)) + */ -#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE)) +#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) +#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) +#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) +#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) +#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) -#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE)) -#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28 | USART_CR3_EIE)) +#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) +#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) +#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) /** * @} */ @@ -305,32 +347,32 @@ typedef struct * @} */ - /* Exported macro ------------------------------------------------------------*/ /** @defgroup UART_Exported_Macros UART Exported Macros * @{ */ - -/** @brief Reset UART handle state +/** @brief Reset UART handle gstate & RxState * @param __HANDLE__: specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None */ -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) -/** @brief Flush the UART DR register +/** @brief Flushs the UART DR register * @param __HANDLE__: specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) -/** @brief Check whether the specified UART flag is set or not. +/** @brief Checks whether the specified UART flag is set or not. * @param __HANDLE__: specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). + * This parameter can be UARTx where x: 1, 2, 3, 4 or 5 to select the USART or + * UART peripheral. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) @@ -347,7 +389,7 @@ typedef struct */ #define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) -/** @brief Clear the specified UART pending flag. +/** @brief Clears the specified UART pending flag. * @param __HANDLE__: specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). @@ -367,58 +409,50 @@ typedef struct * USART_SR register followed by a write operation to USART_DR register. * @note TXE flag is cleared only by a write to the USART_DR register. * - * @retval None */ #define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) -/** @brief Clear the UART PE pending flag. +/** @brief Clears the UART PE pending flag. * @param __HANDLE__: specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None */ -#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ -do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - tmpreg = (__HANDLE__)->Instance->DR; \ - UNUSED(tmpreg); \ -}while(0) - +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ + } while(0U) - -/** @brief Clear the UART FE pending flag. +/** @brief Clears the UART FE pending flag. * @param __HANDLE__: specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None */ #define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) -/** @brief Clear the UART NE pending flag. +/** @brief Clears the UART NE pending flag. * @param __HANDLE__: specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None */ #define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) -/** @brief Clear the UART ORE pending flag. +/** @brief Clears the UART ORE pending flag. * @param __HANDLE__: specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None */ #define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) -/** @brief Clear the UART IDLE pending flag. +/** @brief Clears the UART IDLE pending flag. * @param __HANDLE__: specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). - * @retval None */ #define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - + /** @brief Enable the specified UART interrupt. * @param __HANDLE__: specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral @@ -433,13 +467,11 @@ do{ \ * @arg UART_IT_IDLE: Idle line detection interrupt * @arg UART_IT_PE: Parity Error interrupt * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) - /** @brief Disable the specified UART interrupt. * @param __HANDLE__: specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral @@ -454,13 +486,12 @@ do{ \ * @arg UART_IT_IDLE: Idle line detection interrupt * @arg UART_IT_PE: Parity Error interrupt * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) - -/** @brief Check whether the specified UART interrupt has occurred or not. + +/** @brief Checks whether the specified UART interrupt has occurred or not. * @param __HANDLE__: specifies the UART Handle. * UART Handle selects the USARTx or UARTy peripheral * (USART,UART availability and x,y values depending on device). @@ -475,7 +506,7 @@ do{ \ * @arg UART_IT_ERR: Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == UART_CR2_REG_INDEX)? \ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) /** @brief Enable CTS flow control @@ -488,15 +519,14 @@ do{ \ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__: specifies the UART Handle. - * This parameter can be any USARTx (supporting the HW Flow control feature). + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). * It is used to select the USART peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ do{ \ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ - } while(0) + } while(0U) /** @brief Disable CTS flow control * This macro allows to disable CTS hardware flow control for a given UART instance, @@ -508,15 +538,14 @@ do{ \ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__: specifies the UART Handle. - * This parameter can be any USARTx (supporting the HW Flow control feature). + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). * It is used to select the USART peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ do{ \ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ - } while(0) + } while(0U) /** @brief Enable RTS flow control * This macro allows to enable RTS hardware flow control for a given UART instance, @@ -528,15 +557,14 @@ do{ \ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__: specifies the UART Handle. - * This parameter can be any USARTx (supporting the HW Flow control feature). + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). * It is used to select the USART peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ do{ \ SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ - } while(0) + } while(0U) /** @brief Disable RTS flow control * This macro allows to disable RTS hardware flow control for a given UART instance, @@ -548,124 +576,49 @@ do{ \ * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__: specifies the UART Handle. - * This parameter can be any USARTx (supporting the HW Flow control feature). + * The Handle Instance can be any USARTx (supporting the HW Flow control feature). * It is used to select the USART peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ do{ \ CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ - } while(0) + } while(0U) + +#if defined(USART_CR3_ONEBIT) +/** @brief macros to enables the UART's one bit sample method + * @param __HANDLE__: specifies the UART Handle. + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) +/** @brief macros to disables the UART's one bit sample method + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) +#endif /* USART_CR3_ONEBIT */ /** @brief Enable UART * @param __HANDLE__: specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ + */ #define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable UART - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None + * @param __HANDLE__: specifies the UART Handle. */ #define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) - /** * @} */ - - -/* Private macros --------------------------------------------------------*/ -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ - -#define UART_CR1_REG_INDEX 1 -#define UART_CR2_REG_INDEX 2 -#define UART_CR3_REG_INDEX 3 - -#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25)/(4*(_BAUD_))) -#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100) -#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100) -/* UART BRR = mantissa + overflow + fraction - = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */ -#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4) + \ - (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0)) + \ - (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F)) -#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ - ((LENGTH) == UART_WORDLENGTH_9B)) -#define IS_UART_LIN_WORD_LENGTH(LENGTH) ((LENGTH) == UART_WORDLENGTH_8B) - -#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ - ((STOPBITS) == UART_STOPBITS_2)) - -#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ - ((PARITY) == UART_PARITY_EVEN) || \ - ((PARITY) == UART_PARITY_ODD)) - -#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == UART_HWCONTROL_NONE) || \ - ((CONTROL) == UART_HWCONTROL_RTS) || \ - ((CONTROL) == UART_HWCONTROL_CTS) || \ - ((CONTROL) == UART_HWCONTROL_RTS_CTS)) - -#define IS_UART_MODE(MODE) ((((MODE) & (~((uint32_t)UART_MODE_TX_RX))) == 0x00) && \ - ((MODE) != (uint32_t)0x00000000)) - -#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ - ((STATE) == UART_STATE_ENABLE)) - -#define IS_UART_OVERSAMPLING(SAMPLING) ((SAMPLING) == UART_OVERSAMPLING_16) -#define IS_UART_LIN_OVERSAMPLING(SAMPLING) ((SAMPLING) == UART_OVERSAMPLING_16) - -#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ - ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) - -#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ - ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) - - -/** Check UART Baud rate - * __BAUDRATE__: Baudrate specified by the user - * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz) - * divided by the smallest oversampling used on the USART (i.e. 16) - * Retrun : TRUE or FALSE - */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001) - -/** Check UART Node Address - * __ADDRESS__: UART Node address specified by the user - * UART Node address is used in Multi processor communication for wakeup - * with address mark detection. - * This parameter must be a number between Min_Data = 0 and Max_Data = 15 - * Return : TRUE or FALSE - */ -#define IS_UART_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF) - -/** UART interruptions flag mask - */ -#define UART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ - USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE ) - -/** - * @} - */ - /* Exported functions --------------------------------------------------------*/ - -/** @addtogroup UART_Exported_Functions UART Exported Functions +/** @addtogroup UART_Exported_Functions * @{ */ - -/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup UART_Exported_Functions_Group1 * @{ */ - -/* Initialization and de-initialization functions ****************************/ +/* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); @@ -673,16 +626,14 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); void HAL_UART_MspInit(UART_HandleTypeDef *huart); void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); - /** * @} */ -/** @addtogroup UART_Exported_Functions_Group2 IO operation functions +/** @addtogroup UART_Exported_Functions_Group2 * @{ */ - -/* IO operation functions *****************************************************/ +/* IO operation functions *******************************************************/ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); @@ -692,44 +643,129 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); - +void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart); /** * @} */ -/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions +/** @addtogroup UART_Exported_Functions_Group3 * @{ */ - /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); +/** + * @} + */ +/** @addtogroup UART_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); /** * @} */ -/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Errors functions +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants * @{ */ +/** @brief UART interruptions flag mask + * + */ +#define UART_IT_MASK 0x0000FFFFU -/* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); +#define UART_CR1_REG_INDEX 1U +#define UART_CR2_REG_INDEX 2U +#define UART_CR3_REG_INDEX 3U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ + ((LENGTH) == UART_WORDLENGTH_9B)) +#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ + ((STOPBITS) == UART_STOPBITS_2)) +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ + ((PARITY) == UART_PARITY_EVEN) || \ + ((PARITY) == UART_PARITY_ODD)) +#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == UART_HWCONTROL_NONE) || \ + ((CONTROL) == UART_HWCONTROL_RTS) || \ + ((CONTROL) == UART_HWCONTROL_CTS) || \ + ((CONTROL) == UART_HWCONTROL_RTS_CTS)) +#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U)) +#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ + ((STATE) == UART_STATE_ENABLE)) +#if defined(USART_CR1_OVER8) +#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ + ((SAMPLING) == UART_OVERSAMPLING_8)) +#endif /* USART_CR1_OVER8 */ +#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16)) +#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) +#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) +#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U) +#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU) + +#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_))) +#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) +#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ +#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \ + (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU)) + +#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_))) +#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) +#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ +#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ + ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \ + (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U)) /** * @} */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.c index 5ecfcf102a3..a6d19e9f99e 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.c @@ -2,15 +2,14 @@ ****************************************************************************** * @file stm32f1xx_hal_usart.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief USART HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions + * + Peripheral Control functions @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,7 +18,7 @@ The USART HAL driver can be used as follows: (#) Declare a USART_HandleTypeDef handle structure. - (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API: + (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit () API: (##) Enable the USARTx interface clock. (##) USART pins configuration: (+++) Enable the clock for the USART GPIOs. @@ -34,82 +33,99 @@ (+++) Enable the DMAx interface clock. (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle. + (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle - (used for last byte sending completion detection in DMA non circular mode) + (used for last byte sending completion detection in DMA non circular mode) - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware flow control and Mode(Receiver/Transmitter) in the husart Init structure. (#) Initialize the USART registers by calling the HAL_USART_Init() API: (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_USART_MspInit(&husart) API. - - -@@- The specific USART interrupts (Transmission complete interrupt, + by calling the customized HAL_USART_MspInit(&husart) API. + + -@@- The specific USART interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. - - (#) Three operation modes are available within this driver : - + + (#) Three operation modes are available within this driver : + *** Polling mode IO operation *** ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_USART_Transmit() + [..] + (+) Send an amount of data in blocking mode using HAL_USART_Transmit() (+) Receive an amount of data in blocking mode using HAL_USART_Receive() - - *** Interrupt mode IO operation *** + + *** Interrupt mode IO operation *** =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT() - (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can + [..] + (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT() + (+) At transmission end of transfer HAL_USART_TxHalfCpltCallback is executed and user can add his own code by customization of function pointer HAL_USART_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT() - (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_RxCpltCallback - (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can + (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT() + (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxCpltCallback + (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_USART_ErrorCallback - - *** DMA mode IO operation *** + + *** DMA mode IO operation *** ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA() - (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback - (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can + [..] + (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA() + (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback + (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_USART_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA() - (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback - (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_USART_RxCpltCallback - (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can + (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA() + (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback + (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can + add his own code by customization of function pointer HAL_USART_RxCpltCallback + (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_USART_ErrorCallback - (+) Pause the DMA Transfer using HAL_USART_DMAPause() - (+) Resume the DMA Transfer using HAL_USART_DMAResume() - (+) Stop the DMA Transfer using HAL_USART_DMAStop() - + (+) Pause the DMA Transfer using HAL_USART_DMAPause() + (+) Resume the DMA Transfer using HAL_USART_DMAResume() + (+) Stop the DMA Transfer using HAL_USART_DMAStop() + *** USART HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in USART HAL driver. - - (+) __HAL_USART_ENABLE: Enable the USART peripheral - (+) __HAL_USART_DISABLE: Disable the USART peripheral + + (+) __HAL_USART_ENABLE: Enable the USART peripheral + (+) __HAL_USART_DISABLE: Disable the USART peripheral (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt - (+) __HAL_USART_GET_IT_SOURCE: Check whether the specified USART interrupt has occurred or not - - [..] + + [..] (@) You can refer to the USART HAL driver header file for more useful macros @endverbatim + [..] + (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + the possible USART frame formats are as listed in the following table: + +-------------------------------------------------------------+ + | M bit | PCE bit | USART frame | + |---------------------|---------------------------------------| + | 0 | 0 | | SB | 8 bit data | STB | | + |---------|-----------|---------------------------------------| + | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|-----------|---------------------------------------| + | 1 | 0 | | SB | 9 bit data | STB | | + |---------|-----------|---------------------------------------| + | 1 | 1 | | SB | 8 bit data | PB | STB | | + +-------------------------------------------------------------+ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -148,22 +164,26 @@ * @{ */ #ifdef HAL_USART_MODULE_ENABLED + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup USART_Private_Constants USART Private Constants +/** @addtogroup USART_Private_Constants * @{ */ -#define DUMMY_DATA 0xFFFF +#define DUMMY_DATA 0xFFFFU +#define USART_TIMEOUT_VALUE 22000U /** * @} */ - -/* Private macros --------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @addtogroup USART_Private_Functions USART Private Functions +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup USART_Private_Functions * @{ */ +static void USART_EndTxTransfer(USART_HandleTypeDef *husart); +static void USART_EndRxTransfer(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart); @@ -173,70 +193,57 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void USART_DMAError(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static void USART_DMAError(DMA_HandleTypeDef *hdma); +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); + +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); /** * @} */ -/* Exported functions ---------------------------------------------------------*/ - - +/* Exported functions --------------------------------------------------------*/ /** @defgroup USART_Exported_Functions USART Exported Functions * @{ */ -/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions + * @brief Initialization and Configuration functions * @verbatim ============================================================================== - ##### Initialization and Configuration functions ##### + ##### Initialization and Configuration functions ##### ============================================================================== [..] - This subsection provides a set of functions allowing to initialize the USART + This subsection provides a set of functions allowing to initialize the USART in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: + (+) For the asynchronous mode only these parameters can be configured: (++) Baud Rate - (++) Word Length + (++) Word Length (++) Stop Bit - (++) Parity + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + Depending on the frame length defined by the M bit (8-bits or 9-bits), + please refer to Reference manual for possible USART frame formats. (++) USART polarity (++) USART phase (++) USART LastBit (++) Receiver/transmitter modes [..] - The HAL_USART_Init() function follows the USART synchronous configuration + The HAL_USART_Init() function follows the USART synchronous configuration procedure (details for the procedure are available in reference manuals (RM0008 for STM32F10Xxx MCUs and RM0041 for STM32F100xx MCUs)). @endverbatim * @{ */ - -/* - Additionnal remark: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ -*/ /** * @brief Initializes the USART mode according to the specified * parameters in the USART_InitTypeDef and create the associated handle. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -255,7 +262,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) { /* Allocate lock resource and initialize it */ husart->Lock = HAL_UNLOCKED; - + /* Init the low level hardware */ HAL_USART_MspInit(husart); } @@ -265,11 +272,11 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /* Set the USART Communication parameters */ USART_SetConfig(husart); - /* In USART mode, the following bits must be kept cleared: + /* In USART mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register - HDSEL, SCEN and IREN bits in the USART_CR3 register */ CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN); - CLEAR_BIT(husart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); /* Enable the Peripheral */ __HAL_USART_ENABLE(husart); @@ -283,13 +290,13 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) /** * @brief DeInitializes the USART peripheral. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) { - /* Check the USART handle allocation */ + /* Check the USART handle allocation */ if(husart == NULL) { return HAL_ERROR; @@ -300,9 +307,6 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_BUSY; - /* Disable the Peripheral */ - __HAL_USART_DISABLE(husart); - /* DeInit the low level hardware */ HAL_USART_MspDeInit(husart); @@ -317,66 +321,66 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) /** * @brief USART MSP Init. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ - __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) +__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_MspInit can be implemented in the user file - */ + the HAL_USART_MspInit could be implemented in the user file + */ } /** * @brief USART MSP DeInit. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ - __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) +__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_MspDeInit can be implemented in the user file - */ + the HAL_USART_MspDeInit could be implemented in the user file + */ } /** * @} */ -/** @defgroup USART_Exported_Functions_Group2 IO operation functions - * @brief USART Transmit and Receive functions +/** @defgroup USART_Exported_Functions_Group2 IO operation functions + * @brief USART Transmit and Receive functions * @verbatim ============================================================================== - ##### IO operation functions ##### + ##### IO operation functions ##### ============================================================================== [..] This subsection provides a set of functions allowing to manage the USART synchronous data transfers. - - [..] + + [..] The USART supports master mode only: it cannot receive or send data related to an input clock (SCLK is always an output). (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() - user callbacks + The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() + user callbacks will be executed respectively at the end of the transmit or Receive process - The HAL_USART_ErrorCallback() user callback will be executed when a communication + The HAL_USART_ErrorCallback() user callback will be executed when a communication error is detected (#) Blocking mode APIs are : @@ -411,8 +415,8 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) */ /** - * @brief Simplex Send an amount of data in blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @brief Simplex Send an amount of data in blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @param pTxData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -421,11 +425,12 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) */ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp=0; + uint16_t* tmp; + uint32_t tickstart = 0U; if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -436,15 +441,18 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); + husart->TxXferSize = Size; husart->TxXferCount = Size; - while(husart->TxXferCount > 0) + while(husart->TxXferCount > 0U) { husart->TxXferCount--; if(husart->Init.WordLength == USART_WORDLENGTH_9B) { /* Wait for TC flag in order to write data in DR */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -452,16 +460,16 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF)); if(husart->Init.Parity == USART_PARITY_NONE) { - pTxData += 2; + pTxData += 2U; } else { - pTxData += 1; + pTxData += 1U; } } else { - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -469,8 +477,8 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa } } - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK) - { + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { return HAL_TIMEOUT; } @@ -488,8 +496,8 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa } /** - * @brief Full-Duplex Receive an amount of data in blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @brief Full-Duplex Receive an amount of data in blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @param pRxData: Pointer to data buffer * @param Size: Amount of data to be received @@ -498,59 +506,62 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa */ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp=0; + uint16_t* tmp; + uint32_t tickstart = 0U; if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(husart); husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); + husart->RxXferSize = Size; husart->RxXferCount = Size; /* Check the remain data to be received */ - while(husart->RxXferCount > 0) + while(husart->RxXferCount > 0U) { husart->RxXferCount--; if(husart->Init.WordLength == USART_WORDLENGTH_9B) { /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { return HAL_TIMEOUT; } /* Send dummy byte in order to generate clock */ WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF)); - + /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { return HAL_TIMEOUT; } tmp = (uint16_t*) pRxData ; if(husart->Init.Parity == USART_PARITY_NONE) { *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); - pRxData +=2; + pRxData +=2U; } else { *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF); - pRxData +=1; + pRxData +=1U; } } else { /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) - { + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { return HAL_TIMEOUT; } @@ -558,7 +569,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF)); /* Wait until RXNE flag is set to receive the byte */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -590,22 +601,23 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat } /** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @param pTxData: Pointer to data transmitted buffer - * @param pRxData: Pointer to data received buffer + * @param pRxData: Pointer to data received buffer * @param Size: Amount of data to be sent * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp=0; + uint16_t* tmp; + uint32_t tickstart = 0U; if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -615,20 +627,23 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); + husart->RxXferSize = Size; husart->TxXferSize = Size; husart->TxXferCount = Size; husart->RxXferCount = Size; /* Check the remain data to be received */ - while(husart->TxXferCount > 0) + while(husart->TxXferCount > 0U) { husart->TxXferCount--; husart->RxXferCount--; if(husart->Init.WordLength == USART_WORDLENGTH_9B) { /* Wait for TC flag in order to write data in DR */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -636,15 +651,15 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF)); if(husart->Init.Parity == USART_PARITY_NONE) { - pTxData += 2; + pTxData += 2U; } else { - pTxData += 1; + pTxData += 1U; } - + /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -652,25 +667,25 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t if(husart->Init.Parity == USART_PARITY_NONE) { *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); - pRxData += 2; + pRxData += 2U; } else { *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF); - pRxData += 1; + pRxData += 1U; } - } + } else { /* Wait for TC flag in order to write data in DR */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0x00FF)); /* Wait for RXNE Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK) + if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -701,8 +716,8 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t } /** - * @brief Simplex Send an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @brief Simplex Send an amount of data in non-blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @param pTxData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -711,13 +726,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t */ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) { + /* Check that a Tx process is not already ongoing */ if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(husart); @@ -728,7 +743,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) + /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) are not managed by the USART transmit process to avoid the overrun interrupt when the USART mode is configured for transmit and receive "USART_MODE_TX_RX" to benefit for the frame error and noise interrupts the USART mode should be @@ -751,9 +766,9 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT } /** - * @brief Simplex Receive an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. + * @brief Simplex Receive an amount of data in non-blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. * @param pRxData: Pointer to data buffer * @param Size: Amount of data to be received * @retval HAL status @@ -762,7 +777,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx { if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -800,11 +815,11 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx } /** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @param pTxData: Pointer to data transmitted buffer - * @param pRxData: Pointer to data received buffer + * @param pRxData: Pointer to data received buffer * @param Size: Amount of data to be received * @retval HAL status */ @@ -812,7 +827,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint { if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -848,13 +863,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Simplex Send an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @brief Simplex Send an amount of data in non-blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @param pTxData: Pointer to data buffer * @param Size: Amount of data to be sent @@ -862,16 +877,16 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint */ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) { - uint32_t *tmp=0; + uint32_t *tmp; if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0U)) { return HAL_ERROR; } /* Process Locked */ - __HAL_LOCK(husart); + __HAL_LOCK(husart); husart->pTxBuffPtr = pTxData; husart->TxXferSize = Size; @@ -889,6 +904,9 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p /* Set the DMA error callback */ husart->hdmatx->XferErrorCallback = USART_DMAError; + /* Set the DMA abort callback */ + husart->hdmatx->XferAbortCallback = NULL; + /* Enable the USART transmit DMA channel */ tmp = (uint32_t*)&pTxData; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); @@ -896,13 +914,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC); - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - /* Process Unlocked */ __HAL_UNLOCK(husart); + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + return HAL_OK; } else @@ -912,8 +930,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p } /** - * @brief Full-Duplex Receive an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @brief Full-Duplex Receive an amount of data in non-blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @param pRxData: Pointer to data buffer * @param Size: Amount of data to be received @@ -923,11 +941,11 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p */ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) { - uint32_t *tmp=0; - + uint32_t *tmp; + if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -952,20 +970,42 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /* Set the USART DMA Rx transfer error callback */ husart->hdmarx->XferErrorCallback = USART_DMAError; + /* Set the DMA abort callback */ + husart->hdmarx->XferAbortCallback = NULL; + + /* Set the USART Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + husart->hdmatx->XferHalfCpltCallback = NULL; + husart->hdmatx->XferCpltCallback = NULL; + + /* Set the DMA error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* Set the DMA AbortCpltCallback */ + husart->hdmatx->XferAbortCallback = NULL; + /* Enable the USART receive DMA channel */ tmp = (uint32_t*)&pRxData; HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size); /* Enable the USART transmit DMA channel: the transmit channel is used in order - to generate in the non-blocking mode the clock to the slave device, + to generate in the non-blocking mode the clock to the slave device, this mode isn't a simplex receive mode but a full-duplex receive one */ HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); - /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer - when using the USART in circular mode */ + /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer */ __HAL_USART_CLEAR_OREFLAG(husart); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the USART CR3 register */ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); @@ -973,9 +1013,6 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR in the USART CR3 register */ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - /* Process Unlocked */ - __HAL_UNLOCK(husart); - return HAL_OK; } else @@ -985,22 +1022,22 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR } /** - * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @param pTxData: Pointer to data transmitted buffer - * @param pRxData: Pointer to data received buffer + * @param pRxData: Pointer to data received buffer * @param Size: Amount of data to be received * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - uint32_t *tmp=0; + uint32_t *tmp; if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -1033,6 +1070,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Set the USART DMA Rx transfer error callback */ husart->hdmarx->XferErrorCallback = USART_DMAError; + /* Set the DMA abort callback */ + husart->hdmarx->XferAbortCallback = NULL; + /* Enable the USART receive DMA channel */ tmp = (uint32_t*)&pRxData; HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size); @@ -1040,14 +1080,23 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Enable the USART transmit DMA channel */ tmp = (uint32_t*)&pTxData; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size); - + /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC); /* Clear the Overrun flag: mandatory for the second transfer in circular mode */ __HAL_USART_CLEAR_OREFLAG(husart); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the USART CR3 register */ SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); @@ -1055,9 +1104,6 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin in the USART CR3 register */ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - /* Process Unlocked */ - __HAL_UNLOCK(husart); - return HAL_OK; } else @@ -1068,7 +1114,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /** * @brief Pauses the DMA Transfer. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -1076,19 +1122,19 @@ HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) { /* Process Locked */ __HAL_LOCK(husart); - + /* Disable the USART DMA Tx request */ - CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_DMAT)); - + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + /* Process Unlocked */ __HAL_UNLOCK(husart); - return HAL_OK; + return HAL_OK; } /** * @brief Resumes the DMA Transfer. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ @@ -1096,10 +1142,10 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) { /* Process Locked */ __HAL_LOCK(husart); - + /* Enable the USART DMA Tx request */ SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - + /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -1108,107 +1154,364 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) /** * @brief Stops the DMA Transfer. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) { + uint32_t dmarequest = 0x00U; /* The Lock is not implemented on this API to allow the user application to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() */ - /* Abort the USART DMA Tx channel */ - if(husart->hdmatx != NULL) + /* Stop USART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT); + if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest) { - HAL_DMA_Abort(husart->hdmatx); - } - /* Abort the USART DMA Rx channel */ - if(husart->hdmarx != NULL) - { - HAL_DMA_Abort(husart->hdmarx); + USART_EndTxTransfer(husart); + + /* Abort the USART DMA Tx channel */ + if(husart->hdmatx != NULL) + { + HAL_DMA_Abort(husart->hdmatx); + } + + /* Disable the USART Tx DMA request */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); } - - /* Disable the USART Tx/Rx DMA requests */ - CLEAR_BIT(husart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); - husart->State = HAL_USART_STATE_READY; + /* Stop USART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR); + if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest) + { + USART_EndRxTransfer(husart); + + /* Abort the USART DMA Rx channel */ + if(husart->hdmarx != NULL) + { + HAL_DMA_Abort(husart->hdmarx); + } + + /* Disable the USART Rx DMA request */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } return HAL_OK; } /** - * @brief This function handles USART interrupt request. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) + * @brief Abort ongoing transfer (blocking mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer (either Tx or Rx, + * as described by TransferType parameter) started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) { - uint32_t tmp_flag = 0, tmp_it_source = 0; - - tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_PE); - tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE); - /* USART parity error interrupt occurred -----------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Disable the USART DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) { - husart->ErrorCode |= HAL_USART_ERROR_PE; + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if(husart->hdmatx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + HAL_DMA_Abort(husart->hdmatx); + } } - tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_FE); - tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR); - /* USART frame error interrupt occurred ------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + /* Disable the USART DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { - husart->ErrorCode |= HAL_USART_ERROR_FE; + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if(husart->hdmarx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = NULL; + + HAL_DMA_Abort(husart->hdmarx); + } } - tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_NE); - /* USART noise error interrupt occurred ------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0x00U; + husart->RxXferCount = 0x00U; + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Reset Handle ErrorCode to No Error */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer (either Tx or Rx, + * as described by TransferType parameter) started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable PPP Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status +*/ +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) +{ + uint32_t AbortCplt = 0x01U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if(husart->hdmatx != NULL) { - husart->ErrorCode |= HAL_USART_ERROR_NE; + /* Set DMA Abort Complete callback if USART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback; + } + else + { + husart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if(husart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if USART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback; + } + else + { + husart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the USART DMA Tx request if enabled */ + if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at USART level */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if(husart->hdmatx != NULL) + { + /* USART Tx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if(HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) + { + husart->hdmatx->XferAbortCallback = NULL; + } + else + { + AbortCplt = 0x00U; + } + } } - tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_ORE); - /* USART Over-Run interrupt occurred ---------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + /* Disable the USART DMA Rx request if enabled */ + if(HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) { - husart->ErrorCode |= HAL_USART_ERROR_ORE; + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if(husart->hdmarx != NULL) + { + /* USART Rx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + husart->hdmarx->XferAbortCallback = NULL; + AbortCplt = 0x01U; + } + else + { + AbortCplt = 0x00U; + } + } } - if(husart->ErrorCode != HAL_USART_ERROR_NONE) + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if(AbortCplt == 0x01U) { - /* Clear all the error flag at once */ - __HAL_USART_CLEAR_PEFLAG(husart); + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0x00U; + husart->RxXferCount = 0x00U; - /* Set the USART state ready to be able to start again the process */ - husart->State = HAL_USART_STATE_READY; - - HAL_USART_ErrorCallback(husart); + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ + HAL_USART_AbortCpltCallback(husart); } - tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE); - tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE); - /* USART in mode Receiver --------------------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + return HAL_OK; +} + +/** + * @brief This function handles USART interrupt request. + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) +{ + uint32_t isrflags = READ_REG(husart->Instance->SR); + uint32_t cr1its = READ_REG(husart->Instance->CR1); + uint32_t cr3its = READ_REG(husart->Instance->CR3); + uint32_t errorflags = 0x00U; + uint32_t dmarequest = 0x00U; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); + if(errorflags == RESET) { - if(husart->State == HAL_USART_STATE_BUSY_RX) + /* USART in mode Receiver -------------------------------------------------*/ + if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + USART_Receive_IT(husart); + } + else + { + USART_TransmitReceive_IT(husart); + } + return; + } + } + /* If some errors occur */ + if((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + { + /* USART parity error interrupt occurred ----------------------------------*/ + if(((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) { - USART_Receive_IT(husart); + husart->ErrorCode |= HAL_USART_ERROR_PE; } - else + + /* USART noise error interrupt occurred --------------------------------*/ + if(((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) { - USART_TransmitReceive_IT(husart); + husart->ErrorCode |= HAL_USART_ERROR_NE; } + + /* USART frame error interrupt occurred --------------------------------*/ + if(((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + husart->ErrorCode |= HAL_USART_ERROR_FE; + } + + /* USART Over-Run interrupt occurred -----------------------------------*/ + if(((isrflags & USART_SR_ORE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) + { + husart->ErrorCode |= HAL_USART_ERROR_ORE; + } + + if(husart->ErrorCode != HAL_USART_ERROR_NONE) + { + /* USART in mode Receiver -----------------------------------------------*/ + if(((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) + { + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + USART_Receive_IT(husart); + } + else + { + USART_TransmitReceive_IT(husart); + } + } + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR); + if(((husart->ErrorCode & HAL_USART_ERROR_ORE) != RESET) || dmarequest) + { + /* Set the USART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + USART_EndRxTransfer(husart); + + /* Disable the USART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA Rx channel */ + if(husart->hdmarx != NULL) + { + /* Set the USART DMA Abort callback : + will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; + + if(HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + husart->hdmarx->XferAbortCallback(husart->hdmarx); + } + } + else + { + /* Call user error callback */ + HAL_USART_ErrorCallback(husart); + } + } + else + { + /* Call user error callback */ + HAL_USART_ErrorCallback(husart); + } + } + else + { + /* Call user error callback */ + HAL_USART_ErrorCallback(husart); + husart->ErrorCode = HAL_USART_ERROR_NONE; + } + } + return; } - tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE); - tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE); /* USART in mode Transmitter -----------------------------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + if(((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) { if(husart->State == HAL_USART_STATE_BUSY_TX) { @@ -1218,52 +1521,50 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) { USART_TransmitReceive_IT(husart); } + return; } - - tmp_flag = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC); - tmp_it_source = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC); - /* USART in mode Transmitter (transmission end) -----------------------------*/ - if((tmp_flag != RESET) && (tmp_it_source != RESET)) + + /* USART in mode Transmitter (transmission end) ----------------------------*/ + if(((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) { USART_EndTransmit_IT(husart); - } - + return; + } } - /** * @brief Tx Transfer completed callbacks. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ - __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) +__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_TxCpltCallback can be implemented in the user file + the HAL_USART_TxCpltCallback could be implemented in the user file */ } /** * @brief Tx Half Transfer completed callbacks. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ - __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) +__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_TxHalfCpltCallback can be implemented in the user file + the HAL_USART_TxHalfCpltCallback could be implemented in the user file */ } /** * @brief Rx Transfer completed callbacks. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -1272,13 +1573,13 @@ __weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) /* Prevent unused argument(s) compilation warning */ UNUSED(husart); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_RxCpltCallback can be implemented in the user file + the HAL_USART_RxCpltCallback could be implemented in the user file */ } /** * @brief Rx Half Transfer completed callbacks. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -1287,13 +1588,13 @@ __weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) /* Prevent unused argument(s) compilation warning */ UNUSED(husart); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_RxHalfCpltCallback can be implemented in the user file + the HAL_USART_RxHalfCpltCallback could be implemented in the user file */ } /** * @brief Tx/Rx Transfers completed callback for the non-blocking process. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ @@ -1302,51 +1603,66 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) /* Prevent unused argument(s) compilation warning */ UNUSED(husart); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_TxRxCpltCallback can be implemented in the user file + the HAL_USART_TxRxCpltCallback could be implemented in the user file */ } /** * @brief USART error callbacks. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ - __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) +__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) { /* Prevent unused argument(s) compilation warning */ UNUSED(husart); /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_ErrorCallback can be implemented in the user file - */ + the HAL_USART_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief USART Abort Complete callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_AbortCpltCallback can be implemented in the user file. + */ } /** * @} */ -/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief USART State and Errors functions +/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief USART State and Errors functions * -@verbatim +@verbatim ============================================================================== ##### Peripheral State and Errors functions ##### - ============================================================================== + ============================================================================== [..] - This subsection provides a set of functions allowing to return the State of + This subsection provides a set of functions allowing to return the State of USART communication process, return Peripheral Errors occurred during communication process - (+) HAL_USART_GetState() API can be helpful to check in run-time the state + (+) HAL_USART_GetState() API can be helpful to check in run-time the state of the USART peripheral. - (+) HAL_USART_GetError() check in run-time errors that could be occurred during - communication. + (+) HAL_USART_GetError() check in run-time errors that could be occurred during + communication. @endverbatim * @{ */ /** * @brief Returns the USART state. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL state */ @@ -1379,7 +1695,8 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) * @{ */ /** - * @brief DMA USART transmit process complete callback. + * @brief DMA USART transmit process complete callback. + * @param hdma: DMA handle * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None @@ -1387,19 +1704,17 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - husart->TxXferCount = 0; - + husart->TxXferCount = 0U; if(husart->State == HAL_USART_STATE_BUSY_TX) { /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the USART CR3 register */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - /* Enable the USART Transmit Complete Interrupt */ + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } } @@ -1414,8 +1729,8 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA USART transmit process half complete callback - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA USART transmit process half complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1427,32 +1742,35 @@ static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA USART receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief DMA USART receive process complete callback. + * @param hdma: DMA handle * @retval None */ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* DMA Normal mode */ - if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) + if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - husart->RxXferCount = 0; + husart->RxXferCount = 0x00U; + + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + if(husart->State == HAL_USART_STATE_BUSY_RX) { - /* Disable the DMA transfer for the receiver requests by setting the DMAR bit + /* Disable the DMA transfer for the Transmit/Receiver requests by setting the DMAT/DMAR bit in the USART CR3 register */ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); husart->State= HAL_USART_STATE_READY; HAL_USART_RxCpltCallback(husart); } - /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ else { - /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit + /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit in the USART CR3 register */ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_DMAT | USART_CR3_DMAR)); @@ -1467,7 +1785,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { HAL_USART_RxCpltCallback(husart); } - /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ else { HAL_USART_TxRxCpltCallback(husart); @@ -1476,8 +1794,8 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA USART receive process half complete callback - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA USART receive process half complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1485,108 +1803,208 @@ static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - HAL_USART_RxHalfCpltCallback(husart); + HAL_USART_RxHalfCpltCallback(husart); } /** - * @brief DMA USART communication error callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. + * @brief DMA USART communication error callback. + * @param hdma: DMA handle * @retval None */ -static void USART_DMAError(DMA_HandleTypeDef *hdma) +static void USART_DMAError(DMA_HandleTypeDef *hdma) { + uint32_t dmarequest = 0x00U; USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + husart->RxXferCount = 0x00U; + husart->TxXferCount = 0x00U; + + /* Stop USART DMA Tx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT); + if((husart->State == HAL_USART_STATE_BUSY_TX) && dmarequest) + { + USART_EndTxTransfer(husart); + } + + /* Stop USART DMA Rx request if ongoing */ + dmarequest = HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR); + if((husart->State == HAL_USART_STATE_BUSY_RX) && dmarequest) + { + USART_EndRxTransfer(husart); + } - husart->RxXferCount = 0; - husart->TxXferCount = 0; husart->ErrorCode |= HAL_USART_ERROR_DMA; husart->State= HAL_USART_STATE_READY; - + HAL_USART_ErrorCallback(husart); } /** * @brief This function handles USART Communication Timeout. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @param Flag: specifies the USART flag to check. * @param Status: The new Flag status (SET or RESET). - * @param Timeout: Timeout duration + * @param Tickstart: Tick start value. + * @param Timeout: Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - /* Wait until flag is set */ - if(Status == RESET) + while((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) { - while(__HAL_USART_GET_FLAG(husart, Flag) == RESET) + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout)) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); __HAL_USART_DISABLE_IT(husart, USART_IT_PE); __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - husart->State= HAL_USART_STATE_READY; + husart->State= HAL_USART_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(husart); + /* Process Unlocked */ + __HAL_UNLOCK(husart); - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } } } - else + return HAL_OK; +} + +/** + * @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion). + * @param husart: USART handle. + * @retval None + */ +static void USART_EndTxTransfer(USART_HandleTypeDef *husart) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; +} + +/** + * @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion). + * @param husart: USART handle. + * @retval None + */ +static void USART_EndRxTransfer(USART_HandleTypeDef *husart) +{ + /* Disable RXNE, PE and ERR interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; +} + +/** + * @brief DMA USART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + husart->RxXferCount = 0x00U; + husart->TxXferCount = 0x00U; + + HAL_USART_ErrorCallback(husart); +} + +/** + * @brief DMA USART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + husart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(husart->hdmarx != NULL) { - while(__HAL_USART_GET_FLAG(husart, Flag) != RESET) + if(husart->hdmarx->XferAbortCallback != NULL) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0x00U; + husart->RxXferCount = 0x00U; - husart->State= HAL_USART_STATE_READY; + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(husart); + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; - return HAL_TIMEOUT; - } - } + /* Call user Abort complete callback */ + HAL_USART_AbortCpltCallback(husart); +} + +/** + * @brief DMA USART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + husart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if(husart->hdmatx != NULL) + { + if(husart->hdmatx->XferAbortCallback != NULL) + { + return; } } - return HAL_OK; + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0x00U; + husart->RxXferCount = 0x00U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ + HAL_USART_AbortCpltCallback(husart); } /** - * @brief Simplex Send an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @brief Simplex Send an amount of data in non-blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status * @note The USART errors are not managed to avoid the overrun error. */ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) { - uint16_t* tmp=0; - + uint16_t* tmp; + if(husart->State == HAL_USART_STATE_BUSY_TX) { if(husart->Init.WordLength == USART_WORDLENGTH_9B) @@ -1595,24 +2013,24 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF)); if(husart->Init.Parity == USART_PARITY_NONE) { - husart->pTxBuffPtr += 2; + husart->pTxBuffPtr += 2U; } else { - husart->pTxBuffPtr += 1; + husart->pTxBuffPtr += 1U; } - } + } else - { + { WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF)); } - - if(--husart->TxXferCount == 0) + + if(--husart->TxXferCount == 0U) { /* Disable the USART Transmit data register empty Interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - /* Enable the USART Transmit Complete Interrupt */ + /* Enable the USART Transmit Complete Interrupt */ __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } return HAL_OK; @@ -1623,7 +2041,6 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) } } - /** * @brief Wraps up transmission in non blocking mode. * @param husart: pointer to a USART_HandleTypeDef structure that contains @@ -1632,29 +2049,28 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) */ static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) { - /* Disable the USART Transmit Complete Interrupt */ + /* Disable the USART Transmit Complete Interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TC); - + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - + husart->State = HAL_USART_STATE_READY; - + HAL_USART_TxCpltCallback(husart); - + return HAL_OK; } - /** - * @brief Simplex Receive an amount of data in non-blocking mode. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @brief Simplex Receive an amount of data in non-blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) { - uint16_t* tmp=0; + uint16_t* tmp; if(husart->State == HAL_USART_STATE_BUSY_RX) { if(husart->Init.WordLength == USART_WORDLENGTH_9B) @@ -1663,19 +2079,19 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) if(husart->Init.Parity == USART_PARITY_NONE) { *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); - husart->pRxBuffPtr += 2; + husart->pRxBuffPtr += 2U; } else { *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF); - husart->pRxBuffPtr += 1; + husart->pRxBuffPtr += 1U; } - if(--husart->RxXferCount != 0x00) + if(--husart->RxXferCount != 0x00U) { /* Send dummy byte in order to generate the clock for the slave to send the next data */ WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF)); } - } + } else { if(husart->Init.Parity == USART_PARITY_NONE) @@ -1687,50 +2103,50 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); } - if(--husart->RxXferCount != 0x00) + if(--husart->RxXferCount != 0x00U) { /* Send dummy byte in order to generate the clock for the slave to send the next data */ WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF)); } } - if(husart->RxXferCount == 0) + if(husart->RxXferCount == 0U) { /* Disable the USART RXNE Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); /* Disable the USART Parity Error Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); husart->State = HAL_USART_STATE_READY; HAL_USART_RxCpltCallback(husart); - + return HAL_OK; } return HAL_OK; } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval HAL status */ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { - uint16_t* tmp=0; + uint16_t* tmp; if(husart->State == HAL_USART_STATE_BUSY_TX_RX) { - if(husart->TxXferCount != 0x00) + if(husart->TxXferCount != 0x00U) { if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET) { @@ -1740,13 +2156,13 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF)); if(husart->Init.Parity == USART_PARITY_NONE) { - husart->pTxBuffPtr += 2; + husart->pTxBuffPtr += 2U; } else { - husart->pTxBuffPtr += 1; + husart->pTxBuffPtr += 1U; } - } + } else { WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF)); @@ -1754,14 +2170,14 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) husart->TxXferCount--; /* Check the latest data transmitted */ - if(husart->TxXferCount == 0) + if(husart->TxXferCount == 0U) { - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + CLEAR_BIT(husart->Instance->CR1, USART_CR1_TXEIE); } } } - if(husart->RxXferCount != 0x00) + if(husart->RxXferCount != 0x00U) { if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET) { @@ -1771,14 +2187,14 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) if(husart->Init.Parity == USART_PARITY_NONE) { *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); - husart->pRxBuffPtr += 2; + husart->pRxBuffPtr += 2U; } else { *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF); - husart->pRxBuffPtr += 1; + husart->pRxBuffPtr += 1U; } - } + } else { if(husart->Init.Parity == USART_PARITY_NONE) @@ -1795,15 +2211,16 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) } /* Check the latest data received */ - if(husart->RxXferCount == 0) + if(husart->RxXferCount == 0U) { - __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE); + /* Disable the USART RXNE Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); /* Disable the USART Parity Error Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_PE); + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); husart->State = HAL_USART_STATE_READY; @@ -1816,13 +2233,13 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) } else { - return HAL_BUSY; + return HAL_BUSY; } } /** - * @brief Configures the USART peripheral. - * @param husart: Pointer to a USART_HandleTypeDef structure that contains + * @brief Configures the USART pferipheral. + * @param husart: pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.h index 6ba4f6a86f9..f88eb86fd54 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_hal_usart.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of USART HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -33,7 +33,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F1xx_HAL_USART_H @@ -52,17 +52,16 @@ /** @addtogroup USART * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup USART_Exported_Types USART Exported Types * @{ - */ - + */ -/** +/** * @brief USART Init Structure definition - */ + */ typedef struct { uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. @@ -76,14 +75,14 @@ typedef struct uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref USART_Stop_Bits */ - uint32_t Parity; /*!< Specifies the parity mode. + uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref USART_Parity @note When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref USART_Mode */ uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. @@ -102,68 +101,66 @@ typedef struct */ typedef enum { - HAL_USART_STATE_RESET = 0x00, /*!< Peripheral is not initialized */ - HAL_USART_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */ - HAL_USART_STATE_BUSY = 0x02, /*!< an internal process is ongoing */ - HAL_USART_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_USART_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_USART_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission Reception process is ongoing */ - HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_USART_STATE_ERROR = 0x04 /*!< Error */ + HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not yet initialized */ + HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04U /*!< Error */ }HAL_USART_StateTypeDef; - /** * @brief USART handle Structure definition */ typedef struct { USART_TypeDef *Instance; /*!< USART registers base address */ - - USART_InitTypeDef Init; /*!< Usart communication parameters */ - + + USART_InitTypeDef Init; /*!< Usart communication parameters */ + uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< Usart Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */ - + + uint16_t TxXferSize; /*!< Usart Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */ + uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< Usart Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */ - + + uint16_t RxXferSize; /*!< Usart Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */ + DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */ - + DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_USART_StateTypeDef State; /*!< Usart communication state */ - - __IO uint32_t ErrorCode; /*!< USART Error code */ + __IO HAL_USART_StateTypeDef State; /*!< Usart communication state */ + __IO uint32_t ErrorCode; /*!< USART Error code */ }USART_HandleTypeDef; - /** * @} */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup USART_Exported_Constants USART Exported constants +/** @defgroup USART_Exported_Constants USART Exported Constants * @{ */ -/** @defgroup USART_Error_Codes USART Error Codes +/** @defgroup USART_Error_Code USART Error Code + * @brief USART Error Code * @{ */ -#define HAL_USART_ERROR_NONE ((uint32_t)0x00) /*!< No error */ -#define HAL_USART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ -#define HAL_USART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ -#define HAL_USART_ERROR_FE ((uint32_t)0x04) /*!< frame error */ -#define HAL_USART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ -#define HAL_USART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ +#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */ +#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */ +#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */ +#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */ +#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ /** * @} */ @@ -171,8 +168,8 @@ typedef struct /** @defgroup USART_Word_Length USART Word Length * @{ */ -#define USART_WORDLENGTH_8B ((uint32_t)0x00000000) -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) +#define USART_WORDLENGTH_8B 0x00000000U +#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /** * @} */ @@ -180,10 +177,10 @@ typedef struct /** @defgroup USART_Stop_Bits USART Number of Stop Bits * @{ */ -#define USART_STOPBITS_1 ((uint32_t)0x00000000) -#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) -#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) -#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) +#define USART_STOPBITS_1 0x00000000U +#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) +#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) +#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /** * @} */ @@ -191,9 +188,9 @@ typedef struct /** @defgroup USART_Parity USART Parity * @{ */ -#define USART_PARITY_NONE ((uint32_t)0x00000000) -#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) -#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) +#define USART_PARITY_NONE 0x00000000U +#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) +#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /** * @} */ @@ -201,10 +198,9 @@ typedef struct /** @defgroup USART_Mode USART Mode * @{ */ -#define USART_MODE_RX ((uint32_t)USART_CR1_RE) -#define USART_MODE_TX ((uint32_t)USART_CR1_TE) -#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) - +#define USART_MODE_RX ((uint32_t)USART_CR1_RE) +#define USART_MODE_TX ((uint32_t)USART_CR1_TE) +#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /** * @} */ @@ -212,8 +208,8 @@ typedef struct /** @defgroup USART_Clock USART Clock * @{ */ -#define USART_CLOCK_DISABLE ((uint32_t)0x00000000) -#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) +#define USART_CLOCK_DISABLE 0x00000000U +#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /** * @} */ @@ -221,8 +217,8 @@ typedef struct /** @defgroup USART_Clock_Polarity USART Clock Polarity * @{ */ -#define USART_POLARITY_LOW ((uint32_t)0x00000000) -#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) +#define USART_POLARITY_LOW 0x00000000U +#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /** * @} */ @@ -230,8 +226,8 @@ typedef struct /** @defgroup USART_Clock_Phase USART Clock Phase * @{ */ -#define USART_PHASE_1EDGE ((uint32_t)0x00000000) -#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) +#define USART_PHASE_1EDGE 0x00000000U +#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /** * @} */ @@ -239,8 +235,8 @@ typedef struct /** @defgroup USART_Last_Bit USART Last Bit * @{ */ -#define USART_LASTBIT_DISABLE ((uint32_t)0x00000000) -#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) +#define USART_LASTBIT_DISABLE 0x00000000U +#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /** * @} */ @@ -248,8 +244,8 @@ typedef struct /** @defgroup USART_NACK_State USART NACK State * @{ */ -#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK) -#define USART_NACK_DISABLE ((uint32_t)0x00000000) +#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK) +#define USART_NACK_DISABLE 0x00000000U /** * @} */ @@ -259,9 +255,6 @@ typedef struct * - 0xXXXX : Flag mask in the SR register * @{ */ - -#define USART_FLAG_CTS ((uint32_t)USART_SR_CTS) -#define USART_FLAG_LBD ((uint32_t)USART_SR_LBD) #define USART_FLAG_TXE ((uint32_t)USART_SR_TXE) #define USART_FLAG_TC ((uint32_t)USART_SR_TC) #define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) @@ -276,27 +269,25 @@ typedef struct /** @defgroup USART_Interrupt_definition USART Interrupts Definition * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask (16 bits) in the Y register - * - Y : Interrupt source register (4bits) - * - 0001: CR1 register - * - 0010: CR2 register - * - 0011: CR3 register + * - XXXX : Interrupt mask in the XX register + * - Y : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register * * @{ */ -#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_PEIE)) -#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TXEIE)) -#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_TCIE)) -#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_RXNEIE)) -#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28 | USART_CR1_IDLEIE)) - -#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28 | USART_CR2_LBDIE)) - -#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_CTSIE)) -#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28 | USART_CR3_EIE)) +#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) +#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) +#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) +#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) +#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) +#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) +#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) +#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) /** * @} */ @@ -305,21 +296,18 @@ typedef struct * @} */ - /* Exported macro ------------------------------------------------------------*/ /** @defgroup USART_Exported_Macros USART Exported Macros * @{ */ - /** @brief Reset USART handle state * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) -/** @brief Check whether the specified USART flag is set or not. +/** @brief Checks whether the specified USART flag is set or not. * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __FLAG__: specifies the flag to check. @@ -334,10 +322,9 @@ typedef struct * @arg USART_FLAG_PE: Parity Error flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ - #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) -/** @brief Clear the specified USART pending flags. +/** @brief Clears the specified USART pending flags. * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __FLAG__: specifies the flag to check. @@ -345,62 +332,56 @@ typedef struct * @arg USART_FLAG_TC: Transmission Complete flag. * @arg USART_FLAG_RXNE: Receive data register not empty flag. * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software + * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software * sequence: a read operation to USART_SR register followed by a read * operation to USART_DR register. * @note RXNE flag can be also cleared by a read to the USART_DR register. - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register followed by a write operation to USART_DR register. - * @note TXE flag is cleared only by a write to the USART_DR register. + * @note TC flag can be also cleared by software sequence: a read operation to + * USART_SR register followed by a write operation to USART_DR register + * @note TXE flag is cleared only by a write to the USART_DR register * - * @retval None */ -#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) +#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) /** @brief Clear the USART PE pending flag. * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ -#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \ -do{ \ - __IO uint32_t tmpreg; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - tmpreg = (__HANDLE__)->Instance->DR; \ - UNUSED(tmpreg); \ -}while(0) - +#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg = 0x00U; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + UNUSED(tmpreg); \ + } while(0U) /** @brief Clear the USART FE pending flag. * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the USART NE pending flag. * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the USART ORE pending flag. * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None + */ #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) /** @brief Clear the USART IDLE pending flag. * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__) -/** @brief Enable the specified Usart interrupts. +/** @brief Enable the specified USART interrupts. * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __INTERRUPT__: specifies the USART interrupt source to enable. @@ -411,14 +392,13 @@ do{ \ * @arg USART_IT_IDLE: Idle line detection interrupt * @arg USART_IT_PE: Parity Error interrupt * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None + * This parameter can be: ENABLE or DISABLE. */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \ ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK))) - -/** @brief Disable the specified Usart interrupts. +/** @brief Disable the specified USART interrupts. * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __INTERRUPT__: specifies the USART interrupt source to disable. @@ -429,15 +409,13 @@ do{ \ * @arg USART_IT_IDLE: Idle line detection interrupt * @arg USART_IT_PE: Parity Error interrupt * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None + * This parameter can be: ENABLE or DISABLE. */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ - (((__INTERRUPT__) >> 28) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK))) +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ + (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK))) - - -/** @brief Check whether the specified Usart interrupt has occurred or not. +/** @brief Checks whether the specified USART interrupt has occurred or not. * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). * @param __IT__: specifies the USART interrupt source to check. @@ -450,113 +428,43 @@ do{ \ * @arg USART_IT_PE: Parity Error interrupt * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == USART_CR2_REG_INDEX)? \ +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \ (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK)) /** @brief Enable USART * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None - */ + */ #define __HAL_USART_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE)) /** @brief Disable USART * @param __HANDLE__: specifies the USART Handle. * USART Handle selects the USARTx peripheral (USART availability and x value depending on device). - * @retval None */ #define __HAL_USART_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE)) - - -/** - * @} - */ - - -/* Private macros --------------------------------------------------------*/ -/** @defgroup USART_Private_Macros USART Private Macros - * @{ - */ - -#define USART_CR1_REG_INDEX 1 -#define USART_CR2_REG_INDEX 2 -#define USART_CR3_REG_INDEX 3 - -#define USART_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) -#define USART_DIVMANT(__PCLK__, __BAUD__) (USART_DIV((__PCLK__), (__BAUD__))/100) -#define USART_DIVFRAQ(__PCLK__, __BAUD__) (((USART_DIV((__PCLK__), (__BAUD__)) - (USART_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) -#define USART_BRR(__PCLK__, __BAUD__) ((USART_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(USART_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F)) - -/** Check USART Baud rate - * __BAUDRATE__: Baudrate specified by the user - * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz) - * divided by the smallest oversampling used on the USART (i.e. 16) - * return : TRUE or FALSE - */ -#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4500001) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \ - ((LENGTH) == USART_WORDLENGTH_9B)) - -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \ - ((STOPBITS) == USART_STOPBITS_0_5) || \ - ((STOPBITS) == USART_STOPBITS_1_5) || \ - ((STOPBITS) == USART_STOPBITS_2)) - -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \ - ((PARITY) == USART_PARITY_EVEN) || \ - ((PARITY) == USART_PARITY_ODD)) - -#define IS_USART_MODE(MODE) ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00) && ((MODE) != (uint32_t)0x00000000)) - -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \ - ((CLOCK) == USART_CLOCK_ENABLE)) - -#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH)) - -#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE)) - -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \ - ((LASTBIT) == USART_LASTBIT_ENABLE)) - -#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \ - ((NACK) == USART_NACK_DISABLE)) - -/** USART interruptions flag mask - * - */ -#define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ - USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE ) - /** * @} */ - - /* Exported functions --------------------------------------------------------*/ - -/** @addtogroup USART_Exported_Functions USART Exported Functions +/** @addtogroup USART_Exported_Functions * @{ */ - -/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup USART_Exported_Functions_Group1 * @{ */ - -/* Initialization and de-initialization functions ******************************/ +/* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); void HAL_USART_MspInit(USART_HandleTypeDef *husart); void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); - /** * @} */ -/** @addtogroup USART_Exported_Functions_Group2 IO operation functions +/** @addtogroup USART_Exported_Functions_Group2 * @{ */ - /* IO operation functions *******************************************************/ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); @@ -570,6 +478,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart); + void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); @@ -577,25 +489,91 @@ void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); +void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart); +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); +/** + * @} + */ /** * @} */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_Private_Constants USART Private Constants + * @{ + */ +/** @brief USART interruptions flag mask + * + */ +#define USART_IT_MASK 0x0000FFFFU -/* Peripheral Control functions ***********************************************/ +#define USART_CR1_REG_INDEX 1U +#define USART_CR2_REG_INDEX 2U +#define USART_CR3_REG_INDEX 3U +/** + * @} + */ -/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions +/* Private macros ------------------------------------------------------------*/ +/** @defgroup USART_Private_Macros USART Private Macros * @{ */ +#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \ + ((NACK) == USART_NACK_DISABLE)) -/* Peripheral State and Error functions ***************************************/ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \ + ((LASTBIT) == USART_LASTBIT_ENABLE)) +#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE)) + +#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH)) + +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \ + ((CLOCK) == USART_CLOCK_ENABLE)) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \ + ((LENGTH) == USART_WORDLENGTH_9B)) + +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \ + ((STOPBITS) == USART_STOPBITS_0_5) || \ + ((STOPBITS) == USART_STOPBITS_1_5) || \ + ((STOPBITS) == USART_STOPBITS_2)) + +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \ + ((PARITY) == USART_PARITY_EVEN) || \ + ((PARITY) == USART_PARITY_ODD)) + +#define IS_USART_MODE(MODE) ((((MODE) & 0xFFF3U) == 0x00U) && ((MODE) != 0x00U)) + +#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U) + +#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_))) + +#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U) + +#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U) + +#define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU)) /** * @} */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup USART_Private_Functions USART Private Functions + * @{ + */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.c index 128f16f2bc7..aa435f318f0 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.c @@ -2,22 +2,21 @@ ****************************************************************************** * @file stm32f1xx_hal_wwdg.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral State functions - * + * + Peripheral State functions @verbatim ============================================================================== ##### WWDG specific features ##### ============================================================================== [..] Once enabled the WWDG generates a system reset on expiry of a programmed - time period, unless the program refreshes the Counter (T[6;0] downcounter) + time period, unless the program refreshes the counter (downcounter) before reaching 0x3F value (i.e. a reset is generated when the counter value rolls over from 0x40 to 0x3F). @@ -29,43 +28,63 @@ reset occurs. (+) The WWDG counter input clock is derived from the APB clock divided by a programmable prescaler. - (+) WWDG clock (Hz) = PCLK / (4096 * Prescaler) - (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock - where T[5;0] are the lowest 6 bits of Counter. + (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler) + (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock (+) WWDG Counter refresh is allowed between the following limits : - (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock - (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock + (++) min time (mS) = 1000 * (Counter _ Window) / WWDG clock + (++) max time (mS) = 1000 * (Counter _ 0x40) / WWDG clock - (+) Min-max timeout value @48 MHz(PCLK): ~85,3us / ~5,46 ms + (+) Min-max timeout value at 36 MHz(PCLK1): 910 us / 58.25 ms + + (+) The Early Wakeup Interrupt (EWI) can be used if specific safety + operations or data logging must be performed before the actual reset is + generated. When the downcounter reaches the value 0x40, an EWI interrupt + is generated and the corresponding interrupt service routine (ISR) can + be used to trigger specific actions (such as communications or data + logging), before resetting the device. + In some applications, the EWI interrupt can be used to manage a software + system check and/or system recovery/graceful degradation, without + generating a WWDG reset. In this case, the corresponding interrupt + service routine (ISR) should reload the WWDG counter to avoid the WWDG + reset, then trigger the required actions. + Note:When the EWI interrupt cannot be served, e.g. due to a system lock + in a higher priority task, the WWDG reset will eventually be generated. + + (+) Debug mode : When the microcontroller enters debug mode (core halted), + the WWDG counter either continues to work normally or stops, depending + on DBG_WWDG_STOP configuration bit in DBG module, accessible through + __HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros ##### How to use this driver ##### ============================================================================== [..] (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). - (+) Set the WWDG prescaler, refresh window and counter value - using HAL_WWDG_Init() function. - (+) Start the WWDG using HAL_WWDG_Start() function. - When the WWDG is enabled the counter value should be configured to - a value greater than 0x40 to prevent generating an immediate reset. - (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is - generated when the counter reaches 0x40, and then start the WWDG using - HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can - add his own code by customization of function pointer HAL_WWDG_WakeupCallback - Once enabled, EWI interrupt cannot be disabled except by a system reset. - (+) Then the application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset, using + + (+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup + Interrupt mode using using HAL_WWDG_Init() function. + This enables WWDG peripheral and the downcounter starts downcounting + from given counter value. + Init function can be called again to modify all watchdog parameters, + however if EWI mode has been set once, it can't be clear until next + reset. + + (+) The application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset using HAL_WWDG_Refresh() function. This operation must occur only when - the counter is lower than the refresh window value already programmed. - + the counter is lower than the window value already programmed. + + (+) if Early Wakeup Interrupt mode is enable an interrupt is generated when + the counter reaches 0x40. User can add his own code in weak function + HAL_WWDG_EarlyWakeupCallback(). + *** WWDG HAL driver macros list *** ================================== [..] Below the list of most used macros in WWDG HAL driver. - - (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral - (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status - (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags - (+) __HAL_WWDG_ENABLE_IT: Enables the WWDG early wakeup interrupt + + (+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source. + (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status. + (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags. @endverbatim ****************************************************************************** @@ -96,7 +115,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" @@ -105,13 +124,12 @@ * @{ */ +#ifdef HAL_WWDG_MODULE_ENABLED /** @defgroup WWDG WWDG * @brief WWDG HAL module driver. * @{ */ -#ifdef HAL_WWDG_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -123,30 +141,28 @@ * @{ */ -/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim +/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions. + * +@verbatim ============================================================================== - ##### Initialization and de-initialization functions ##### + ##### Initialization and Configuration functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize the WWDG according to the specified parameters - in the WWDG_InitTypeDef and create the associated handle - (+) DeInitialize the WWDG peripheral - (+) Initialize the WWDG MSP - (+) DeInitialize the WWDG MSP - + (+) Initialize and start the WWDG according to the specified parameters + in the WWDG_InitTypeDef of associated handle. + (+) Initialize the WWDG MSP. + @endverbatim * @{ */ /** - * @brief Initializes the WWDG according to the specified - * parameters in the WWDG_InitTypeDef and creates the associated handle. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @brief Initialize the WWDG according to the specified. + * parameters in the WWDG_InitTypeDef of associated handle. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) @@ -160,103 +176,39 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) /* Check the parameters */ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler)); - assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); - assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); - - if(hwwdg->State == HAL_WWDG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hwwdg->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ - HAL_WWDG_MspInit(hwwdg); - } - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Set WWDG Prescaler and Window */ - MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window)); - - /* Set WWDG Counter */ - MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter); + assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); + assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); + assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode)); - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Return function status */ - return HAL_OK; -} + /* Init the low level hardware */ + HAL_WWDG_MspInit(hwwdg); -/** - * @brief DeInitializes the WWDG peripheral. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) -{ - /* Check the WWDG handle allocation */ - if(hwwdg == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); + /* Set WWDG Counter */ + WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* DeInit the low level hardware */ - HAL_WWDG_MspDeInit(hwwdg); - - /* Reset WWDG Control register */ - hwwdg->Instance->CR = (uint32_t)0x0000007F; - - /* Reset WWDG Configuration register */ - hwwdg->Instance->CFR = (uint32_t)0x0000007F; - - /* Reset WWDG Status register */ - hwwdg->Instance->SR = 0; - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hwwdg); + /* Set WWDG Prescaler and Window */ + WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window)); /* Return function status */ return HAL_OK; } /** - * @brief Initializes the WWDG MSP. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @brief Initialize the WWDG MSP. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @note When rewriting this function in user file, mechanism may be added + * to avoid multiple initialize when HAL_WWDG_Init function is called + * again to change parameters. * @retval None */ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) { /* Prevent unused argument(s) compilation warning */ UNUSED(hwwdg); - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_WWDG_MspInit could be implemented in the user file - */ -} -/** - * @brief DeInitializes the WWDG MSP. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval None - */ -__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hwwdg); - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_WWDG_MspDeInit could be implemented in the user file + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_WWDG_MspInit could be implemented in the user file */ } @@ -264,184 +216,82 @@ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) * @} */ -/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions +/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions * -@verbatim +@verbatim ============================================================================== - ##### IO operation functions ##### + ##### IO operation functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: - (+) Start the WWDG. (+) Refresh the WWDG. - (+) Handle WWDG interrupt request. + (+) Handle WWDG interrupt request and associated function callback. @endverbatim * @{ */ /** - * @brief Starts the WWDG. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @brief Refresh the WWDG. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval HAL status */ -HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg) +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg) { - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Enable the peripheral */ - __HAL_WWDG_ENABLE(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the WWDG with interrupt enabled. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg) -{ - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Enable the Early Wakeup Interrupt */ - __HAL_WWDG_ENABLE_IT(hwwdg, WWDG_IT_EWI); - - /* Enable the peripheral */ - __HAL_WWDG_ENABLE(hwwdg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Refreshes the WWDG. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @param Counter: value of counter to put in WWDG counter - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) -{ - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to WWDG CR the WWDG Counter value to refresh with */ - MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); - + WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter)); + /* Return function status */ return HAL_OK; } /** - * @brief Handles WWDG interrupt request. - * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations - * or data logging must be performed before the actual reset is generated. - * The EWI interrupt is enabled when calling HAL_WWDG_Start_IT function. - * When the downcounter reaches the value 0x40, and EWI interrupt is - * generated and the corresponding Interrupt Service Routine (ISR) can - * be used to trigger specific actions (such as communications or data - * logging), before resetting the device. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @brief Handle WWDG interrupt request. + * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations + * or data logging must be performed before the actual reset is generated. + * The EWI interrupt is enabled by calling HAL_WWDG_Init function with + * EWIMode set to WWDG_EWI_ENABLE. + * When the downcounter reaches the value 0x40, and EWI interrupt is + * generated and the corresponding Interrupt Service Routine (ISR) can + * be used to trigger specific actions (such as communications or data + * logging), before resetting the device. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) -{ +{ /* Check if Early Wakeup Interrupt is enable */ if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) { - /* Wheck if WWDG Early Wakeup Interrupt occurred */ - if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) - { - /* Early Wakeup callback */ - HAL_WWDG_WakeupCallback(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - + /* Check if WWDG Early Wakeup Interrupt occurred */ + if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) + { /* Clear the WWDG Early Wakeup flag */ - __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF); - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); + __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF); + + /* Early Wakeup callback */ + HAL_WWDG_EarlyWakeupCallback(hwwdg); + } } -} } /** - * @brief Early Wakeup WWDG callback. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. + * @brief WWDG Early Wakeup callback. + * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. * @retval None */ -__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) +__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg) { /* Prevent unused argument(s) compilation warning */ UNUSED(hwwdg); - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_WWDG_WakeupCallback could be implemented in the user file - */ -} -/** - * @} - */ - -/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the WWDG state. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL state - */ -HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg) -{ - return hwwdg->State; + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file + */ } /** diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.h index e4fb044b22a..4f6510af0f2 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_wwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_hal_wwdg.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention @@ -55,54 +55,39 @@ */ /* Exported types ------------------------------------------------------------*/ - /** @defgroup WWDG_Exported_Types WWDG Exported Types * @{ */ -/** - * @brief WWDG HAL State Structure definition - */ -typedef enum -{ - HAL_WWDG_STATE_RESET = 0x00, /*!< WWDG not yet initialized or disabled */ - HAL_WWDG_STATE_READY = 0x01, /*!< WWDG initialized and ready for use */ - HAL_WWDG_STATE_BUSY = 0x02, /*!< WWDG internal process is ongoing */ - HAL_WWDG_STATE_TIMEOUT = 0x03, /*!< WWDG timeout state */ - HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */ -}HAL_WWDG_StateTypeDef; - /** - * @brief WWDG Init structure definition - */ + * @brief WWDG Init structure definition + */ typedef struct { - uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. - This parameter can be a value of @ref WWDG_Prescaler */ - - uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. - This parameter must be a number lower than Max_Data = 0x80 */ - - uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. - This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ + uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. + This parameter can be a value of @ref WWDG_Prescaler */ + + uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. + This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */ + + uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. + This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ + + uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. + This parameter can be a value of @ref WWDG_EWI_Mode */ }WWDG_InitTypeDef; -/** - * @brief WWDG handle Structure definition - */ +/** + * @brief WWDG handle Structure definition + */ typedef struct { WWDG_TypeDef *Instance; /*!< Register base address */ - + WWDG_InitTypeDef Init; /*!< WWDG required parameters */ - - HAL_LockTypeDef Lock; /*!< WWDG locking object */ - - __IO HAL_WWDG_StateTypeDef State; /*!< WWDG communication state */ - -}WWDG_HandleTypeDef; +}WWDG_HandleTypeDef; /** * @} */ @@ -115,8 +100,8 @@ typedef struct /** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition * @{ - */ -#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */ + */ +#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */ /** * @} */ @@ -124,8 +109,8 @@ typedef struct /** @defgroup WWDG_Flag_definition WWDG Flag definition * @brief WWDG Flag definition * @{ - */ -#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */ + */ +#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */ /** * @} */ @@ -133,33 +118,43 @@ typedef struct /** @defgroup WWDG_Prescaler WWDG Prescaler * @{ */ -#define WWDG_PRESCALER_1 ((uint32_t)0x00000000) /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ #define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ #define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ #define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */ +/** + * @} + */ +/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode + * @{ + */ +#define WWDG_EWI_DISABLE 0x00000000U /*!< EWI Disable */ +#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */ /** * @} - */ + */ /** * @} - */ + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup WWDG_Private_Macros WWDG Private Macros * @{ */ -#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ - ((__PRESCALER__) == WWDG_PRESCALER_2) || \ - ((__PRESCALER__) == WWDG_PRESCALER_4) || \ - ((__PRESCALER__) == WWDG_PRESCALER_8)) +#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ + ((__PRESCALER__) == WWDG_PRESCALER_2) || \ + ((__PRESCALER__) == WWDG_PRESCALER_4) || \ + ((__PRESCALER__) == WWDG_PRESCALER_8)) -#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F) +#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W)) - -#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F)) +#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T)) + +#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \ + ((__MODE__) == WWDG_EWI_DISABLE)) /** * @} */ @@ -171,55 +166,28 @@ typedef struct * @{ */ -/** @brief Reset WWDG handle state - * @param __HANDLE__: WWDG handle - * @retval None - */ -#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_WWDG_STATE_RESET) - /** * @brief Enables the WWDG peripheral. * @param __HANDLE__: WWDG handle * @retval None */ -#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) - -/** - * @brief Disables the WWDG peripheral. - * @param __HANDLE__: WWDG handle - * @note WARNING: This is a dummy macro for HAL code alignment. - * Once enable, WWDG Peripheral cannot be disabled except by a system reset. - * @retval None - */ -#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */ +#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) /** * @brief Enables the WWDG early wakeup interrupt. * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the interrupt to enable. + * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt * @note Once enabled this interrupt cannot be disabled except by a system reset. * @retval None */ -#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__)) +#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__)) /** - * @brief Disables the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the interrupt to disable. - * This parameter can be one of the following values: - * @arg WWDG_IT_EWI: Early wakeup interrupt - * @note WARNING: This is a dummy macro for HAL code alignment. - * Once enabled this interrupt cannot be disabled except by a system reset. - * @retval None - */ -#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */ - -/** - * @brief Gets the selected WWDG's it status. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the it to check. + * @brief Checks whether the selected WWDG interrupt has occurred or not. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the it to check. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT * @retval The new state of WWDG_FLAG (SET or RESET). @@ -236,9 +204,9 @@ typedef struct #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) /** - * @brief Gets the selected WWDG's flag status. - * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to check. + * @brief Check whether the specified WWDG flag is set or not. + * @param __HANDLE__ WWDG handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag * @retval The new state of WWDG_FLAG (SET or RESET). @@ -253,7 +221,7 @@ typedef struct * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag * @retval None */ -#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) +#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) /** @brief Checks if the specified WWDG interrupt source is enabled or disabled. * @param __HANDLE__: WWDG Handle. @@ -266,10 +234,9 @@ typedef struct /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ - /** @addtogroup WWDG_Exported_Functions * @{ */ @@ -278,51 +245,35 @@ typedef struct * @{ */ /* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); -HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg); - +HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); /** * @} */ - + /** @addtogroup WWDG_Exported_Functions_Group2 * @{ */ /* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg); -HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg); -HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter); -void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); - +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg); /** * @} */ -/** @addtogroup WWDG_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions **************************************************/ -HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg); - /** * @} - */ + */ /** * @} - */ + */ /** * @} - */ + */ -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_adc.c new file mode 100644 index 00000000000..24ff8f3713e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_adc.c @@ -0,0 +1,903 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_adc.c + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief ADC LL module driver + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_adc.h" +#include "stm32f1xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (ADC1) || defined (ADC2) || defined (ADC3) + +/** @addtogroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup ADC_LL_Private_Macros + * @{ + */ + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* common to several ADC instances. */ +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC instance. */ +#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ + ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ + || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ + ) + +#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ + ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ + || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ + ) + +#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ + ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ + || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC group regular */ +#if defined(ADC3) +#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ + ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ + ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ + ) \ + : \ + ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \ + ) \ + ) +#else +#if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC) +#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ + ) +#else +#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + ) +#endif +#endif +#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ + ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ + || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ + ) + +#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ + ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ + ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ + ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC group injected */ +#if defined(ADC3) +#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ + ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \ + ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ + ) \ + : \ + ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \ + ) \ + ) +#else +#if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC) +#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ + ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ + ) +#else +#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ + ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ + ) +#endif +#endif +#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ + ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ + || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ + ) + +#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ + ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ + || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ + || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ + || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ + ) + +#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ + ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ + || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ + ) + +#if defined(ADC_MULTIMODE_SUPPORT) +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* multimode. */ +#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ + ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_FAST) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_SLOW) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM) \ + ) + +#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ + ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ + || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ + || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ + ) + +#endif /* ADC_MULTIMODE_SUPPORT */ +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize registers of all ADC instances belonging to + * the same ADC common instance to their default reset values. + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + + /* Force reset of ADC clock (core clock) */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1); + + /* Release reset of ADC clock (core clock) */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1); + + return SUCCESS; +} + +/** + * @brief Initialize some features of ADC common parameters + * (all ADC instances belonging to the same ADC common instance) + * and multimode (for devices with several ADC instances available). + * @note The setting of ADC common parameters is conditioned to + * ADC instances state: + * All ADC instances belonging to the same ADC common instance + * must be disabled. + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are initialized + * - ERROR: ADC common registers are not initialized + */ +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); +#if defined(ADC_MULTIMODE_SUPPORT) + assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Note: Hardware constraint (refer to description of functions */ + /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ + /* On this STM32 serie, setting of these features is conditioned to */ + /* ADC state: */ + /* All ADC instances of the ADC common group must be disabled. */ + if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) + { + /* Configuration of ADC hierarchical scope: */ + /* - common to several ADC */ + /* (all ADC instances belonging to the same ADC common instance) */ + /* - multimode (if several ADC instances available on the */ + /* selected device) */ + /* - Set ADC multimode configuration */ + /* - Set ADC multimode DMA transfer */ + /* - Set ADC multimode: delay between 2 sampling phases */ +#if defined(ADC_MULTIMODE_SUPPORT) + if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + { + MODIFY_REG(ADCxy_COMMON->CR1, + ADC_CR1_DUALMOD, + ADC_CommonInitStruct->Multimode + ); + } + else + { + MODIFY_REG(ADCxy_COMMON->CR1, + ADC_CR1_DUALMOD, + LL_ADC_MULTI_INDEPENDENT + ); + } +#endif + } + else + { + /* Initialization error: One or several ADC instances belonging to */ + /* the same ADC common instance are not disabled. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. + * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +{ + /* Set ADC_CommonInitStruct fields to default values */ + /* Set fields of ADC common */ + /* (all ADC instances belonging to the same ADC common instance) */ + +#if defined(ADC_MULTIMODE_SUPPORT) + /* Set fields of ADC multimode */ + ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; +#endif /* ADC_MULTIMODE_SUPPORT */ +} + +/** + * @brief De-initialize registers of the selected ADC instance + * to their default reset values. + * @note To reset all ADC instances quickly (perform a hard reset), + * use function @ref LL_ADC_CommonDeInit(). + * @param ADCx ADC instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are de-initialized + * - ERROR: ADC registers are not de-initialized + */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + /* Disable ADC instance if not already disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 1U) + { + /* Set ADC group regular trigger source to SW start to ensure to not */ + /* have an external trigger event occurring during the conversion stop */ + /* ADC disable process. */ + LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); + + /* Set ADC group injected trigger source to SW start to ensure to not */ + /* have an external trigger event occurring during the conversion stop */ + /* ADC disable process. */ + LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); + + /* Disable the ADC instance */ + LL_ADC_Disable(ADCx); + } + + /* Check whether ADC state is compliant with expected state */ + /* (hardware requirements of bits state to reset registers below) */ + if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) + { + /* ========== Reset ADC registers ========== */ + /* Reset register SR */ + CLEAR_BIT(ADCx->SR, + ( LL_ADC_FLAG_STRT + | LL_ADC_FLAG_JSTRT + | LL_ADC_FLAG_EOS + | LL_ADC_FLAG_JEOS + | LL_ADC_FLAG_AWD1 ) + ); + + /* Reset register CR1 */ + #if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG) + + CLEAR_BIT(ADCx->CR1, + ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DUALMOD + | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN + | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN + | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE + | ADC_CR1_AWDCH ) + ); + #else + + CLEAR_BIT(ADCx->CR1, + ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM + | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO + | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE + | ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH ) + ); + #endif + + /* Reset register CR2 */ + CLEAR_BIT(ADCx->CR2, + ( ADC_CR2_TSVREFE + | ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL + | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL + | ADC_CR2_ALIGN | ADC_CR2_DMA + | ADC_CR2_RSTCAL | ADC_CR2_CAL + | ADC_CR2_CONT | ADC_CR2_ADON ) + ); + + /* Reset register SMPR1 */ + CLEAR_BIT(ADCx->SMPR1, + ( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 + | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 + | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) + ); + + /* Reset register SMPR2 */ + CLEAR_BIT(ADCx->SMPR2, + ( ADC_SMPR2_SMP9 + | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 + | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 + | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) + ); + + /* Reset register JOFR1 */ + CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); + /* Reset register JOFR2 */ + CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); + /* Reset register JOFR3 */ + CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); + /* Reset register JOFR4 */ + CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); + + /* Reset register HTR */ + SET_BIT(ADCx->HTR, ADC_HTR_HT); + /* Reset register LTR */ + CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); + + /* Reset register SQR1 */ + CLEAR_BIT(ADCx->SQR1, + ( ADC_SQR1_L + | ADC_SQR1_SQ16 + | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) + ); + + /* Reset register SQR2 */ + CLEAR_BIT(ADCx->SQR2, + ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 + | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) + ); + + + /* Reset register JSQR */ + CLEAR_BIT(ADCx->JSQR, + ( ADC_JSQR_JL + | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 + | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) + ); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable */ + + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ + /* bits in access mode read only, no direct reset applicable */ + + } + + return status; +} + +/** + * @brief Initialize some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Affects both group regular and group injected (availability + * of ADC group injected depends on STM32 families). + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, some other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular or group injected sequencer: + * map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); + assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 0U) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC instance */ + /* - Set ADC conversion data alignment */ + MODIFY_REG(ADCx->CR1, + ADC_CR1_SCAN + , + ADC_InitStruct->SequencersScanMode + ); + + MODIFY_REG(ADCx->CR2, + ADC_CR2_ALIGN + , + ADC_InitStruct->DataAlignment + ); + + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_InitTypeDef field to default value. + * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) +{ + /* Set ADC_InitStruct fields to default values */ + /* Set fields of ADC instance */ + ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; + + /* Enable scan mode to have a generic behavior with ADC of other */ + /* STM32 families, without this setting available: */ + /* ADC group regular sequencer and ADC group injected sequencer depend */ + /* only of their own configuration. */ + ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; + +} + +/** + * @brief Initialize some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular or group injected sequencer: + * map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); +#if defined(ADC3) + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource)); +#else + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); +#endif + assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); + if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + { + assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + } + assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); + assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 0U) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC group regular */ + /* - Set ADC group regular trigger source */ + /* - Set ADC group regular sequencer length */ + /* - Set ADC group regular sequencer discontinuous mode */ + /* - Set ADC group regular continuous mode */ + /* - Set ADC group regular conversion data transfer: no transfer or */ + /* transfer by DMA, and DMA requests mode */ + /* Note: On this STM32 serie, ADC trigger edge is set when starting */ + /* ADC conversion. */ + /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ + if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + { + MODIFY_REG(ADCx->CR1, + ADC_CR1_DISCEN + | ADC_CR1_DISCNUM + , + ADC_REG_InitStruct->SequencerLength + | ADC_REG_InitStruct->SequencerDiscont + ); + } + else + { + MODIFY_REG(ADCx->CR1, + ADC_CR1_DISCEN + | ADC_CR1_DISCNUM + , + ADC_REG_InitStruct->SequencerLength + | LL_ADC_REG_SEQ_DISCONT_DISABLE + ); + } + + MODIFY_REG(ADCx->CR2, + ADC_CR2_EXTSEL + | ADC_CR2_CONT + | ADC_CR2_DMA + , + ADC_REG_InitStruct->TriggerSource + | ADC_REG_InitStruct->ContinuousMode + | ADC_REG_InitStruct->DMATransfer + ); + + /* Set ADC group regular sequencer length and scan direction */ + /* Note: Hardware constraint (refer to description of this function): */ + /* Note: If ADC instance feature scan mode is disabled */ + /* (refer to ADC instance initialization structure */ + /* parameter @ref SequencersScanMode */ + /* or function @ref LL_ADC_SetSequencersScanMode() ), */ + /* this parameter is discarded. */ + LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. + * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +{ + /* Set ADC_REG_InitStruct fields to default values */ + /* Set fields of ADC group regular */ + /* Note: On this STM32 serie, ADC trigger edge is set when starting */ + /* ADC conversion. */ + /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ + ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; + ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; + ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; +} + +/** + * @brief Initialize some features of ADC group injected. + * @note These parameters have an impact on ADC scope: ADC group injected. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "INJ"). + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group injected sequencer: + * map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); +#if defined(ADC3) + assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource)); +#else + assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); +#endif + assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); + if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) + { + assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); + } + assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 0U) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC group injected */ + /* - Set ADC group injected trigger source */ + /* - Set ADC group injected sequencer length */ + /* - Set ADC group injected sequencer discontinuous mode */ + /* - Set ADC group injected conversion trigger: independent or */ + /* from ADC group regular */ + /* Note: On this STM32 serie, ADC trigger edge is set when starting */ + /* ADC conversion. */ + /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ + if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + { + MODIFY_REG(ADCx->CR1, + ADC_CR1_JDISCEN + | ADC_CR1_JAUTO + , + ADC_INJ_InitStruct->SequencerDiscont + | ADC_INJ_InitStruct->TrigAuto + ); + } + else + { + MODIFY_REG(ADCx->CR1, + ADC_CR1_JDISCEN + | ADC_CR1_JAUTO + , + LL_ADC_REG_SEQ_DISCONT_DISABLE + | ADC_INJ_InitStruct->TrigAuto + ); + } + + MODIFY_REG(ADCx->CR2, + ADC_CR2_JEXTSEL + , + ADC_INJ_InitStruct->TriggerSource + ); + + /* Note: Hardware constraint (refer to description of this function): */ + /* Note: If ADC instance feature scan mode is disabled */ + /* (refer to ADC instance initialization structure */ + /* parameter @ref SequencersScanMode */ + /* or function @ref LL_ADC_SetSequencersScanMode() ), */ + /* this parameter is discarded. */ + LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. + * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) +{ + /* Set ADC_INJ_InitStruct fields to default values */ + /* Set fields of ADC group injected */ + ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; + ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; + ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; + ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 || ADC2 || ADC3 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_adc.h new file mode 100644 index 00000000000..b0c7a490dcf --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_adc.h @@ -0,0 +1,3950 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_adc.h + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief Header file of ADC LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_ADC_H +#define __STM32F1xx_LL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (ADC1) || defined (ADC2) || defined (ADC3) + +/** @defgroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Constants ADC Private Constants + * @{ + */ + +/* Internal mask for ADC group regular sequencer: */ +/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ +/* - sequencer register offset */ +/* - sequencer rank bits position into the selected register */ + +/* Internal register offset for ADC group regular sequencer configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_SQR1_REGOFFSET 0x00000000U +#define ADC_SQR2_REGOFFSET 0x00000100U +#define ADC_SQR3_REGOFFSET 0x00000200U +#define ADC_SQR4_REGOFFSET 0x00000300U + +#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) +#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Definition of ADC group regular sequencer bits information to be inserted */ +/* into ADC group regular sequencer ranks literals definition. */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ +#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ +#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ +#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ +#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ +#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ +#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ +#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ +#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ + +/* Internal mask for ADC group injected sequencer: */ +/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ +/* - data register offset */ +/* - offset register offset */ +/* - sequencer rank bits position into the selected register */ + +/* Internal register offset for ADC group injected data register */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_JDR1_REGOFFSET 0x00000000U +#define ADC_JDR2_REGOFFSET 0x00000100U +#define ADC_JDR3_REGOFFSET 0x00000200U +#define ADC_JDR4_REGOFFSET 0x00000300U + +/* Internal register offset for ADC group injected offset configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_JOFR1_REGOFFSET 0x00000000U +#define ADC_JOFR2_REGOFFSET 0x00001000U +#define ADC_JOFR3_REGOFFSET 0x00002000U +#define ADC_JOFR4_REGOFFSET 0x00003000U + +#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) +#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) +#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Internal mask for ADC channel: */ +/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ +/* - channel identifier defined by number */ +/* - channel differentiation between external channels (connected to */ +/* GPIO pins) and internal channels (connected to internal paths) */ +/* - channel sampling time defined by SMPRx register offset */ +/* and SMPx bits positions into SMPRx register */ +#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) +/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ + +/* Channel differentiation between external and internal channels */ +#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ +#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) + +/* Internal register offset for ADC channel sampling time configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_SMPR1_REGOFFSET 0x00000000U +#define ADC_SMPR2_REGOFFSET 0x02000000U +#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) + +#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U +#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ + +/* Definition of channels ID number information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_NUMBER 0x00000000U +#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) +#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) +#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) +#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) +#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) + +/* Definition of channels sampling time information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ +#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ +#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ +#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ +#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ +#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ +#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ +#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ +#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ +#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ +#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ +#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ +#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ +#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ +#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ +#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ +#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ +#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ + +/* Internal mask for ADC analog watchdog: */ +/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ +/* (concatenation of multiple bits used in different analog watchdogs, */ +/* (feature of several watchdogs not available on all STM32 families)). */ +/* - analog watchdog 1: monitored channel defined by number, */ +/* selection of ADC group (ADC groups regular and-or injected). */ + +/* Internal register offset for ADC analog watchdog channel configuration */ +#define ADC_AWD_CR1_REGOFFSET 0x00000000U + +#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) + +#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) +#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) + +/* Internal register offset for ADC analog watchdog threshold configuration */ +#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U +#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U +#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) + +/* ADC registers bits positions */ +#define ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Macros ADC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: isolate bits with the + * selected mask and shift them to the register LSB + * (shift mask on register position bit 0). + * @param __BITS__ Bits in register 32 bits + * @param __MASK__ Mask in register 32 bits + * @retval Bits in register 32 bits + */ +#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ + (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address + */ +#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of ADC common parameters + * and multimode + * (all ADC instances belonging to the same ADC common instance). + * @note The setting of these parameters by function @ref LL_ADC_CommonInit() + * is conditioned to ADC instances state (all ADC instances + * sharing the same ADC common instance): + * All ADC instances sharing the same ADC common instance must be + * disabled. + */ +typedef struct +{ + uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). + This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ +} LL_ADC_CommonInitTypeDef; +/** + * @brief Structure definition of some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Affects both group regular and group injected (availability + * of ADC group injected depends on STM32 families). + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t DataAlignment; /*!< Set ADC conversion data alignment. + This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ + + uint32_t SequencersScanMode; /*!< Set ADC scan selection. + This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ + +} LL_ADC_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_REG_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE + @note On this STM32 serie, external trigger is set with trigger polarity: rising edge + (only trigger polarity available on this STM32 serie). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH + @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE + @note This parameter has an effect only if group regular sequencer is enabled + (scan length of 2 ranks or more). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ + + uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). + This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE + Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ + + uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. + This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ + +} LL_ADC_REG_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group injected. + * @note These parameters have an impact on ADC scope: ADC group injected. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "INJ"). + * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE + @note On this STM32 serie, external trigger is set with trigger polarity: rising edge + (only trigger polarity available on this STM32 serie). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. + This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH + @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE + @note This parameter has an effect only if group injected sequencer is enabled + (scan length of 2 ranks or more). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ + + uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. + This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO + Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ + +} LL_ADC_INJ_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_LL_EC_FLAG ADC flags + * @brief Flags defines which can be used with LL_ADC_ReadReg function + * @{ + */ +#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ +#define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ +#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ +#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ +#if defined(ADC_MULTIMODE_SUPPORT) +#define LL_ADC_FLAG_EOS_MST ADC_SR_EOC /*!< ADC flag ADC multimode master group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ +#define LL_ADC_FLAG_EOS_SLV ADC_SR_EOC /*!< ADC flag ADC multimode slave group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ +#define LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC /*!< ADC flag ADC multimode slave group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ +#define LL_ADC_FLAG_AWD1_MST ADC_SR_AWD /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ +#define LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave (on STM32F1, this flag must be read from ADC instance slave: ADC2) */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions + * @{ + */ +#define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */ +#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + * @{ + */ +/* List of ADC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ +#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +#if defined(ADC_MULTIMODE_SUPPORT) +#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + * @{ + */ +/* Note: Other measurement paths to internal channels may be available */ +/* (connections to other peripherals). */ +/* If they are not listed below, they do not require any specific */ +/* path enable. In this case, Access to measurement path is done */ +/* only by selecting the corresponding ADC internal channel. */ +#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment + * @{ + */ +#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection + * @{ + */ +#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ +#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/ +#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F1, ADC channel available only on ADC instance: ADC1. */ +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + * @{ + */ +/* ADC group regular external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */ +#define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +/* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) +/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */ +/* XL-density devices. */ +/* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */ +/* A remap of trigger must be done at top level (refer to */ +/* AFIO peripheral). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).*/ +#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined (STM32F103xE) || defined (STM32F103xG) +/* ADC group regular external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */ +#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + * @{ + */ +#define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG /*!< ADC group regular conversion trigger polarity set to rising edge */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode +* @{ +*/ +#define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data + * @{ + */ +#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ +#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ +#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ +#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ +#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ +#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ +#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ +#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ +#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ +#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ +#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ +#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ +#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ +#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ +#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ +#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ +#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source + * @{ + */ +/* ADC group injected external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */ +#define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal: SW start. */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +/* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ +#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) +/* Note: TIM8_CH4 is available on ADC1 and ADC2 only in high-density and */ +/* XL-density devices. */ +/* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */ +/* A remap of trigger must be done at top level (refer to */ +/* AFIO peripheral). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). */ +#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */ +#if defined (STM32F103xE) || defined (STM32F103xG) +/* ADC group injected external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge + * @{ + */ +#define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG /*!< ADC group injected conversion trigger polarity set to rising edge */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode +* @{ +*/ +#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ +#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ +/** + * @} + */ + + +/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length + * @{ + */ +#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */ +#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks + * @{ + */ +#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */ +#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */ +#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */ +#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */ +#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels + * @{ + */ +#define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ +#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ +#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ +#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + * @{ + */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ +/** + * @} + */ + +#if !defined(ADC_MULTIMODE_SUPPORT) +/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode + * @{ + */ +#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ +/** + * @} + */ +#endif +#if defined(ADC_MULTIMODE_SUPPORT) +/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode + * @{ + */ +#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ +#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices)) */ +#define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */ +#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */ +#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ +#define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave + * @{ + */ +#define LL_ADC_MULTI_MASTER ( ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: ADC master */ +#define LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA ) /*!< In multimode, selection among several ADC instances: ADC slave */ +#define LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ +/** + * @} + */ + +#endif /* ADC_MULTIMODE_SUPPORT */ + + +/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + * @note Only ADC IP HW delays are defined in ADC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ +/* not timeout values. */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Indications for estimation of ADC timeout delays, for this */ +/* STM32 serie: */ +/* - ADC enable time: maximum delay is 1us */ +/* (refer to device datasheet, parameter "tSTAB") */ +/* - ADC conversion time: duration depending on ADC clock and ADC */ +/* configuration. */ +/* (refer to device reference manual, section "Timing") */ + +/* Delay for temperature sensor stabilization time. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U) /*!< Delay for internal voltage reference stabilization time */ + +/* Delay required between ADC disable and ADC calibration start. */ +/* Note: On this STM32 serie, before starting a calibration, */ +/* ADC must be disabled. */ +/* A minimum number of ADC clock cycles are required */ +/* between ADC disable state and calibration start. */ +/* Refer to literal @ref LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES. */ +/* Wait time can be computed in user application by waiting for the */ +/* equivalent number of CPU cycles, by taking into account */ +/* ratio of CPU clock versus ADC clock prescalers. */ +/* Unit: ADC clock cycles. */ +#define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between ADC disable and ADC calibration start */ + +/* Delay required between end of ADC Enable and the start of ADC calibration. */ +/* Note: On this STM32 serie, a minimum number of ADC clock cycles */ +/* are required between the end of ADC enable and the start of ADC */ +/* calibration. */ +/* Wait time can be computed in user application by waiting for the */ +/* equivalent number of CPU cycles, by taking into account */ +/* ratio of CPU clock versus ADC clock prescalers. */ +/* Unit: ADC clock cycles. */ +#define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between end of ADC enable and the start of ADC calibration */ + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals LL_ADC_CHANNEL_x. + * @note Example: + * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + +/** + * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "LL_ADC_CHANNEL_4". + * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) <= 9U) \ + ? ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + : \ + ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + ) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + */ +#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + (((__ADC_INSTANCE__) == ADC1) \ + ? ( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \ + ) \ + : \ + (0U) \ + ) + +/** + * @brief Helper macro to define ADC analog watchdog parameter: + * define a single channel to monitor with analog watchdog + * from sequencer channel and groups definition. + * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). + * Example: + * LL_ADC_SetAnalogWDMonitChannels( + * ADC1, LL_ADC_AWD1, + * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @param __GROUP__ This parameter can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @arg @ref LL_ADC_GROUP_INJECTED + * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + */ +#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ + (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ + : \ + ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ + : \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ + ) + +/** + * @brief Helper macro to set the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_SetAnalogWDThresholds + * (< ADCx param >, + * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */ +/* This macro has been kept anyway for compatibility with other */ +/* STM32 families featuring different ADC resolutions. */ +#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ + ((__AWD_THRESHOLD__) << (0U)) + +/** + * @brief Helper macro to get the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to get the value of + * analog watchdog threshold high (on 8 bits): + * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION + * (LL_ADC_RESOLUTION_8B, + * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */ +/* This macro has been kept anyway for compatibility with other */ +/* STM32 families featuring different ADC resolutions. */ +#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ + (__AWD_THRESHOLD_12_BITS__) + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Helper macro to get the ADC multimode conversion data of ADC master + * or ADC slave from raw value with both ADC conversion data concatenated. + * @note This macro is intended to be used when multimode transfer by DMA + * is enabled. + * In this case the transferred data need to processed with this macro + * to separate the conversion data of ADC master and ADC slave. + * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ + (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA) +#endif + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On STM32F1, there is no common ADC instance. + * However, ADC instance ADC1 has a role of common ADC instance + * for ADC1 and ADC2: + * this instance is used to manage internal channels + * and multimode (these features are managed in ADC common + * instances on some other STM32 devices). + * ADC instance ADC3 (if available on the selected device) + * has no ADC common instance. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#if defined(ADC1) && defined(ADC2) && defined(ADC3) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \ + ? ( \ + (ADC12_COMMON) \ + ) \ + : \ + ( \ + (0U) \ + ) \ + ) +#elif defined(ADC1) && defined(ADC2) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC12_COMMON) +#else +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC1_COMMON) +#endif + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @note On STM32F1, there is no common ADC instance. + * However, ADC instance ADC1 has a role of common ADC instance + * for ADC1 and ADC2: + * this instance is used to manage internal channels + * and multimode (these features are managed in ADC common + * instances on some other STM32 devices). + * ADC instance ADC3 (if available on the selected device) + * has no ADC common instance. + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#if defined(ADC1) && defined(ADC2) && defined(ADC3) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (((__ADCXY_COMMON__) == ADC12_COMMON) \ + ? ( \ + (LL_ADC_IsEnabled(ADC1) | \ + LL_ADC_IsEnabled(ADC2) ) \ + ) \ + : \ + ( \ + LL_ADC_IsEnabled(ADC3) \ + ) \ + ) +#elif defined(ADC1) && defined(ADC2) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1) | \ + LL_ADC_IsEnabled(ADC2) ) +#else +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + LL_ADC_IsEnabled(ADC1) +#endif + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + (0xFFFU) + + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be known from + * user board environment or can be calculated using ADC measurement. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ + ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + ) + + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be known from + * user board environment or can be calculated using ADC measurement. + * @note ADC measurement data must correspond to a resolution of 12bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * On STM32F1, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32F1, refer to device datasheet parameter "V25". + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + ((( ( \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000) \ + - \ + (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000) \ + ) \ + ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (__TEMPSENSOR_CALX_TEMP__) \ + ) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management + * @{ + */ +/* Note: LL ADC functions to set DMA transfer are located into sections of */ +/* configuration of ADC instance, groups and multimode (if available): */ +/* @ref LL_ADC_REG_SetDMATransfer(), ... */ + +/** + * @brief Function to help to configure DMA transfer from ADC: retrieve the + * ADC register address from ADC instance and a list of ADC registers + * intended to be used (most commonly) with DMA transfer. + * @note These ADC registers are data registers: + * when ADC conversion data is available in ADC data registers, + * ADC generates a DMA transfer request. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), + * (uint32_t)&< array or variable >, + * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + * @note For devices with several ADC: in multimode, some devices + * use a different data register outside of ADC instance scope + * (common data register). This macro manages this register difference, + * only ADC instance has to be set as parameter. + * @note On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer + * capability, not ADC2 (ADC2 and ADC3 instances not available on + * all devices). + * @note On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3. + * Therefore, the corresponding parameter of data transfer + * for multimode can be used only with ADC1 and ADC2. + * (ADC2 and ADC3 instances not available on all devices). + * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr + * @param ADCx ADC instance + * @param Register This parameter can be one of the following values: + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) + * + * (1) Available on devices with several ADC instances. + * @retval ADC register address + */ +#if defined(ADC_MULTIMODE_SUPPORT) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +{ + register uint32_t data_reg_addr = 0U; + + if (Register == LL_ADC_DMA_REG_REGULAR_DATA) + { + /* Retrieve address of register DR */ + data_reg_addr = (uint32_t)&(ADCx->DR); + } + else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ + { + /* Retrieve address of register of multimode data */ + data_reg_addr = (uint32_t)&(ADC12_COMMON->DR); + } + + return data_reg_addr; +} +#else +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +{ + /* Retrieve address of register DR */ + return (uint32_t)&(ADCx->DR); +} +#endif + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances + * @{ + */ + +/** + * @brief Set parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal); +} + +/** + * @brief Get parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Set ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); +} + +/** + * @brief Get ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + */ +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); +} + +/** + * @brief Set ADC sequencers scan mode, for all ADC groups + * (group regular, group injected). + * @note According to sequencers scan mode : + * - If disabled: ADC conversion is performed in unitary conversion + * mode (one channel converted, that defined in rank 1). + * Configuration of sequencers of all ADC groups + * (sequencer scan length, ...) is discarded: equivalent to + * scan length of 1 rank. + * - If enabled: ADC conversions are performed in sequence conversions + * mode, according to configuration of sequencers of + * each ADC group (sequencer scan length, ...). + * Refer to function @ref LL_ADC_REG_SetSequencerLength() + * and to function @ref LL_ADC_INJ_SetSequencerLength(). + * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode + * @param ADCx ADC instance + * @param ScanMode This parameter can be one of the following values: + * @arg @ref LL_ADC_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_SEQ_SCAN_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); +} + +/** + * @brief Get ADC sequencers scan mode, for all ADC groups + * (group regular, group injected). + * @note According to sequencers scan mode : + * - If disabled: ADC conversion is performed in unitary conversion + * mode (one channel converted, that defined in rank 1). + * Configuration of sequencers of all ADC groups + * (sequencer scan length, ...) is discarded: equivalent to + * scan length of 1 rank. + * - If enabled: ADC conversions are performed in sequence conversions + * mode, according to configuration of sequencers of + * each ADC group (sequencer scan length, ...). + * Refer to function @ref LL_ADC_REG_SetSequencerLength() + * and to function @ref LL_ADC_INJ_SetSequencerLength(). + * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_SEQ_SCAN_ENABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Set ADC group regular conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note On this STM32 serie, external trigger is set with trigger polarity: + * rising edge (only trigger polarity available on this STM32 serie). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3) + * + * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n + * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n + * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n + * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ +/* Note: On this STM32 serie, ADC group regular external trigger edge */ +/* is used to perform a ADC conversion start. */ +/* This function does not set external trigger edge. */ +/* This feature is set using function */ +/* @ref LL_ADC_REG_StartConversionExtTrig(). */ + MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); +} + +/** + * @brief Get ADC group regular conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note To determine whether group regular trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") + * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3) + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3) + * + * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n + * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n + * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n + * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL)); +} + +/** + * @brief Get ADC group regular conversion trigger source internal (SW start) + or external. + * @note In case of group regular trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_REG_GetTriggerSource(). + * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE)); +} + + +/** + * @brief Set ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note On this STM32 serie, group regular sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); +} + +/** + * @brief Get ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note On this STM32 serie, group regular sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); +} + +/** + * @brief Set ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note It is not possible to enable both ADC auto-injected mode + * and ADC group regular sequencer discontinuous mode. + * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n + * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); +} + +/** + * @brief Get ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n + * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); +} + +/** + * @brief Set ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note This function performs configuration of: + * - Channels ordering into each rank of scan sequence: + * whatever channel can be placed into whatever rank. + * @note On this STM32 serie, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 serie, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register and register position depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), + (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note On this STM32 serie, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + + return (uint32_t) (READ_BIT(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) + ); +} + +/** + * @brief Set ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode + * @param ADCx ADC instance + * @param Continuous This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); +} + +/** + * @brief Get ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); +} + +/** + * @brief Set ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer + * @param ADCx ADC instance + * @param DMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer); +} + +/** + * @brief Get ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Set ADC group injected conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note On this STM32 serie, external trigger is set with trigger polarity: + * rising edge (only trigger polarity available on this STM32 serie). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3) + * + * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n + * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n + * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n + * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ +/* Note: On this STM32 serie, ADC group injected external trigger edge */ +/* is used to perform a ADC conversion start. */ +/* This function does not set external trigger edge. */ +/* This feature is set using function */ +/* @ref LL_ADC_INJ_StartConversionExtTrig(). */ + MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); +} + +/** + * @brief Get ADC group injected conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note To determine whether group injected trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") + * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3) + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3) + * + * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n + * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n + * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n + * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL)); +} + +/** + * @brief Get ADC group injected conversion trigger source internal (SW start) + or external + * @note In case of group injected trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_INJ_GetTriggerSource. + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE); +} + +/** + * @brief Set ADC group injected sequencer length and scan direction. + * @note This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note On this STM32 serie, group injected sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); +} + +/** + * @brief Get ADC group injected sequencer length and scan direction. + * @note This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note On this STM32 serie, group injected sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); +} + +/** + * @brief Set ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); +} + +/** + * @brief Get ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); +} + +/** + * @brief Set ADC group injected sequence: channel on the selected + * sequence rank. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 serie, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; + + MODIFY_REG(ADCx->JSQR, + ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))), + (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))); +} + +/** + * @brief Get ADC group injected sequence: channel on the selected + * sequence rank. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +{ + register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; + + return (uint32_t)(READ_BIT(ADCx->JSQR, + ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))) + >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))) + ); +} + +/** + * @brief Set ADC group injected conversion trigger: + * independent or from ADC group regular. + * @note This mode can be used to extend number of data registers + * updated after one ADC conversion trigger and with data + * permanently kept (not erased by successive conversions of scan of + * ADC sequencer ranks), up to 5 data registers: + * 1 data register on ADC group regular, 4 data registers + * on ADC group injected. + * @note If ADC group injected injected trigger source is set to an + * external trigger, this feature must be must be set to + * independent trigger. + * ADC group injected automatic trigger is compliant only with + * group injected trigger source set to SW start, without any + * further action on ADC group injected conversion start or stop: + * in this case, ADC group injected is controlled only + * from ADC group regular. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto + * @param ADCx ADC instance + * @param TrigAuto This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); +} + +/** + * @brief Get ADC group injected conversion trigger: + * independent or from ADC group regular. + * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); +} + +/** + * @brief Set ADC group injected offset. + * @note It sets: + * - ADC group injected rank to which the offset programmed + * will be applied + * - Offset level (offset to be subtracted from the raw + * converted data). + * Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @note Offset cannot be enabled or disabled. + * To emulate offset disabled, set an offset value equal to 0. + * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n + * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n + * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n + * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_JOFR1_JOFFSET1, + OffsetLevel); +} + +/** + * @brief Get ADC group injected offset. + * @note It gives offset level (offset to be subtracted from the raw converted data). + * Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n + * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n + * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n + * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_JOFR1_JOFFSET1) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels + * @{ + */ + +/** + * @brief Set sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 serie. + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) +{ + /* Set bits with content of parameter "SamplingTime" with bits position */ + /* in register and register position depending on parameter "Channel". */ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), + SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); +} + +/** + * @brief Get sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 serie. + * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) + >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog + * @{ + */ + +/** + * @brief Set ADC analog watchdog monitored channels: + * a single channel or all channels, + * on ADC groups regular and-or injected. + * @note Once monitored channels are selected, analog watchdog + * is enabled. + * @note In case of need to define a single channel to monitor + * with analog watchdog from sequencer channel definition, + * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). + * @note On this STM32 serie, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n + * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n + * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDChannelGroup This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1) + * + * (1) On STM32F1, parameter available only on ADC instance: ADC1. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) +{ + MODIFY_REG(ADCx->CR1, + (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), + AWDChannelGroup); +} + +/** + * @brief Get ADC analog watchdog monitored channel. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Applicable only when the analog watchdog is set to monitor + * one channel. + * @note On this STM32 serie, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n + * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n + * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); +} + +/** + * @brief Set ADC analog watchdog threshold value of threshold + * high or low. + * @note On this STM32 serie, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n + * LTR LT LL_ADC_SetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + + MODIFY_REG(*preg, + ADC_HTR_HT, + AWDThresholdValue); +} + +/** + * @brief Get ADC analog watchdog threshold value of threshold high or + * threshold low. + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). + * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n + * LTR LT LL_ADC_GetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF +*/ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + + return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode + * @{ + */ + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Set ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @rmtoll CR1 DUALMOD LL_ADC_SetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param Multimode This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) +{ + MODIFY_REG(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD, Multimode); +} + +/** + * @brief Get ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @rmtoll CR1 DUALMOD LL_ADC_GetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD)); +} + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ +/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Enable the selected ADC instance. + * @note On this STM32 serie, after ADC enable, a delay for + * ADC internal analog stabilization is required before performing a + * ADC conversion start. + * Refer to device datasheet, parameter tSTAB. + * @rmtoll CR2 ADON LL_ADC_Enable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_ADON); +} + +/** + * @brief Disable the selected ADC instance. + * @rmtoll CR2 ADON LL_ADC_Disable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); +} + +/** + * @brief Get the selected ADC instance enable state. + * @rmtoll CR2 ADON LL_ADC_IsEnabled + * @param ADCx ADC instance + * @retval 0: ADC is disabled, 1: ADC is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); +} + +/** + * @brief Start ADC calibration in the mode single-ended + * or differential (for devices with differential mode available). + * @note On this STM32 serie, before starting a calibration, + * ADC must be disabled. + * A minimum number of ADC clock cycles are required + * between ADC disable state and calibration start. + * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES. + * @note On this STM32 serie, hardware prerequisite before starting a calibration: + the ADC must have been in power-on state for at least + two ADC clock cycles. + * @rmtoll CR2 CAL LL_ADC_StartCalibration + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_CAL); +} + +/** + * @brief Get ADC calibration state. + * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing + * @param ADCx ADC instance + * @retval 0: calibration complete, 1: calibration in progress. + */ +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Start ADC group regular conversion. + * @note On this STM32 serie, this function is relevant only for + * internal trigger (SW start), not for external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * start must be performed using function + * @ref LL_ADC_REG_StartConversionExtTrig(). + * (if external trigger edge would have been set during ADC other + * settings, ADC conversion would start at trigger event + * as soon as ADC is enabled). + * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); +} + +/** + * @brief Start ADC group regular conversion from external trigger. + * @note ADC conversion will start at next trigger event (on the selected + * trigger edge) following the ADC start conversion command. + * @note On this STM32 serie, this function is relevant for + * ADC conversion start from external trigger. + * If internal trigger (SW start) is needed, perform ADC conversion + * start using function @ref LL_ADC_REG_StartConversionSWStart(). + * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + SET_BIT(ADCx->CR2, ExternalTriggerEdge); +} + +/** + * @brief Stop ADC group regular conversion from external trigger. + * @note No more ADC conversion will start at next trigger event + * following the ADC stop conversion command. + * If a conversion is on-going, it will be completed. + * @note On this STM32 serie, there is no specific command + * to stop a conversion on-going or to stop ADC converting + * in continuous mode. These actions can be performed + * using function @ref LL_ADC_Disable(). + * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTSEL); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Get ADC multimode conversion data of ADC master, ADC slave + * or raw data with ADC master and slave concatenated. + * @note If raw data with ADC master and slave concatenated is retrieved, + * a macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * (however this macro is mainly intended for multimode + * transfer by DMA, because this function can do the same + * by getting multimode conversion data of ADC master or ADC slave + * separately). + * @rmtoll DR DATA LL_ADC_REG_ReadMultiConversionData32\n + * DR ADC2DATA LL_ADC_REG_ReadMultiConversionData32 + * @param ADCx ADC instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param ConversionData This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @arg @ref LL_ADC_MULTI_MASTER_SLAVE + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_TypeDef *ADCx, uint32_t ConversionData) +{ + return (uint32_t)(READ_BIT(ADCx->DR, + ADC_DR_ADC2DATA) + >> POSITION_VAL(ConversionData) + ); +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Start ADC group injected conversion. + * @note On this STM32 serie, this function is relevant only for + * internal trigger (SW start), not for external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * start must be performed using function + * @ref LL_ADC_INJ_StartConversionExtTrig(). + * (if external trigger edge would have been set during ADC other + * settings, ADC conversion would start at trigger event + * as soon as ADC is enabled). + * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG)); +} + +/** + * @brief Start ADC group injected conversion from external trigger. + * @note ADC conversion will start at next trigger event (on the selected + * trigger edge) following the ADC start conversion command. + * @note On this STM32 serie, this function is relevant for + * ADC conversion start from external trigger. + * If internal trigger (SW start) is needed, perform ADC conversion + * start using function @ref LL_ADC_INJ_StartConversionSWStart(). + * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + SET_BIT(ADCx->CR2, ExternalTriggerEdge); +} + +/** + * @brief Stop ADC group injected conversion from external trigger. + * @note No more ADC conversion will start at next trigger event + * following the ADC stop conversion command. + * If a conversion is on-going, it will be completed. + * @note On this STM32 serie, there is no specific command + * to stop a conversion on-going or to stop ADC converting + * in continuous mode. These actions can be performed + * using function @ref LL_ADC_Disable(). + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTSEL); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint16_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management + * @{ + */ + +/** + * @brief Get flag ADC group regular end of sequence conversions. + * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); +} + + +/** + * @brief Get flag ADC group injected end of sequence conversions. + * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); +} + +/** + * @brief Get flag ADC analog watchdog 1 flag + * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); +} + +/** + * @brief Clear flag ADC group regular end of sequence conversions. + * @rmtoll SR EOC LL_ADC_ClearFlag_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS); +} + + +/** + * @brief Clear flag ADC group injected end of sequence conversions. + * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); +} + +/** + * @brief Clear flag ADC analog watchdog 1. + * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master. + * @rmtoll SR EOC LL_ADC_IsActiveFlag_MST_EOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 serie, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_EOC) == (ADC_SR_EOC)); +} + +/** + * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave. + * @rmtoll SR EOC LL_ADC_IsActiveFlag_SLV_EOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 serie, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); + + return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)); +} + + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. + * @rmtoll SR JEOC LL_ADC_IsActiveFlag_MST_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADC1->SR, ADC_SR_JEOC) == (ADC_SR_JEOC)); +} + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave. + * @rmtoll SR JEOC LL_ADC_IsActiveFlag_SLV_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); + + return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)); +} + +/** + * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. + * @rmtoll SR AWD LL_ADC_IsActiveFlag_MST_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADC1->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); +} + +/** + * @brief Get flag multimode analog watchdog 1 of the ADC slave. + * @rmtoll SR AWD LL_ADC_IsActiveFlag_SLV_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U); + + return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); +} + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_IT_Management ADC IT management + * @{ + */ + +/** + * @brief Enable interruption ADC group regular end of sequence conversions. + * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + SET_BIT(ADCx->CR1, ADC_CR1_EOCIE); +} + + +/** + * @brief Enable interruption ADC group injected end of sequence conversions. + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); +} + +/** + * @brief Enable interruption ADC analog watchdog 1. + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); +} + +/** + * @brief Disable interruption ADC group regular end of sequence conversions. + * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE); +} + + +/** + * @brief Disable interruption ADC group injected end of sequence conversions. + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); +} + +/** + * @brief Disable interruption ADC analog watchdog 1. + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); +} + +/** + * @brief Get state of interruption ADC group regular end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group regular */ + /* end of unitary conversion. */ + /* Flag noted as "EOC" is corresponding to flag "EOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); +} + + +/** + * @brief Get state of interruption ADC group injected end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); +} + +/** + * @brief Get state of interruption ADC analog watchdog 1 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/* Initialization of some features of ADC common parameters and multimode */ +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); + +/* De-initialization of ADC instance, ADC group regular and ADC group injected */ +/* (availability of ADC group injected depends on STM32 families) */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); + +/* Initialization of some features of ADC instance */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); + +/* Initialization of some features of ADC instance and ADC group regular */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); + +/* Initialization of some features of ADC instance and ADC group injected */ +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 || ADC2 || ADC3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_ADC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_bus.h index d715aa491af..c28b643b287 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_bus.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_bus.h * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of BUS LL module. @verbatim diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_cortex.h index c682cb74894..74a32036730 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_cortex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_cortex.h * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of CORTEX LL module. @verbatim ============================================================================== @@ -86,8 +86,8 @@ extern "C" { /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source * @{ */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/ -#define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ /** * @} */ @@ -107,7 +107,7 @@ extern "C" { /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control * @{ */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ @@ -118,14 +118,14 @@ extern "C" { /** @defgroup CORTEX_LL_EC_REGION MPU Region Number * @{ */ -#define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00U) /*!< REGION Number 0 */ -#define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01U) /*!< REGION Number 1 */ -#define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02U) /*!< REGION Number 2 */ -#define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03U) /*!< REGION Number 3 */ -#define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04U) /*!< REGION Number 4 */ -#define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05U) /*!< REGION Number 5 */ -#define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06U) /*!< REGION Number 6 */ -#define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07U) /*!< REGION Number 7 */ +#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ /** * @} */ @@ -133,34 +133,34 @@ extern "C" { /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size * @{ */ -#define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ /** * @} */ @@ -168,12 +168,12 @@ extern "C" { /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges * @{ */ -#define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/ -#define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/ -#define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */ -#define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */ -#define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/ -#define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */ +#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ /** * @} */ @@ -181,10 +181,10 @@ extern "C" { /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level * @{ */ -#define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */ -#define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */ -#define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */ -#define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */ +#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ +#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ /** * @} */ @@ -192,7 +192,7 @@ extern "C" { /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access * @{ */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00U) /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ /** * @} @@ -202,7 +202,7 @@ extern "C" { * @{ */ #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ -#define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00U) /*!< Not Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ /** * @} */ @@ -211,7 +211,7 @@ extern "C" { * @{ */ #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ -#define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ /** * @} */ @@ -220,7 +220,7 @@ extern "C" { * @{ */ #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ -#define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.c index de4e3c24a6e..7d07f8fe745 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_crc.c * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief CRC LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.h index 8155b0d1f84..e6bc9b33d64 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_crc.h * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of CRC LL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dac.c new file mode 100644 index 00000000000..60b8730367f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dac.c @@ -0,0 +1,274 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_dac.c + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief DAC LL module driver + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_dac.h" +#include "stm32f1xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (DAC) + +/** @addtogroup DAC_LL DAC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup DAC_LL_Private_Macros + * @{ + */ + +#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ + ( \ + ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ + || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ + ) + +#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ + ( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ + || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ + ) +#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ + ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + ) + +#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \ + ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \ + ) + +#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ + ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ + || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ + ) + +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DAC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize registers of the selected DAC instance + * to their default reset values. + * @param DACx DAC instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DAC registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) +{ + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(DACx)); + + /* Force reset of DAC1 clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1); + + /* Release reset of DAC1 clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1); + return SUCCESS; +} + +/** + * @brief Initialize some features of DAC instance. + * @note The setting of these parameters by function @ref LL_DAC_Init() + * is conditioned to DAC state: + * DAC instance must be disabled. + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DAC registers are initialized + * - ERROR: DAC registers are not initialized + */ +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(DACx)); + assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel)); + assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource)); + assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer)); + assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration)); + if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) + { + assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig)); + } + + /* Note: Hardware constraint (refer to description of this function) */ + /* DAC instance must be disabled. */ + if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U) + { + /* Configuration of DAC channel: */ + /* - TriggerSource */ + /* - WaveAutoGeneration */ + /* - OutputBuffer */ + if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) + { + MODIFY_REG(DACx->CR, + ( DAC_CR_TSEL1 + | DAC_CR_WAVE1 + | DAC_CR_MAMP1 + | DAC_CR_BOFF1 + ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + , + ( DAC_InitStruct->TriggerSource + | DAC_InitStruct->WaveAutoGeneration + | DAC_InitStruct->WaveAutoGenerationConfig + | DAC_InitStruct->OutputBuffer + ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); + } + else + { + MODIFY_REG(DACx->CR, + ( DAC_CR_TSEL1 + | DAC_CR_WAVE1 + | DAC_CR_BOFF1 + ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + , + ( DAC_InitStruct->TriggerSource + | LL_DAC_WAVE_AUTO_GENERATION_NONE + | DAC_InitStruct->OutputBuffer + ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); + } + } + else + { + /* Initialization error: DAC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_DAC_InitTypeDef field to default value. + * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) +{ + /* Set DAC_InitStruct fields to default values */ + DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE; + DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE; + /* Note: Parameter discarded if wave auto generation is disabled, */ + /* set anyway to its default value. */ + DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0; + DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dac.h new file mode 100644 index 00000000000..d3a3b7d0fe4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dac.h @@ -0,0 +1,1349 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_dac.h + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief Header file of DAC LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_DAC_H +#define __STM32F1xx_LL_DAC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (DAC) + +/** @defgroup DAC_LL DAC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DAC_LL_Private_Constants DAC Private Constants + * @{ + */ + +/* Internal masks for DAC channels definition */ +/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ +/* - channel bits position into register CR */ +/* - channel bits position into register SWTRIG */ +/* - channel register offset of data holding register DHRx */ +/* - channel register offset of data output register DORx */ +#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ +#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ +#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) + +#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ +#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ +#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) + +#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ +#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ +#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U +#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U +#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U +#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) + +#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ +#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ +#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) + +/* DAC registers bits positions */ +#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ +#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ +#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ + +/* Miscellaneous data */ +#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DAC_LL_Private_Macros DAC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: isolate bits with the + * selected mask and shift them to the register LSB + * (shift mask on register position bit 0). + * @param __BITS__ Bits in register 32 bits + * @param __MASK__ Mask in register 32 bits + * @retval Bits in register 32 bits +*/ +#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \ + (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address +*/ +#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of DAC instance. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). + This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ + + uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. + This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ + + uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. + If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS + If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE + @note If waveform automatic generation mode is disabled, this parameter is discarded. + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */ + + uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. + This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER + + This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ + +} LL_DAC_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants + * @{ + */ + +/** @defgroup DAC_LL_EC_GET_FLAG DAC flags + * @brief Flags defines which can be used with LL_DAC_ReadReg function + * @{ + */ +/* DAC channel 1 flags */ +#if defined(DAC_SR_DMAUDR1) +#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ +#endif /* DAC_SR_DMAUDR1 */ + +/* DAC channel 2 flags */ +#if defined(DAC_SR_DMAUDR2) +#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ +#endif /* DAC_SR_DMAUDR2 */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_IT DAC interruptions + * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions + * @{ + */ +#if defined(DAC_CR_DMAUDRIE1) +#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ +#endif /* DAC_CR_DMAUDRIE1 */ +#if defined(DAC_CR_DMAUDRIE2) +#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ +#endif /* DAC_CR_DMAUDRIE2 */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_CHANNEL DAC channels + * @{ + */ +#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ +#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source + * @{ + */ +#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ +#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ +#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode + * @{ + */ +#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ +#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits + * @{ + */ +#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude + * @{ + */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer + * @{ + */ +#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ +#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ +/** + * @} + */ + + +/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution + * @{ + */ +#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ +#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose + * @{ + */ +/* List of DAC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ +#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */ +#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */ +#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays + * @note Only DAC IP HW delays are defined in DAC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Delay for DAC channel voltage settling time from DAC channel startup */ +/* (transition from disable to enable). */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm (min), 50pF (max) */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tWAKEUP"). */ +/* Unit: us */ +#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ + +/* Delay for DAC channel voltage settling time. */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm min, 50pF max */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSETTLING"). */ +/* Unit: us */ +#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros + * @{ + */ + +/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros + * @{ + */ + +/** + * @brief Write a value in DAC register + * @param __INSTANCE__ DAC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DAC register + * @param __INSTANCE__ DAC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + +/** + * @} + */ + +/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro + * @{ + */ + +/** + * @brief Helper macro to get DAC channel number in decimal format + * from literals LL_DAC_CHANNEL_x. + * Example: + * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) + * will return decimal number "1". + * @note The input can be a value from functions where a channel + * number is returned. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval 1...2 + */ +#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + ((__CHANNEL__) & DAC_SWTR_CHX_MASK) + +/** + * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x + * from number in decimal format. + * Example: + * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) + * will return a data equivalent to "LL_DAC_CHANNEL_1". + * @note If the input parameter does not correspond to a DAC channel, + * this macro returns value '0'. + * @param __DECIMAL_NB__ 1...2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + */ +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) == 1U) \ + ? ( \ + LL_DAC_CHANNEL_1 \ + ) \ + : \ + (((__DECIMAL_NB__) == 2U) \ + ? ( \ + LL_DAC_CHANNEL_2 \ + ) \ + : \ + ( \ + 0 \ + ) \ + ) \ + ) + +/** + * @brief Helper macro to define the DAC conversion data full-scale digital + * value corresponding to the selected DAC resolution. + * @note DAC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __DAC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_DAC_RESOLUTION_12B + * @arg @ref LL_DAC_RESOLUTION_8B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) + +/** + * @brief Helper macro to calculate the DAC conversion data (unit: digital + * value) corresponding to a voltage (unit: mVolt). + * @note This helper macro is intended to provide input data in voltage + * rather than digital value, + * to be used with LL DAC functions such as + * @ref LL_DAC_ConvertData12RightAligned(). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel + * (unit: mVolt). + * @param __DAC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_DAC_RESOLUTION_12B + * @arg @ref LL_DAC_RESOLUTION_8B + * @retval DAC conversion data (unit: digital value) + */ +#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ + __DAC_VOLTAGE__,\ + __DAC_RESOLUTION__) \ + ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ + ) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions + * @{ + */ +/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels + * @{ + */ + +/** + * @brief Set the conversion trigger source for the selected DAC channel. + * @note For conversion trigger source to be effective, DAC trigger + * must be enabled using function @ref LL_DAC_EnableTrigger(). + * @note To set conversion trigger source, DAC channel must be disabled. + * Otherwise, the setting is discarded. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n + * CR TSEL2 LL_DAC_SetTriggerSource + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_DAC_TRIG_SOFTWARE + * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) +{ + MODIFY_REG(DACx->CR, + DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the conversion trigger source for the selected DAC channel. + * @note For conversion trigger source to be effective, DAC trigger + * must be enabled using function @ref LL_DAC_EnableTrigger(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n + * CR TSEL2 LL_DAC_GetTriggerSource + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_TRIG_SOFTWARE + * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 + */ +__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the waveform automatic generation mode + * for the selected DAC channel. + * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n + * CR WAVE2 LL_DAC_SetWaveAutoGeneration + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param WaveAutoGeneration This parameter can be one of the following values: + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) +{ + MODIFY_REG(DACx->CR, + DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the waveform automatic generation mode + * for the selected DAC channel. + * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n + * CR WAVE2 LL_DAC_GetWaveAutoGeneration + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the noise waveform generation for the selected DAC channel: + * Noise mode and parameters LFSR (linear feedback shift register). + * @note For wave generation to be effective, DAC channel + * wave generation mode must be enabled using + * function @ref LL_DAC_SetWaveAutoGeneration(). + * @note This setting can be set when the selected DAC channel is disabled + * (otherwise, the setting operation is ignored). + * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n + * CR MAMP2 LL_DAC_SetWaveNoiseLFSR + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param NoiseLFSRMask This parameter can be one of the following values: + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) +{ + MODIFY_REG(DACx->CR, + DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Set the noise waveform generation for the selected DAC channel: + * Noise mode and parameters LFSR (linear feedback shift register). + * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n + * CR MAMP2 LL_DAC_GetWaveNoiseLFSR + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the triangle waveform generation for the selected DAC channel: + * triangle mode and amplitude. + * @note For wave generation to be effective, DAC channel + * wave generation mode must be enabled using + * function @ref LL_DAC_SetWaveAutoGeneration(). + * @note This setting can be set when the selected DAC channel is disabled + * (otherwise, the setting operation is ignored). + * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n + * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param TriangleAmplitude This parameter can be one of the following values: + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude) +{ + MODIFY_REG(DACx->CR, + DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Set the triangle waveform generation for the selected DAC channel: + * triangle mode and amplitude. + * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n + * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the output buffer for the selected DAC channel. + * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n + * CR BOFF2 LL_DAC_SetOutputBuffer + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param OutputBuffer This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) +{ + MODIFY_REG(DACx->CR, + DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the output buffer state for the selected DAC channel. + * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n + * CR BOFF2 LL_DAC_GetOutputBuffer + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + */ +__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DAC DMA transfer request of the selected channel. + * @note To configure DMA source address (peripheral address), + * use function @ref LL_DAC_DMA_GetRegAddr(). + * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n + * CR DMAEN2 LL_DAC_EnableDMAReq + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Disable DAC DMA transfer request of the selected channel. + * @note To configure DMA source address (peripheral address), + * use function @ref LL_DAC_DMA_GetRegAddr(). + * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n + * CR DMAEN2 LL_DAC_DisableDMAReq + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + CLEAR_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get DAC DMA transfer request state of the selected channel. + * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) + * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n + * CR DMAEN2 LL_DAC_IsDMAReqEnabled + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (READ_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); +} + +/** + * @brief Function to help to configure DMA transfer to DAC: retrieve the + * DAC register address from DAC instance and a list of DAC registers + * intended to be used (most commonly) with DMA transfer. + * @note These DAC registers are data holding registers: + * when DAC conversion is requested, DAC generates a DMA transfer + * request to have data available in DAC data holding registers. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * (uint32_t)&< array or variable >, + * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), + * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); + * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n + * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n + * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param Register This parameter can be one of the following values: + * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED + * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED + * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED + * @retval DAC register address + */ +__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) +{ + /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ + /* DAC channel selected. */ + return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register)))); +} +/** + * @} + */ + +/** @defgroup DAC_LL_EF_Operation Operation on DAC channels + * @{ + */ + +/** + * @brief Enable DAC selected channel. + * @rmtoll CR EN1 LL_DAC_Enable\n + * CR EN2 LL_DAC_Enable + * @note After enable from off state, DAC channel requires a delay + * for output voltage to reach accuracy +/- 1 LSB. + * Refer to device datasheet, parameter "tWAKEUP". + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Disable DAC selected channel. + * @rmtoll CR EN1 LL_DAC_Disable\n + * CR EN2 LL_DAC_Disable + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + CLEAR_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get DAC enable state of the selected channel. + * (0: DAC channel is disabled, 1: DAC channel is enabled) + * @rmtoll CR EN1 LL_DAC_IsEnabled\n + * CR EN2 LL_DAC_IsEnabled + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (READ_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); +} + +/** + * @brief Enable DAC trigger of the selected channel. + * @note - If DAC trigger is disabled, DAC conversion is performed + * automatically once the data holding register is updated, + * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": + * @ref LL_DAC_ConvertData12RightAligned(), ... + * - If DAC trigger is enabled, DAC conversion is performed + * only when a hardware of software trigger event is occurring. + * Select trigger source using + * function @ref LL_DAC_SetTriggerSource(). + * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n + * CR TEN2 LL_DAC_EnableTrigger + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Disable DAC trigger of the selected channel. + * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n + * CR TEN2 LL_DAC_DisableTrigger + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + CLEAR_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get DAC trigger state of the selected channel. + * (0: DAC trigger is disabled, 1: DAC trigger is enabled) + * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n + * CR TEN2 LL_DAC_IsTriggerEnabled + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (READ_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); +} + +/** + * @brief Trig DAC conversion by software for the selected DAC channel. + * @note Preliminarily, DAC trigger must be set to software trigger + * using function @ref LL_DAC_SetTriggerSource() + * with parameter "LL_DAC_TRIGGER_SOFTWARE". + * and DAC trigger must be enabled using + * function @ref LL_DAC_EnableTrigger(). + * @note For devices featuring DAC with 2 channels: this function + * can perform a SW start of both DAC channels simultaneously. + * Two channels can be selected as parameter. + * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) + * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n + * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion + * @param DACx DAC instance + * @param DAC_Channel This parameter can a combination of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval None + */ +__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->SWTRIGR, + (DAC_Channel & DAC_SWTR_CHX_MASK)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (LSB aligned on bit 0), + * for the selected DAC channel. + * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n + * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) +{ + register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + DAC_DHR12R1_DACC1DHR, + Data); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (MSB aligned on bit 15), + * for the selected DAC channel. + * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n + * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) +{ + register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + DAC_DHR12L1_DACC1DHR, + Data); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 8 bits left alignment (LSB aligned on bit 0), + * for the selected DAC channel. + * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n + * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) +{ + register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + DAC_DHR8R1_DACC1DHR, + Data); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (LSB aligned on bit 0), + * for both DAC channels. + * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n + * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned + * @param DACx DAC instance + * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF + * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +{ + MODIFY_REG(DACx->DHR12RD, + (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), + ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (MSB aligned on bit 15), + * for both DAC channels. + * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n + * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned + * @param DACx DAC instance + * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF + * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +{ + /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ + /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ + /* the 4 LSB must be taken into account for the shift value. */ + MODIFY_REG(DACx->DHR12LD, + (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), + ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 8 bits left alignment (LSB aligned on bit 0), + * for both DAC channels. + * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n + * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned + * @param DACx DAC instance + * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF + * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +{ + MODIFY_REG(DACx->DHR8RD, + (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), + ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); +} + +/** + * @brief Retrieve output data currently generated for the selected DAC channel. + * @note Whatever alignment and resolution settings + * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": + * @ref LL_DAC_ConvertData12RightAligned(), ...), + * output data format is 12 bits right aligned (LSB aligned on bit 0). + * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n + * DOR2 DACC2DOR LL_DAC_RetrieveOutputData + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK)); + + return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); +} + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management + * @{ + */ +#if defined(DAC_SR_DMAUDR1) +/** + * @brief Get DAC underrun flag for DAC channel 1 + * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)); +} +#endif /* DAC_SR_DMAUDR1 */ + +#if defined(DAC_SR_DMAUDR2) +/** + * @brief Get DAC underrun flag for DAC channel 2 + * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)); +} +#endif /* DAC_SR_DMAUDR2 */ + +#if defined(DAC_SR_DMAUDR1) +/** + * @brief Clear DAC underrun flag for DAC channel 1 + * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) +{ + WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); +} +#endif /* DAC_SR_DMAUDR1 */ + +#if defined(DAC_SR_DMAUDR2) +/** + * @brief Clear DAC underrun flag for DAC channel 2 + * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) +{ + WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); +} +#endif /* DAC_SR_DMAUDR2 */ + +/** + * @} + */ +/** @defgroup DAC_LL_EF_IT_Management IT management + * @{ + */ + +#if defined(DAC_CR_DMAUDRIE1) +/** + * @brief Enable DMA underrun interrupt for DAC channel 1 + * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) +{ + SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); +} +#endif /* DAC_CR_DMAUDRIE1 */ + +#if defined(DAC_CR_DMAUDRIE2) +/** + * @brief Enable DMA underrun interrupt for DAC channel 2 + * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) +{ + SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); +} +#endif /* DAC_CR_DMAUDRIE2 */ + +#if defined(DAC_CR_DMAUDRIE1) +/** + * @brief Disable DMA underrun interrupt for DAC channel 1 + * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); +} +#endif /* DAC_CR_DMAUDRIE1 */ + +#if defined(DAC_CR_DMAUDRIE2) +/** + * @brief Disable DMA underrun interrupt for DAC channel 2 + * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); +} +#endif /* DAC_CR_DMAUDRIE2 */ + +#if defined(DAC_CR_DMAUDRIE1) +/** + * @brief Get DMA underrun interrupt for DAC channel 1 + * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)); +} +#endif /* DAC_CR_DMAUDRIE1 */ + +#if defined(DAC_CR_DMAUDRIE2) +/** + * @brief Get DMA underrun interrupt for DAC channel 2 + * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) +{ + return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)); +} +#endif /* DAC_CR_DMAUDRIE2 */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx); +ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct); +void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_DAC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dma.c new file mode 100644 index 00000000000..d90bfa04f01 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dma.c @@ -0,0 +1,331 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_dma.c + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief DMA LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_dma.h" +#include "stm32f1xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup DMA_LL_Private_Macros + * @{ + */ +#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) + +#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ + ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) + +#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ + ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) + +#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ + ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) + +#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) + +#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) + +#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) + +#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ + ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ + ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ + ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) + +#if defined (DMA2) +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7))) || \ + (((INSTANCE) == DMA2) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5)))) +#else +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7)))) +#endif +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the DMA registers to their default reset values. + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are de-initialized + * - ERROR: DMA registers are not de-initialized + */ +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) +{ + DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; + ErrorStatus status = SUCCESS; + + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Disable the selected DMAx_Channely */ + CLEAR_BIT(tmp->CCR, DMA_CCR_EN); + + /* Reset DMAx_Channely control register */ + LL_DMA_WriteReg(tmp, CCR, 0U); + + /* Reset DMAx_Channely remaining bytes register */ + LL_DMA_WriteReg(tmp, CNDTR, 0U); + + /* Reset DMAx_Channely peripheral address register */ + LL_DMA_WriteReg(tmp, CPAR, 0U); + + /* Reset DMAx_Channely memory address register */ + LL_DMA_WriteReg(tmp, CMAR, 0U); + + if (Channel == LL_DMA_CHANNEL_1) + { + /* Reset interrupt pending bits for DMAx Channel1 */ + LL_DMA_ClearFlag_GI1(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_2) + { + /* Reset interrupt pending bits for DMAx Channel2 */ + LL_DMA_ClearFlag_GI2(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_3) + { + /* Reset interrupt pending bits for DMAx Channel3 */ + LL_DMA_ClearFlag_GI3(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_4) + { + /* Reset interrupt pending bits for DMAx Channel4 */ + LL_DMA_ClearFlag_GI4(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_5) + { + /* Reset interrupt pending bits for DMAx Channel5 */ + LL_DMA_ClearFlag_GI5(DMAx); + } + + else if (Channel == LL_DMA_CHANNEL_6) + { + /* Reset interrupt pending bits for DMAx Channel6 */ + LL_DMA_ClearFlag_GI6(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_7) + { + /* Reset interrupt pending bits for DMAx Channel7 */ + LL_DMA_ClearFlag_GI7(DMAx); + } + else + { + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : + * @arg @ref __LL_DMA_GET_INSTANCE + * @arg @ref __LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are initialized + * - ERROR: Not applicable + */ +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Check the DMA parameters from DMA_InitStruct */ + assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); + assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); + assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); + assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); + assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); + assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); + assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); + assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); + + /*---------------------------- DMAx CCR Configuration ------------------------ + * Configure DMAx_Channely: data transfer direction, data transfer mode, + * peripheral and memory increment mode, + * data size alignment and priority level with parameters : + * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits + * - Mode: DMA_CCR_CIRC bit + * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit + * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit + * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits + * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits + * - Priority: DMA_CCR_PL[1:0] bits + */ + LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ + DMA_InitStruct->Mode | \ + DMA_InitStruct->PeriphOrM2MSrcIncMode | \ + DMA_InitStruct->MemoryOrM2MDstIncMode | \ + DMA_InitStruct->PeriphOrM2MSrcDataSize | \ + DMA_InitStruct->MemoryOrM2MDstDataSize | \ + DMA_InitStruct->Priority); + + /*-------------------------- DMAx CMAR Configuration ------------------------- + * Configure the memory or destination base address with parameter : + * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits + */ + LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); + + /*-------------------------- DMAx CPAR Configuration ------------------------- + * Configure the peripheral or source base address with parameter : + * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits + */ + LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); + + /*--------------------------- DMAx CNDTR Configuration ----------------------- + * Configure the peripheral base address with parameter : + * - NbData: DMA_CNDTR_NDT[15:0] bits + */ + LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_DMA_InitTypeDef field to default value. + * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval None + */ +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Set DMA_InitStruct fields to default values */ + DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; + DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; + DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; + DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + DMA_InitStruct->NbData = 0x00000000U; + DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dma.h new file mode 100644 index 00000000000..fda0a074889 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_dma.h @@ -0,0 +1,1978 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_dma.h + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_DMA_H +#define __STM32F1xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) +}; +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ + +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#if defined(DMA2) +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) +#else +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) +#endif + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#if defined (DMA2) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#endif + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#if defined (DMA2) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); +} + +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); +} + +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); +} + +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); +} + +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); +} + +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); +} + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); +} + +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); +} + +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); +} + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); +} + +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); +} + +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); +} + +/** + * @brief Clear Channel 1 global interrupt flag. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); +} + +/** + * @brief Clear Channel 6 global interrupt flag. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} + +/** + * @brief Clear Channel 7 global interrupt flag. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); +} + +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} + +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); +} + +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} + +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); +} + +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} + +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.c index 2715899a428..c3d094ad66d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_exti.c * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief EXTI LL module driver. ****************************************************************************** * @attention @@ -107,7 +107,7 @@ uint32_t LL_EXTI_DeInit(void) LL_EXTI_WriteReg(FTSR, 0x00000000U); /* Software interrupt event register set to default reset values */ LL_EXTI_WriteReg(SWIER, 0x00000000U); - /* Pending register set to default reset values */ + /* Pending register clear */ LL_EXTI_WriteReg(PR, 0x000FFFFFU); return SUCCESS; diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.h index 5146fc04c82..38e337815db 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_exti.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_exti.h * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of EXTI LL module. ****************************************************************************** * @attention @@ -167,10 +167,10 @@ typedef struct #define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ -#define LL_EXTI_LINE_ALL ((uint32_t)0xFFFFFFFFU) /*!< All Extended line */ +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ #if defined(USE_FULL_LL_DRIVER) -#define LL_EXTI_LINE_NONE ((uint32_t)0x00000000U) /*!< None Extended line */ +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ #endif /*USE_FULL_LL_DRIVER*/ /** @@ -181,9 +181,9 @@ typedef struct /** @defgroup EXTI_LL_EC_MODE Mode * @{ */ -#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ -#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ -#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02) /*!< Interrupt & Event Mode */ /** * @} */ @@ -191,10 +191,10 @@ typedef struct /** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger * @{ */ -#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ -#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ -#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ -#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.c index 16da9a93273..ecff5920e37 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_fsmc.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief FSMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -35,17 +35,17 @@ (++) Static random access memory (SRAM). (++) NOR Flash memory. (++) PSRAM (4 memory banks). - (++) 16-bit PC Card compatible devices + (++) 16-bit PC Card compatible devices. (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of - data - (+) Independent Chip Select control for each memory bank - (+) Independent configuration for each memory bank - + data. + (+) Independent Chip Select control for each memory bank. + (+) Independent configuration for each memory bank. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -79,10 +79,10 @@ * @{ */ -#if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) - #if defined(FSMC_BANK1) +#if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) + /** @defgroup FSMC_LL FSMC Low Layer * @brief FSMC driver modules * @{ @@ -90,78 +90,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants - * @{ - */ - -/* ----------------------- FSMC registers bit mask --------------------------- */ -/* --- PCR Register ---*/ -/* PCR register clear mask */ -#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN | \ - FSMC_PCRx_PTYP | FSMC_PCRx_PWID | \ - FSMC_PCRx_ECCEN | FSMC_PCRx_TCLR | \ - FSMC_PCRx_TAR | FSMC_PCRx_ECCPS)) - -/* --- SR Register ---*/ -/* SR register clear mask */ -#define SR_CLEAR_MASK ((uint32_t)(FSMC_SRx_IRS | FSMC_SRx_ILS | FSMC_SRx_IFS | \ - FSMC_SRx_IREN | FSMC_SRx_ILEN | FSMC_SRx_IFEN)) - -/* --- PMEM Register ---*/ -/* PMEM register clear mask */ -#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEMx_MEMSETx | FSMC_PMEMx_MEMWAITx |\ - FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx)) - -/* --- PATT Register ---*/ -/* PATT register clear mask */ -#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATTx_ATTSETx | FSMC_PATTx_ATTWAITx |\ - FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx)) - -/* --- BCR Register ---*/ -/* BCR register clear mask */ -#define BCR_CLEAR_MASK ((uint32_t)(FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | \ - FSMC_BCRx_MTYP | FSMC_BCRx_MWID | \ - FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | \ - FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \ - FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | \ - FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | \ - FSMC_BCRx_CBURSTRW)) -/* --- BTR Register ---*/ -/* BTR register clear mask */ -#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD |\ - FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\ - FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT |\ - FSMC_BTRx_ACCMOD)) - -/* --- BWTR Register ---*/ -/* BWTR register clear mask */ -#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) -#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \ - FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \ - FSMC_BWTRx_BUSTURN)) -#else -#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \ - FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \ - FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT)) -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ - -/* --- PIO4 Register ---*/ -/* PIO4 register clear mask */ -#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \ - FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4)) -/** - * @} - */ - /* Private macro -------------------------------------------------------------*/ -/** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros - * @{ - */ - -/** - * @} - */ - /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -190,13 +119,12 @@ (+) FSMC NORSRAM bank enable/disable write operation using the functions FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() - @endverbatim * @{ */ - -/** @defgroup FSMC_NORSRAM_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions + +/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1 + * @brief Initialization and Configuration functions * @verbatim ============================================================================== @@ -281,12 +209,11 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_ return HAL_OK; } - /** - * @brief DeInitialize the FSMC_NORSRAM peripheral + * @brief DeInitialize the FSMC_NORSRAM peripheral * @param Device: Pointer to NORSRAM device instance * @param ExDevice: Pointer to NORSRAM extended mode device instance - * @param Bank: NORSRAM bank number + * @param Bank: NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) @@ -301,19 +228,19 @@ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM /* De-initialize the FSMC_NORSRAM device */ /* FSMC_NORSRAM_BANK1 */ - if (Bank == FSMC_NORSRAM_BANK1) + if(Bank == FSMC_NORSRAM_BANK1) { - Device->BTCR[Bank] = 0x000030DB; + Device->BTCR[Bank] = 0x000030DBU; } /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */ else - { - Device->BTCR[Bank] = 0x000030D2; + { + Device->BTCR[Bank] = 0x000030D2U; } - - Device->BTCR[Bank + 1] = 0x0FFFFFFF; - ExDevice->BWTR[Bank] = 0x0FFFFFFF; - + + Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; + ExDevice->BWTR[Bank] = 0x0FFFFFFFU; + return HAL_OK; } @@ -340,14 +267,14 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO assert_param(IS_FSMC_NORSRAM_BANK(Bank)); /* Set FSMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1], \ - BTR_CLEAR_MASK, \ - (uint32_t)(Timing->AddressSetupTime | \ - ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) | \ - ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BTRx_DATAST)) | \ - ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BTRx_BUSTURN)) | \ - (((Timing->CLKDivision) - 1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) | \ - (((Timing->DataLatency) - 2) << POSITION_VAL(FSMC_BTRx_DATLAT)) | \ + MODIFY_REG(Device->BTCR[Bank + 1U], \ + BTR_CLEAR_MASK, \ + (uint32_t)(Timing->AddressSetupTime | \ + ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) | \ + ((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) | \ + ((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) | \ + (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | \ + (((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) | \ (Timing->AccessMode))); return HAL_OK; @@ -359,7 +286,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO * @param Device: Pointer to NORSRAM device instance * @param Timing: Pointer to NORSRAM Timing structure * @param Bank: NORSRAM bank number - * @param ExtendedMode: FSMC Extended Mode + * @param ExtendedMode FSMC Extended Mode * This parameter can be one of the following values: * @arg FSMC_EXTENDED_MODE_DISABLE * @arg FSMC_EXTENDED_MODE_ENABLE @@ -371,14 +298,14 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeD assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) + if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) { /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device)); assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); -#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); #else assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); @@ -388,42 +315,39 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeD assert_param(IS_FSMC_NORSRAM_BANK(Bank)); /* Set NORSRAM device timing register for write configuration, if extended mode is used */ -#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) - MODIFY_REG(Device->BWTR[Bank], \ - BWTR_CLEAR_MASK, \ - (uint32_t)(Timing->AddressSetupTime | \ - ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \ - ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) | \ - Timing->AccessMode | \ - ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN)))); +#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) + MODIFY_REG(Device->BWTR[Bank], \ + BWTR_CLEAR_MASK, \ + (uint32_t)(Timing->AddressSetupTime | \ + ((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) | \ + ((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) | \ + Timing->AccessMode | \ + ((Timing->BusTurnAroundDuration) << FSMC_BWTRx_BUSTURN_Pos))); #else - MODIFY_REG(Device->BWTR[Bank], \ - BWTR_CLEAR_MASK, \ - (uint32_t)(Timing->AddressSetupTime | \ - ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \ - ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) | \ - Timing->AccessMode | \ - (((Timing->CLKDivision) - 1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) | \ - (((Timing->DataLatency) - 2) << POSITION_VAL(FSMC_BWTRx_DATLAT)))); + MODIFY_REG(Device->BWTR[Bank], \ + BWTR_CLEAR_MASK, \ + (uint32_t)(Timing->AddressSetupTime | \ + ((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) | \ + ((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) | \ + Timing->AccessMode | \ + (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | \ + (((Timing->DataLatency) - 2U) << FSMC_BWTRx_DATLAT_Pos))); #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ } else { - Device->BWTR[Bank] = 0x0FFFFFFF; + Device->BWTR[Bank] = 0x0FFFFFFFU; } return HAL_OK; } - - /** * @} */ - /** @defgroup FSMC_NORSRAM_Group2 Control functions - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### FSMC_NORSRAM Control functions ##### @@ -471,7 +395,6 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi return HAL_OK; } - /** * @} */ @@ -479,6 +402,7 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi /** * @} */ + #if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) /** @defgroup FSMC_NAND FSMC NAND Controller functions * @brief NAND Controller functions @@ -506,8 +430,8 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi */ /** @defgroup FSMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim ============================================================================== ##### Initialization and de_initialization functions ##### @@ -545,28 +469,27 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe if (Init->NandBank == FSMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | \ - FSMC_PCR_MEMORY_TYPE_NAND | \ - Init->MemoryDataWidth | \ - Init->EccComputation | \ - Init->ECCPageSize | \ - ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR)) | \ - ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR)))); + MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | + FSMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) | + ((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos))); } else { /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | \ - FSMC_PCR_MEMORY_TYPE_NAND | \ - Init->MemoryDataWidth | \ - Init->EccComputation | \ - Init->ECCPageSize | \ - ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR)) | \ - ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR)))); + MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | + FSMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) | + ((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos))); } return HAL_OK; - } /** @@ -588,21 +511,21 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, F assert_param(IS_FSMC_NAND_BANK(Bank)); /* Set FMC_NAND device timing parameters */ - if (Bank == FSMC_NAND_BANK2) + if(Bank == FSMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | \ - ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx)) | \ - ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx)) | \ - ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx)))); + MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | \ + ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | \ + ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | \ + ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos))); } else { /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | \ - ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx)) | \ - ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx)) | \ - ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx)))); + MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | \ + ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | \ + ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | \ + ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos))); } return HAL_OK; @@ -627,21 +550,21 @@ HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device assert_param(IS_FSMC_NAND_BANK(Bank)); /* Set FMC_NAND device timing parameters */ - if (Bank == FSMC_NAND_BANK2) + if(Bank == FSMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | \ - ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) | \ - ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) | \ - ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx)))); + MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | \ + ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \ + ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \ + ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos))); } else { /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | \ - ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) | \ - ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) | \ - ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx)))); + MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | \ + ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \ + ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \ + ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos))); } return HAL_OK; @@ -649,7 +572,7 @@ HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device /** - * @brief DeInitializes the FSMC_NAND device + * @brief DeInitializes the FSMC_NAND device * @param Device: Pointer to NAND device instance * @param Bank: NAND bank number * @retval HAL status @@ -664,22 +587,22 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) __FSMC_NAND_DISABLE(Device, Bank); /* De-initialize the NAND Bank */ - if (Bank == FSMC_NAND_BANK2) + if(Bank == FSMC_NAND_BANK2) { /* Set the FSMC_NAND_BANK2 registers to their reset values */ - WRITE_REG(Device->PCR2, 0x00000018); - WRITE_REG(Device->SR2, 0x00000040); - WRITE_REG(Device->PMEM2, 0xFCFCFCFC); - WRITE_REG(Device->PATT2, 0xFCFCFCFC); + WRITE_REG(Device->PCR2, 0x00000018U); + WRITE_REG(Device->SR2, 0x00000040U); + WRITE_REG(Device->PMEM2, 0xFCFCFCFCU); + WRITE_REG(Device->PATT2, 0xFCFCFCFCU); } /* FSMC_Bank3_NAND */ else { /* Set the FSMC_NAND_BANK3 registers to their reset values */ - WRITE_REG(Device->PCR3, 0x00000018); - WRITE_REG(Device->SR3, 0x00000040); - WRITE_REG(Device->PMEM3, 0xFCFCFCFC); - WRITE_REG(Device->PATT3, 0xFCFCFCFC); + WRITE_REG(Device->PCR3, 0x00000018U); + WRITE_REG(Device->SR3, 0x00000040U); + WRITE_REG(Device->PMEM3, 0xFCFCFCFCU); + WRITE_REG(Device->PATT3, 0xFCFCFCFCU); } return HAL_OK; @@ -691,8 +614,8 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) /** @defgroup FSMC_NAND_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### FSMC_NAND Control functions ##### @@ -705,7 +628,6 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) * @{ */ - /** * @brief Enables dynamically FSMC_NAND ECC feature. * @param Device: Pointer to NAND device instance @@ -719,7 +641,7 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) assert_param(IS_FSMC_NAND_BANK(Bank)); /* Enable ECC feature */ - if (Bank == FSMC_NAND_BANK2) + if(Bank == FSMC_NAND_BANK2) { SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN); } @@ -731,7 +653,6 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) return HAL_OK; } - /** * @brief Disables dynamically FSMC_NAND ECC feature. * @param Device: Pointer to NAND device instance @@ -745,7 +666,7 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank assert_param(IS_FSMC_NAND_BANK(Bank)); /* Disable ECC feature */ - if (Bank == FSMC_NAND_BANK2) + if(Bank == FSMC_NAND_BANK2) { CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN); } @@ -762,13 +683,13 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank * @param Device: Pointer to NAND device instance * @param ECCval: Pointer to ECC value * @param Bank: NAND bank number - * @param Timeout: Timeout wait value + * @param Timeout: Timeout wait value * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { - uint32_t tickstart = 0; - + uint32_t tickstart = 0U; + /* Check the parameters */ assert_param(IS_FSMC_NAND_DEVICE(Device)); assert_param(IS_FSMC_NAND_BANK(Bank)); @@ -776,20 +697,20 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, /* Get tick */ tickstart = HAL_GetTick(); - /* Wait untill FIFO is empty */ - while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) + /* Wait until FIFO is empty */ + while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) { /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + if(Timeout != HAL_MAX_DELAY) { - if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { return HAL_TIMEOUT; } } } - if (Bank == FSMC_NAND_BANK2) + if(Bank == FSMC_NAND_BANK2) { /* Get the ECCR2 register value */ *ECCval = (uint32_t)Device->ECCR2; @@ -811,8 +732,6 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, * @} */ -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ -#if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) /** @defgroup FSMC_PCCARD FSMC PCCARD Controller functions * @brief PCCARD Controller functions * @@ -833,14 +752,13 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, (+) FSMC PCCARD bank IO space timing configuration using the function FSMC_PCCARD_IOSpace_Timing_Init() - @endverbatim * @{ */ /** @defgroup FSMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim ============================================================================== ##### Initialization and de_initialization functions ##### @@ -871,14 +789,14 @@ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_Init assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); /* Set FSMC_PCCARD device control parameters */ - MODIFY_REG(Device->PCR4, \ + MODIFY_REG(Device->PCR4, (FSMC_PCRx_PTYP | FSMC_PCRx_PWAITEN | FSMC_PCRx_PWID | - FSMC_PCRx_TCLR | FSMC_PCRx_TAR), \ - (FSMC_PCR_MEMORY_TYPE_PCCARD | \ - Init->Waitfeature | \ - FSMC_NAND_PCC_MEM_BUS_WIDTH_16 | \ - (Init->TCLRSetupTime << POSITION_VAL(FSMC_PCRx_TCLR)) | \ - (Init->TARSetupTime << POSITION_VAL(FSMC_PCRx_TAR)))); + FSMC_PCRx_TCLR | FSMC_PCRx_TAR), + (FSMC_PCR_MEMORY_TYPE_PCCARD | + Init->Waitfeature | + FSMC_NAND_PCC_MEM_BUS_WIDTH_16 | + (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos) | + (Init->TARSetupTime << FSMC_PCRx_TAR_Pos))); return HAL_OK; @@ -901,11 +819,11 @@ HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Devic assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); /* Set PCCARD timing parameters */ - MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK, \ - (Timing->SetupTime | \ - ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx)) | \ - ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx)) | \ - ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx)))); + MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK, + (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | + ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | + ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos))); return HAL_OK; } @@ -928,10 +846,10 @@ HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *De /* Set PCCARD timing parameters */ MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, \ - (Timing->SetupTime | \ - ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) | \ - ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) | \ - ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx)))); + (Timing->SetupTime | \ + ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \ + ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \ + ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos))); return HAL_OK; } @@ -953,11 +871,11 @@ HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, F assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); /* Set FSMC_PCCARD device timing parameters */ - MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \ - (Timing->SetupTime | \ - (Timing->WaitSetupTime << POSITION_VAL(FSMC_PIO4_IOWAIT4)) | \ - (Timing->HoldSetupTime << POSITION_VAL(FSMC_PIO4_IOHOLD4)) | \ - (Timing->HiZSetupTime << POSITION_VAL(FSMC_PIO4_IOHIZ4)))); + MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \ + (Timing->SetupTime | \ + (Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) | \ + (Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) | \ + (Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos))); return HAL_OK; } @@ -976,11 +894,11 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) __FSMC_PCCARD_DISABLE(Device); /* De-initialize the FSMC_PCCARD device */ - WRITE_REG(Device->PCR4, 0x00000018); - WRITE_REG(Device->SR4, 0x00000040); - WRITE_REG(Device->PMEM4, 0xFCFCFCFC); - WRITE_REG(Device->PATT4, 0xFCFCFCFC); - WRITE_REG(Device->PIO4, 0xFCFCFCFC); + WRITE_REG(Device->PCR4, 0x00000018U); + WRITE_REG(Device->SR4, 0x00000040U); + WRITE_REG(Device->PMEM4, 0xFCFCFCFCU); + WRITE_REG(Device->PATT4, 0xFCFCFCFCU); + WRITE_REG(Device->PIO4, 0xFCFCFCFCU); return HAL_OK; } @@ -1002,9 +920,9 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) * @} */ -#endif /* FSMC_BANK1 */ +#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */ -#endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */ +#endif /* FSMC_BANK1 */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.h index d3c77504d8e..b04c4a7d4dc 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_ll_fsmc.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of FSMC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -56,206 +56,6 @@ extern "C" { * @{ */ -/** @addtogroup FSMC_LL_Private_Macros - * @{ - */ - -#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ - ((__BANK__) == FSMC_NORSRAM_BANK2) || \ - ((__BANK__) == FSMC_NORSRAM_BANK3) || \ - ((__BANK__) == FSMC_NORSRAM_BANK4)) - -#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) - -#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) - -#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) - -#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) - -#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ - ((__MODE__) == FSMC_ACCESS_MODE_B) || \ - ((__MODE__) == FSMC_ACCESS_MODE_C) || \ - ((__MODE__) == FSMC_ACCESS_MODE_D)) - -#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \ - ((__BANK__) == FSMC_NAND_BANK3)) - -#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ - ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) - -#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) - -#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ - ((__STATE__) == FSMC_NAND_ECC_ENABLE)) - -#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ - ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ - ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ - ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ - ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ - ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) - -/** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time - * @{ - */ -#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time - * @{ - */ -#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FSMC_Setup_Time FSMC_Setup_Time - * @{ - */ -#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time - * @{ - */ -#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time - * @{ - */ -#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time - * @{ - */ -#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255) -/** - * @} - */ - -/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance - * @{ - */ - -#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) - -/** - * @} - */ - -/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance - * @{ - */ - -#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) - -/** - * @} - */ - -/** @defgroup FSMC_NAND_Device_Instance FSMC NAND Device Instance - * @{ - */ -#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) -/** - * @} - */ - -/** @defgroup FSMC_PCCARD_Device_Instance FSMC PCCARD Device Instance - * @{ - */ -#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) - -/** - * @} - */ -#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) - -#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) - -#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) - -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) - -#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) - -#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) - -#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) - -#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) - -#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) - -/** @defgroup FSMC_Data_Latency FSMC Data Latency - * @{ - */ -#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time - * @{ - */ -#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time - * @{ - */ -#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time - * @{ - */ -#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration - * @{ - */ -#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) -/** - * @} - */ - -/** - * @} - */ /* Exported typedef ----------------------------------------------------------*/ @@ -263,18 +63,8 @@ extern "C" { * @{ */ -#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef -#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef -#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef -#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef - -#define FSMC_NORSRAM_DEVICE FSMC_Bank1 -#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E -#define FSMC_NAND_DEVICE FSMC_Bank2_3 -#define FSMC_PCCARD_DEVICE FSMC_Bank4 - /** - * @brief FSMC_NORSRAM Configuration Structure definition + * @brief FSMC NORSRAM Configuration Structure definition */ typedef struct { @@ -329,7 +119,7 @@ typedef struct }FSMC_NORSRAM_InitTypeDef; /** - * @brief FSMC_NORSRAM Timing parameters structure definition + * @brief FSMC NORSRAM Timing parameters structure definition */ typedef struct { @@ -368,30 +158,30 @@ typedef struct with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ + This parameter can be a value of @ref FSMC_Access_Mode */ }FSMC_NORSRAM_TimingTypeDef; #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) /** - * @brief FSMC_NAND Configuration Structure definition + * @brief FSMC NAND Configuration Structure definition */ typedef struct { uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ + This parameter can be a value of @ref FSMC_NAND_Bank */ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. - This parameter can be any value of @ref FSMC_Wait_feature */ + This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_NAND_Data_Width */ + This parameter can be any value of @ref FSMC_NAND_Data_Width */ uint32_t EccComputation; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ + This parameter can be any value of @ref FSMC_ECC */ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ + This parameter can be any value of @ref FSMC_ECC_Page_Size */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -404,7 +194,7 @@ typedef struct }FSMC_NAND_InitTypeDef; /** - * @brief FSMC_NAND_PCCARD Timing parameters structure definition + * @brief FSMC NAND/PCCARD Timing parameters structure definition */ typedef struct { @@ -435,15 +225,13 @@ typedef struct }FSMC_NAND_PCC_TimingTypeDef; -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ -#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) /** - * @brief FSMC_NAND Configuration Structure definition + * @brief FSMC NAND Configuration Structure definition */ typedef struct { uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. - This parameter can be any value of @ref FSMC_Wait_feature */ + This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -454,7 +242,6 @@ typedef struct This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ }FSMC_PCCARD_InitTypeDef; - #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ /** * @} @@ -469,15 +256,13 @@ typedef struct /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants * @{ */ - /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank * @{ */ -#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000) -#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002) -#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004) -#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006) - +#define FSMC_NORSRAM_BANK1 0x00000000U +#define FSMC_NORSRAM_BANK2 0x00000002U +#define FSMC_NORSRAM_BANK3 0x00000004U +#define FSMC_NORSRAM_BANK4 0x00000006U /** * @} */ @@ -485,10 +270,8 @@ typedef struct /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing * @{ */ - -#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) +#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN) - /** * @} */ @@ -496,11 +279,9 @@ typedef struct /** @defgroup FSMC_Memory_Type FSMC Memory Type * @{ */ - -#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) +#define FSMC_MEMORY_TYPE_SRAM 0x00000000U #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0) #define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1) - /** * @} */ @@ -508,11 +289,9 @@ typedef struct /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width * @{ */ - -#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0) #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1) - /** * @} */ @@ -520,9 +299,8 @@ typedef struct /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access * @{ */ - #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN) -#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) +#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U /** * @} */ @@ -530,22 +308,17 @@ typedef struct /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode * @{ */ - -#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) +#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN) - /** * @} */ - /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity * @{ */ - -#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) +#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL) - /** * @} */ @@ -553,10 +326,8 @@ typedef struct /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode * @{ */ - -#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000) +#define FSMC_WRAP_MODE_DISABLE 0x00000000U #define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD) - /** * @} */ @@ -564,10 +335,8 @@ typedef struct /** @defgroup FSMC_Wait_Timing FSMC Wait Timing * @{ */ - -#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) +#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG) - /** * @} */ @@ -575,10 +344,8 @@ typedef struct /** @defgroup FSMC_Write_Operation FSMC Write Operation * @{ */ - -#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) +#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN) - /** * @} */ @@ -586,10 +353,8 @@ typedef struct /** @defgroup FSMC_Wait_Signal FSMC Wait Signal * @{ */ - -#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) +#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN) - /** * @} */ @@ -597,10 +362,8 @@ typedef struct /** @defgroup FSMC_Extended_Mode FSMC Extended Mode * @{ */ - -#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) +#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD) - /** * @} */ @@ -608,10 +371,8 @@ typedef struct /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait * @{ */ - -#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) +#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT) - /** * @} */ @@ -619,10 +380,8 @@ typedef struct /** @defgroup FSMC_Write_Burst FSMC Write Burst * @{ */ - -#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) +#define FSMC_WRITE_BURST_DISABLE 0x00000000U #define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW) - /** * @} */ @@ -630,12 +389,10 @@ typedef struct /** @defgroup FSMC_Access_Mode FSMC Access Mode * @{ */ - -#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000) +#define FSMC_ACCESS_MODE_A 0x00000000U #define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0) #define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1) #define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1)) - /** * @} */ @@ -648,13 +405,11 @@ typedef struct /** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller * @{ */ - /** @defgroup FSMC_NAND_Bank FSMC NAND Bank * @{ */ -#define FSMC_NAND_BANK2 ((uint32_t)0x00000010) -#define FSMC_NAND_BANK3 ((uint32_t)0x00000100) - +#define FSMC_NAND_BANK2 0x00000010U +#define FSMC_NAND_BANK3 0x00000100U /** * @} */ @@ -662,9 +417,8 @@ typedef struct /** @defgroup FSMC_Wait_feature FSMC Wait feature * @{ */ -#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) +#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FSMC_PCRx_PWAITEN) - /** * @} */ @@ -672,7 +426,7 @@ typedef struct /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type * @{ */ -#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000) +#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U #define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FSMC_PCRx_PTYP) /** * @} @@ -681,9 +435,8 @@ typedef struct /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width * @{ */ -#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) +#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_PCRx_PWID_0) - /** * @} */ @@ -691,9 +444,8 @@ typedef struct /** @defgroup FSMC_ECC FSMC NAND ECC * @{ */ -#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) +#define FSMC_NAND_ECC_DISABLE 0x00000000U #define FSMC_NAND_ECC_ENABLE ((uint32_t)FSMC_PCRx_ECCEN) - /** * @} */ @@ -701,30 +453,33 @@ typedef struct /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size * @{ */ -#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) +#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FSMC_PCRx_ECCPS_0) #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FSMC_PCRx_ECCPS_1) #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_1) #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FSMC_PCRx_ECCPS_2) #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_2) +/** + * @} + */ /** * @} */ +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ -/** @defgroup FSMC_Interrupt_definition FSMC Interrupt definition +/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition * @brief FSMC Interrupt definition * @{ */ #define FSMC_IT_RISING_EDGE ((uint32_t)FSMC_SRx_IREN) #define FSMC_IT_LEVEL ((uint32_t)FSMC_SRx_ILEN) #define FSMC_IT_FALLING_EDGE ((uint32_t)FSMC_SRx_IFEN) - /** * @} */ -/** @defgroup FSMC_Flag_definition FSMC Flag definition +/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition * @brief FSMC Flag definition * @{ */ @@ -732,43 +487,52 @@ typedef struct #define FSMC_FLAG_LEVEL ((uint32_t)FSMC_SRx_ILS) #define FSMC_FLAG_FALLING_EDGE ((uint32_t)FSMC_SRx_IFS) #define FSMC_FLAG_FEMPT ((uint32_t)FSMC_SRx_FEMPT) - /** * @} */ +/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition + * @{ + */ +#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef +#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef +#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef +#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef + +#define FSMC_NORSRAM_DEVICE FSMC_Bank1 +#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E +#define FSMC_NAND_DEVICE FSMC_Bank2_3 +#define FSMC_PCCARD_DEVICE FSMC_Bank4 /** * @} */ -#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ - /** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros * @{ */ -/** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros - * @brief macros to handle NOR device enable/disable and read/write operations - * @{ - */ +/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros + * @brief macros to handle NOR device enable/disable and read/write operations + * @{ + */ /** * @brief Enable the NORSRAM device access. - * @param __INSTANCE__ FSMC_NORSRAM Instance - * @param __BANK__ FSMC_NORSRAM Bank + * @param __INSTANCE__: FSMC_NORSRAM Instance + * @param __BANK__: FSMC_NORSRAM Bank * @retval none */ #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN) /** * @brief Disable the NORSRAM device access. - * @param __INSTANCE__ FSMC_NORSRAM Instance - * @param __BANK__ FSMC_NORSRAM Bank + * @param __INSTANCE__: FSMC_NORSRAM Instance + * @param __BANK__: FSMC_NORSRAM Bank * @retval none */ #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN) @@ -778,48 +542,46 @@ typedef struct */ #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) -/** @defgroup FSMC_NAND_Macros FSMC NAND Macros - * @brief macros to handle NAND device enable/disable - * @{ - */ +/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros + * @brief macros to handle NAND device enable/disable + * @{ + */ /** * @brief Enable the NAND device access. - * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank + * @param __INSTANCE__: FSMC_NAND Instance + * @param __BANK__: FSMC_NAND Bank * @retval None */ #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \ - SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) + SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) /** * @brief Disable the NAND device access. - * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank + * @param __INSTANCE__: FSMC_NAND Instance + * @param __BANK__: FSMC_NAND Bank * @retval None */ #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \ - CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) - + CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) /** * @} */ -/** @defgroup FSMC_PCCARD_Macros FSMC PCCARD Macros - * @brief macros to handle PCCARD read/write operations - * @{ - */ - +/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros + * @brief macros to handle PCCARD read/write operations + * @{ + */ /** * @brief Enable the PCCARD device access. - * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __INSTANCE__: FSMC_PCCARD Instance * @retval None */ #define __FSMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN) /** * @brief Disable the PCCARD device access. - * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __INSTANCE__: FSMC_PCCARD Instance * @retval None */ #define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN) @@ -827,20 +589,20 @@ typedef struct * @} */ -/** @defgroup FSMC_Interrupt FSMC Interrupt - * @brief macros to handle FSMC interrupts - * @{ - */ +/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros + * @brief macros to handle FSMC flags and interrupts + * @{ + */ /** * @brief Enable the NAND device interrupt. - * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank - * @param __INTERRUPT__ FSMC_NAND interrupt + * @param __INSTANCE__: FSMC_NAND Instance + * @param __BANK__: FSMC_NAND Bank + * @param __INTERRUPT__: FSMC_NAND interrupt * This parameter can be any combination of the following values: - * @arg FSMC_IT_RISING_EDGE Interrupt rising edge. - * @arg FSMC_IT_LEVEL Interrupt level. - * @arg FSMC_IT_FALLING_EDGE Interrupt falling edge. + * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FSMC_IT_LEVEL: Interrupt level. + * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None */ #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \ @@ -848,13 +610,13 @@ typedef struct /** * @brief Disable the NAND device interrupt. - * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank - * @param __INTERRUPT__ FSMC_NAND interrupt + * @param __INSTANCE__: FSMC_NAND Instance + * @param __BANK__: FSMC_NAND Bank + * @param __INTERRUPT__: FSMC_NAND interrupt * This parameter can be any combination of the following values: - * @arg FSMC_IT_RISING_EDGE Interrupt rising edge. - * @arg FSMC_IT_LEVEL Interrupt level. - * @arg FSMC_IT_FALLING_EDGE Interrupt falling edge. + * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FSMC_IT_LEVEL: Interrupt level. + * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None */ #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \ @@ -862,29 +624,28 @@ typedef struct /** * @brief Get flag status of the NAND device. - * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank - * @param __FLAG__ FSMC_NAND flag + * @param __INSTANCE__: FSMC_NAND Instance + * @param __BANK__ : FSMC_NAND Bank + * @param __FLAG__ : FSMC_NAND flag * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag. - * @arg FSMC_FLAG_LEVEL Interrupt level edge flag. - * @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT FIFO empty flag. + * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. * @retval The state of FLAG (SET or RESET). */ #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) - /** * @brief Clear flag status of the NAND device. - * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank - * @param __FLAG__ FSMC_NAND flag + * @param __INSTANCE__: FSMC_NAND Instance + * @param __BANK__: FSMC_NAND Bank + * @param __FLAG__: FSMC_NAND flag * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag. - * @arg FSMC_FLAG_LEVEL Interrupt level edge flag. - * @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT FIFO empty flag. + * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. * @retval None */ #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \ @@ -892,50 +653,50 @@ typedef struct /** * @brief Enable the PCCARD device interrupt. - * @param __INSTANCE__ FSMC_PCCARD Instance - * @param __INTERRUPT__ FSMC_PCCARD interrupt + * @param __INSTANCE__: FSMC_PCCARD Instance + * @param __INTERRUPT__: FSMC_PCCARD interrupt * This parameter can be any combination of the following values: - * @arg FSMC_IT_RISING_EDGE Interrupt rising edge. - * @arg FSMC_IT_LEVEL Interrupt level. - * @arg FSMC_IT_FALLING_EDGE Interrupt falling edge. + * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FSMC_IT_LEVEL: Interrupt level. + * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None */ #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__)) /** * @brief Disable the PCCARD device interrupt. - * @param __INSTANCE__ FSMC_PCCARD Instance - * @param __INTERRUPT__ FSMC_PCCARD interrupt + * @param __INSTANCE__: FSMC_PCCARD Instance + * @param __INTERRUPT__: FSMC_PCCARD interrupt * This parameter can be any combination of the following values: - * @arg FSMC_IT_RISING_EDGE Interrupt rising edge. - * @arg FSMC_IT_LEVEL Interrupt level. - * @arg FSMC_IT_FALLING_EDGE Interrupt falling edge. + * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. + * @arg FSMC_IT_LEVEL: Interrupt level. + * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None */ #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__)) /** * @brief Get flag status of the PCCARD device. - * @param __INSTANCE__ FSMC_PCCARD Instance - * @param __FLAG__ FSMC_PCCARD flag + * @param __INSTANCE__: FSMC_PCCARD Instance + * @param __FLAG__: FSMC_PCCARD flag * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag. - * @arg FSMC_FLAG_LEVEL Interrupt level edge flag. - * @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT FIFO empty flag. + * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. * @retval The state of FLAG (SET or RESET). */ #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) /** * @brief Clear flag status of the PCCARD device. - * @param __INSTANCE__ FSMC_PCCARD Instance - * @param __FLAG__ FSMC_PCCARD flag + * @param __INSTANCE__: FSMC_PCCARD Instance + * @param __FLAG__: FSMC_PCCARD flag * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RISING_EDGE Interrupt rising edge flag. - * @arg FSMC_FLAG_LEVEL Interrupt level edge flag. - * @arg FSMC_FLAG_FALLING_EDGE Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT FIFO empty flag. + * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. * @retval None */ #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__)) @@ -943,46 +704,296 @@ typedef struct /** * @} */ - #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ /** * @} */ +/** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros + * @{ + */ +#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ + ((__BANK__) == FSMC_NORSRAM_BANK2) || \ + ((__BANK__) == FSMC_NORSRAM_BANK3) || \ + ((__BANK__) == FSMC_NORSRAM_BANK4)) + +#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) + +#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) + +#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) + +#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) + +#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ + ((__MODE__) == FSMC_ACCESS_MODE_B) || \ + ((__MODE__) == FSMC_ACCESS_MODE_C) || \ + ((__MODE__) == FSMC_ACCESS_MODE_D)) + +#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \ + ((__BANK__) == FSMC_NAND_BANK3)) + +#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ + ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) + +#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) + +#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ + ((__STATE__) == FSMC_NAND_ECC_ENABLE)) + +#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) + +/** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time + * @{ + */ +#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time + * @{ + */ +#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time FSMC_Setup_Time + * @{ + */ +#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255U) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time + * @{ + */ +#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255U) +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time + * @{ + */ +#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255U) +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time + * @{ + */ +#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255U) +/** + * @} + */ + +/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance + * @{ + */ +#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) +/** + * @} + */ + +/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance + * @{ + */ +#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) +/** + * @} + */ + +/** @defgroup FSMC_NAND_Device_Instance FSMC NAND Device Instance + * @{ + */ +#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) +/** + * @} + */ + +/** @defgroup FSMC_PCCARD_Device_Instance FSMC PCCARD Device Instance + * @{ + */ +#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) + +/** + * @} + */ +#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) + +#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) + +#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ + ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) + +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) + +#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) + +#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) + +#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) + +#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) + +#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) + +/** @defgroup FSMC_Data_Latency FSMC Data Latency + * @{ + */ +#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time + * @{ + */ +#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time + * @{ + */ +#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time + * @{ + */ +#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration + * @{ + */ +#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants + * @{ + */ + +/* ----------------------- FSMC registers bit mask --------------------------- */ +#if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN | \ + FSMC_PCRx_PTYP | FSMC_PCRx_PWID | \ + FSMC_PCRx_ECCEN | FSMC_PCRx_TCLR | \ + FSMC_PCRx_TAR | FSMC_PCRx_ECCPS)) + +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEMx_MEMSETx | FSMC_PMEMx_MEMWAITx |\ + FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATTx_ATTSETx | FSMC_PATTx_ATTWAITx |\ + FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx)) + +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ +/* --- BCR Register ---*/ +/* BCR register clear mask */ +#define BCR_CLEAR_MASK ((uint32_t)(FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | \ + FSMC_BCRx_MTYP | FSMC_BCRx_MWID | \ + FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | \ + FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \ + FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | \ + FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | \ + FSMC_BCRx_CBURSTRW)) +/* --- BTR Register ---*/ +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD |\ + FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\ + FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT |\ + FSMC_BTRx_ACCMOD)) + +/* --- BWTR Register ---*/ +/* BWTR register clear mask */ +#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) +#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \ + FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \ + FSMC_BWTRx_BUSTURN)) +#else +#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \ + FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \ + FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT)) +#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ + +/* --- PIO4 Register ---*/ +/* PIO4 register clear mask */ +#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \ + FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4)) +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup FSMC_LL_Exported_Functions - * @{ - */ + * @{ + */ /** @addtogroup FSMC_NORSRAM - * @{ - */ + * @{ + */ /** @addtogroup FSMC_NORSRAM_Group1 - * @{ - */ - + * @{ + */ /* FSMC_NORSRAM Controller functions ******************************************/ /* Initialization/de-initialization functions */ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); - /** * @} */ /** @addtogroup FSMC_NORSRAM_Group2 - * @{ - */ - + * @{ + */ /* FSMC_NORSRAM Control functions */ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); - /** * @} */ @@ -993,33 +1004,29 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Dev #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) /** @addtogroup FSMC_NAND - * @{ - */ + * @{ + */ /* FSMC_NAND Controller functions **********************************************/ /* Initialization/de-initialization functions */ /** @addtogroup FSMC_NAND_Exported_Functions_Group1 - * @{ - */ - + * @{ + */ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); - /** * @} */ /* FSMC_NAND Control functions */ /** @addtogroup FSMC_NAND_Exported_Functions_Group2 - * @{ - */ - + * @{ + */ HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); - /** * @} */ @@ -1029,21 +1036,19 @@ HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, */ /** @addtogroup FSMC_PCCARD - * @{ - */ + * @{ + */ /* FSMC_PCCARD Controller functions ********************************************/ /* Initialization/de-initialization functions */ /** @addtogroup FSMC_PCCARD_Exported_Functions_Group1 - * @{ - */ - + * @{ + */ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); - /** * @} */ @@ -1051,8 +1056,8 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); /** * @} */ - #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ + /** * @} */ @@ -1060,7 +1065,6 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); /** * @} */ - #endif /* FSMC_BANK1 */ /** diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.c index ee061717120..43360fa9d68 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_gpio.c * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief GPIO LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.h index 91af0dac53c..6035560fe4b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_gpio.h * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of GPIO LL module. ****************************************************************************** * @attention @@ -127,28 +127,28 @@ typedef struct /** @defgroup GPIO_LL_EC_PIN PIN * @{ */ -#define LL_GPIO_PIN_0 (GPIO_BSRR_BS0 << 8) | 0x00000001U /*!< Select pin 0 */ -#define LL_GPIO_PIN_1 (GPIO_BSRR_BS1 << 8) | 0x00000002U /*!< Select pin 1 */ -#define LL_GPIO_PIN_2 (GPIO_BSRR_BS2 << 8) | 0x00000004U /*!< Select pin 2 */ -#define LL_GPIO_PIN_3 (GPIO_BSRR_BS3 << 8) | 0x00000008U /*!< Select pin 3 */ -#define LL_GPIO_PIN_4 (GPIO_BSRR_BS4 << 8) | 0x00000010U /*!< Select pin 4 */ -#define LL_GPIO_PIN_5 (GPIO_BSRR_BS5 << 8) | 0x00000020U /*!< Select pin 5 */ -#define LL_GPIO_PIN_6 (GPIO_BSRR_BS6 << 8) | 0x00000040U /*!< Select pin 6 */ -#define LL_GPIO_PIN_7 (GPIO_BSRR_BS7 << 8) | 0x00000080U /*!< Select pin 7 */ -#define LL_GPIO_PIN_8 (GPIO_BSRR_BS8 << 8) | 0x04000001U /*!< Select pin 8 */ -#define LL_GPIO_PIN_9 (GPIO_BSRR_BS9 << 8) | 0x04000002U /*!< Select pin 9 */ -#define LL_GPIO_PIN_10 (GPIO_BSRR_BS10 << 8) | 0x04000004U /*!< Select pin 10 */ -#define LL_GPIO_PIN_11 (GPIO_BSRR_BS11 << 8) | 0x04000008U /*!< Select pin 11 */ -#define LL_GPIO_PIN_12 (GPIO_BSRR_BS12 << 8) | 0x04000010U /*!< Select pin 12 */ -#define LL_GPIO_PIN_13 (GPIO_BSRR_BS13 << 8) | 0x04000020U /*!< Select pin 13 */ -#define LL_GPIO_PIN_14 (GPIO_BSRR_BS14 << 8) | 0x04000040U /*!< Select pin 14 */ -#define LL_GPIO_PIN_15 (GPIO_BSRR_BS15 << 8) | 0x04000080U /*!< Select pin 15 */ -#define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \ - LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \ - LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \ - LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \ - LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \ - LL_GPIO_PIN_15) /*!< Select all pins */ +#define LL_GPIO_PIN_0 (GPIO_BSRR_BS0 << 8) | 0x00000001U /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 (GPIO_BSRR_BS1 << 8) | 0x00000002U /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 (GPIO_BSRR_BS2 << 8) | 0x00000004U /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 (GPIO_BSRR_BS3 << 8) | 0x00000008U /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 (GPIO_BSRR_BS4 << 8) | 0x00000010U /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 (GPIO_BSRR_BS5 << 8) | 0x00000020U /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 (GPIO_BSRR_BS6 << 8) | 0x00000040U /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 (GPIO_BSRR_BS7 << 8) | 0x00000080U /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 (GPIO_BSRR_BS8 << 8) | 0x04000001U /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 (GPIO_BSRR_BS9 << 8) | 0x04000002U /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 (GPIO_BSRR_BS10 << 8) | 0x04000004U /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 (GPIO_BSRR_BS11 << 8) | 0x04000008U /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 (GPIO_BSRR_BS12 << 8) | 0x04000010U /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 (GPIO_BSRR_BS13 << 8) | 0x04000020U /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 (GPIO_BSRR_BS14 << 8) | 0x04000040U /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 (GPIO_BSRR_BS15 << 8) | 0x04000080U /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \ + LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \ + LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \ + LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \ + LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \ + LL_GPIO_PIN_15) /*!< Select all pins */ /** * @} */ @@ -202,22 +202,22 @@ typedef struct * @{ */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ -#define LL_GPIO_AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ +#define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ +#define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ +#define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ +#define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ +#define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ +#define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ +#define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ +#define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ +#define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ +#define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ +#define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ +#define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ +#define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ +#define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ +#define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ +#define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ /** * @} @@ -227,11 +227,11 @@ typedef struct * @{ */ -#define LL_GPIO_AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ -#define LL_GPIO_AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ -#define LL_GPIO_AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ -#define LL_GPIO_AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ -#define LL_GPIO_AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ +#define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ +#define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ +#define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ +#define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ +#define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ /** * @} @@ -240,13 +240,13 @@ typedef struct /** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT * @{ */ -#define LL_GPIO_AFIO_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */ -#define LL_GPIO_AFIO_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */ -#define LL_GPIO_AFIO_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */ -#define LL_GPIO_AFIO_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */ -#define LL_GPIO_AFIO_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */ -#define LL_GPIO_AFIO_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */ -#define LL_GPIO_AFIO_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */ +#define LL_GPIO_AF_EXTI_PORTA (uint32_t)0 /*!< EXTI PORT A */ +#define LL_GPIO_AF_EXTI_PORTB (uint32_t)1 /*!< EXTI PORT B */ +#define LL_GPIO_AF_EXTI_PORTC (uint32_t)2 /*!< EXTI PORT C */ +#define LL_GPIO_AF_EXTI_PORTD (uint32_t)3 /*!< EXTI PORT D */ +#define LL_GPIO_AF_EXTI_PORTE (uint32_t)4 /*!< EXTI PORT E */ +#define LL_GPIO_AF_EXTI_PORTF (uint32_t)5 /*!< EXTI PORT F */ +#define LL_GPIO_AF_EXTI_PORTG (uint32_t)6 /*!< EXTI PORT G */ /** * @} */ @@ -254,22 +254,22 @@ typedef struct /** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE * @{ */ -#define LL_GPIO_AFIO_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */ -#define LL_GPIO_AFIO_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */ -#define LL_GPIO_AFIO_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */ -#define LL_GPIO_AFIO_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */ -#define LL_GPIO_AFIO_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */ -#define LL_GPIO_AFIO_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */ -#define LL_GPIO_AFIO_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */ -#define LL_GPIO_AFIO_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */ -#define LL_GPIO_AFIO_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */ -#define LL_GPIO_AFIO_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */ -#define LL_GPIO_AFIO_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */ -#define LL_GPIO_AFIO_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */ -#define LL_GPIO_AFIO_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */ -#define LL_GPIO_AFIO_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */ -#define LL_GPIO_AFIO_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */ -#define LL_GPIO_AFIO_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */ +#define LL_GPIO_AF_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_GPIO_AF_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_GPIO_AF_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_GPIO_AF_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_GPIO_AF_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_GPIO_AF_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_GPIO_AF_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_GPIO_AF_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_GPIO_AF_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_GPIO_AF_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_GPIO_AF_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_GPIO_AF_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_GPIO_AF_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_GPIO_AF_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_GPIO_AF_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_GPIO_AF_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3) /*!< EXTI_POSITION_12 | EXTICR[3] */ /** * @} */ @@ -888,305 +888,371 @@ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @} */ -/** @defgroup GPIO_AFIO_AF_REMAPPING Alternate Function Remapping +/** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping * @brief This section propose definition to remap the alternate function to some other port/pins. * @{ */ /** * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. - * @rmtoll MAPR SPI1_REMAP LL_GPIO_AFIO_REMAP_SPI1_ENABLE + * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1 * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SPI1_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP); } /** * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. - * @rmtoll MAPR SPI1_REMAP LL_GPIO_AFIO_REMAP_SPI1_DISABLE + * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1 * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SPI1_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP); } +/** + * @brief Check if SPI1 has been remaped or not + * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP)); +} + /** * @brief Enable the remapping of I2C1 alternate function SCL and SDA. - * @rmtoll MAPR I2C1_REMAP LL_GPIO_AFIO_REMAP_I2C1_ENABLE + * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1 * @note ENABLE: Remap (SCL/PB8, SDA/PB9) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_I2C1_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP); } /** * @brief Disable the remapping of I2C1 alternate function SCL and SDA. - * @rmtoll MAPR I2C1_REMAP LL_GPIO_AFIO_REMAP_I2C1_DISABLE + * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1 * @note DISABLE: No remap (SCL/PB6, SDA/PB7) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_I2C1_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP); } +/** + * @brief Check if I2C1 has been remaped or not + * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP)); +} + /** * @brief Enable the remapping of USART1 alternate function TX and RX. - * @rmtoll MAPR USART1_REMAP LL_GPIO_AFIO_REMAP_USART1_ENABLE + * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1 * @note ENABLE: Remap (TX/PB6, RX/PB7) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART1_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP); } /** * @brief Disable the remapping of USART1 alternate function TX and RX. - * @rmtoll MAPR USART1_REMAP LL_GPIO_AFIO_REMAP_USART1_DISABLE + * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1 * @note DISABLE: No remap (TX/PA9, RX/PA10) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART1_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP); } +/** + * @brief Check if USART1 has been remaped or not + * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP)); +} + /** * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. - * @rmtoll MAPR USART2_REMAP LL_GPIO_AFIO_REMAP_USART2_ENABLE + * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2 * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART2_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP); } /** * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. - * @rmtoll MAPR USART2_REMAP LL_GPIO_AFIO_REMAP_USART2_DISABLE + * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2 * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART2_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP); } +/** + * @brief Check if USART2 has been remaped or not + * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP)); +} + #if defined (AFIO_MAPR_USART3_REMAP) /** * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. - * @rmtoll MAPR USART3_REMAP LL_GPIO_AFIO_REMAP_USART3_ENABLE + * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3 * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART3_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP); } /** * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. - * @rmtoll MAPR USART3_REMAP LL_GPIO_AFIO_REMAP_USART3_PARTIAL + * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3 * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART3_PARTIAL(void) +__STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_PARTIALREMAP); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP); } /** * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. - * @rmtoll MAPR USART3_REMAP LL_GPIO_AFIO_REMAP_USART3_DISABLE + * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3 * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_USART3_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_USART3_REMAP, AFIO_MAPR_USART3_REMAP_NOREMAP); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP); } #endif /** * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) - * @rmtoll MAPR TIM1_REMAP LL_GPIO_AFIO_REMAP_TIM1_ENABLE + * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1 * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM1_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP); } /** * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) - * @rmtoll MAPR TIM1_REMAP LL_GPIO_AFIO_REMAP_TIM1_PARTIAL + * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1 * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM1_PARTIAL(void) +__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP); } /** * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) - * @rmtoll MAPR TIM1_REMAP LL_GPIO_AFIO_REMAP_TIM1_DISABLE + * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1 * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM1_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP, AFIO_MAPR_TIM1_REMAP_NOREMAP); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP); } /** * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) - * @rmtoll MAPR TIM2_REMAP LL_GPIO_AFIO_REMAP_TIM2_ENABLE + * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2 * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM2_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP); } /** * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) - * @rmtoll MAPR TIM2_REMAP LL_GPIO_AFIO_REMAP_TIM2_PARTIAL_2 + * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2 * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM2_PARTIAL_2(void) +__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2); } /** * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) - * @rmtoll MAPR TIM2_REMAP LL_GPIO_AFIO_REMAP_TIM2_PARTIAL_1 + * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2 * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM2_PARTIAL_1(void) +__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1); } /** * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) - * @rmtoll MAPR TIM2_REMAP LL_GPIO_AFIO_REMAP_TIM2_PARTIAL_1 + * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2 * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM2_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP, AFIO_MAPR_TIM2_REMAP_NOREMAP); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP); } /** * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 - * @rmtoll MAPR TIM3_REMAP LL_GPIO_AFIO_REMAP_TIM3_ENABLE + * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3 * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) * @note TIM3_ETR on PE0 is not re-mapped. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM3_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP); } /** * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 - * @rmtoll MAPR TIM3_REMAP LL_GPIO_AFIO_REMAP_TIM3_PARTIAL + * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3 * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) * @note TIM3_ETR on PE0 is not re-mapped. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM3_PARTIAL(void) +__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP); } /** * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 - * @rmtoll MAPR TIM3_REMAP LL_GPIO_AFIO_REMAP_TIM3_DISABLE + * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3 * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) * @note TIM3_ETR on PE0 is not re-mapped. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM3_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP, AFIO_MAPR_TIM3_REMAP_NOREMAP); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP); } #if defined(AFIO_MAPR_TIM4_REMAP) /** * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. - * @rmtoll MAPR TIM4_REMAP LL_GPIO_AFIO_REMAP_TIM4_ENABLE + * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4 * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) * @note TIM4_ETR on PE0 is not re-mapped. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM4_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP); } /** * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. - * @rmtoll MAPR TIM4_REMAP LL_GPIO_AFIO_REMAP_TIM4_DISABLE + * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4 * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) * @note TIM4_ETR on PE0 is not re-mapped. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM4_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP); } + +/** + * @brief Check if TIM4 has been remaped or not + * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP)); +} #endif #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) /** * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. - * @rmtoll MAPR CAN_REMAP LL_GPIO_AFIO_REMAP_CAN1_1 + * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1 * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CAN1_1(void) +__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP1); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1); } /** * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. - * @rmtoll MAPR CAN_REMAP LL_GPIO_AFIO_REMAP_CAN1_2 + * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1 * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CAN1_2(void) +__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP2); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2); } /** * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. - * @rmtoll MAPR CAN_REMAP LL_GPIO_AFIO_REMAP_CAN1_3 + * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1 * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CAN1_3(void) +__STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_CAN_REMAP, AFIO_MAPR_CAN_REMAP_REMAP3); + CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP); + SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3); } #endif @@ -1195,11 +1261,11 @@ __STATIC_INLINE void LL_GPIO_AFIO_REMAP_CAN1_3(void) * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available * on 100-pin and 144-pin packages, no need for remapping). - * @rmtoll MAPR PD01_REMAP LL_GPIO_AFIO_REMAP_PD01_ENABLE + * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01 * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_PD01_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP); } @@ -1209,114 +1275,154 @@ __STATIC_INLINE void LL_GPIO_AFIO_REMAP_PD01_ENABLE(void) * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available * on 100-pin and 144-pin packages, no need for remapping). - * @rmtoll MAPR PD01_REMAP LL_GPIO_AFIO_REMAP_PD01_DISABLE + * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01 * @note DISABLE: No remapping of PD0 and PD1 * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_PD01_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP); } +/** + * @brief Check if PD01 has been remaped or not + * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP)); +} + #if defined(AFIO_MAPR_TIM5CH4_IREMAP) /** * @brief Enable the remapping of TIM5CH4. - * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AFIO_REMAP_TIM5CH4_ENABLE + * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4 * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. * @note This function is available only in high density value line devices. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM5CH4_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP); } /** * @brief Disable the remapping of TIM5CH4. - * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AFIO_REMAP_TIM5CH4_DISABLE + * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4 * @note DISABLE: TIM5_CH4 is connected to PA3 * @note This function is available only in high density value line devices. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM5CH4_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP); } + +/** + * @brief Check if TIM5CH4 has been remaped or not + * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP)); +} #endif #if defined(AFIO_MAPR_ETH_REMAP) /** * @brief Enable the remapping of Ethernet MAC connections with the PHY. - * @rmtoll MAPR ETH_REMAP LL_GPIO_AFIO_REMAP_ETH_ENABLE + * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ETH_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP); } /** * @brief Disable the remapping of Ethernet MAC connections with the PHY. - * @rmtoll MAPR ETH_REMAP LL_GPIO_AFIO_REMAP_ETH_DISABLE + * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ETH_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP); } + +/** + * @brief Check if ETH has been remaped or not + * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP)); +} #endif #if defined(AFIO_MAPR_CAN2_REMAP) /** * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. - * @rmtoll MAPR CAN2_REMAP LL_GPIO_AFIO_REMAP_CAN2_ENABLE + * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2 * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CAN2_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP); } /** * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. - * @rmtoll MAPR CAN2_REMAP LL_GPIO_AFIO_REMAP_CAN2_DISABLE + * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2 * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CAN2_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP); } + +/** + * @brief Check if CAN2 has been remaped or not + * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP)); +} #endif #if defined(AFIO_MAPR_MII_RMII_SEL) /** * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. - * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AFIO_REMAP_ETH_RMII + * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ETH_RMII(void) +__STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL); } /** * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. - * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AFIO_REMAP_ETH_MII + * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ETH_MII(void) +__STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL); } @@ -1325,194 +1431,248 @@ __STATIC_INLINE void LL_GPIO_AFIO_REMAP_ETH_MII(void) #if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP) /** * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). - * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AFIO_REMAP_ADC1_ETRGINJ_ENABLE + * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC1_ETRGINJ_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP); } /** * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). - * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AFIO_REMAP_ADC1_ETRGINJ_DISABLE + * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC1_ETRGINJ_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP); } + +/** + * @brief Check if ADC1_ETRGINJ has been remaped or not + * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP)); +} #endif #if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP) /** * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). - * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AFIO_REMAP_ADC1_ETRGREG_ENABLE + * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC1_ETRGREG_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP); } /** * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). - * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AFIO_REMAP_ADC1_ETRGREG_DISABLE + * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC1_ETRGREG_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP); } + +/** + * @brief Check if ADC1_ETRGREG has been remaped or not + * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP)); +} #endif #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) /** * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). - * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AFIO_REMAP_ADC2_ETRGINJ_ENABLE + * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC2_ETRGINJ_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP); } /** * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). - * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AFIO_REMAP_ADC2_ETRGINJ_DISABLE + * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC2_ETRGINJ_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP); } + +/** + * @brief Check if ADC2_ETRGINJ has been remaped or not + * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP)); +} #endif #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) /** * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). - * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AFIO_REMAP_ADC2_ETRGREG_ENABLE + * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC2_ETRGREG_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP); } /** * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). - * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AFIO_REMAP_ADC2_ETRGREG_DISABLE + * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_ADC2_ETRGREG_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP); } + +/** + * @brief Check if ADC2_ETRGREG has been remaped or not + * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP)); +} #endif /** * @brief Enable the Serial wire JTAG configuration - * @rmtoll MAPR SWJ_CFG LL_GPIO_AFIO_REMAP_SWJ_ENABLE + * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SWJ_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET); + CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); + SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET); } /** * @brief Enable the Serial wire JTAG configuration - * @rmtoll MAPR SWJ_CFG LL_GPIO_AFIO_REMAP_SWJ_NONJTRST + * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SWJ_NONJTRST(void) +__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST); + CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); + SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST); } /** * @brief Enable the Serial wire JTAG configuration - * @rmtoll MAPR SWJ_CFG LL_GPIO_AFIO_REMAP_SWJ_NOJTAG + * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SWJ_NOJTAG(void) +__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); + CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); + SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); } /** * @brief Disable the Serial wire JTAG configuration - * @rmtoll MAPR SWJ_CFG LL_GPIO_AFIO_REMAP_SWJ_DISABLE + * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SWJ_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void) { - MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE); + CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); + SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE); } #if defined(AFIO_MAPR_SPI3_REMAP) /** * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. - * @rmtoll MAPR SPI3_REMAP LL_GPIO_AFIO_REMAP_SPI3_ENABLE + * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3 * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SPI3_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP); } /** * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. - * @rmtoll MAPR SPI3_REMAP LL_GPIO_AFIO_REMAP_SPI3_DISABLE + * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3 * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_SPI3_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP); } + +/** + * @brief Check if SPI3 has been remaped or not + * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void) +{ + return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP)); +} #endif #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) /** * @brief Control of TIM2_ITR1 internal mapping. - * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AFIO_TIM2ITR1_TO_USB + * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_TIM2ITR1_TO_USB(void) +__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP); } /** * @brief Control of TIM2_ITR1 internal mapping. - * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AFIO_TIM2ITR1_TO_ETH + * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_TIM2ITR1_TO_ETH(void) +__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP); } @@ -1522,24 +1682,24 @@ __STATIC_INLINE void LL_GPIO_AFIO_TIM2ITR1_TO_ETH(void) /** * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). - * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AFIO_ETH_PTP_PPS_ENABLE + * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS * @note ENABLE: PTP_PPS is output on PB5 pin. * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_ETH_PTP_PPS_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void) { SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP); } /** * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). - * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AFIO_ETH_PTP_PPS_DISABLE + * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS * @note DISABLE: PTP_PPS not output on PB5 pin. * @note This bit is available only in connectivity line devices and is reserved otherwise. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_ETH_PTP_PPS_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void) { CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP); } @@ -1549,146 +1709,196 @@ __STATIC_INLINE void LL_GPIO_AFIO_ETH_PTP_PPS_DISABLE(void) /** * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. - * @rmtoll MAPR TIM9_REMAP LL_GPIO_AFIO_REMAP_TIM9_ENABLE + * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9 * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM9_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); } /** * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. - * @rmtoll MAPR TIM9_REMAP LL_GPIO_AFIO_REMAP_TIM9_ENABLE + * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9 * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM9_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); } + +/** + * @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not + * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP)); +} #endif #if defined(AFIO_MAPR2_TIM10_REMAP) /** * @brief Enable the remapping of TIM10_CH1. - * @rmtoll MAPR TIM10_REMAP LL_GPIO_AFIO_REMAP_TIM10_ENABLE + * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10 * @note ENABLE: Remap (TIM10_CH1 on PF6). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM10_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); } /** * @brief Disable the remapping of TIM10_CH1. - * @rmtoll MAPR TIM10_REMAP LL_GPIO_AFIO_REMAP_TIM10_DISABLE + * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10 * @note DISABLE: No remap (TIM10_CH1 on PB8). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM10_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); } + +/** + * @brief Check if TIM10_CH1 has been remaped or not + * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP)); +} #endif #if defined(AFIO_MAPR2_TIM11_REMAP) /** * @brief Enable the remapping of TIM11_CH1. - * @rmtoll MAPR TIM11_REMAP LL_GPIO_AFIO_REMAP_TIM11_ENABLE + * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11 * @note ENABLE: Remap (TIM11_CH1 on PF7). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM11_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); } /** * @brief Disable the remapping of TIM11_CH1. - * @rmtoll MAPR TIM11_REMAP LL_GPIO_AFIO_REMAP_TIM11_DISABLE + * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11 * @note DISABLE: No remap (TIM11_CH1 on PB9). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM11_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); } + +/** + * @brief Check if TIM11_CH1 has been remaped or not + * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP)); +} #endif #if defined(AFIO_MAPR2_TIM13_REMAP) /** * @brief Enable the remapping of TIM13_CH1. - * @rmtoll MAPR TIM13_REMAP LL_GPIO_AFIO_REMAP_TIM13_ENABLE + * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13 * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM13_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); } /** * @brief Disable the remapping of TIM13_CH1. - * @rmtoll MAPR TIM13_REMAP LL_GPIO_AFIO_REMAP_TIM13_DISABLE + * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13 * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM13_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); } + +/** + * @brief Check if TIM13_CH1 has been remaped or not + * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP)); +} #endif #if defined(AFIO_MAPR2_TIM14_REMAP) /** * @brief Enable the remapping of TIM14_CH1. - * @rmtoll MAPR TIM14_REMAP LL_GPIO_AFIO_REMAP_TIM14_ENABLE + * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14 * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM14_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); } /** * @brief Disable the remapping of TIM14_CH1. - * @rmtoll MAPR TIM14_REMAP LL_GPIO_AFIO_REMAP_TIM14_DISABLE + * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14 * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM14_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); } + +/** + * @brief Check if TIM14_CH1 has been remaped or not + * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP)); +} #endif #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) /** * @brief Controls the use of the optional FSMC_NADV signal. - * @rmtoll MAPR FSMC_NADV LL_GPIO_AFIO_FSMCNADV_DISCONNECTED + * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_FSMCNADV_DISCONNECTED(void) +__STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); } /** * @brief Controls the use of the optional FSMC_NADV signal. - * @rmtoll MAPR FSMC_NADV LL_GPIO_AFIO_FSMCNADV_CONNECTED + * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV * @note CONNECTED: The NADV signal is connected to the output (default). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_FSMCNADV_CONNECTED(void) +__STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); } @@ -1698,176 +1908,246 @@ __STATIC_INLINE void LL_GPIO_AFIO_FSMCNADV_CONNECTED(void) /** * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. - * @rmtoll MAPR TIM15_REMAP LL_GPIO_AFIO_REMAP_TIM15_ENABLE + * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15 * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM15_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); } /** * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. - * @rmtoll MAPR TIM15_REMAP LL_GPIO_AFIO_REMAP_TIM15_DISABLE + * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15 * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM15_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); } + +/** + * @brief Check if TIM15_CH1 has been remaped or not + * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP)); +} #endif #if defined(AFIO_MAPR2_TIM16_REMAP) /** * @brief Enable the remapping of TIM16_CH1. - * @rmtoll MAPR TIM16_REMAP LL_GPIO_AFIO_REMAP_TIM16_ENABLE + * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16 * @note ENABLE: Remap (TIM16_CH1 on PA6). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM16_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); } /** * @brief Disable the remapping of TIM16_CH1. - * @rmtoll MAPR TIM16_REMAP LL_GPIO_AFIO_REMAP_TIM16_DISABLE + * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16 * @note DISABLE: No remap (TIM16_CH1 on PB8). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM16_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); } + +/** + * @brief Check if TIM16_CH1 has been remaped or not + * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP)); +} #endif #if defined(AFIO_MAPR2_TIM17_REMAP) /** * @brief Enable the remapping of TIM17_CH1. - * @rmtoll MAPR TIM17_REMAP LL_GPIO_AFIO_REMAP_TIM17_ENABLE + * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17 * @note ENABLE: Remap (TIM17_CH1 on PA7). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM17_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); } /** * @brief Disable the remapping of TIM17_CH1. - * @rmtoll MAPR TIM17_REMAP LL_GPIO_AFIO_REMAP_TIM17_DISABLE + * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17 * @note DISABLE: No remap (TIM17_CH1 on PB9). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM17_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); } + +/** + * @brief Check if TIM17_CH1 has been remaped or not + * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP)); +} #endif #if defined(AFIO_MAPR2_CEC_REMAP) /** * @brief Enable the remapping of CEC. - * @rmtoll MAPR CEC_REMAP LL_GPIO_AFIO_REMAP_CEC_ENABLE + * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC * @note ENABLE: Remap (CEC on PB10). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CEC_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); } /** * @brief Disable the remapping of CEC. - * @rmtoll MAPR CEC_REMAP LL_GPIO_AFIO_REMAP_CEC_DISABLE + * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC * @note DISABLE: No remap (CEC on PB8). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_CEC_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); } + +/** + * @brief Check if CEC has been remaped or not + * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP)); +} #endif #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) /** * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. - * @rmtoll MAPR TIM1_DMA_REMAP LL_GPIO_AFIO_REMAP_TIM1DMA_ENABLE + * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM1DMA_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); } /** * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. - * @rmtoll MAPR TIM1_DMA_REMAP LL_GPIO_AFIO_REMAP_TIM1DMA_DISABLE + * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM1DMA_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); } + +/** + * @brief Check if TIM1DMA has been remaped or not + * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP)); +} #endif #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) /** * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. - * @rmtoll MAPR TIM76_DAC_DMA_REMAP LL_GPIO_AFIO_REMAP_TIM67DACDMA_ENABLE + * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM67DACDMA_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); } /** * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. - * @rmtoll MAPR TIM76_DAC_DMA_REMAP LL_GPIO_AFIO_REMAP_TIM67DACDMA_DISABLE + * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM67DACDMA_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); } + +/** + * @brief Check if TIM67DACDMA has been remaped or not + * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP)); +} #endif #if defined(AFIO_MAPR2_TIM12_REMAP) /** * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. - * @rmtoll MAPR TIM12_REMAP LL_GPIO_AFIO_REMAP_TIM12_ENABLE + * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12 * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). * @note This bit is available only in high density value line devices. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM12_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); } /** * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. - * @rmtoll MAPR TIM12_REMAP LL_GPIO_AFIO_REMAP_TIM12_DISABLE + * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12 * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). * @note This bit is available only in high density value line devices. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM12_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); } + +/** + * @brief Check if TIM12_CH1 has been remaped or not + * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP)); +} #endif #if defined(AFIO_MAPR2_MISC_REMAP) @@ -1877,13 +2157,13 @@ __STATIC_INLINE void LL_GPIO_AFIO_REMAP_TIM12_DISABLE(void) * This bit is set and cleared by software. It controls miscellaneous features. * The DMA2 channel 5 interrupt position in the vector table. * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). - * @rmtoll MAPR MISC_REMAP LL_GPIO_AFIO_REMAP_MISC_ENABLE + * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is * selected as DAC Trigger 3, TIM15 triggers TIM1/3. * @note This bit is available only in high density value line devices. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_MISC_ENABLE(void) +__STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void) { SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); } @@ -1893,77 +2173,87 @@ __STATIC_INLINE void LL_GPIO_AFIO_REMAP_MISC_ENABLE(void) * This bit is set and cleared by software. It controls miscellaneous features. * The DMA2 channel 5 interrupt position in the vector table. * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). - * @rmtoll MAPR MISC_REMAP LL_GPIO_AFIO_REMAP_MISC_DISABLE + * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. * @note This bit is available only in high density value line devices. * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_REMAP_MISC_DISABLE(void) +__STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void) { CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); } + +/** + * @brief Check if MISC has been remaped or not + * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void) +{ + return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP)); +} #endif /** * @} */ -/** @defgroup GPIO_AFIO_LL_EVENTOUT Output Event configuration +/** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration * @brief This section propose definition to Configure EVENTOUT Cortex feature . * @{ */ /** * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. - * @rmtoll EVCR PORT LL_GPIO_AFIO_ConfigEventout\n - * EVCR PIN LL_GPIO_AFIO_ConfigEventout + * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n + * EVCR PIN LL_GPIO_AF_ConfigEventout * @param LL_GPIO_PortSource This parameter can be one of the following values: - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PORT_A - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PORT_B - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PORT_C - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PORT_D - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PORT_E + * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A + * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B + * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C + * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D + * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E * @param LL_GPIO_PinSource This parameter can be one of the following values: - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_0 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_1 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_2 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_3 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_4 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_5 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_6 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_7 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_8 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_9 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_10 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_11 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_12 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_13 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_14 - * @arg @ref LL_GPIO_AFIO_EVENTOUT_PIN_15 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14 + * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15 * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource) +__STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource) { MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource)); } /** * @brief Enables the Event Output. - * @rmtoll EVCR EVOE LL_GPIO_AFIO_EnableEventout + * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_EnableEventout(void) +__STATIC_INLINE void LL_GPIO_AF_EnableEventout(void) { SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); } /** * @brief Disables the Event Output. - * @rmtoll EVCR EVOE LL_GPIO_AFIO_DisableEventout + * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout * @retval None */ -__STATIC_INLINE void LL_GPIO_AFIO_DisableEventout(void) +__STATIC_INLINE void LL_GPIO_AF_DisableEventout(void) { CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); } @@ -1971,82 +2261,82 @@ __STATIC_INLINE void LL_GPIO_AFIO_DisableEventout(void) /** * @} */ -/** @defgroup GPIO_AFIO_LL_EXTI EXTI external interrupt +/** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt * @brief This section Configure source input for the EXTI external interrupt . * @{ */ /** * @brief Configure source input for the EXTI external interrupt. - * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AFIO_SetEXTISource\n - * AFIO_EXTICR2 EXTIx LL_GPIO_AFIO_SetEXTISource\n - * AFIO_EXTICR3 EXTIx LL_GPIO_AFIO_SetEXTISource\n - * AFIO_EXTICR4 EXTIx LL_GPIO_AFIO_SetEXTISource + * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n + * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n + * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n + * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource * @param Port This parameter can be one of the following values: - * @arg @ref LL_GPIO_AFIO_EXTI_PORTA - * @arg @ref LL_GPIO_AFIO_EXTI_PORTB - * @arg @ref LL_GPIO_AFIO_EXTI_PORTC - * @arg @ref LL_GPIO_AFIO_EXTI_PORTD - * @arg @ref LL_GPIO_AFIO_EXTI_PORTE - * @arg @ref LL_GPIO_AFIO_EXTI_PORTF - * @arg @ref LL_GPIO_AFIO_EXTI_PORTG + * @arg @ref LL_GPIO_AF_EXTI_PORTA + * @arg @ref LL_GPIO_AF_EXTI_PORTB + * @arg @ref LL_GPIO_AF_EXTI_PORTC + * @arg @ref LL_GPIO_AF_EXTI_PORTD + * @arg @ref LL_GPIO_AF_EXTI_PORTE + * @arg @ref LL_GPIO_AF_EXTI_PORTF + * @arg @ref LL_GPIO_AF_EXTI_PORTG * @param Line This parameter can be one of the following values: - * @arg @ref LL_GPIO_AFIO_EXTI_LINE0 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE1 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE2 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE3 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE4 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE5 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE6 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE7 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE8 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE9 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE10 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE11 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE12 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE13 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE14 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE15 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_AFIO_SetEXTISource(uint32_t Port, uint32_t Line) + * @arg @ref LL_GPIO_AF_EXTI_LINE0 + * @arg @ref LL_GPIO_AF_EXTI_LINE1 + * @arg @ref LL_GPIO_AF_EXTI_LINE2 + * @arg @ref LL_GPIO_AF_EXTI_LINE3 + * @arg @ref LL_GPIO_AF_EXTI_LINE4 + * @arg @ref LL_GPIO_AF_EXTI_LINE5 + * @arg @ref LL_GPIO_AF_EXTI_LINE6 + * @arg @ref LL_GPIO_AF_EXTI_LINE7 + * @arg @ref LL_GPIO_AF_EXTI_LINE8 + * @arg @ref LL_GPIO_AF_EXTI_LINE9 + * @arg @ref LL_GPIO_AF_EXTI_LINE10 + * @arg @ref LL_GPIO_AF_EXTI_LINE11 + * @arg @ref LL_GPIO_AF_EXTI_LINE12 + * @arg @ref LL_GPIO_AF_EXTI_LINE13 + * @arg @ref LL_GPIO_AF_EXTI_LINE14 + * @arg @ref LL_GPIO_AF_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line) { MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16))); } /** * @brief Get the configured defined for specific EXTI Line - * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AFIO_GetEXTISource\n - * AFIO_EXTICR2 EXTIx LL_GPIO_AFIO_GetEXTISource\n - * AFIO_EXTICR3 EXTIx LL_GPIO_AFIO_GetEXTISource\n - * AFIO_EXTICR4 EXTIx LL_GPIO_AFIO_GetEXTISource + * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n + * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n + * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n + * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource * @param Line This parameter can be one of the following values: - * @arg @ref LL_GPIO_AFIO_EXTI_LINE0 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE1 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE2 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE3 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE4 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE5 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE6 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE7 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE8 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE9 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE10 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE11 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE12 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE13 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE14 - * @arg @ref LL_GPIO_AFIO_EXTI_LINE15 + * @arg @ref LL_GPIO_AF_EXTI_LINE0 + * @arg @ref LL_GPIO_AF_EXTI_LINE1 + * @arg @ref LL_GPIO_AF_EXTI_LINE2 + * @arg @ref LL_GPIO_AF_EXTI_LINE3 + * @arg @ref LL_GPIO_AF_EXTI_LINE4 + * @arg @ref LL_GPIO_AF_EXTI_LINE5 + * @arg @ref LL_GPIO_AF_EXTI_LINE6 + * @arg @ref LL_GPIO_AF_EXTI_LINE7 + * @arg @ref LL_GPIO_AF_EXTI_LINE8 + * @arg @ref LL_GPIO_AF_EXTI_LINE9 + * @arg @ref LL_GPIO_AF_EXTI_LINE10 + * @arg @ref LL_GPIO_AF_EXTI_LINE11 + * @arg @ref LL_GPIO_AF_EXTI_LINE12 + * @arg @ref LL_GPIO_AF_EXTI_LINE13 + * @arg @ref LL_GPIO_AF_EXTI_LINE14 + * @arg @ref LL_GPIO_AF_EXTI_LINE15 * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AFIO_EXTI_PORTA - * @arg @ref LL_GPIO_AFIO_EXTI_PORTB - * @arg @ref LL_GPIO_AFIO_EXTI_PORTC - * @arg @ref LL_GPIO_AFIO_EXTI_PORTD - * @arg @ref LL_GPIO_AFIO_EXTI_PORTE - * @arg @ref LL_GPIO_AFIO_EXTI_PORTF - * @arg @ref LL_GPIO_AFIO_EXTI_PORTG - */ -__STATIC_INLINE uint32_t LL_GPIO_AFIO_GetEXTISource(uint32_t Line) + * @arg @ref LL_GPIO_AF_EXTI_PORTA + * @arg @ref LL_GPIO_AF_EXTI_PORTB + * @arg @ref LL_GPIO_AF_EXTI_PORTC + * @arg @ref LL_GPIO_AF_EXTI_PORTD + * @arg @ref LL_GPIO_AF_EXTI_PORTE + * @arg @ref LL_GPIO_AF_EXTI_PORTF + * @arg @ref LL_GPIO_AF_EXTI_PORTG + */ +__STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line) { return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16)); } diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.c new file mode 100644 index 00000000000..0a882f75435 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.c @@ -0,0 +1,239 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_i2c.c + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief I2C LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_i2c.h" +#include "stm32f1xx_ll_bus.h" +#include "stm32f1xx_ll_rcc.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_LL_Private_Macros + * @{ + */ + +#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP)) + +#define IS_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST)) + +#define IS_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \ + ((__VALUE__) == LL_I2C_DUTYCYCLE_16_9)) + +#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) + +#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \ + ((__VALUE__) == LL_I2C_NACK)) + +#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \ + ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the I2C registers to their default reset values. + * @param I2Cx I2C Instance. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I2C registers are de-initialized + * - ERROR: I2C registers are not de-initialized + */ +uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx) +{ + ErrorStatus status = SUCCESS; + + /* Check the I2C Instance I2Cx */ + assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + + if (I2Cx == I2C1) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); + } +#if defined(I2C2) + else if (I2Cx == I2C2) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2); + + } +#endif /* I2C2 */ + else + { + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. + * @param I2Cx I2C Instance. + * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I2C registers are initialized + * - ERROR: Not applicable + */ +uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) +{ + LL_RCC_ClocksTypeDef rcc_clocks; + + /* Check the I2C Instance I2Cx */ + assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + + /* Check the I2C parameters from I2C_InitStruct */ + assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode)); + assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle)); + assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1)); + assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge)); + assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize)); + + /* Disable the selected I2Cx Peripheral */ + LL_I2C_Disable(I2Cx); + + /* Retrieve Clock frequencies */ + LL_RCC_GetSystemClocksFreq(&rcc_clocks); + + /*---------------------------- I2Cx SCL Clock Speed Configuration ------------ + * Configure the SCL speed : + * - ClockSpeed: I2C_CR2_FREQ[5:0], I2C_TRISE_TRISE[5:0], I2C_CCR_FS, + * and I2C_CCR_CCR[11:0] bits + * - DutyCycle: I2C_CCR_DUTY[7:0] bits + */ + LL_I2C_ConfigSpeed(I2Cx, rcc_clocks.PCLK1_Frequency, I2C_InitStruct->ClockSpeed, I2C_InitStruct->DutyCycle); + + /*---------------------------- I2Cx OAR1 Configuration ----------------------- + * Disable, Configure and Enable I2Cx device own address 1 with parameters : + * - OwnAddress1: I2C_OAR1_ADD[9:8], I2C_OAR1_ADD[7:1] and I2C_OAR1_ADD0 bits + * - OwnAddrSize: I2C_OAR1_ADDMODE bit + */ + LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize); + + /*---------------------------- I2Cx MODE Configuration ----------------------- + * Configure I2Cx peripheral mode with parameter : + * - PeripheralMode: I2C_CR1_SMBUS, I2C_CR1_SMBTYPE and I2C_CR1_ENARP bits + */ + LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode); + + /* Enable the selected I2Cx Peripheral */ + LL_I2C_Enable(I2Cx); + + /*---------------------------- I2Cx CR2 Configuration ------------------------ + * Configure the ACKnowledge or Non ACKnowledge condition + * after the address receive match code or next received byte with parameter : + * - TypeAcknowledge: I2C_CR2_NACK bit + */ + LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_I2C_InitTypeDef field to default value. + * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure. + * @retval None + */ +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) +{ + /* Set I2C_InitStruct fields to default values */ + I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C; + I2C_InitStruct->ClockSpeed = 5000U; + I2C_InitStruct->DutyCycle = LL_I2C_DUTYCYCLE_2; + I2C_InitStruct->OwnAddress1 = 0U; + I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK; + I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h new file mode 100644 index 00000000000..98081ddc45a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h @@ -0,0 +1,1802 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_i2c.h + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_I2C_H +#define __STM32F1xx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Constants I2C Private Constants + * @{ + */ + +/* Defines used to perform compute and check in the macros */ +#define LL_I2C_MAX_SPEED_STANDARD 100000U +#define LL_I2C_MAX_SPEED_FAST 400000U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_Private_Macros I2C Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ + + uint32_t ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz (in Hz) + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod() + or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */ + + uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */ + + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE + + This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ + + uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ +} LL_I2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_ReadReg function + * @{ + */ +#define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */ +#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or + Address matched flag (slave mode) */ +#define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */ +#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */ +#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */ +#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */ +#define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */ +#define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */ +#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */ +#define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */ +#define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */ +#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */ +#define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */ +#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */ +#define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */ +#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */ +#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */ +#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */ +#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + * @{ + */ +#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */ +#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */ +#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle + * @{ + */ +#define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */ +#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode + * @{ + */ +#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */ +#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */ +#define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Convert Peripheral Clock Frequency in Mhz. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @retval Value of peripheral clock (in Mhz) + */ +#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U) + +/** + * @brief Convert Peripheral Clock Frequency in Hz. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz). + * @retval Value of peripheral clock (in Hz) + */ +#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U) + +/** + * @brief Compute I2C Clock rising time. + * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz). + * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). + * @retval Value between Min_Data=0x02 and Max_Data=0x3F + */ +#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) + +/** + * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). + * @param __DUTYCYCLE__ This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. + */ +#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \ + (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \ + (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__)))) + +/** + * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz). + * @retval Value between Min_Data=0x004 and Max_Data=0xFFF. + */ +#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) + +/** + * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz). + * @param __DUTYCYCLE__ This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval Value between Min_Data=0x001 and Max_Data=0xFFF + */ +#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \ + (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \ + (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U)))) + +/** + * @brief Get the Least significant bits of a 10-Bits address. + * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) + +/** + * @brief Convert a 10-Bits address to a 10-Bits header with Write direction. + * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. + * @retval Value between Min_Data=0xF0 and Max_Data=0xF6 + */ +#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) + +/** + * @brief Convert a 10-Bits address to a 10-Bits header with Read direction. + * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. + * @retval Value between Min_Data=0xF1 and Max_Data=0xF7 + */ +#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_I2C_Enable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @rmtoll CR1 PE LL_I2C_Disable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_I2C_IsEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)); +} + + +/** + * @brief Enable DMA transmission requests. + * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); +} + +/** + * @brief Get the data register address used for DMA transfer. + * @rmtoll DR DR LL_I2C_DMA_GetRegAddr + * @param I2Cx I2C Instance. + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx) +{ + return (uint32_t) & (I2Cx->DR); +} + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)); +} + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ENGC); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n + * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n + * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n + * OAR1 ADDMODE LL_I2C_SetOwnAddress1 + * @param I2Cx I2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize); +} + +/** + * @brief Set the 7bits Own Address2. + * @note This action has no effect if own address2 is enabled. + * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2 + * @param I2Cx I2C Instance. + * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2) +{ + MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2); +} + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL)); +} + +/** + * @brief Configure the Peripheral clock frequency. + * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock + * @param I2Cx I2C Instance. + * @param PeriphClock Peripheral Clock (in Hz) + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock)); +} + +/** + * @brief Get the Peripheral clock frequency. + * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock + * @param I2Cx I2C Instance. + * @retval Value of Peripheral Clock (in Hz) + */ +__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ))); +} + +/** + * @brief Configure the Duty cycle (Fast mode only). + * @rmtoll CCR DUTY LL_I2C_SetDutyCycle + * @param I2Cx I2C Instance. + * @param DutyCycle This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle) +{ + MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle); +} + +/** + * @brief Get the Duty cycle (Fast mode only). + * @rmtoll CCR DUTY LL_I2C_GetDutyCycle + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + */ +__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY)); +} + +/** + * @brief Configure the I2C master clock speed mode. + * @rmtoll CCR FS LL_I2C_SetClockSpeedMode + * @param I2Cx I2C Instance. + * @param ClockSpeedMode This parameter can be one of the following values: + * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE + * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode) +{ + MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode); +} + +/** + * @brief Get the the I2C master speed mode. + * @rmtoll CCR FS LL_I2C_GetClockSpeedMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE + * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS)); +} + +/** + * @brief Configure the SCL, SDA rising time. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll TRISE TRISE LL_I2C_SetRiseTime + * @param I2Cx I2C Instance. + * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime) +{ + MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime); +} + +/** + * @brief Get the SCL, SDA rising time. + * @rmtoll TRISE TRISE LL_I2C_GetRiseTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x02 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE)); +} + +/** + * @brief Configure the SCL high and low period. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CCR CCR LL_I2C_SetClockPeriod + * @param I2Cx I2C Instance. + * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod) +{ + MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod); +} + +/** + * @brief Get the SCL high and low period. + * @rmtoll CCR CCR LL_I2C_GetClockPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR)); +} + +/** + * @brief Configure the SCL speed. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n + * TRISE TRISE LL_I2C_ConfigSpeed\n + * CCR FS LL_I2C_ConfigSpeed\n + * CCR DUTY LL_I2C_ConfigSpeed\n + * CCR CCR LL_I2C_ConfigSpeed + * @param I2Cx I2C Instance. + * @param PeriphClock Peripheral Clock (in Hz) + * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz). + * @param DutyCycle This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed, + uint32_t DutyCycle) +{ + register uint32_t freqrange = 0x0U; + register uint32_t clockconfig = 0x0U; + + /* Compute frequency range */ + freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock); + + /* Configure I2Cx: Frequency range register */ + MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange); + + /* Configure I2Cx: Rise Time register */ + MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed)); + + /* Configure Speed mode, Duty Cycle and Clock control register value */ + if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD) + { + /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */ + clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \ + __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \ + DutyCycle; + } + else + { + /* Set Speed mode at standard for Clock Speed request in standard clock range */ + clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \ + __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed); + } + + /* Configure I2Cx: Clock control register */ + MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig); +} + +/** + * @brief Configure peripheral mode. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBUS LL_I2C_SetMode\n + * CR1 SMBTYPE LL_I2C_SetMode\n + * CR1 ENARP LL_I2C_SetMode + * @param I2Cx I2C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBUS LL_I2C_GetMode\n + * CR1 SMBTYPE LL_I2C_GetMode\n + * CR1 ENARP LL_I2C_GetMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + */ +__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ALERT); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT)); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC)); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n + * CR2 ITBUFEN LL_I2C_EnableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Disable TXE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n + * CR2 ITBUFEN LL_I2C_DisableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Check if the TXE Interrupt is enabled or disabled. + * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n + * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n + * CR2 ITBUFEN LL_I2C_EnableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n + * CR2 ITBUFEN LL_I2C_DisableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n + * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); +} + +/** + * @brief Enable Events interrupts. + * @note Any of these events will generate interrupt : + * Start Bit (SB) + * Address sent, Address matched (ADDR) + * 10-bit header sent (ADD10) + * Stop detection (STOPF) + * Byte transfer finished (BTF) + * + * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) : + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); +} + +/** + * @brief Disable Events interrupts. + * @note Any of these events will generate interrupt : + * Start Bit (SB) + * Address sent, Address matched (ADDR) + * 10-bit header sent (ADD10) + * Stop detection (STOPF) + * Byte transfer finished (BTF) + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); +} + +/** + * @brief Check if Events interrupts are enabled or disabled. + * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN)); +} + +/** + * @brief Enable Buffer interrupts. + * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) : + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); +} + +/** + * @brief Disable Buffer interrupts. + * @note Any of these Buffer events will generate interrupt : + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); +} + +/** + * @brief Check if Buffer interrupts are enabled or disabled. + * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN)); +} + +/** + * @brief Enable Error interrupts. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Bus Error detection (BERR) + * Arbitration Loss (ARLO) + * Acknowledge Failure(AF) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (SMBALERT) + * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN); +} + +/** + * @brief Disable Error interrupts. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Bus Error detection (BERR) + * Arbitration Loss (ARLO) + * Acknowledge Failure(AF) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (SMBALERT) + * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN)); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE)); +} + +/** + * @brief Indicate the status of Byte Transfer Finished flag. + * RESET: When Data byte transfer not done. + * SET: When Data byte transfer succeeded. + * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF)); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE)); +} + +/** + * @brief Indicate the status of Start Bit (master mode). + * @note RESET: When No Start condition. + * SET: When Start condition is generated. + * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB)); +} + +/** + * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode). + * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR)); +} + +/** + * @brief Indicate the status of 10-bit header sent (master mode). + * @note RESET: When no ADD10 event occured. + * SET: When the master has sent the first address byte (header). + * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10)); +} + +/** + * @brief Indicate the status of Acknowledge failure flag. + * @note RESET: No acknowledge failure. + * SET: When an acknowledge failure is received after a byte transmission. + * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF)); +} + +/** + * @brief Indicate the status of Stop detection flag (slave mode). + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF)); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR)); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO)); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag. + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR)); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR)); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT)); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT)); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY)); +} + +/** + * @brief Indicate the status of Dual flag. + * @note RESET: Received address matched with OAR1. + * SET: Received address matched with OAR2. + * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF)); +} + +/** + * @brief Indicate the status of SMBus Host address reception (Slave mode). + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: No SMBus Host address + * SET: SMBus Host address received. + * @note This status is cleared by hardware after a STOP condition or repeated START condition. + * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST)); +} + +/** + * @brief Indicate the status of SMBus Device default address reception (Slave mode). + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: No SMBus Device default address + * SET: SMBus Device default address received. + * @note This status is cleared by hardware after a STOP condition or repeated START condition. + * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT)); +} + +/** + * @brief Indicate the status of General call address reception (Slave mode). + * @note RESET: No Generall call address + * SET: General call address received. + * @note This status is cleared by hardware after a STOP condition or repeated START condition. + * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL)); +} + +/** + * @brief Indicate the status of Master/Slave flag. + * @note RESET: Slave Mode. + * SET: Master Mode. + * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL)); +} + +/** + * @brief Clear Address Matched flag. + * @note Clearing this flag is done by a read access to the I2Cx_SR1 + * register followed by a read access to the I2Cx_SR2 register. + * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + __IO uint32_t tmpreg; + tmpreg = I2Cx->SR1; + (void) tmpreg; + tmpreg = I2Cx->SR2; + (void) tmpreg; +} + +/** + * @brief Clear Acknowledge failure flag. + * @rmtoll SR1 AF LL_I2C_ClearFlag_AF + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF); +} + +/** + * @brief Clear Stop detection flag. + * @note Clearing this flag is done by a read access to the I2Cx_SR1 + * register followed by a write access to I2Cx_CR1 register. + * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n + * CR1 PE LL_I2C_ClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + __IO uint32_t tmpreg; + tmpreg = I2Cx->SR1; + (void) tmpreg; + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR); +} + +/** + * @brief Clear SMBus PEC error flag. + * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT); +} + +/** + * @brief Clear SMBus Alert flag. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable Reset of I2C peripheral. + * @rmtoll CR1 SWRST LL_I2C_EnableReset + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_SWRST); +} + +/** + * @brief Disable Reset of I2C peripheral. + * @rmtoll CR1 SWRST LL_I2C_DisableReset + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST); +} + +/** + * @brief Check if the I2C peripheral is under reset state or not. + * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST)); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + * @note Usage in Slave or Master mode. + * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData + * @param I2Cx I2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR1 START LL_I2C_GenerateStartCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOP); +} + +/** + * @brief Enable bit POS (master/host mode). + * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC. + * @rmtoll CR1 POS LL_I2C_EnableBitPOS + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_POS); +} + +/** + * @brief Disable bit POS (master/host mode). + * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC. + * @rmtoll CR1 POS LL_I2C_DisableBitPOS + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS); +} + +/** + * @brief Check if bit POS is enabled or disabled. + * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS)); +} + +/** + * @brief Indicate the value of transfer direction. + * @note RESET: Bus is in read transfer (peripheral point of view). + * SET: Bus is in write transfer (peripheral point of view). + * @rmtoll SR2 TRA LL_I2C_GetTransferDirection + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA)); +} + +/** + * @brief Enable DMA last transfer. + * @note This action mean that next DMA EOT is the last transfer. + * @rmtoll CR2 LAST LL_I2C_EnableLastDMA + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_LAST); +} + +/** + * @brief Disable DMA last transfer. + * @note This action mean that next DMA EOT is not the last transfer. + * @rmtoll CR2 LAST LL_I2C_DisableLastDMA + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST); +} + +/** + * @brief Check if DMA last transfer is enabled or disabled. + * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST)); +} + +/** + * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This feature is cleared by hardware when the PEC byte is transferred or compared, + * or by a START or STOP condition, it is also cleared by software. + * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PEC); +} + +/** + * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC); +} + +/** + * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC)); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos); +} + +/** + * @brief Read Receive Data register. + * @rmtoll DR DR LL_I2C_ReceiveData8 + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +{ + return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll DR DR LL_I2C_TransmitData8 + * @param I2Cx I2C Instance. + * @param Data Value between Min_Data=0x0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) +{ + MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); +uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx); +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_iwdg.h new file mode 100644 index 00000000000..2605939096b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_iwdg.h @@ -0,0 +1,329 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_iwdg.h + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief Header file of IWDG LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_IWDG_H +#define __STM32F1xx_LL_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(IWDG) + +/** @defgroup IWDG_LL IWDG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants + * @{ + */ + +#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ +#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ +#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ +#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants + * @{ + */ + +/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_IWDG_ReadReg function + * @{ + */ +#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ +#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ + +/** + * @} + */ + +/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider + * @{ + */ +#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ +#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ +#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ +#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ +#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */ +#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ +#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros + * @{ + */ + +/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions + * @{ + */ +/** @defgroup IWDG_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Start the Independent Watchdog + * @note Except if the hardware watchdog option is selected + * @rmtoll KR KEY LL_IWDG_Enable + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE); +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * @rmtoll KR KEY LL_IWDG_ReloadCounter + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD); +} + +/** + * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_EnableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); +} + +/** + * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_DisableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); +} + +/** + * @brief Select the prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_SetPrescaler + * @param IWDGx IWDG Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) +{ + WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); +} + +/** + * @brief Get the selected prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_GetPrescaler + * @param IWDGx IWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + */ +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +{ + return (uint32_t)(READ_REG(IWDGx->PR)); +} + +/** + * @brief Specify the IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_SetReloadCounter + * @param IWDGx IWDG Instance + * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) +{ + WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); +} + +/** + * @brief Get the specified IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_GetReloadCounter + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +{ + return (uint32_t)(READ_REG(IWDGx->RLR)); +} + + +/** + * @} + */ + +/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if flag Prescaler Value Update is set or not + * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +{ + return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)); +} + +/** + * @brief Check if flag Reload Value Update is set or not + * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +{ + return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)); +} + + +/** + * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not + * @rmtoll SR PVU LL_IWDG_IsReady\n + * SR RVU LL_IWDG_IsReady + * @param IWDGx IWDG Instance + * @retval State of bits (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +{ + return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* IWDG) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_IWDG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.c index af58b118cd1..947d47ac436 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_pwr.c * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief PWR LL module driver. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.h index 4c5c3455dc2..a1ad470b15a 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_pwr.h * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of PWR LL module. ****************************************************************************** * @attention @@ -93,7 +93,7 @@ extern "C" { * @{ */ #define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (ith low power regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ #define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ /** * @} @@ -102,8 +102,8 @@ extern "C" { /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode * @{ */ -#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep mode */ -#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */ /** * @} */ @@ -125,7 +125,7 @@ extern "C" { /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins * @{ */ -#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */ /** * @} */ @@ -206,7 +206,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) } /** - * @brief Set voltage regulator mode during deep sleep mode + * @brief Set voltage Regulator mode during deep sleep mode * @rmtoll CR LPDS LL_PWR_SetRegulModeDS * @param RegulMode This parameter can be one of the following values: * @arg @ref LL_PWR_REGU_DSMODE_MAIN @@ -219,7 +219,7 @@ __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) } /** - * @brief Get voltage regulator mode during deep sleep mode + * @brief Get voltage Regulator mode during deep sleep mode * @rmtoll CR LPDS LL_PWR_GetRegulModeDS * @retval Returned value can be one of the following values: * @arg @ref LL_PWR_REGU_DSMODE_MAIN @@ -231,7 +231,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) } /** - * @brief Set power down mode when CPU enters deepsleep + * @brief Set Power Down mode when CPU enters deepsleep * @rmtoll CR PDDS LL_PWR_SetPowerMode\n * @rmtoll CR LPDS LL_PWR_SetPowerMode * @param PDMode This parameter can be one of the following values: @@ -246,7 +246,7 @@ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) } /** - * @brief Get power down mode when CPU enters deepsleep + * @brief Get Power Down mode when CPU enters deepsleep * @rmtoll CR PDDS LL_PWR_GetPowerMode\n * @rmtoll CR LPDS LL_PWR_GetPowerMode * @retval Returned value can be one of the following values: @@ -420,6 +420,11 @@ __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) { SET_BIT(PWR->CR, PWR_CR_CWUF); } + +/** + * @} + */ + #if defined(USE_FULL_LL_DRIVER) /** @defgroup PWR_LL_EF_Init De-initialization function * @{ @@ -438,10 +443,6 @@ ErrorStatus LL_PWR_DeInit(void); * @} */ -/** - * @} - */ - #endif /* defined(PWR) */ /** diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.c index e13376a66f9..d931ff9b677 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_rcc.c * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief RCC LL module driver. ****************************************************************************** * @attention @@ -55,7 +55,6 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ - /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ /** @addtogroup RCC_LL_Private_Macros @@ -71,7 +70,6 @@ #endif /* USB */ #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE)) - /** * @} */ @@ -95,7 +93,6 @@ uint32_t RCC_PLL2_GetFreqClockFreq(void); * @} */ - /* Exported functions --------------------------------------------------------*/ /** @addtogroup RCC_LL_Exported_Functions * @{ @@ -163,13 +160,13 @@ ErrorStatus LL_RCC_DeInit(void) /* Reset PLL3ON bit */ CLEAR_BIT(vl_mask, RCC_CR_PLL3ON); #endif /* RCC_CR_PLL3ON */ - + LL_RCC_WriteReg(CR, vl_mask); /* Set HSITRIM bits to the reset value */ LL_RCC_HSI_SetCalibTrimming(0x10U); -#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT) +#if defined(RCC_CFGR2_PREDIV1) /* Reset CFGR2 register */ vl_mask = 0x00000000U; @@ -184,7 +181,7 @@ ErrorStatus LL_RCC_DeInit(void) #endif /* RCC_PLLI2S_SUPPORT */ LL_RCC_WriteReg(CFGR2, vl_mask); -#endif /* RCC_PREDIV1_DIV_2_16_SUPPORT */ +#endif /* RCC_CFGR2_PREDIV1 */ /* Disable all interrupts */ LL_RCC_WriteReg(CIR, 0x00000000U); @@ -245,7 +242,7 @@ void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) * @arg @ref LL_RCC_I2S2_CLKSOURCE * @arg @ref LL_RCC_I2S3_CLKSOURCE * @retval I2S clock frequency (in Hz) - * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used */ + */ uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) { uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; @@ -264,13 +261,14 @@ uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */ case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO: default: - i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2; + i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U; break; } return i2s_frequency; } #endif /* RCC_CFGR2_I2S2SRC */ + #if defined(USB) || defined(USB_OTG_FS) /** * @brief Return USBx clock frequency @@ -278,7 +276,6 @@ uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) * @arg @ref LL_RCC_USB_CLKSOURCE * @retval USB clock frequency (in Hz) * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready - * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected */ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) { @@ -302,7 +299,7 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) default: if (LL_RCC_PLL_IsReady()) { - usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3) / 2; + usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U; } break; #endif /* RCC_CFGR_USBPRE */ @@ -319,11 +316,11 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) /* USBCLK = PLLVCO/3 = (2 x PLLCLK) / 3 */ - case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 1.5 used as USB clock source */ + case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */ default: if (LL_RCC_PLL_IsReady()) { - usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2) / 3; + usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U; } break; #endif /* RCC_CFGR_OTGFSPRE */ @@ -338,16 +335,15 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) * @param ADCxSource This parameter can be one of the following values: * @arg @ref LL_RCC_ADC_CLKSOURCE * @retval ADC clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready */ uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) { uint32_t adc_prescaler = 0U; - uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + uint32_t adc_frequency = 0U; /* Check parameter */ assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource)); - + /* Get ADC prescaler */ adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource); @@ -450,21 +446,21 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) switch (pllsource) { case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */ - pllinputfreq = HSI_VALUE / 2; + pllinputfreq = HSI_VALUE / 2U; break; case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1); + pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U); break; #if defined(RCC_PLL2_SUPPORT) case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */ - pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1); + pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U); break; #endif /* RCC_PLL2_SUPPORT */ default: - pllinputfreq = HSI_VALUE / 2; + pllinputfreq = HSI_VALUE / 2U; break; } return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator()); diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h index de79141d041..c87d5652063 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_rcc.h * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of RCC LL module. ****************************************************************************** * @attention @@ -58,54 +58,7 @@ extern "C" { /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_LL_Private_Variables RCC Private Variables - * @{ - */ - -/** - * @} - */ - /* Private constants ---------------------------------------------------------*/ -/** @defgroup RCC_LL_Private_Constants RCC Private Constants - * @{ - */ -/* Define used for feature activation */ -#if defined(RCC_CFGR2_PREDIV2) -#define RCC_PREDIV2_SUPPORT -#endif /* RCC_CFGR2_PREDIV2 */ - -#if defined(RCC_CR_PLL3ON) -#define RCC_PLLI2S_SUPPORT -#endif /* RCC_CR_PLL3ON */ - -#if defined(RCC_CR_PLL2ON) -#define RCC_PLL2_SUPPORT -#endif /* RCC_CR_PLL2ON */ - -#if defined(RCC_CFGR2_PREDIV1SRC) -#define RCC_SRC_PREDIV1_SUPPORT -#endif /* RCC_CFGR2_PREDIV1SRC */ - -#if defined(RCC_CFGR2_PREDIV1) -#define RCC_PREDIV1_DIV_2_16_SUPPORT -#endif /* RCC_CFGR2_PREDIV1 */ - - -/* Defines used for the bit position in the register and perform offsets*/ -#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */ -#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */ -#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */ -#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /*!< field position in register RCC_CR */ -#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /*!< field position in register RCC_CR */ -#define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMULL) /*!< field position in register RCC_CFGR */ -#define RCC_POSITION_I2S2SRC 17U /*!< field position in register RCC_CFGR2 */ -#define RCC_POSITION_I2S3SRC 18U /*!< field position in register RCC_CFGR2 */ - -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_Private_Macros RCC Private Macros @@ -157,19 +110,19 @@ typedef struct * @{ */ #if !defined (HSE_VALUE) -#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the HSE oscillator in Hz */ +#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSI_VALUE) -#define HSI_VALUE ((uint32_t)8000000U) /*!< Value of the HSI oscillator in Hz */ +#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ #endif /* HSI_VALUE */ #if !defined (LSE_VALUE) -#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the LSE oscillator in Hz */ +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ #endif /* LSE_VALUE */ #if !defined (LSI_VALUE) -#define LSI_VALUE ((uint32_t)32000U) /*!< Value of the LSI oscillator in Hz */ +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ /** * @} @@ -202,13 +155,13 @@ typedef struct #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ #define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */ #define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ -#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ -#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ -#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ -#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ -#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ -#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ -#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ /** * @} */ @@ -222,13 +175,13 @@ typedef struct #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ -#define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */ -#define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */ +#define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */ +#define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */ /** * @} */ -#if defined(RCC_PREDIV2_SUPPORT) +#if defined(RCC_CFGR2_PREDIV2) /** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor * @{ */ @@ -252,7 +205,7 @@ typedef struct * @} */ -#endif /* RCC_PREDIV2_SUPPORT */ +#endif /* RCC_CFGR2_PREDIV2 */ /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch * @{ @@ -332,7 +285,7 @@ typedef struct #define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCOSEL_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ #endif /* RCC_CFGR_MCOSEL_EXT_HSE */ #if defined(RCC_CFGR_MCOSEL_PLL3CLK) -#define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCOSEL_PLL3CLK /*!< PLLI2S clock selected as MCO source */ +#define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCOSEL_PLL3CLK /*!< PLLI2S clock selected as MCO source */ #endif /* RCC_CFGR_MCOSEL_PLL3CLK */ /** * @} @@ -342,8 +295,8 @@ typedef struct /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency * @{ */ -#define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /*!< No clock enabled for the peripheral */ -#define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ /** * @} */ @@ -353,14 +306,13 @@ typedef struct /** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection * @{ */ -#define LL_RCC_I2S2_CLKSOURCE_SYSCLK (uint32_t)(RCC_CFGR2_I2S2SRC | (0x00000000 >> 16)) /*!< System clock (SYSCLK) selected as I2S2 clock entry */ -#define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */ -#define LL_RCC_I2S3_CLKSOURCE_SYSCLK (uint32_t)(RCC_CFGR2_I2S3SRC | (0x00000000 >> 16)) /*!< System clock (SYSCLK) selected as I2S3 clock entry */ -#define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */ +#define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /*!< System clock (SYSCLK) selected as I2S2 clock entry */ +#define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */ +#define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /*!< System clock (SYSCLK) selected as I2S3 clock entry */ +#define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */ /** * @} */ - #endif /* RCC_CFGR2_I2S2SRC */ #if defined(USB_OTG_FS) || defined(USB) @@ -368,17 +320,16 @@ typedef struct * @{ */ #if defined(RCC_CFGR_USBPRE) -#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */ -#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 ((uint32_t)0x00000000) /*!< PLL clock is divided by 1.5 */ -#endif /*RCC_CFGR_USBPRE*/ -#if defined(RCC_CFGR_OTGFSPRE) -#define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */ -#define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 ((uint32_t)0x00000000) /*!< PLL clock is divided by 3 */ +#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */ +#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */ +#endif /*RCC_CFGR_USBPRE*/ +#if defined(RCC_CFGR_OTGFSPRE) +#define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */ +#define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */ #endif /*RCC_CFGR_OTGFSPRE*/ /** * @} */ - #endif /* USB_OTG_FS || USB */ /** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection @@ -408,7 +359,7 @@ typedef struct /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source * @{ */ -#define LL_RCC_USB_CLKSOURCE ((uint32_t)0x00400000) /*!< USB Clock source selection */ +#define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */ /** * @} */ @@ -426,10 +377,10 @@ typedef struct /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection * @{ */ -#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */ /** * @} */ @@ -467,14 +418,14 @@ typedef struct /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE * @{ */ -#define LL_RCC_PLLSOURCE_HSI_DIV_2 ((uint32_t)0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */ -#if defined(RCC_SRC_PREDIV1_SUPPORT) -#define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */ -#endif /*RCC_SRC_PREDIV1_SUPPORT*/ +#define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */ +#if defined(RCC_CFGR2_PREDIV1SRC) +#define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */ +#endif /*RCC_CFGR2_PREDIV1SRC*/ -#define LL_RCC_PLLSOURCE_HSE_DIV_1 RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ -#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT) +#define LL_RCC_PLLSOURCE_HSE_DIV_1 RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ +#if defined(RCC_CFGR2_PREDIV1) #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */ @@ -490,26 +441,26 @@ typedef struct #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */ #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */ -#if defined(RCC_SRC_PREDIV1_SUPPORT) -#define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/2 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/3 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/4 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/5 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/6 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/7 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/8 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/9 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/10 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/11 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/12 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/13 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/14 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/15 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4) /*!< PLL2/16 clock selected as PLL entry clock source */ -#endif /*RCC_SRC_PREDIV1_SUPPORT*/ +#if defined(RCC_CFGR2_PREDIV1SRC) +#define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/2 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/3 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/4 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/5 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/6 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/7 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/8 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/9 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/10 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/11 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/12 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/13 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/14 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/15 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/16 clock selected as PLL entry clock source */ +#endif /*RCC_CFGR2_PREDIV1SRC*/ #else #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */ -#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/ +#endif /*RCC_CFGR2_PREDIV1*/ /** * @} */ @@ -517,7 +468,7 @@ typedef struct /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor * @{ */ -#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT) +#if defined(RCC_CFGR2_PREDIV1) #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */ #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */ #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */ @@ -535,9 +486,9 @@ typedef struct #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */ #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */ #else -#define LL_RCC_PREDIV_DIV_1 ((uint32_t)0x00000000U) /*!< HSE divider clock clock not divided */ -#define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */ -#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/ +#define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock not divided */ +#define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */ +#endif /*RCC_CFGR2_PREDIV1*/ /** * @} */ @@ -632,7 +583,7 @@ typedef struct */ #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \ (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \ - ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_POSITION_PLLMUL) + 2U)) :\ + ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\ (((__INPUTFREQ__) * 13U) / 2U)) #else @@ -658,7 +609,7 @@ typedef struct * @arg @ref LL_RCC_PLL_MUL_16 * @retval PLL clock frequency (in Hz) */ -#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_POSITION_PLLMUL) + 2U)) +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U)) #endif /* RCC_CFGR_PLLMULL6_5 */ #if defined(RCC_PLLI2S_SUPPORT) @@ -695,7 +646,7 @@ typedef struct * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 * @retval PLLI2S clock frequency (in Hz) */ -#define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2U)) / (((__PLLI2SDIV__) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1U)) +#define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U)) #endif /* RCC_PLLI2S_SUPPORT */ #if defined(RCC_PLL2_SUPPORT) @@ -732,7 +683,7 @@ typedef struct * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16 * @retval PLL2 clock frequency (in Hz) */ -#define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2U)) / (((__PLL2DIV__) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1U)) +#define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U)) #endif /* RCC_PLL2_SUPPORT */ /** @@ -752,7 +703,7 @@ typedef struct * @arg @ref LL_RCC_SYSCLK_DIV_512 * @retval HCLK clock frequency (in Hz) */ -#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]) +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) /** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) @@ -767,7 +718,7 @@ typedef struct * @arg @ref LL_RCC_APB1_DIV_16 * @retval PCLK1 clock frequency (in Hz) */ -#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1]) +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) /** * @brief Helper macro to calculate the PCLK2 frequency (ABP2) @@ -782,7 +733,7 @@ typedef struct * @arg @ref LL_RCC_APB2_DIV_16 * @retval PCLK2 clock frequency (in Hz) */ -#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2]) +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) /** * @} @@ -861,7 +812,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); } -#if defined(RCC_PREDIV2_SUPPORT) +#if defined(RCC_CFGR2_PREDIV2) /** * @brief Get PREDIV2 division factor * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2 @@ -887,7 +838,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void) { return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)); } -#endif /* RCC_PREDIV2_SUPPORT */ +#endif /* RCC_CFGR2_PREDIV2 */ /** * @} @@ -936,7 +887,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) */ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) { - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_POSITION_HSICAL); + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); } /** @@ -950,7 +901,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) */ __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) { - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_POSITION_HSITRIM); + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); } /** @@ -960,7 +911,7 @@ __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) */ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) { - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_POSITION_HSITRIM); + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); } /** @@ -1306,7 +1257,7 @@ __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource) */ __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) { - return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16 | I2Sx); + return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx); } #endif /* RCC_CFGR2_I2S2SRC */ @@ -1542,14 +1493,14 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMu { MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL, (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul); -#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT) -#if defined(RCC_SRC_PREDIV1_SUPPORT) +#if defined(RCC_CFGR2_PREDIV1) +#if defined(RCC_CFGR2_PREDIV1SRC) MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC), - (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4)) >> 4)); + (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U)); #else MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1)); -#endif /*RCC_SRC_PREDIV1_SUPPORT*/ -#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/ +#endif /*RCC_CFGR2_PREDIV1SRC*/ +#endif /*RCC_CFGR2_PREDIV1*/ } /** @@ -1565,11 +1516,13 @@ __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMu */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) { -#if defined(RCC_SRC_PREDIV1_SUPPORT) - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC) | (READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4)); +#if defined(RCC_CFGR2_PREDIV1SRC) + register uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC); + register uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); + return (uint32_t)(pllsrc | predivsrc); #else return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); -#endif /*RCC_SRC_PREDIV1_SUPPORT*/ +#endif /*RCC_CFGR2_PREDIV1SRC*/ } /** @@ -1627,11 +1580,11 @@ __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) */ __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void) { -#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT) +#if defined(RCC_CFGR2_PREDIV1) return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)); #else return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)); -#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/ +#endif /*RCC_CFGR2_PREDIV1*/ } /** @@ -2321,7 +2274,7 @@ ErrorStatus LL_RCC_DeInit(void); * @{ */ void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); -#if defined(RCC_CFGR2_I2S2SRC) +#if defined(RCC_CFGR2_I2S2SRC) uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); #endif /* RCC_CFGR2_I2S2SRC */ #if defined(USB_OTG_FS) || defined(USB) diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rtc.c new file mode 100644 index 00000000000..48510d246e3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rtc.c @@ -0,0 +1,558 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_rtc.c + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief RTC LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_rtc.h" +#include "stm32f1xx_ll_cortex.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @addtogroup RTC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Constants + * @{ + */ +/* Default values used for prescaler */ +#define RTC_ASYNCH_PRESC_DEFAULT 0x00007FFFU + +/* Values used for timeout */ +#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */ +#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Macros + * @{ + */ + +#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0xFFFFFU) + +#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \ + || ((__VALUE__) == LL_RTC_FORMAT_BCD)) + +#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U) +#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U) +#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U) +#define IS_LL_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_NONE) || \ + ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_RTCCLOCK) || \ + ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_ALARM) || \ + ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_SECOND)) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_LL_EF_Init + * @{ + */ + +/** + * @brief De-Initializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * registers. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are de-initialized + * - ERROR: RTC registers are not de-initialized + */ +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) +{ + ErrorStatus status = ERROR; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + LL_RTC_WriteReg(RTCx,CNTL, 0x0000); + LL_RTC_WriteReg(RTCx,CNTH, 0x0000); + LL_RTC_WriteReg(RTCx,PRLH, 0x0000); + LL_RTC_WriteReg(RTCx,PRLL, 0x8000); + LL_RTC_WriteReg(RTCx,CRH, 0x0000); + LL_RTC_WriteReg(RTCx,CRL, 0x0020); + + /* Reset Tamper and alternate functions configuration register */ + LL_RTC_WriteReg(BKP,RTCCR, 0x00000000U); + LL_RTC_WriteReg(BKP,CR, 0x00000000U); + LL_RTC_WriteReg(BKP,CSR, 0x00000000U); + + /* Exit Initialization Mode */ + if(LL_RTC_ExitInitMode(RTCx) == ERROR) + { + return ERROR; + } + + /* Wait till the RTC RSF flag is set */ + status = LL_RTC_WaitForSynchro(RTCx); + + /* Clear RSF Flag */ + LL_RTC_ClearFlag_RS(RTCx); + } + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTCx RTC Instance + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @note the user should call LL_RTC_StructInit() or the structure of Prescaler + * need to be initialized before RTC init() + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler)); + assert_param(IS_LL_RTC_CALIB_OUTPUT(RTC_InitStruct->OutPutSource)); + /* Waiting for synchro */ + if(LL_RTC_WaitForSynchro(RTCx) != ERROR) + { + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Clear Flag Bits */ + LL_RTC_ClearFlag_ALR(RTCx); + LL_RTC_ClearFlag_OW(RTCx); + LL_RTC_ClearFlag_SEC(RTCx); + + if(RTC_InitStruct->OutPutSource != LL_RTC_CALIB_OUTPUT_NONE) + { + /* Disable the selected Tamper Pin */ + LL_RTC_TAMPER_Disable(BKP); + } + /* Set the signal which will be routed to RTC Tamper Pin */ + LL_RTC_SetOutputSource(BKP, RTC_InitStruct->OutPutSource); + + /* Configure Synchronous and Asynchronous prescaler factor */ + LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler); + + /* Exit Initialization Mode */ + LL_RTC_ExitInitMode(RTCx); + + status = SUCCESS; + } + } + return status; +} + +/** + * @brief Set each @ref LL_RTC_InitTypeDef field to default value. + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct) +{ + /* Set RTC_InitStruct fields to default values */ + RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT; + RTC_InitStruct->OutPutSource = LL_RTC_CALIB_OUTPUT_NONE; +} + +/** + * @brief Set the RTC current time. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * @note The user should call LL_RTC_TIME_StructInit() or the structure + * of time need to be initialized before time init() + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + ErrorStatus status = ERROR; + uint32_t counter_time = 0U; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours)); + assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds)); + } + else + { + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))); + } + + /* Enter Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + counter_time = (uint32_t)(((uint32_t)RTC_TimeStruct->Hours * 3600U) + \ + ((uint32_t)RTC_TimeStruct->Minutes * 60U) + \ + ((uint32_t)RTC_TimeStruct->Seconds)); + LL_RTC_TIME_Set(RTCx, counter_time); + } + else + { + counter_time = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)) * 3600U) + \ + ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)) * 60U) + \ + ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)))); + LL_RTC_TIME_Set(RTCx, counter_time); + } + status = SUCCESS; + } + /* Exit Initialization mode */ + LL_RTC_ExitInitMode(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec). + * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->Hours = 0U; + RTC_TimeStruct->Minutes = 0U; + RTC_TimeStruct->Seconds = 0U; +} + +/** + * @brief Set the RTC Alarm. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @note the user should call LL_RTC_ALARM_StructInit() or the structure + * of Alarm need to be initialized before Alarm init() + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ALARM registers are configured + * - ERROR: ALARM registers are not configured + */ +ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + ErrorStatus status = ERROR; + uint32_t counter_alarm = 0U; + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + } + else + { + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + } + + /* Enter Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + counter_alarm = (uint32_t)(((uint32_t)RTC_AlarmStruct->AlarmTime.Hours * 3600U) + \ + ((uint32_t)RTC_AlarmStruct->AlarmTime.Minutes * 60U) + \ + ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds)); + LL_RTC_ALARM_Set(RTCx, counter_alarm); + } + else + { + counter_alarm = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)) * 3600U) + \ + ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)) * 60U) + \ + ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)))); + LL_RTC_ALARM_Set(RTCx, counter_alarm); + } + status = SUCCESS; + } + /* Exit Initialization mode */ + LL_RTC_ExitInitMode(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARM field to default value (Time = 00h:00mn:00sec / + * Day = 1st day of the month/Mask = all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.Hours = 0U; + RTC_AlarmStruct->AlarmTime.Minutes = 0U; + RTC_AlarmStruct->AlarmTime.Seconds = 0U; +} + +/** + * @brief Enters the RTC Initialization mode. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp = 0U; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); + while ((timeout != 0U) && (tmp != 1U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout --; + } + tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Exit the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC exited from in Init mode + * - ERROR: Not applicable + */ +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp = 0U; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable initialization mode */ + LL_RTC_EnableWriteProtection(RTCx); + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); + while ((timeout != 0U) && (tmp != 1U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout --; + } + tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + return status; +} + +/** + * @brief Set the Time Counter + * @param RTCx RTC Instance + * @param TimeCounter this value can be from 0 to 0xFFFFFFFF + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Counter register configured + * - ERROR: Not applicable + */ +ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter) +{ + ErrorStatus status = ERROR; + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Enter Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + LL_RTC_TIME_Set(RTCx, TimeCounter); + status = SUCCESS; + } + /* Exit Initialization mode */ + LL_RTC_ExitInitMode(RTCx); + + return status; +} + +/** + * @brief Set Alarm Counter. + * @param RTCx RTC Instance + * @param AlarmCounter this value can be from 0 to 0xFFFFFFFF + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC exited from in Init mode + * - ERROR: Not applicable + */ +ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter) +{ + ErrorStatus status = ERROR; + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Enter Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + LL_RTC_ALARM_Set(RTCx, AlarmCounter); + status = SUCCESS; + } + /* Exit Initialization mode */ + LL_RTC_ExitInitMode(RTCx); + + return status; +} + +/** + * @brief Waits until the RTC registers are synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp = 0U; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Clear RSF flag */ + LL_RTC_ClearFlag_RS(RTCx); + + /* Wait the registers to be synchronised */ + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + while ((timeout != 0U) && (tmp != 0U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout--; + } + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + + return (status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rtc.h new file mode 100644 index 00000000000..4d157120be2 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rtc.h @@ -0,0 +1,1021 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_rtc.h + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief Header file of RTC LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_RTC_H +#define __STM32F1xx_LL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @defgroup RTC_LL RTC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_Private_Macros RTC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetAsynchPrescaler(). */ + + uint32_t OutPutSource; /*!< Specifies which signal will be routed to the RTC Tamper pin. + This parameter can be a value of @ref LL_RTC_Output_Source + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetOutputSource(). */ + +} LL_RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hours. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ +} LL_RTC_TimeTypeDef; + + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + +} LL_RTC_AlarmTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants + * @{ + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EC_FORMAT FORMAT + * @{ + */ +#define LL_RTC_FORMAT_BIN (0x000000000U) /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD (0x000000001U) /*!< BCD data format */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RTC_LL_EC_BKP BACKUP + * @{ + */ +#if RTC_BKP_NUMBER > 0 +#define LL_RTC_BKP_DR1 (0x00000001U) +#define LL_RTC_BKP_DR2 (0x00000002U) +#define LL_RTC_BKP_DR3 (0x00000003U) +#define LL_RTC_BKP_DR4 (0x00000004U) +#define LL_RTC_BKP_DR5 (0x00000005U) +#define LL_RTC_BKP_DR6 (0x00000006U) +#define LL_RTC_BKP_DR7 (0x00000007U) +#define LL_RTC_BKP_DR8 (0x00000008U) +#define LL_RTC_BKP_DR9 (0x00000009U) +#define LL_RTC_BKP_DR10 (0x0000000AU) +#endif /* RTC_BKP_NUMBER > 0 */ +#if RTC_BKP_NUMBER > 10 +#define LL_RTC_BKP_DR11 (0x0000000BU) +#define LL_RTC_BKP_DR12 (0x0000000CU) +#define LL_RTC_BKP_DR13 (0x0000000DU) +#define LL_RTC_BKP_DR14 (0x0000000EU) +#define LL_RTC_BKP_DR15 (0x0000000FU) +#define LL_RTC_BKP_DR16 (0x00000010U) +#define LL_RTC_BKP_DR17 (0x00000011U) +#define LL_RTC_BKP_DR18 (0x00000012U) +#define LL_RTC_BKP_DR19 (0x00000013U) +#define LL_RTC_BKP_DR20 (0x00000014U) +#define LL_RTC_BKP_DR21 (0x00000015U) +#define LL_RTC_BKP_DR22 (0x00000016U) +#define LL_RTC_BKP_DR23 (0x00000017U) +#define LL_RTC_BKP_DR24 (0x00000018U) +#define LL_RTC_BKP_DR25 (0x00000019U) +#define LL_RTC_BKP_DR26 (0x0000001AU) +#define LL_RTC_BKP_DR27 (0x0000001BU) +#define LL_RTC_BKP_DR28 (0x0000001CU) +#define LL_RTC_BKP_DR29 (0x0000001DU) +#define LL_RTC_BKP_DR30 (0x0000001EU) +#define LL_RTC_BKP_DR31 (0x0000001FU) +#define LL_RTC_BKP_DR32 (0x00000020U) +#define LL_RTC_BKP_DR33 (0x00000021U) +#define LL_RTC_BKP_DR34 (0x00000022U) +#define LL_RTC_BKP_DR35 (0x00000023U) +#define LL_RTC_BKP_DR36 (0x00000024U) +#define LL_RTC_BKP_DR37 (0x00000025U) +#define LL_RTC_BKP_DR38 (0x00000026U) +#define LL_RTC_BKP_DR39 (0x00000027U) +#define LL_RTC_BKP_DR40 (0x00000028U) +#define LL_RTC_BKP_DR41 (0x00000029U) +#define LL_RTC_BKP_DR42 (0x0000002AU) +#endif /* RTC_BKP_NUMBER > 10 */ + +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPLEVEL Tamper Active Level + * @{ + */ +#define LL_RTC_TAMPER_ACTIVELEVEL_LOW BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ +#define LL_RTC_TAMPER_ACTIVELEVEL_HIGH (0x00000000U) /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */ + +/** + * @} + */ + +/** @defgroup LL_RTC_Output_Source Clock Source to output on the Tamper Pin + * @{ + */ +#define LL_RTC_CALIB_OUTPUT_NONE (0x00000000U) /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_RTCCLOCK BKP_RTCCR_CCO /*!< Calibration output is RTC Clock with a frequency divided by 64 on the TAMPER Pin */ +#define LL_RTC_CALIB_OUTPUT_ALARM BKP_RTCCR_ASOE /*!< Calibration output is Alarm pulse signal on the TAMPER pin */ +#define LL_RTC_CALIB_OUTPUT_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Calibration output is Second pulse signal on the TAMPER pin*/ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Convert Convert helper Macros + * @{ + */ + +/** + * @brief Helper macro to convert a value from 2 digit decimal format to BCD format + * @param __VALUE__ Byte to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U)) + +/** + * @brief Helper macro to convert a value from BCD format to 2 digit decimal format + * @param __VALUE__ BCD value to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Set Asynchronous prescaler factor + * @rmtoll PRLH PRL LL_RTC_SetAsynchPrescaler\n + * @rmtoll PRLL PRL LL_RTC_SetAsynchPrescaler\n + * @param RTCx RTC Instance + * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0xFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) +{ + MODIFY_REG(RTCx->PRLH, RTC_PRLH_PRL, (AsynchPrescaler >> 16)); + MODIFY_REG(RTCx->PRLL, RTC_PRLL_PRL, (AsynchPrescaler & RTC_PRLL_PRL)); +} + +/** + * @brief Get Asynchronous prescaler factor + * @rmtoll DIVH DIV LL_RTC_GetDivider\n + * @rmtoll DIVL DIV LL_RTC_GetDivider\n + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_GetDivider(RTC_TypeDef *RTCx) +{ + register uint16_t Highprescaler = 0 , Lowprescaler = 0; + Highprescaler = READ_REG(RTCx->DIVH & RTC_DIVH_RTC_DIV); + Lowprescaler = READ_REG(RTCx->DIVL & RTC_DIVL_RTC_DIV); + + return (((uint32_t) Highprescaler << 16U) | Lowprescaler); +} + +/** + * @brief Set Output Source + * @rmtoll RTCCR CCO LL_RTC_SetOutputSource + * @rmtoll RTCCR ASOE LL_RTC_SetOutputSource + * @rmtoll RTCCR ASOS LL_RTC_SetOutputSource + * @param BKPx BKP Instance + * @param OutputSource This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK + * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM + * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetOutputSource(BKP_TypeDef *BKPx, uint32_t OutputSource) +{ + MODIFY_REG(BKPx->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), OutputSource); +} + +/** + * @brief Get Output Source + * @rmtoll RTCCR CCO LL_RTC_GetOutPutSource + * @rmtoll RTCCR ASOE LL_RTC_GetOutPutSource + * @rmtoll RTCCR ASOS LL_RTC_GetOutPutSource + * @param BKPx BKP Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK + * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM + * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND + */ +__STATIC_INLINE uint32_t LL_RTC_GetOutPutSource(BKP_TypeDef *BKPx) +{ + return (uint32_t)(READ_BIT(BKPx->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS))); +} + +/** + * @brief Enable the write protection for RTC registers. + * @rmtoll CRL CNF LL_RTC_EnableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_CNF); +} + +/** + * @brief Disable the write protection for RTC registers. + * @rmtoll CRL RTC_CRL_CNF LL_RTC_DisableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CRL, RTC_CRL_CNF); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Time Time + * @{ + */ + +/** + * @brief Set time counter in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function) + * @rmtoll CNTH CNT LL_RTC_TIME_Set\n + * CNTL CNT LL_RTC_TIME_Set\n + * @param RTCx RTC Instance + * @param TimeCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Set(RTC_TypeDef *RTCx, uint32_t TimeCounter) +{ + /* Set RTC COUNTER MSB word */ + WRITE_REG(RTCx->CNTH, (TimeCounter >> 16U)); + /* Set RTC COUNTER LSB word */ + WRITE_REG(RTCx->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); +} + +/** + * @brief Get time counter in BCD format + * @rmtoll CNTH CNT LL_RTC_TIME_Get\n + * CNTL CNT LL_RTC_TIME_Get\n + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +{ + register uint16_t high = 0, low = 0; + + high = READ_REG(RTCx->CNTH & RTC_CNTH_RTC_CNT); + low = READ_REG(RTCx->CNTL & RTC_CNTL_RTC_CNT); + return ((uint32_t)(((uint32_t) high << 16U) | low)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARM ALARM + * @{ + */ + +/** + * @brief Set Alarm Counter + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll ALRH ALR LL_RTC_ALARM_Set\n + * @rmtoll ALRL ALR LL_RTC_ALARM_Set\n + * @param RTCx RTC Instance + * @param AlarmCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALARM_Set(RTC_TypeDef *RTCx, uint32_t AlarmCounter) +{ + /* Set RTC COUNTER MSB word */ + WRITE_REG(RTCx->ALRH, (AlarmCounter >> 16)); + /* Set RTC COUNTER LSB word */ + WRITE_REG(RTCx->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR)); +} + +/** + * @brief Get Alarm Counter + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll ALRH ALR LL_RTC_ALARM_Get\n + * @rmtoll ALRL ALR LL_RTC_ALARM_Get\n + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE uint32_t LL_RTC_ALARM_Get(RTC_TypeDef *RTCx) +{ + register uint16_t high = 0, low = 0; + + high = READ_REG(RTCx->ALRH & RTC_ALRH_RTC_ALR); + low = READ_REG(RTCx->ALRL & RTC_ALRL_RTC_ALR); + + return (((uint32_t) high << 16U) | low); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Tamper Tamper + * @{ + */ + +/** + * @brief Enable RTC_TAMPx input detection + * @rmtoll CR TPE LL_RTC_TAMPER_Enable\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Enable(BKP_TypeDef *BKPx) +{ + SET_BIT(BKPx->CR, BKP_CR_TPE); +} + +/** + * @brief Disable RTC_TAMPx Tamper + * @rmtoll CR TPE LL_RTC_TAMPER_Disable\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Disable(BKP_TypeDef *BKPx) +{ + CLEAR_BIT(BKP->CR, BKP_CR_TPE); +} + +/** + * @brief Enable Active level for Tamper input + * @rmtoll CR TPAL LL_RTC_TAMPER_SetActiveLevel\n + * @param BKPx BKP Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_LOW + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetActiveLevel(BKP_TypeDef *BKPx, uint32_t Tamper) +{ + MODIFY_REG(BKPx->CR, BKP_CR_TPAL, Tamper); +} + +/** + * @brief Disable Active level for Tamper input + * @rmtoll CR TPAL LL_RTC_TAMPER_SetActiveLevel\n + * @retval None + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetActiveLevel(BKP_TypeDef *BKPx) +{ + return (uint32_t)(READ_BIT(BKPx->CR, BKP_CR_TPAL)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers + * @{ + */ + +/** + * @brief Writes a data in a specified RTC Backup data register. + * @rmtoll BKPDR DR LL_RTC_BKP_SetRegister + * @param BKPx BKP Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 (*) + * @arg @ref LL_RTC_BKP_DR12 (*) + * @arg @ref LL_RTC_BKP_DR13 (*) + * @arg @ref LL_RTC_BKP_DR14 (*) + * @arg @ref LL_RTC_BKP_DR15 (*) + * @arg @ref LL_RTC_BKP_DR16 (*) + * @arg @ref LL_RTC_BKP_DR17 (*) + * @arg @ref LL_RTC_BKP_DR18 (*) + * @arg @ref LL_RTC_BKP_DR19 (*) + * @arg @ref LL_RTC_BKP_DR20 (*) + * @arg @ref LL_RTC_BKP_DR21 (*) + * @arg @ref LL_RTC_BKP_DR22 (*) + * @arg @ref LL_RTC_BKP_DR23 (*) + * @arg @ref LL_RTC_BKP_DR24 (*) + * @arg @ref LL_RTC_BKP_DR25 (*) + * @arg @ref LL_RTC_BKP_DR26 (*) + * @arg @ref LL_RTC_BKP_DR27 (*) + * @arg @ref LL_RTC_BKP_DR28 (*) + * @arg @ref LL_RTC_BKP_DR29 (*) + * @arg @ref LL_RTC_BKP_DR30 (*) + * @arg @ref LL_RTC_BKP_DR31 (*) + * @arg @ref LL_RTC_BKP_DR32 (*) + * @arg @ref LL_RTC_BKP_DR33 (*) + * @arg @ref LL_RTC_BKP_DR34 (*) + * @arg @ref LL_RTC_BKP_DR35 (*) + * @arg @ref LL_RTC_BKP_DR36 (*) + * @arg @ref LL_RTC_BKP_DR37 (*) + * @arg @ref LL_RTC_BKP_DR38 (*) + * @arg @ref LL_RTC_BKP_DR39 (*) + * @arg @ref LL_RTC_BKP_DR40 (*) + * @arg @ref LL_RTC_BKP_DR41 (*) + * @arg @ref LL_RTC_BKP_DR42 (*) + * (*) value not defined in all devices. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_BKP_SetRegister(BKP_TypeDef *BKPx, uint32_t BackupRegister, uint32_t Data) +{ + register uint32_t tmp = 0U; + + tmp = (uint32_t)BKP_BASE; + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @rmtoll BKPDR DR LL_RTC_BKP_GetRegister + * @param BKPx BKP Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg @ref LL_RTC_BKP_DR5 + * @arg @ref LL_RTC_BKP_DR6 + * @arg @ref LL_RTC_BKP_DR7 + * @arg @ref LL_RTC_BKP_DR8 + * @arg @ref LL_RTC_BKP_DR9 + * @arg @ref LL_RTC_BKP_DR10 + * @arg @ref LL_RTC_BKP_DR11 (*) + * @arg @ref LL_RTC_BKP_DR12 (*) + * @arg @ref LL_RTC_BKP_DR13 (*) + * @arg @ref LL_RTC_BKP_DR14 (*) + * @arg @ref LL_RTC_BKP_DR15 (*) + * @arg @ref LL_RTC_BKP_DR16 (*) + * @arg @ref LL_RTC_BKP_DR17 (*) + * @arg @ref LL_RTC_BKP_DR18 (*) + * @arg @ref LL_RTC_BKP_DR19 (*) + * @arg @ref LL_RTC_BKP_DR20 (*) + * @arg @ref LL_RTC_BKP_DR21 (*) + * @arg @ref LL_RTC_BKP_DR22 (*) + * @arg @ref LL_RTC_BKP_DR23 (*) + * @arg @ref LL_RTC_BKP_DR24 (*) + * @arg @ref LL_RTC_BKP_DR25 (*) + * @arg @ref LL_RTC_BKP_DR26 (*) + * @arg @ref LL_RTC_BKP_DR27 (*) + * @arg @ref LL_RTC_BKP_DR28 (*) + * @arg @ref LL_RTC_BKP_DR29 (*) + * @arg @ref LL_RTC_BKP_DR30 (*) + * @arg @ref LL_RTC_BKP_DR31 (*) + * @arg @ref LL_RTC_BKP_DR32 (*) + * @arg @ref LL_RTC_BKP_DR33 (*) + * @arg @ref LL_RTC_BKP_DR34 (*) + * @arg @ref LL_RTC_BKP_DR35 (*) + * @arg @ref LL_RTC_BKP_DR36 (*) + * @arg @ref LL_RTC_BKP_DR37 (*) + * @arg @ref LL_RTC_BKP_DR38 (*) + * @arg @ref LL_RTC_BKP_DR39 (*) + * @arg @ref LL_RTC_BKP_DR40 (*) + * @arg @ref LL_RTC_BKP_DR41 (*) + * @arg @ref LL_RTC_BKP_DR42 (*) + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(BKP_TypeDef *BKPx, uint32_t BackupRegister) +{ + register uint32_t tmp = 0U; + + tmp = (uint32_t)BKP_BASE; + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return ((*(__IO uint32_t *)tmp) & BKP_DR1_D); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Calibration Calibration + * @{ + */ + +/** + * @brief Set the coarse digital calibration + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function) + * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n + * @param BKPx RTC Instance + * @param Value value of coarse calibration expressed in ppm (coded on 5 bits) + * @note This Calibration value should be between 0 and 121 when using positive sign with a 4-ppm step. + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetCoarseDigital(BKP_TypeDef* BKPx, uint32_t Value) +{ + MODIFY_REG(BKPx->RTCCR,BKP_RTCCR_CAL, Value); +} + +/** + * @brief Get the coarse digital calibration value + * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n + * @param BKPx BKP Instance + * @retval value of coarse calibration expressed in ppm (coded on 5 bits) + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigital(BKP_TypeDef *BKPx) +{ + return (uint32_t)(READ_BIT(BKPx->RTCCR, BKP_RTCCR_CAL)); +} +/** + * @} + */ + +/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get RTC_TAMPI Interruption detection flag + * @rmtoll CSR TIF LL_RTC_IsActiveFlag_TAMPI + * @param BKPx BKP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMPI(BKP_TypeDef *BKPx) +{ + return (READ_BIT(BKPx->CSR, BKP_CSR_TIF) == (BKP_CSR_TIF)); +} + +/** + * @brief Clear RTC_TAMP Interruption detection flag + * @rmtoll CSR CTI LL_RTC_ClearFlag_TAMPI + * @param BKPx BKP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMPI(BKP_TypeDef *BKPx) +{ + SET_BIT(BKPx->CSR, BKP_CSR_CTI); +} + +/** + * @brief Get RTC_TAMPE Event detection flag + * @rmtoll CSR TEF LL_RTC_IsActiveFlag_TAMPE + * @param BKPx BKP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMPE(BKP_TypeDef *BKPx) +{ + return (READ_BIT(BKPx->CSR, BKP_CSR_TEF) == (BKP_CSR_TEF)); +} + +/** + * @brief Clear RTC_TAMPE Even detection flag + * @rmtoll CSR CTE LL_RTC_ClearFlag_TAMPE + * @param BKPx BKP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMPE(BKP_TypeDef *BKPx) +{ + SET_BIT(BKPx->CSR, BKP_CSR_CTE); +} + +/** + * @brief Get Alarm flag + * @rmtoll CRL ALRF LL_RTC_IsActiveFlag_ALR + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALR(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_ALRF) == (RTC_CRL_ALRF)); +} + +/** + * @brief Clear Alarm flag + * @rmtoll CRL ALRF LL_RTC_ClearFlag_ALR + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALR(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_ALRF); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll CRL RSF LL_RTC_IsActiveFlag_RS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_RSF) == (RTC_CRL_RSF)); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll CRL RSF LL_RTC_ClearFlag_RS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_RSF); +} + +/** + * @brief Get Registers OverFlow flag + * @rmtoll CRL OWF LL_RTC_IsActiveFlag_OW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_OW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_OWF) == (RTC_CRL_OWF)); +} + +/** + * @brief Clear Registers OverFlow flag + * @rmtoll CRL OWF LL_RTC_ClearFlag_OW + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_OW(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_OWF); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll CRL SECF LL_RTC_IsActiveFlag_SEC + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SEC(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_SECF) == (RTC_CRL_SECF)); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll CRL SECF LL_RTC_ClearFlag_SEC + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_SEC(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_SECF); +} + +/** + * @brief Get RTC Operation OFF status flag + * @rmtoll CRL RTOFF LL_RTC_IsActiveFlag_RTOF + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RTOF(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_RTOFF) == (RTC_CRL_RTOFF)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Alarm interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH ALRIE LL_RTC_EnableIT_ALR + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALR(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CRH, RTC_CRH_ALRIE); +} + +/** + * @brief Disable Alarm interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH ALRIE LL_RTC_DisableIT_ALR + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALR(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRH, RTC_CRH_ALRIE); +} + +/** + * @brief Check if Alarm interrupt is enabled or not + * @rmtoll CRH ALRIE LL_RTC_IsEnabledIT_ALR + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALR(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRH, RTC_CRH_ALRIE) == (RTC_CRH_ALRIE)); +} + +/** + * @brief Enable Second Interrupt interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH SECIE LL_RTC_EnableIT_SEC + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_SEC(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CRH, RTC_CRH_SECIE); +} + +/** + * @brief Disable Second interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH SECIE LL_RTC_DisableIT_SEC + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_SEC(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRH, RTC_CRH_SECIE); +} + +/** + * @brief Check if Second interrupt is enabled or not + * @rmtoll CRH SECIE LL_RTC_IsEnabledIT_SEC + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SEC(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRH, RTC_CRH_SECIE) == (RTC_CRH_SECIE)); +} + +/** + * @brief Enable OverFlow interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH OWIE LL_RTC_EnableIT_OW + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_OW(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CRH, RTC_CRH_OWIE); +} + +/** + * @brief Disable OverFlow interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH OWIE LL_RTC_DisableIT_OW + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_OW(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRH, RTC_CRH_OWIE); +} + +/** + * @brief Check if OverFlow interrupt is enabled or not + * @rmtoll CRH OWIE LL_RTC_IsEnabledIT_OW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_OW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRH, RTC_CRH_OWIE) == (RTC_CRH_OWIE)); +} + +/** + * @brief Enable Tamper interrupt + * @rmtoll CSR TPIE LL_RTC_EnableIT_TAMP + * @param BKPx BKP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP(BKP_TypeDef *BKPx) +{ + SET_BIT(BKPx->CSR,BKP_CSR_TPIE); +} + +/** + * @brief Disable Tamper interrupt + * @rmtoll CSR TPIE LL_RTC_EnableIT_TAMP + * @param BKPx BKP Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP(BKP_TypeDef *BKPx) +{ + CLEAR_BIT(BKPx->CSR,BKP_CSR_TPIE); +} + +/** + * @brief Check if all the TAMPER interrupts are enabled or not + * @rmtoll CSR TPIE LL_RTC_IsEnabledIT_TAMP + * @param BKPx BKP Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(BKP_TypeDef *BKPx) +{ + return (READ_BIT(BKPx->CSR,BKP_CSR_TPIE) == BKP_CSR_TPIE); +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct); +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct); +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct); +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct); +ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter); +ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_RTC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.c index d3eccbf236b..f8d04bc1171 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.c @@ -2,12 +2,12 @@ ****************************************************************************** * @file stm32f1xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 - * @brief SDMMC Low Layer HAL module driver. + * @version V1.1.0 + * @date 14-April-2017 + * @brief SDIO Low Layer HAL module driver. * * This file provides firmware functions to manage the following - * functionalities of the SDMMC peripheral: + * functionalities of the SDIO peripheral: * + Initialization/de-initialization functions * + I/O operation functions * + Peripheral Control functions @@ -17,11 +17,11 @@ ============================================================================== ##### SDMMC peripheral features ##### ============================================================================== - [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2 - peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA + [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2 + peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA devices. - - [..] The SDIO features include the following: + + [..] The SDMMC features include the following: (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) @@ -38,9 +38,9 @@ ============================================================================== [..] This driver is a considered as a driver of service for external devices drivers - that interfaces with the SDIO peripheral. - According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs - is used in the device's driver to perform SDIO operations and functionalities. + that interfaces with the SDMMC peripheral. + According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs + is used in the device's driver to perform SDMMC operations and functionalities. This driver is almost transparent for the final user, it is only used to implement other functionalities of the external device. @@ -50,10 +50,10 @@ (++) SDIO adapter clock (SDIOCLK = HCLK) (++) AHB bus clock (HCLK/2) - -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition: - Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) + -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition: + Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK)) - (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO + (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC peripheral. (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx) @@ -84,11 +84,11 @@ -@@- To check if the command is well received, read the SDIO_CMDRESP register using the SDIO_GetCommandResponse(). - The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the + The SDMMC responses registers (SDIO_RESP1 to SDIO_RESP2), use the SDIO_GetResponse() function. (+) To control the DPSM (Data Path State Machine) and send/receive - data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), + data to/from the card use the SDIO_ConfigData(), SDIO_GetDataCounter(), SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions. *** Read Operations *** @@ -100,14 +100,14 @@ (++) Data TimeOut (++) Data Length (++) Data Block size - (++) Data Transfer direction: should be from card (To SDIO) + (++) Data Transfer direction: should be from card (To SDMMC) (++) Data Transfer mode (++) DPSM Status (Enable or Disable) - (#) Configure the SDIO resources to receive the data from the card - according to selected transfer mode. + (#) Configure the SDMMC resources to receive the data from the card + according to selected transfer mode (Refer to Step 8, 9 and 10). - (#) Send the selected Read command. + (#) Send the selected Read command (refer to step 11). (#) Use the SDIO flags/interrupts to check the transfer status. @@ -124,18 +124,27 @@ (++) Data Transfer mode (++) DPSM Status (Enable or Disable) - (#) Configure the SDIO resources to send the data to the card according to + (#) Configure the SDMMC resources to send the data to the card according to selected transfer mode. (#) Send the selected Write command. (#) Use the SDIO flags/interrupts to check the transfer status. + + *** Command management operations *** + ===================================== + [..] + (#) The commands used for Read/Write//Erase operations are managed in + separate functions. + Each function allows to send the needed command with the related argument, + then check the response. + By the same approach, you could implement a command and check the response. @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -165,7 +174,6 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" -#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) #if defined(STM32F103xE) || defined(STM32F103xG) @@ -174,22 +182,30 @@ */ /** @defgroup SDMMC_LL SDMMC Low Layer - * @brief Low layer module for SD and MMC driver + * @brief Low layer module for SD * @{ */ +#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx); +static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout); +static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx); +static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx); +static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx); +static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA); + +/* Exported functions --------------------------------------------------------*/ -/** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions +/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions * @{ */ -/** @defgroup HAL_SDMMC_LL_Group1 Initialization and de-initialization functions +/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -203,14 +219,16 @@ */ /** - * @brief Initializes the SDIO according to the specified - * parameters in the SDIO_InitTypeDef and create the associated handle. - * @param SDIOx: Pointer to SDIO register base - * @param Init: SDIO initialization structure + * @brief Initializes the SDMMC according to the specified + * parameters in the SDMMC_InitTypeDef and create the associated handle. + * @param SDIOx: Pointer to SDMMC register base + * @param Init: SDMMC initialization structure * @retval HAL status */ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) { + uint32_t tmpreg = 0U; + /* Check the parameters */ assert_param(IS_SDIO_ALL_INSTANCE(SDIOx)); assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); @@ -220,18 +238,22 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); assert_param(IS_SDIO_CLKDIV(Init.ClockDiv)); - /* Set SDIO configuration parameters */ - /* Write to SDIO CLKCR */ - MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge |\ - Init.ClockBypass |\ - Init.ClockPowerSave |\ - Init.BusWide |\ - Init.HardwareFlowControl |\ - Init.ClockDiv); + /* Set SDMMC configuration parameters */ + tmpreg |= (Init.ClockEdge |\ + Init.ClockBypass |\ + Init.ClockPowerSave |\ + Init.BusWide |\ + Init.HardwareFlowControl |\ + Init.ClockDiv + ); + + /* Write to SDMMC CLKCR */ + MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); return HAL_OK; } + /** * @} */ @@ -241,10 +263,10 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) * @verbatim =============================================================================== - ##### IO operation functions ##### - =============================================================================== + ##### I/O operation functions ##### + =============================================================================== [..] - This subsection provides a set of functions allowing to manage the SDIO data + This subsection provides a set of functions allowing to manage the SDMMC data transfers. @endverbatim @@ -253,7 +275,7 @@ HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init) /** * @brief Read data (word) from Rx FIFO in blocking mode (polling) - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx: Pointer to SDMMC register base * @retval HAL status */ uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) @@ -264,7 +286,7 @@ uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx) /** * @brief Write data (word) to Tx FIFO in blocking mode (polling) - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx: Pointer to SDMMC register base * @param pWriteData: pointer to data to write * @retval HAL status */ @@ -288,7 +310,7 @@ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) ##### Peripheral Control functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to control the SDIO data + This subsection provides a set of functions allowing to control the SDMMC data transfers. @endverbatim @@ -296,8 +318,8 @@ HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData) */ /** - * @brief Set SDIO Power state to ON. - * @param SDIOx: Pointer to SDIO register base + * @brief Set SDMMC Power state to ON. + * @param SDIOx: Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) @@ -305,25 +327,25 @@ HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) /* Set power state to ON */ SDIOx->POWER = SDIO_POWER_PWRCTRL; - return HAL_OK; + return HAL_OK; } /** - * @brief Set SDIO Power state to OFF. - * @param SDIOx: Pointer to SDIO register base + * @brief Set SDMMC Power state to OFF. + * @param SDIOx: Pointer to SDMMC register base * @retval HAL status */ HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx) { /* Set power state to OFF */ - SDIOx->POWER = (uint32_t)0x00000000; + SDIOx->POWER = 0x00000000U; return HAL_OK; } /** - * @brief Get SDIO Power state. - * @param SDIOx: Pointer to SDIO register base + * @brief Get SDMMC Power state. + * @param SDIOx: Pointer to SDMMC register base * @retval Power status of the controller. The returned value can be one of the * following values: * - 0x00: Power OFF @@ -336,37 +358,41 @@ uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx) } /** - * @brief Configure the SDIO command path according to the specified parameters in + * @brief Configure the SDMMC command path according to the specified parameters in * SDIO_CmdInitTypeDef structure and send the command - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx: Pointer to SDMMC register base * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains - * the configuration information for the SDIO command + * the configuration information for the SDMMC command * @retval HAL status */ HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command) { + uint32_t tmpreg = 0U; + /* Check the parameters */ assert_param(IS_SDIO_CMD_INDEX(Command->CmdIndex)); assert_param(IS_SDIO_RESPONSE(Command->Response)); assert_param(IS_SDIO_WAIT(Command->WaitForInterrupt)); assert_param(IS_SDIO_CPSM(Command->CPSM)); - /* Set the SDIO Argument value */ + /* Set the SDMMC Argument value */ SDIOx->ARG = Command->Argument; - /* Set SDIO command parameters */ - /* Write to SDIO CMD register */ - MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, Command->CmdIndex |\ - Command->Response |\ - Command->WaitForInterrupt |\ - Command->CPSM); + /* Set SDMMC command parameters */ + tmpreg |= (uint32_t)(Command->CmdIndex |\ + Command->Response |\ + Command->WaitForInterrupt |\ + Command->CPSM); + + /* Write to SDMMC CMD register */ + MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); return HAL_OK; } /** * @brief Return the command index of last command for which response received - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx: Pointer to SDMMC register base * @retval Command index of the last command response received */ uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) @@ -377,7 +403,8 @@ uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) /** * @brief Return the response received from the card for the last command - * @param SDIO_RESP: Specifies the SDIO response register. + * @param SDIOx: Pointer to SDMMC register base + * @param Response: Specifies the SDMMC response register. * This parameter can be one of the following values: * @arg SDIO_RESP1: Response Register 1 * @arg SDIO_RESP2: Response Register 2 @@ -387,27 +414,29 @@ uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx) */ uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response) { - __IO uint32_t tmp = 0; + __IO uint32_t tmp = 0U; /* Check the parameters */ assert_param(IS_SDIO_RESP(Response)); /* Get the response */ - tmp = SDIO_RESP_ADDR + Response; + tmp = (uint32_t)&(SDIOx->RESP1) + Response; return (*(__IO uint32_t *) tmp); } /** - * @brief Configure the SDIO data path according to the specified + * @brief Configure the SDMMC data path according to the specified * parameters in the SDIO_DataInitTypeDef. - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx: Pointer to SDMMC register base * @param Data : pointer to a SDIO_DataInitTypeDef structure - * that contains the configuration information for the SDIO data. + * that contains the configuration information for the SDMMC data. * @retval HAL status */ -HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data) +HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data) { + uint32_t tmpreg = 0U; + /* Check the parameters */ assert_param(IS_SDIO_DATA_LENGTH(Data->DataLength)); assert_param(IS_SDIO_BLOCK_SIZE(Data->DataBlockSize)); @@ -415,18 +444,20 @@ HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Dat assert_param(IS_SDIO_TRANSFER_MODE(Data->TransferMode)); assert_param(IS_SDIO_DPSM(Data->DPSM)); - /* Set the SDIO Data TimeOut value */ + /* Set the SDMMC Data TimeOut value */ SDIOx->DTIMER = Data->DataTimeOut; - /* Set the SDIO DataLength value */ + /* Set the SDMMC DataLength value */ SDIOx->DLEN = Data->DataLength; - /* Set the SDIO data configuration parameters */ - /* Write to SDIO DCTRL */ - MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, Data->DataBlockSize |\ - Data->TransferDir |\ - Data->TransferMode |\ - Data->DPSM); + /* Set the SDMMC data configuration parameters */ + tmpreg |= (uint32_t)(Data->DataBlockSize |\ + Data->TransferDir |\ + Data->TransferMode |\ + Data->DPSM); + + /* Write to SDMMC DCTRL */ + MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); return HAL_OK; @@ -434,7 +465,7 @@ HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Dat /** * @brief Returns number of remaining data bytes to be transferred. - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx: Pointer to SDMMC register base * @retval Number of remaining data bytes to be transferred */ uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) @@ -444,7 +475,7 @@ uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx) /** * @brief Get the FIFO data - * @param SDIOx: Pointer to SDIO register base + * @param SDIOx: Pointer to SDMMC register base * @retval Data received */ uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) @@ -452,26 +483,1001 @@ uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx) return (SDIOx->FIFO); } - /** * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * @param SDIOx: Pointer to SDMMC register base + * @param SDIO_ReadWaitMode: SDMMC Read Wait operation mode. * This parameter can be: - * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2 + * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK + * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 * @retval None */ -HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode) +HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode) { /* Check the parameters */ assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - /* Set SDIO read wait mode */ - MODIFY_REG(SDIO->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode); + + /* Set SDMMC read wait mode */ + MODIFY_REG(SDIOx->DCTRL, SDIO_DCTRL_RWMOD, SDIO_ReadWaitMode); return HAL_OK; } +/** + * @} + */ + + +/** @defgroup HAL_SDMMC_LL_Group4 Command management functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Commands management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed commands. + +@endverbatim + * @{ + */ + +/** + * @brief Send the Data Block Lenght command and check the response + * @param SDIOx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)BlockSize; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_BLOCKLEN, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Read Single Block command and check the response + * @param SDIOx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_SINGLE_BLOCK, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Read Multi Block command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_READ_MULT_BLOCK, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Write Single Block command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Write Multi Block command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_WRITE_MULT_BLOCK, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Start Address Erase command for SD and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)StartAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_START, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the End Address Erase command for SD and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)EndAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_ERASE_GRP_END, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Start Address Erase command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)StartAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_START, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the End Address Erase command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)EndAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE_GRP_END, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Erase command and check the response + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_ERASE, SDIO_MAXERASETIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Stop Transfer command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD12 STOP_TRANSMISSION */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_STOP_TRANSMISSION, 100000000U); + + return errorstate; +} + +/** + * @brief Send the Select Deselect command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @param addr: Address of the card to be selected + * @retval HAL status + */ +uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD7 SDMMC_SEL_DESEL_CARD */ + sdmmc_cmdinit.Argument = (uint32_t)Addr; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEL_DESEL_CARD, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Go Idle State command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; + sdmmc_cmdinit.Response = SDIO_RESPONSE_NO; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdError(SDIOx); + + return errorstate; +} + +/** + * @brief Send the Operating Condition command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD8 to verify SD card interface operating condition */ + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + /* CMD Response: R7 */ + sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp7(SDIOx); + + return errorstate; +} + +/** + * @brief Send the Application command to verify that that the next command + * is an application specific com-mand rather than a standard command + * and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = (uint32_t)Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + /* If there is a HAL_ERROR, it is a MMC card, else + it is a SD card: SD card 2.0 (voltage range mismatch) + or SD card 1.x */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_CMD, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the command asking the accessed card to send its operating + * condition register (OCR) + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | SdType; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp3(SDIOx); + + return errorstate; +} + +/** + * @brief Send the Bus Width command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = (uint32_t)BusWidth; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send SCR command and check the response. + * @param SDIOx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD51 SD_APP_SEND_SCR */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_SEND_SCR, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send CID command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD2 ALL_SEND_CID */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; + sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp2(SDIOx); + + return errorstate; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = (uint32_t)Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; + sdmmc_cmdinit.Response = SDIO_RESPONSE_LONG; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp2(SDIOx); + + return errorstate; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + /* Send CMD3 SD_CMD_SET_REL_ADDR */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp6(SDIOx, SDMMC_CMD_SET_REL_ADDR, pRCA); + + return errorstate; +} + +/** + * @brief Send the Status command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = (uint32_t)Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SEND_STATUS, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Status register command and check the response. + * @param SDIOx: Pointer to SDIO register base + * @retval HAL status + */ +uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SD_APP_STATUS, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Sends host capacity support information and activates the card's + * initialization process. Send SDMMC_CMD_SEND_OP_COND command + * @param SDIOx: Pointer to SDIO register base + * @parame Argument: Argument used for the command + * @retval HAL status + */ +uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp3(SDIOx); + + return errorstate; +} + +/** + * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand + * @param SDIOx: Pointer to SDIO register base + * @parame Argument: Argument used for the command + * @retval HAL status + */ +uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate = SDMMC_ERROR_NONE; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SWITCH, SDIO_CMDTIMEOUT); + + return errorstate; +} + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief Checks for error conditions for CMD0. + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT)); + + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS); + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R1 response. + * @param hsd: SD handle + * @param SD_CMD: The sent command index + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout) +{ + uint32_t response_r1; + + /* 8 is the number of required instructions cycles for the below loop statement. + The Timeout is expressed in ms */ + register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)); + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Check response received is of desired command */ + if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS); + + /* We have received response, retrieve it for analysis */ + response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); + + if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) + { + return SDMMC_ERROR_NONE; + } + else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) + { + return SDMMC_ERROR_ADDR_OUT_OF_RANGE; + } + else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) + { + return SDMMC_ERROR_ADDR_MISALIGNED; + } + else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) + { + return SDMMC_ERROR_BLOCK_LEN_ERR; + } + else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) + { + return SDMMC_ERROR_ERASE_SEQ_ERR; + } + else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) + { + return SDMMC_ERROR_BAD_ERASE_PARAM; + } + else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) + { + return SDMMC_ERROR_WRITE_PROT_VIOLATION; + } + else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) + { + return SDMMC_ERROR_LOCK_UNLOCK_FAILED; + } + else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) + { + return SDMMC_ERROR_CARD_ECC_FAILED; + } + else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) + { + return SDMMC_ERROR_CC_ERR; + } + else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) + { + return SDMMC_ERROR_STREAM_READ_UNDERRUN; + } + else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) + { + return SDMMC_ERROR_STREAM_WRITE_OVERRUN; + } + else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) + { + return SDMMC_ERROR_CID_CSD_OVERWRITE; + } + else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) + { + return SDMMC_ERROR_WP_ERASE_SKIP; + } + else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) + { + return SDMMC_ERROR_CARD_ECC_DISABLED; + } + else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) + { + return SDMMC_ERROR_ERASE_RESET; + } + else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) + { + return SDMMC_ERROR_AKE_SEQ_ERR; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + +/** + * @brief Checks for error conditions for R2 (CID or CSD) response. + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)); + + if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if (__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* No error flag set */ + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS); + } + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R3 (OCR) response. + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)); + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else + + { + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS); + } + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R6 (RCA) response. + * @param hsd: SD handle + * @param SD_CMD: The sent command index + * @param pRCA: Pointer to the variable that will contain the SD card relative + * address RCA + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA) +{ + uint32_t response_r1; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)); + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL)) + { + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Check response received is of desired command */ + if(SDIO_GetCommandResponse(SDIOx) != SD_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_FLAGS); + + /* We have received response, retrieve it. */ + response_r1 = SDIO_GetResponse(SDIOx, SDIO_RESP1); + + if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) + { + *pRCA = (uint16_t) (response_r1 >> 16); + + return SDMMC_ERROR_NONE; + } + else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + +/** + * @brief Checks for error conditions for R7 response. + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + register uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT)); + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CTIMEOUT)) + { + /* Card is SD V2.0 compliant */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + + if(__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDREND)) + { + /* Card is SD V2.0 compliant */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_FLAG_CMDREND); + } + + return SDMMC_ERROR_NONE; + +} /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.h index 22009d814ce..7ff5f3784e8 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_sdmmc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32f1xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of low layer SDMMC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -147,11 +147,201 @@ typedef struct /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants * @{ */ +#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ +#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ +#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ +#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ +#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ +#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ +#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ +#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ +#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ +#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ +#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ +#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ +#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ +#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ +#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ +#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ +#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ +#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ +#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ +#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ +#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ +#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ +#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ +#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ -/** @defgroup SDMMC_LL_Clock_Edge Clock Edge +/** + * @brief SDMMC Commands Index + */ +#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its + operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information + and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */ +#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands + (read, write, lock). Default block length is fixed to 512 Bytes. Not effective + for SDHS and SDXC. */ +#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by + STOP_TRANSMISSION command. */ +#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command + system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased. + Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by + the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather + than a standard command. */ +#define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card + for general purpose/application specific commands. */ +#define SDMMC_CMD_NO_CMD ((uint8_t)64) /*!< No command */ + +/** + * @brief Following commands are SD Card Specific commands. + * SDMMC_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus + widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with + 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to + send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */ + +/** + * @brief Following commands are SD Card Specific security commands. + * SDMMC_CMD_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43) +#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44) +#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) +#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) +#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) +#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) +#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) + +/** + * @brief Masks for errors Card Status R1 (OCR Register) + */ +#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U +#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U +#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U +#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U +#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U +#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U +#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U +#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U +#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U +#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U +#define SDMMC_OCR_CC_ERROR 0x00100000U +#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U +#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U +#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U +#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U +#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U +#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U +#define SDMMC_OCR_ERASE_RESET 0x00002000U +#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U +#define SDMMC_OCR_ERRORBITS 0xFDFFE008U + +/** + * @brief Masks for R6 Response + */ +#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U +#define SDMMC_R6_ILLEGAL_CMD 0x00004000U +#define SDMMC_R6_COM_CRC_FAILED 0x00008000U + +#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U +#define SDMMC_HIGH_CAPACITY 0x40000000U +#define SDMMC_STD_CAPACITY 0x00000000U +#define SDMMC_CHECK_PATTERN 0x000001AAU + +#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU + +#define SDMMC_MAX_TRIAL 0x0000FFFFU + +#define SDMMC_ALLZERO 0x00000000U + +#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U +#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U +#define SDMMC_CARD_LOCKED 0x02000000U + +#define SDMMC_DATATIMEOUT 0xFFFFFFFFU + +#define SDMMC_0TO7BITS 0x000000FFU +#define SDMMC_8TO15BITS 0x0000FF00U +#define SDMMC_16TO23BITS 0x00FF0000U +#define SDMMC_24TO31BITS 0xFF000000U +#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU + +#define SDMMC_HALFFIFO 0x00000008U +#define SDMMC_HALFFIFOBYTES 0x00000020U + +/** + * @brief Command Class supported + */ +#define SDIO_CCCC_ERASE 0x00000020U + +#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */ +#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ + + +/** @defgroup SDIO_LL_Clock_Edge Clock Edge * @{ */ -#define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000) +#define SDIO_CLOCK_EDGE_RISING 0x00000000U #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ @@ -160,10 +350,10 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass +/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass * @{ */ -#define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) +#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ @@ -172,10 +362,10 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving +/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving * @{ */ -#define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) +#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ @@ -184,10 +374,10 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Bus_Wide Bus Width +/** @defgroup SDIO_LL_Bus_Wide Bus Width * @{ */ -#define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000) +#define SDIO_BUS_WIDE_1B 0x00000000U #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 @@ -198,10 +388,10 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control +/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control * @{ */ -#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) +#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ @@ -210,26 +400,26 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Clock_Division Clock Division +/** @defgroup SDIO_LL_Clock_Division Clock Division * @{ */ -#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF) +#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU) /** * @} */ -/** @defgroup SDMMC_LL_Command_Index Command Index +/** @defgroup SDIO_LL_Command_Index Command Index * @{ */ -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U) /** * @} */ -/** @defgroup SDMMC_LL_Response_Type Response Type +/** @defgroup SDIO_LL_Response_Type Response Type * @{ */ -#define SDIO_RESPONSE_NO ((uint32_t)0x00000000) +#define SDIO_RESPONSE_NO 0x00000000U #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP @@ -240,10 +430,10 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt +/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt * @{ */ -#define SDIO_WAIT_NO ((uint32_t)0x00000000) +#define SDIO_WAIT_NO 0x00000000U #define SDIO_WAIT_IT SDIO_CMD_WAITINT #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND @@ -254,10 +444,10 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_CPSM_State CPSM State +/** @defgroup SDIO_LL_CPSM_State CPSM State * @{ */ -#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000) +#define SDIO_CPSM_DISABLE 0x00000000U #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ @@ -266,13 +456,13 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Response_Registers Response Register +/** @defgroup SDIO_LL_Response_Registers Response Register * @{ */ -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define SDIO_RESP1 0x00000000U +#define SDIO_RESP2 0x00000004U +#define SDIO_RESP3 0x00000008U +#define SDIO_RESP4 0x0000000CU #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ ((RESP) == SDIO_RESP2) || \ @@ -282,18 +472,18 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Data_Length Data Lenght +/** @defgroup SDIO_LL_Data_Length Data Lenght * @{ */ -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) /** * @} */ -/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size +/** @defgroup SDIO_LL_Data_Block_Size Data Block Size * @{ */ -#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) +#define SDIO_DATABLOCK_SIZE_1B 0x00000000U #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) @@ -328,10 +518,10 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction +/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction * @{ */ -#define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) +#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ @@ -340,10 +530,10 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Transfer_Type Transfer Type +/** @defgroup SDIO_LL_Transfer_Type Transfer Type * @{ */ -#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) +#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ @@ -352,10 +542,10 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_DPSM_State DPSM State +/** @defgroup SDIO_LL_DPSM_State DPSM State * @{ */ -#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000) +#define SDIO_DPSM_DISABLE 0x00000000U #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ @@ -364,10 +554,10 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode +/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode * @{ */ -#define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000) +#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ @@ -376,7 +566,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources +/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources * @{ */ #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL @@ -403,7 +593,6 @@ typedef struct #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND - /** * @} */ @@ -435,25 +624,82 @@ typedef struct #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND - +#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ + SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ + SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ + SDIO_FLAG_DBCKEND)) /** * @} */ /** * @} - */ + */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros +/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros * @{ */ - -/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions - * @brief SDMMC_LL registers bit address in the alias region + +/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region + * @{ + */ +/* ------------ SDIO registers bit address in the alias region -------------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U) +#define CLKEN_BITNUMBER 0x08U +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U)) + +/* --- CMD Register ---*/ +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0CU) +#define SDIOSUSPEND_BITNUMBER 0x0BU +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BITNUMBER 0x0CU +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U)) + +/* Alias word address of NIEN bit */ +#define NIEN_BITNUMBER 0x0DU +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BITNUMBER 0x0EU +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U)) + +/* --- DCTRL Register ---*/ +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU) +#define DMAEN_BITNUMBER 0x03U +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BITNUMBER 0x08U +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BITNUMBER 0x09U +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BITNUMBER 0x0AU +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BITNUMBER 0x0BU +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U)) +/** + * @} + */ + +/** @defgroup SDIO_LL_Register Bits And Addresses Definitions + * @brief SDIO_LL registers bit address in the alias region * @{ */ - /* ---------------------- SDIO registers bit mask --------------------------- */ /* --- CLKCR Register ---*/ /* CLKCR register clear mask */ @@ -484,38 +730,38 @@ typedef struct /** * @} */ - -/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + +/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ /** * @brief Enable the SDIO device. * @param __INSTANCE__: SDIO Instance * @retval None */ -#define __SDIO_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDIO_CLKCR_CLKEN) +#define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) /** * @brief Disable the SDIO device. * @param __INSTANCE__: SDIO Instance * @retval None */ -#define __SDIO_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDIO_CLKCR_CLKEN) +#define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) /** * @brief Enable the SDIO DMA transfer. - * @param None + * @param __INSTANCE__: SDIO Instance * @retval None */ -#define __SDIO_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_DMAEN) +#define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) /** * @brief Disable the SDIO DMA transfer. - * @param None + * @param __INSTANCE__: SDIO Instance * @retval None */ -#define __SDIO_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_DMAEN) +#define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) /** * @brief Enable the SDIO device interrupt. @@ -531,8 +777,6 @@ typedef struct * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt * @arg SDIO_IT_TXACT: Data transmit in progress interrupt @@ -545,8 +789,7 @@ typedef struct * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt * @retval None */ #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) @@ -565,8 +808,6 @@ typedef struct * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt * @arg SDIO_IT_TXACT: Data transmit in progress interrupt @@ -579,8 +820,7 @@ typedef struct * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt * @retval None */ #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) @@ -599,7 +839,6 @@ typedef struct * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDIO_FLAG_CMDACT: Command transfer in progress * @arg SDIO_FLAG_TXACT: Data transmit in progress @@ -613,10 +852,9 @@ typedef struct * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 * @retval The new state of SDIO_FLAG (SET or RESET). */ -#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) +#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) /** @@ -633,13 +871,11 @@ typedef struct * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 * @retval None */ -#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) +#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) /** * @brief Checks whether the specified SDIO interrupt has occurred or not. @@ -655,8 +891,6 @@ typedef struct * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt * @arg SDIO_IT_TXACT: Data transmit in progress interrupt @@ -670,10 +904,9 @@ typedef struct * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt * @retval The new state of SDIO_IT (SET or RESET). */ -#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) +#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Clears the SDIO's interrupt pending bits. @@ -689,120 +922,110 @@ typedef struct * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 * @retval None */ -#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) +#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) /** * @brief Enable Start the SD I/O Read Wait operation. * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_RWSTART) +#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) /** * @brief Disable Start the SD I/O Read Wait operations. * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_RWSTART) +#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) /** * @brief Enable Start the SD I/O Read Wait operation. * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_RWSTOP) +#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) /** * @brief Disable Stop the SD I/O Read Wait operations. * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_RWSTOP) +#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) /** * @brief Enable the SD I/O Mode Operation. * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_SDIOEN) +#define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) /** * @brief Disable the SD I/O Mode Operation. * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_SDIOEN) +#define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) /** * @brief Enable the SD I/O Suspend command sending. * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_SDIOSUSPEND) +#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) /** * @brief Disable the SD I/O Suspend command sending. * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_SDIOSUSPEND) - +#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) /** * @brief Enable the command completion signal. - * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_CEATA_CMD_COMPLETION_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_ENCMDCOMPL) +#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) /** * @brief Disable the command completion signal. - * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_CEATA_CMD_COMPLETION_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_ENCMDCOMPL) +#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) /** * @brief Enable the CE-ATA interrupt. - * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_CEATA_ENABLE_IT(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_NIEN) +#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U) /** * @brief Disable the CE-ATA interrupt. - * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_CEATA_DISABLE_IT(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_NIEN) +#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U) /** * @brief Enable send CE-ATA command (CMD61). - * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_CEATA_SENDCMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_CEATACMD) +#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) /** * @brief Disable send CE-ATA command (CMD61). - * @param __INSTANCE__ : Pointer to SDIO register base * @retval None */ -#define __SDIO_CEATA_SENDCMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_CEATACMD) +#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) /** * @} */ - + /** * @} */ - + /* Exported functions --------------------------------------------------------*/ /** @addtogroup SDMMC_LL_Exported_Functions * @{ @@ -842,12 +1065,40 @@ uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response); /* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data); +HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data); uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); -/* SDIO Cards mode management functions */ -HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode); +/* SDMMC Cards mode management functions */ +HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode); + +/* SDMMC Commands management functions */ +uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize); +uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); +uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); +uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); +uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); +uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); +uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); +uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr); +uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType); +uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); +uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); +uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); + +uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); +uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_spi.c new file mode 100644 index 00000000000..67262c96e92 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_spi.c @@ -0,0 +1,562 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_spi.c + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief SPI LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_spi.h" +#include "stm32f1xx_ll_bus.h" +#include "stm32f1xx_ll_rcc.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) || defined (SPI3) + +/** @addtogroup SPI_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SPI_LL_Private_Constants SPI Private Constants + * @{ + */ +/* SPI registers Masks */ +#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \ + SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \ + SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \ + SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \ + SPI_CR1_BIDIMODE) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Private_Macros SPI Private Macros + * @{ + */ +#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ + || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ + || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ + || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) + +#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ + || ((__VALUE__) == LL_SPI_MODE_SLAVE)) + +#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) + +#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ + || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) + +#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ + || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) + +#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ + || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ + || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) + +#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) + +#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ + || ((__VALUE__) == LL_SPI_MSB_FIRST)) + +#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \ + || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) + +#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + +#if defined(SPI1) + if (SPIx == SPI1) + { + /* Force reset of SPI clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); + + /* Release reset of SPI clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); + + status = SUCCESS; + } +#endif /* SPI1 */ +#if defined(SPI2) + if (SPIx == SPI2) + { + /* Force reset of SPI clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); + + /* Release reset of SPI clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); + + status = SUCCESS; + } +#endif /* SPI2 */ +#if defined(SPI3) + if (SPIx == SPI3) + { + /* Force reset of SPI clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3); + + /* Release reset of SPI clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); + + status = SUCCESS; + } +#endif /* SPI3 */ + + return status; +} + +/** + * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), + * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the SPI Instance SPIx*/ + assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + + /* Check the SPI parameters from SPI_InitStruct*/ + assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); + assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); + assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); + assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); + assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); + assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); + assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate)); + assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); + assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); + + if (LL_SPI_IsEnabled(SPIx) == 0x00000000U) + { + /*---------------------------- SPIx CR1 Configuration ------------------------ + * Configure SPIx CR1 with parameters: + * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits + * - Master/Slave Mode: SPI_CR1_MSTR bit + * - DataWidth: SPI_CR1_DFF bit + * - ClockPolarity: SPI_CR1_CPOL bit + * - ClockPhase: SPI_CR1_CPHA bit + * - NSS management: SPI_CR1_SSM bit + * - BaudRate prescaler: SPI_CR1_BR[2:0] bits + * - BitOrder: SPI_CR1_LSBFIRST bit + * - CRCCalculation: SPI_CR1_CRCEN bit + */ + MODIFY_REG(SPIx->CR1, + SPI_CR1_CLEAR_MASK, + SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth | + SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase | + SPI_InitStruct->NSS | SPI_InitStruct->BaudRate | + SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation); + + /*---------------------------- SPIx CR2 Configuration ------------------------ + * Configure SPIx CR2 with parameters: + * - NSS management: SSOE bit + */ + MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U)); + + /*---------------------------- SPIx CRCPR Configuration ---------------------- + * Configure SPIx CRCPR with parameters: + * - CRCPoly: CRCPOLY[15:0] bits + */ + if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); + LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); + } + status = SUCCESS; + } + +#if defined (SPI_I2S_SUPPORT) + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2S_SUPPORT */ + return status; +} + +/** + * @brief Set each @ref LL_SPI_InitTypeDef field to default value. + * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) +{ + /* Set SPI_InitStruct fields to default values */ + SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; + SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; + SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; + SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; + SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; + SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; + SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; + SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; + SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + SPI_InitStruct->CRCPoly = 7U; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#if defined(SPI_I2S_SUPPORT) +/** @addtogroup I2S_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Constants I2S Private Constants + * @{ + */ +/* I2S registers Masks */ +#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ + SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) + +#define I2S_I2SPR_CLEAR_MASK 0x0002U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Macros I2S Private Macros + * @{ + */ + +#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) + +#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ + || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) + +#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ + || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ + || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ + || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ + || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) + +#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ + || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ + || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ + || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) + +#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ + || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) + +#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ + && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ + || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) + +#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) + +#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ + || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI/I2S registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +{ + return LL_SPI_DeInit(SPIx); +} + +/** + * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), + * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are Initialized + * - ERROR: SPI registers are not Initialized + */ +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) +{ + uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U; + uint32_t tmp = 0U; + uint32_t sourceclock = 0U; +#if defined(I2S2_I2S3_CLOCK_FEATURE) +#else + LL_RCC_ClocksTypeDef rcc_clocks; +#endif /* I2S2_I2S3_CLOCK_FEATURE */ + ErrorStatus status = ERROR; + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); + assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); + assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); + assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); + assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); + assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); + + if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) + { + /*---------------------------- SPIx I2SCFGR Configuration -------------------- + * Configure SPIx I2SCFGR with parameters: + * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit + * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits + * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits + * - ClockPolarity: SPI_I2SCFGR_CKPOL bit + */ + + /* Write to SPIx I2SCFGR */ + MODIFY_REG(SPIx->I2SCFGR, + I2S_I2SCFGR_CLEAR_MASK, + I2S_InitStruct->Mode | I2S_InitStruct->Standard | + I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | + SPI_I2SCFGR_I2SMOD); + + /*---------------------------- SPIx I2SPR Configuration ---------------------- + * Configure SPIx I2SPR with parameters: + * - MCLKOutput: SPI_I2SPR_MCKOE bit + * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits + */ + + /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) + * else, default values are used: i2sodd = 0U, i2sdiv = 2U. + */ + if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) + { + /* Check the frame length (For the Prescaler computing) + * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). + */ + if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) + { + /* Packet length is 32 bits */ + packetlength = 2U; + } +#if defined(I2S2_I2S3_CLOCK_FEATURE) + /* If an external I2S clock has to be used, the specific define should be set + in the project configuration or in the stm32f1xx_ll_rcc.h file */ + if(SPIx == SPI2) + { + /* Get the I2S source clock value */ + sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE); + } + else /* SPI3 */ + { + /* Get the I2S source clock value */ + sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S3_CLKSOURCE); + } +#else + /* I2S Clock source is System clock: Get System Clock frequency */ + LL_RCC_GetSystemClocksFreq(&rcc_clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = rcc_clocks.SYSCLK_Frequency; +#endif /* I2S2_I2S3_CLOCK_FEATURE */ + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + } + + /* Remove the floating point */ + tmp = tmp / 10U; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2U); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t)(i2sodd << 8U); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) + { + /* Set the default values */ + i2sdiv = 2U; + i2sodd = 0U; + } + + /* Write to SPIx I2SPR register the computed value */ + WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); + + status = SUCCESS; + } + return status; +} + +/** + * @brief Set each @ref LL_I2S_InitTypeDef field to default value. + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; + I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; + I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; + I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; + I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; + I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; +} + +/** + * @brief Set linear and parity prescaler. + * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n + * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). + * @param SPIx SPI Instance + * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF. + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) +{ + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); + assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); + + /* Write to SPIx I2SPR */ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI_I2S_SUPPORT */ + +#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_spi.h new file mode 100644 index 00000000000..c8c6061ee42 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_spi.h @@ -0,0 +1,1922 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_spi.h + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_SPI_H +#define __STM32F1xx_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) || defined (SPI3) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure + * @{ + */ + +/** + * @brief SPI Init structures definition + */ +typedef struct +{ + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_LL_EC_MODE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_LL_EC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_LL_EC_PHASE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. The slave clock does not need to be set. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + +} LL_SPI_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function + * @{ + */ +#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ +#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ +#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ +#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ +#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ +#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ +/** + * @} + */ + + +/** @defgroup SPI_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ +#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ +#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ +#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ +#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ +#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ +#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode + * @{ + */ +#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ +#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ +#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */ +#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + * @{ + */ +#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral + * @rmtoll CR1 SPE LL_SPI_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @rmtoll CR1 SPE LL_SPI_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled + * @rmtoll CR1 SPE LL_SPI_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)); +} + +/** + * @brief Set SPI operation mode to Master or Slave + * @note This bit should not be changed when communication is ongoing. + * @rmtoll CR1 MSTR LL_SPI_SetMode\n + * CR1 SSI LL_SPI_SetMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); +} + +/** + * @brief Get SPI operation mode (Master or Slave) + * @rmtoll CR1 MSTR LL_SPI_GetMode\n + * CR1 SSI LL_SPI_GetMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); +} + + +/** + * @brief Set clock phase + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPHA LL_SPI_SetClockPhase + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); +} + +/** + * @brief Get clock phase + * @rmtoll CR1 CPHA LL_SPI_GetClockPhase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); +} + +/** + * @brief Set clock polarity + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); +} + +/** + * @brief Get clock polarity + * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); +} + +/** + * @brief Set baud rate prescaler + * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. + * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler + * @param SPIx SPI Instance + * @param BaudRate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); +} + +/** + * @brief Get baud rate prescaler + * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); +} + +/** + * @brief Set transfer bit order + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); +} + +/** + * @brief Get transfer bit order + * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); +} + +/** + * @brief Set transfer direction mode + * @note For Half-Duplex mode, Rx Direction is set by default. + * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. + * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n + * CR1 BIDIMODE LL_SPI_SetTransferDirection\n + * CR1 BIDIOE LL_SPI_SetTransferDirection + * @param SPIx SPI Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); +} + +/** + * @brief Get transfer direction mode + * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n + * CR1 BIDIMODE LL_SPI_GetTransferDirection\n + * CR1 BIDIOE LL_SPI_GetTransferDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); +} + +/** + * @brief Set frame data width + * @rmtoll CR1 DFF LL_SPI_SetDataWidth + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth); +} + +/** + * @brief Get frame data width + * @rmtoll CR1 DFF LL_SPI_GetDataWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_CRC_Management CRC Management + * @{ + */ + +/** + * @brief Enable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_EnableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Disable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_DisableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Check if CRC is enabled + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)); +} + +/** + * @brief Set CRCNext to transfer CRC on the line + * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. + * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); +} + +/** + * @brief Set polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial + * @param SPIx SPI Instance + * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); +} + +/** + * @brief Get polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPR)); +} + +/** + * @brief Get Rx CRC + * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRCR)); +} + +/** + * @brief Get Tx CRC + * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRCR)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management + * @{ + */ + +/** + * @brief Set NSS mode + * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. + * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_SetNSSMode + * @param SPIx SPI Instance + * @param NSS This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); + MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); +} + +/** + * @brief Get NSS mode + * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_GetNSSMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +{ + register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + return (Ssm | Ssoe); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)); +} + +/** + * @brief Get CRC error flag + * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)); +} + +/** + * @brief Get mode fault error flag + * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)); +} + +/** + * @brief Get busy flag + * @note The BSY flag is cleared under any one of the following conditions: + * -When the SPI is correctly disabled + * -When a fault is detected in Master mode (MODF bit set to 1) + * -In Master mode, when it finishes a data transmission and no new data is ready to be + * sent + * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between + * each data transfer. + * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)); +} + + +/** + * @brief Clear CRC error flag + * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); +} + +/** + * @brief Clear mode fault error flag + * @note Clearing this flag is done by a read access to the SPIx_SR + * register followed by a write access to the SPIx_CR1 register + * @rmtoll SR MODF LL_SPI_ClearFlag_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; + tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); + (void) tmpreg; +} + +/** + * @brief Clear overrun error flag + * @note Clearing this flag is done by a read access to the SPIx_DR + * register followed by a read access to the SPIx_SR register + * @rmtoll SR OVR LL_SPI_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->DR; + (void) tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable error interrupt + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Enable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Enable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Disable error interrupt + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Disable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Disable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Check if error interrupt is enabled + * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)); +} + +/** + * @brief Check if Rx buffer not empty interrupt is enabled + * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)); +} + +/** + * @brief Check if Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll DR DR LL_SPI_DMA_GetRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +{ + return (uint32_t) & (SPIx->DR); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA Management + * @{ + */ + +/** + * @brief Read 8-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData8 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +{ + return (uint8_t)(READ_REG(SPIx->DR)); +} + +/** + * @brief Read 16-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) +{ + return (uint16_t)(READ_REG(SPIx->DR)); +} + +/** + * @brief Write 8-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData8 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +{ + SPIx->DR = TxData; +} + +/** + * @brief Write 16-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + SPIx->DR = TxData; +} + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +/** + * @} + */ + +#if defined(SPI_I2S_SUPPORT) +/** @defgroup I2S_LL I2S + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure + * @{ + */ + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_LL_EC_MODE + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_STANDARD + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ + + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ + + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT + + This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ + + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ + + Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity + and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ + + + uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_LL_EC_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ + +} LL_I2S_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2S_ReadReg function + * @{ + */ +#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ +#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ +#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ +#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_DATA_FORMAT Data format + * @{ + */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ +#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_STANDARD I2s Standard + * @{ + */ +#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ +#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ +#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ +#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ +#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ +#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ +#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ +#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor + * @{ + */ +#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output + * @{ + */ +#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ +#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency + * @{ + */ + +#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros + * @{ + */ + +/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Select I2S mode and Enable I2S peripheral + * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n + * I2SCFGR I2SE LL_I2S_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Disable I2S peripheral + * @rmtoll I2SCFGR I2SE LL_I2S_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Check if I2S peripheral is enabled + * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)); +} + +/** + * @brief Set I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n + * I2SCFGR CHLEN LL_I2S_SetDataFormat + * @param SPIx SPI Instance + * @param DataFormat This parameter can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat); +} + +/** + * @brief Get I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n + * I2SCFGR CHLEN LL_I2S_GetDataFormat + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + */ +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); +} + +/** + * @brief Set I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + SET_BIT(SPIx->I2SCFGR, ClockPolarity); +} + +/** + * @brief Get I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); +} + +/** + * @brief Set I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n + * I2SCFGR PCMSYNC LL_I2S_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); +} + +/** + * @brief Get I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n + * I2SCFGR PCMSYNC LL_I2S_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + */ +__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); +} + +/** + * @brief Set I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode); +} + +/** + * @brief Get I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); +} + +/** + * @brief Set I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear + * @param SPIx SPI Instance + * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear); +} + +/** + * @brief Get I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear + * @param SPIx SPI Instance + * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); +} + +/** + * @brief Set I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity + * @param SPIx SPI Instance + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U); +} + +/** + * @brief Get I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); +} + +/** + * @brief Enable the master clock ouput (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Disable the master clock ouput (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Check if the master clock ouput (Pin MCK) is enabled + * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_FLAG FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_RXNE(SPIx); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_TXE(SPIx); +} + +/** + * @brief Get busy flag + * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_BSY(SPIx); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_OVR(SPIx); +} + +/** + * @brief Get underrun error flag + * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)); +} + +/** + * @brief Get channel side flag. + * @note 0: Channel Left has to be transmitted or has been received\n + * 1: Channel Right has to be transmitted or has been received\n + * It has no significance in PCM mode. + * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) +{ + return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)); +} + +/** + * @brief Clear overrun error flag + * @rmtoll SR OVR LL_I2S_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_OVR(SPIx); +} + +/** + * @brief Clear underrun error flag + * @rmtoll SR UDR LL_I2S_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void)tmpreg; +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_IT Interrupt Management + * @{ + */ + +/** + * @brief Enable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_ERR(SPIx); +} + +/** + * @brief Enable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_RXNE(SPIx); +} + +/** + * @brief Enable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_TXE(SPIx); +} + +/** + * @brief Disable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_ERR(SPIx); +} + +/** + * @brief Disable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_RXNE(SPIx); +} + +/** + * @brief Disable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_TXE(SPIx); +} + +/** + * @brief Check if ERR IT is enabled + * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_ERR(SPIx); +} + +/** + * @brief Check if RXNE IT is enabled + * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_RXNE(SPIx); +} + +/** + * @brief Check if TXE IT is enabled + * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_TXE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DMA DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_RX(SPIx); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_RX(SPIx); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_RX(SPIx); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_TX(SPIx); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_TX(SPIx); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_TX(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DATA DATA Management + * @{ + */ + +/** + * @brief Read 16-Bits in data register + * @rmtoll DR DR LL_I2S_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) +{ + return LL_SPI_ReceiveData16(SPIx); +} + +/** + * @brief Write 16-Bits in data register + * @rmtoll DR DR LL_I2S_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + LL_SPI_TransmitData16(SPIx, TxData); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI_I2S_SUPPORT */ + +#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_SPI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_system.h index 3f86e375bc0..7f204c23f4b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_system.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_system.h * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of SYSTEM LL module. @verbatim ============================================================================== @@ -76,9 +76,6 @@ extern "C" { * @{ */ -/* Defines used for position in the register */ -#define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID) - /** * @} */ @@ -96,7 +93,7 @@ extern "C" { /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment * @{ */ -#define LL_DBGMCU_TRACE_NONE (uint32_t)0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ @@ -177,7 +174,7 @@ extern "C" { * @{ */ #if defined(FLASH_ACR_LATENCY) -#define LL_FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */ +#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ #else @@ -231,7 +228,7 @@ __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) */ __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) { - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION); + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_tim.c new file mode 100644 index 00000000000..ef5edc88885 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_tim.c @@ -0,0 +1,1216 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_tim.c + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief TIM LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_tim.h" +#include "stm32f1xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) + +/** @addtogroup TIM_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup TIM_LL_Private_Macros + * @{ + */ +#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) + +#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) + +#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ + || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM2)) + +#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ + || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) + +#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ + || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) + +#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ + || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) + +#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) + +#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) + +#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + +#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) + +#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + +#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + +#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + +#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + +#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + +#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + +#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup TIM_LL_Private_Functions TIM Private Functions + * @{ + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_LL_Exported_Functions + * @{ + */ + +/** @addtogroup TIM_LL_EF_Init + * @{ + */ + +/** + * @brief Set TIMx registers to their reset values. + * @param TIMx Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: invalid TIMx instance + */ +ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) +{ + ErrorStatus result = SUCCESS; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + + if (TIMx == TIM2) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); + } +#if defined(TIM1) + else if (TIMx == TIM1) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); + } +#endif +#if defined(TIM3) + else if (TIMx == TIM3) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); + } +#endif +#if defined(TIM4) + else if (TIMx == TIM4) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); + } +#endif +#if defined(TIM5) + else if (TIMx == TIM5) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); + } +#endif +#if defined(TIM6) + else if (TIMx == TIM6) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); + } +#endif +#if defined (TIM7) + else if (TIMx == TIM7) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); + } +#endif +#if defined(TIM8) + else if (TIMx == TIM8) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); + } +#endif +#if defined(TIM9) + else if (TIMx == TIM9) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9); + } +#endif +#if defined(TIM10) + else if (TIMx == TIM10) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10); + } +#endif +#if defined(TIM11) + else if (TIMx == TIM11) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11); + } +#endif +#if defined(TIM12) + else if (TIMx == TIM12) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); + } +#endif +#if defined(TIM13) + else if (TIMx == TIM13) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); + } +#endif +#if defined(TIM14) + else if (TIMx == TIM14) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14); + } +#endif +#if defined(TIM15) + else if (TIMx == TIM15) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15); + } +#endif +#if defined(TIM16) + else if (TIMx == TIM16) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); + } +#endif +#if defined(TIM17) + else if (TIMx == TIM17) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); + } +#endif + else + { + result = ERROR; + } + + return result; +} + +/** + * @brief Set the fields of the time base unit configuration data structure + * to their default values. + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) + * @retval None + */ +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->Prescaler = (uint16_t)0x0000; + TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct->Autoreload = 0xFFFFFFFFU; + TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; +} + +/** + * @brief Configure the TIMx time base unit. + * @param TIMx Timer Instance + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) +{ + uint32_t tmpcr1 = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); + assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); + + tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); + + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); + } + + /* Write to TIMx CR1 */ + LL_TIM_WriteReg(TIMx, CR1, tmpcr1); + + /* Set the Autoreload value */ + LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); + + /* Set the Prescaler value */ + LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); + } + + /* Generate an update event to reload the Prescaler + and the repetition counter value (if applicable) immediately */ + LL_TIM_GenerateEvent_UPDATE(TIMx); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx output channel configuration data + * structure to their default values. + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) + * @retval None + */ +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + /* Set the default configuration */ + TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; + TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->CompareValue = 0x00000000U; + TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; + TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; +} + +/** + * @brief Configure the TIMx output channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = OC1Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = OC2Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = OC3Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = OC4Config(TIMx, TIM_OC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Set the fields of the TIMx input channel configuration data + * structure to their default values. + * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) + * @retval None + */ +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; + TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the TIMx input channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = IC1Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = IC2Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = IC3Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = IC4Config(TIMx, TIM_IC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Fills each TIM_EncoderInitStruct field with its default value + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) + * @retval None + */ +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + /* Set the default configuration */ + TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; + TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the encoder interface of the timer instance. + * @param TIMx Timer Instance + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Configure TI1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + + /* Configure TI2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + + /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Set encoder mode */ + LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx Hall sensor interface configuration data + * structure to their default values. + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) + * @retval None + */ +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + /* Set the default configuration */ + TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_HallSensorInitStruct->CommutationDelay = 0U; +} + +/** + * @brief Configure the Hall sensor interface of the timer instance. + * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR + * to the TI1 input channel + * @note TIMx slave mode controller is configured in reset mode. + Selected internal trigger is TI1F_ED. + * @note Channel 1 is configured as input, IC1 is mapped on TRC. + * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed + * between 2 changes on the inputs. It gives information about motor speed. + * @note Channel 2 is configured in output PWM 2 mode. + * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. + * @note OC2REF is selected as trigger output on TRGO. + * @param TIMx Timer Instance + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + uint32_t tmpcr2 = 0U; + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpsmcr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx SMCR register value */ + tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); + + /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ + tmpcr2 |= TIM_CR2_TI1S; + + /* OC2REF signal is used as trigger output (TRGO) */ + tmpcr2 |= LL_TIM_TRGO_OC2REF; + + /* Configure the slave mode controller */ + tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); + tmpsmcr |= LL_TIM_TS_TI1F_ED; + tmpsmcr |= LL_TIM_SLAVEMODE_RESET; + + /* Configure input channel 1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); + + /* Configure input channel 2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); + tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); + + /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx SMCR */ + LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + /* Write to TIMx CCR2 */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); + + return SUCCESS; +} + +/** + * @brief Set the fields of the Break and Dead Time configuration data structure + * to their default values. + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @retval None + */ +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; + TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; + TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; +} + +/** + * @brief Configure the Break and Dead Time feature of the timer instance. + * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked + * depending on the LOCK configuration, it can be necessary to configure all of + * them during the first write access to the TIMx_BDTR register. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @param TIMx Timer Instance + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Break and Dead Time is initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); + assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); + assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); + assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); + assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); + + /* Set TIMx_BDTR */ + LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); + + return SUCCESS; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_LL_Private_Functions TIM Private Functions + * @brief Private functions + * @{ + */ +/** + * @brief Configure the TIMx output channel 1. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); + + /* Set the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 2. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1 = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 3. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 4. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2 = 0U; + uint32_t tmpccer = 0U; + uint32_t tmpcr2 = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + + +/** + * @brief Configure the TIMx input channel 1. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC1E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC1P | TIM_CCER_CC1NP), + (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 2. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC2E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC2P | TIM_CCER_CC2NP), + ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 3. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC3E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC3P | TIM_CCER_CC3NP), + ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 4. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC4E Bit */ + MODIFY_REG(TIMx->CCER, + TIM_CCER_CC4P, + ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); + + return SUCCESS; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_tim.h new file mode 100644 index 00000000000..2f93fbd948a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_tim.h @@ -0,0 +1,3837 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_tim.h + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_TIM_H +#define __STM32F1xx_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U /* 6: TIMx_CH4 */ +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U /* 6: OC4M, OC4FE, OC4PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U /* 6: CC4S, IC4PSC, IC4F */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U /* 6: CC4P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U /* 6: OIS4 */ +}; +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + + + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ +(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ +((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ +((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ +((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ +((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ +((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ + + uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity + * @{ + */ +#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ +#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State + * @{ + */ +#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros + * @{ + */ + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ +((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + return (READ_BIT(TIMx->CCER, Channels) == (Channels)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS1N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS1N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return (READ_BIT(*pReg, bitfield) == bitfield); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return (READ_BIT(*pReg, bitfield) == bitfield); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return (READ_BIT(*pReg, bitfield) == bitfield); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals). + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); +} + +/** + * @brief Get captured value for input channel 1. + * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR3 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Configure the break input. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) +{ + MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); +} + +/** + * @} + */ + + +/** + * @} + */ + + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA-Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_TIM_H */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usart.c new file mode 100644 index 00000000000..04b047a0b2b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usart.c @@ -0,0 +1,451 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_usart.c + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief USART LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx_ll_usart.h" +#include "stm32f1xx_ll_rcc.h" +#include "stm32f1xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) + +/** @addtogroup USART_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Constants + * @{ + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Macros + * @{ + */ + +/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available + * divided by the smallest oversampling used on the USART (i.e. 8) */ +#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U) + +#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + +#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) + +#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + +#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + +#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + +#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + +#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + +#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + +#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) + +#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USART_LL_Exported_Functions + * @{ + */ + +/** @addtogroup USART_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize USART registers (Registers restored to their default values). + * @param USARTx USART Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers are de-initialized + * - ERROR: USART registers are not de-initialized + */ +ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + + if (USARTx == USART1) + { + /* Force reset of USART clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); + + /* Release reset of USART clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); + } + else if (USARTx == USART2) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); + } +#if defined(USART3) + else if (USARTx == USART3) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3); + } +#endif /* USART3 */ +#if defined(UART4) + else if (USARTx == UART4) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4); + } +#endif /* UART4 */ +#if defined(UART5) + else if (USARTx == UART5) + { + /* Force reset of UART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5); + + /* Release reset of UART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5); + } +#endif /* UART5 */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize USART registers according to the specified + * parameters in USART_InitStruct. + * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), + * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). + * @param USARTx USART Instance + * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure + * that contains the configuration information for the specified USART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers are initialized according to USART_InitStruct content + * - ERROR: Problem occurred during USART Registers initialization + */ +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + LL_RCC_ClocksTypeDef rcc_clocks; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); + assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); + assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); + assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity)); + assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection)); + assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl)); +#if defined(USART_CR1_OVER8) + assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling)); +#endif /* USART_OverSampling_Feature */ + + /* USART needs to be in disabled state, in order to be able to configure some bits in + CRx registers */ + if (LL_USART_IsEnabled(USARTx) == 0U) + { + /*---------------------------- USART CR1 Configuration ----------------------- + * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters: + * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value + * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value + * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value + * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value. + */ +#if defined(USART_CR1_OVER8) + MODIFY_REG(USARTx->CR1, + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + (USART_InitStruct->DataWidth | USART_InitStruct->Parity | + USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling)); +#else + MODIFY_REG(USARTx->CR1, + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | + USART_CR1_TE | USART_CR1_RE), + (USART_InitStruct->DataWidth | USART_InitStruct->Parity | + USART_InitStruct->TransferDirection)); +#endif /* USART_OverSampling_Feature */ + + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Stop bits) with parameters: + * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. + * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). + */ + LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); + + /*---------------------------- USART CR3 Configuration ----------------------- + * Configure USARTx CR3 (Hardware Flow Control) with parameters: + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. + */ + LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); + + /*---------------------------- USART BRR Configuration ----------------------- + * Retrieve Clock frequency used for USART Peripheral + */ + LL_RCC_GetSystemClocksFreq(&rcc_clocks); + if (USARTx == USART1) + { + periphclk = rcc_clocks.PCLK2_Frequency; + } + else if (USARTx == USART2) + { + periphclk = rcc_clocks.PCLK1_Frequency; + } +#if defined(USART3) + else if (USARTx == USART3) + { + periphclk = rcc_clocks.PCLK1_Frequency; + } +#endif /* USART3 */ +#if defined(UART4) + else if (USARTx == UART4) + { + periphclk = rcc_clocks.PCLK1_Frequency; + } +#endif /* UART4 */ +#if defined(UART5) + else if (USARTx == UART5) + { + periphclk = rcc_clocks.PCLK1_Frequency; + } +#endif /* UART5 */ + else + { + /* Nothing to do, as error code is already assigned to ERROR value */ + } + + /* Configure the USART Baud Rate : + - valid baud rate value (different from 0) is required + - Peripheral clock as returned by RCC service, should be valid (different from 0). + */ + if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + && (USART_InitStruct->BaudRate != 0U)) + { + status = SUCCESS; +#if defined(USART_CR1_OVER8) + LL_USART_SetBaudRate(USARTx, + periphclk, + USART_InitStruct->OverSampling, + USART_InitStruct->BaudRate); +#else + LL_USART_SetBaudRate(USARTx, + periphclk, + USART_InitStruct->BaudRate); +#endif /* USART_OverSampling_Feature */ + } + } + /* Endif (=> USART not in Disabled state => return ERROR) */ + + return (status); +} + +/** + * @brief Set each @ref LL_USART_InitTypeDef field to default value. + * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) +{ + /* Set USART_InitStruct fields to default values */ + USART_InitStruct->BaudRate = 9600U; + USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; + USART_InitStruct->StopBits = LL_USART_STOPBITS_1; + USART_InitStruct->Parity = LL_USART_PARITY_NONE ; + USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX; + USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE; +#if defined(USART_CR1_OVER8) + USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16; +#endif /* USART_OverSampling_Feature */ +} + +/** + * @brief Initialize USART Clock related settings according to the + * specified parameters in the USART_ClockInitStruct. + * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), + * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param USARTx USART Instance + * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * that contains the Clock configuration information for the specified USART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content + * - ERROR: Problem occurred during USART Registers initialization + */ +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check USART Instance and Clock signal output parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput)); + + /* USART needs to be in disabled state, in order to be able to configure some bits in + CRx registers */ + if (LL_USART_IsEnabled(USARTx) == 0U) + { + /*---------------------------- USART CR2 Configuration -----------------------*/ + /* If Clock signal has to be output */ + if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) + { + /* Deactivate Clock signal delivery : + * - Disable Clock Output: USART_CR2_CLKEN cleared + */ + LL_USART_DisableSCLKOutput(USARTx); + } + else + { + /* Ensure USART instance is USART capable */ + assert_param(IS_USART_INSTANCE(USARTx)); + + /* Check clock related parameters */ + assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Clock signal related bits) with parameters: + * - Enable Clock Output: USART_CR2_CLKEN set + * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value + * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value + * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. + */ + MODIFY_REG(USARTx->CR2, + USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | + USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); + } + } + /* Else (USART not in Disabled state => return ERROR */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. + * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + /* Set LL_USART_ClockInitStruct fields with default values */ + USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; + USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usart.h new file mode 100644 index 00000000000..00983287a16 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usart.h @@ -0,0 +1,2589 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_usart.h + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_USART_H +#define __STM32F1xx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets*/ +#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ + +#if defined(USART_CR1_OVER8) + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ + +#endif /* USART_OverSampling_Feature */ +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_SR_PE USART_SR_PE /*!< Parity error flag */ +#define LL_USART_SR_FE USART_SR_FE /*!< Framing error flag */ +#define LL_USART_SR_NE USART_SR_NE /*!< Noise detected flag */ +#define LL_USART_SR_ORE USART_SR_ORE /*!< Overrun error flag */ +#define LL_USART_SR_IDLE USART_SR_IDLE /*!< Idle line detected flag */ +#define LL_USART_SR_RXNE USART_SR_RXNE /*!< Read data register not empty flag */ +#define LL_USART_SR_TC USART_SR_TC /*!< Transmission complete flag */ +#define LL_USART_SR_TXE USART_SR_TXE /*!< Transmit data register empty flag */ +#define LL_USART_SR_LBD USART_SR_LBD /*!< LIN break detection flag */ +#define LL_USART_SR_CTS USART_SR_CTS /*!< CTS flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +#if defined(USART_CR1_OVER8) +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +#endif /* USART_OverSampling_Feature */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__))) +#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100) +#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ + ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \ + (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__))) +#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100) +#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100) +/* USART BRR = mantissa + overflow + fraction + = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \ + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_SR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +#if defined(USART_CR1_OVER8) +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +#endif /* USART_OverSampling_Feature */ +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @rmtoll CR2 ADD LL_USART_SetNodeAddress + * @param USARTx USART Instance + * @param NodeAddress 4 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD)); +} + +/** + * @brief Return 4 bit Address of the USART node as set in ADD field of CR2. + * @note only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +#if defined(USART_CR3_ONEBIT) +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); +} +#endif /* USART_OneBitSampling_Feature */ + +#if defined(USART_CR1_OVER8) +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, + uint32_t BaudRate) +{ + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) +{ + register uint32_t usartdiv = 0x0U; + register uint32_t brrresult = 0x0U; + + usartdiv = USARTx->BRR; + + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + if ((usartdiv & 0xFFF7U) != 0U) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + brrresult = (PeriphClk * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = PeriphClk / usartdiv; + } + } + return (brrresult); +} +#else +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t BaudRate) +{ + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk) +{ + register uint32_t usartdiv = 0x0U; + register uint32_t brrresult = 0x0U; + + usartdiv = USARTx->BRR; + + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = PeriphClk / usartdiv; + } + return (brrresult); +} +#endif /* USART_OverSampling_Feature */ + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); +} + +/** + * @brief Enable Smartcard mode + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll SR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE)); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll SR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE)); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll SR NF LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE)); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll SR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE)); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll SR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE)); +} + +/** + * @brief Check if the USART Read Data Register Not Empty Flag is set or not + * @rmtoll SR RXNE LL_USART_IsActiveFlag_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE)); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll SR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC)); +} + +/** + * @brief Check if the USART Transmit Data Register Empty Flag is set or not + * @rmtoll SR TXE LL_USART_IsActiveFlag_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE)); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll SR LBD LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD)); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS)); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll CR1 SBK LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK)); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll CR1 RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU)); +} + +/** + * @brief Clear Parity Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * NE, FE, ORE, IDLE would also be cleared. + * @rmtoll SR PE LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Framing Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, ORE, IDLE would also be cleared. + * @rmtoll SR FE LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Noise detected Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, FE, ORE, IDLE would also be cleared. + * @rmtoll SR NF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear OverRun Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, FE, IDLE would also be cleared. + * @rmtoll SR ORE LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear IDLE line detected Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, FE, ORE would also be cleared. + * @rmtoll SR IDLE LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll SR TC LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR , ~(USART_SR_TC)); +} + +/** + * @brief Clear RX Not Empty Flag + * @rmtoll SR RXNE LL_USART_ClearFlag_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR , ~(USART_SR_RXNE)); +} + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll SR LBD LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR , ~(USART_SR_LBD)); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll SR CTS LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR , ~(USART_SR_CTS)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Enable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Enable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Disable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Disable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); +} + +/** + * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); +} + +/** + * @brief Check if the USART TX Empty Interrupt is enabled or disabled. + * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll DR DR LL_USART_DMA_GetRegAddr + * @note Address of Data Register is valid for both Transmit and Receive transfers. + * @param USARTx USART Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) +{ + /* return address of DR register */ + return ((uint32_t) &(USARTx->DR)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll DR DR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR)); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll DR DR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll DR DR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->DR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll DR DR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->DR = Value & 0x1FFU; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request Break sending + * @rmtoll CR1 SBK LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_SBK); +} + +/** + * @brief Put USART in Mute mode + * @rmtoll CR1 RWU LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RWU); +} + +/** + * @brief Put USART in Active mode + * @rmtoll CR1 RWU LL_USART_RequestExitMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RWU); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_USART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.c index a698106e451..7cf32611ee7 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_usb.c * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following @@ -123,6 +123,9 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); */ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(cfg); + /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; @@ -177,7 +180,7 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeD { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; } - else if ( mode == USB_DEVICE_MODE) + else if (mode == USB_DEVICE_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; } @@ -276,7 +279,7 @@ HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; } - + if (cfg.vbus_sensing_enable == ENABLE) { USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); @@ -297,7 +300,7 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num ) { uint32_t count = 0; - USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)(num << 6)); do { @@ -346,6 +349,9 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + USBx_DEVICE->DCFG |= speed; return HAL_OK; } @@ -361,7 +367,9 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { uint8_t speed = 0; - + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ)) { @@ -383,6 +391,9 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + if (ep->is_in) { /* Assign a Tx FIFO */ @@ -397,7 +408,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy if (ep->is_in == 1) { USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); - + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) { USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ @@ -426,6 +437,9 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + /* Read DEPCTLn register */ if (ep->is_in == 1) { @@ -451,7 +465,9 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) { uint16_t pktcnt = 0; - + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + /* IN endpoint */ if (ep->is_in == 1) { @@ -557,6 +573,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe */ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + /* IN endpoint */ if (ep->is_in == 1) { @@ -630,7 +649,9 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) { uint32_t count32b = 0 , index = 0; - + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + count32b = (len + 3) / 4; for (index = 0; index < count32b; index++, src += 4) { @@ -651,7 +672,9 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { uint32_t index = 0; uint32_t count32b = (len + 3) / 4; - + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + for ( index = 0; index < count32b; index++, dest += 4 ) { *(__packed uint32_t *)dest = USBx_DFIFO(0); @@ -668,6 +691,9 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) */ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + if (ep->is_in == 1) { if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0) @@ -695,6 +721,9 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef */ HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + if (ep->is_in == 1) { USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; @@ -752,6 +781,9 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(address); USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD); USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD; @@ -765,6 +797,9 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t addre */ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; HAL_Delay(3); @@ -778,6 +813,9 @@ HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; HAL_Delay(3); @@ -806,6 +844,9 @@ uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) { uint32_t tmpreg = 0; + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + tmpreg = USBx_DEVICE->DAINT; tmpreg &= USBx_DEVICE->DAINTMSK; return ((tmpreg & 0xffff0000) >> 16); @@ -819,6 +860,9 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) { uint32_t tmpreg = 0; + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + tmpreg = USBx_DEVICE->DAINT; tmpreg &= USBx_DEVICE->DAINTMSK; return ((tmpreg & 0xFFFF)); @@ -833,6 +877,9 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) */ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + uint32_t tmpreg = 0; tmpreg = USBx_OUTEP(epnum)->DOEPINT; tmpreg &= USBx_DEVICE->DOEPMSK; @@ -849,7 +896,9 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) { uint32_t tmpreg = 0, msk = 0, emp = 0; - + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + msk = USBx_DEVICE->DIEPMSK; emp = USBx_DEVICE->DIEPEMPMSK; msk |= ((emp >> epnum) & 0x1) << 7; @@ -878,6 +927,9 @@ void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) */ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + return ((USBx->GINTSTS ) & 0x1); } @@ -888,6 +940,8 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); /* Set the MPS of the IN EP based on the enumeration speed */ USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; @@ -908,6 +962,9 @@ HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(psetup); USBx_OUTEP(0)->DOEPTSIZ = 0; USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8); @@ -999,6 +1056,9 @@ HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef */ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS); @@ -1023,7 +1083,9 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) { __IO uint32_t hprt0 = 0; - + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + hprt0 = USBx_HPRT0; hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ @@ -1046,7 +1108,9 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) { __IO uint32_t hprt0 = 0; - + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + hprt0 = USBx_HPRT0; hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); @@ -1073,7 +1137,9 @@ HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) { __IO uint32_t hprt0 = 0; - + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + hprt0 = USBx_HPRT0; return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); } @@ -1085,6 +1151,9 @@ uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) */ uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); } @@ -1292,6 +1361,9 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe */ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + return ((USBx_HOST->HAINT) & 0xFFFF); } @@ -1305,9 +1377,12 @@ uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) { uint32_t count = 0; - + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + /* Check for space in the request queue to issue the halt. */ - if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18))) + if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) || + (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK))) { USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; @@ -1368,7 +1443,9 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) { uint8_t num_packets = 1; uint32_t tmpreg = 0; - + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ USB_OTG_HCTSIZ_DOPING; @@ -1442,6 +1519,8 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) { /* active Remote wakeup signalling */ @@ -1457,6 +1536,8 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); /* active Remote wakeup signalling */ USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); return HAL_OK; @@ -1477,6 +1558,9 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(cfg); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -1496,7 +1580,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) /* Set winterruptmask variable */ winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ - | USB_CNTR_ESOFM | USB_CNTR_RESETM; + | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM; /* Set interrupt mask */ USBx->CNTR |= winterruptmask; @@ -1534,6 +1618,9 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(mode); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -1550,7 +1637,10 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) * @retval HAL status */ HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) -{ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(cfg); + /* Init Device */ /*CNTR_FRES = 1*/ USBx->CNTR = USB_CNTR_FRES; @@ -1563,6 +1653,9 @@ HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) /*Set Btable Address*/ USBx->BTABLE = BTABLE_ADDRESS; + + /* Enable USB Device Interrupt mask */ + USB_EnableGlobalInt(USBx); return HAL_OK; } @@ -1575,8 +1668,11 @@ HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) 15 means Flush all Tx FIFOs * @retval HAL status */ -HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) +HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(num); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -1591,6 +1687,8 @@ HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) */ HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -1832,6 +1930,11 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(src); + UNUSED(ch_ep_num); + UNUSED(len); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -1849,6 +1952,10 @@ HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep */ void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(dest); + UNUSED(len); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -1948,6 +2055,8 @@ HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address) */ HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -1962,6 +2071,8 @@ HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) */ HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -1989,6 +2100,8 @@ uint32_t USB_ReadInterrupts (USB_TypeDef *USBx) */ uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -2003,6 +2116,8 @@ uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) */ uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -2019,6 +2134,9 @@ uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) */ uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(epnum); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -2035,6 +2153,9 @@ uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) */ uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(epnum); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -2050,6 +2171,9 @@ uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) */ void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(interrupt); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. @@ -2064,6 +2188,9 @@ void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt) */ HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(USBx); + UNUSED(psetup); /* NOTE : - This function is not required by USB Device FS peripheral, it is used only by USB OTG FS peripheral. - This function is added to ensure compatibility across platforms. diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.h index 03adbeae2ae..4538acba4c0 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_usb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_usb.h * @author MCD Application Team - * @version V1.0.5 - * @date 06-December-2016 + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of USB Low Layer HAL module. ****************************************************************************** * @attention diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.c index 9d68c2df4ad..91e071a15b7 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_utils.c * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief UTILS LL module driver. ****************************************************************************** * @attention @@ -128,7 +128,7 @@ || ((__VALUE__) == LL_RCC_PLL_MUL_16)) #endif /* RCC_CFGR_PLLMULL6_5 */ -#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT) +#if defined(RCC_CFGR2_PREDIV1) #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \ ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \ ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \ @@ -475,13 +475,13 @@ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTIL assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); /* Check different PLL parameters according to RM */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); -#elif defined (RCC_PREDIV1_DIV_2_16_SUPPORT) +#if defined (RCC_CFGR2_PREDIV1) pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul); +#elif defined(RCC_CFGR2_PREDIV1SRC) + pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); #else pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul); -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ +#endif /*RCC_CFGR2_PREDIV1SRC*/ assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); return pllfreq; @@ -512,14 +512,14 @@ static ErrorStatus UTILS_PLL_IsBusy(void) } #endif /* RCC_PLL2_SUPPORT */ -#if defined(RCC_PLL3_SUPPORT) - /* Check if PLL3 is busy*/ - if (LL_RCC_PLL3_IsReady() != 0U) +#if defined(RCC_PLLI2S_SUPPORT) + /* Check if PLLI2S is busy*/ + if (LL_RCC_PLLI2S_IsReady() != 0U) { - /* PLL3 configuration cannot be modified */ + /* PLLI2S configuration cannot be modified */ status = ERROR; } -#endif /* RCC_PLL3_SUPPORT */ +#endif /* RCC_PLLI2S_SUPPORT */ return status; } @@ -536,14 +536,18 @@ static ErrorStatus UTILS_PLL_IsBusy(void) static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) { ErrorStatus status = SUCCESS; +#if defined(FLASH_ACR_LATENCY) uint32_t sysclk_frequency_current = 0U; +#endif /* FLASH_ACR_LATENCY */ assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); +#if defined(FLASH_ACR_LATENCY) /* Calculate current SYSCLK frequency */ - sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]); + sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]); +#endif /* FLASH_ACR_LATENCY */ /* Increasing the number of wait states because of higher CPU frequency */ #if defined (FLASH_ACR_LATENCY) diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.h index c9a65233a7e..1ac615c853d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_utils.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f1xx_ll_utils.h * @author MCD Application Team - * @version $VERSION$ - * @date $DATE$ + * @version V1.1.0 + * @date 14-April-2017 * @brief Header file of UTILS LL module. @verbatim ============================================================================== diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_wwdg.h new file mode 100644 index 00000000000..7330ac806af --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_wwdg.h @@ -0,0 +1,342 @@ +/** + ****************************************************************************** + * @file stm32f1xx_ll_wwdg.h + * @author MCD Application Team + * @version V1.1.0 + * @date 14-April-2017 + * @brief Header file of WWDG LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F1xx_LL_WWDG_H +#define __STM32F1xx_LL_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f1xx.h" + +/** @addtogroup STM32F1xx_LL_Driver + * @{ + */ + +#if defined (WWDG) + +/** @defgroup WWDG_LL WWDG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants + * @{ + */ + + +/** @defgroup WWDG_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions + * @{ + */ +#define LL_WWDG_CFR_EWI WWDG_CFR_EWI +/** + * @} + */ + +/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER +* @{ +*/ +#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros + * @{ + */ +/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in WWDG register + * @param __INSTANCE__ WWDG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in WWDG register + * @param __INSTANCE__ WWDG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions + * @{ + */ + +/** @defgroup WWDG_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable Window Watchdog. The watchdog is always disabled after a reset. + * @note It is enabled by setting the WDGA bit in the WWDG_CR register, + * then it cannot be disabled again except by a reset. + * This bit is set by software and only cleared by hardware after a reset. + * When WDGA = 1, the watchdog can generate a reset. + * @rmtoll CR WDGA LL_WWDG_Enable + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) +{ + SET_BIT(WWDGx->CR, WWDG_CR_WDGA); +} + +/** + * @brief Checks if Window Watchdog is enabled + * @rmtoll CR WDGA LL_WWDG_IsEnabled + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)); +} + +/** + * @brief Set the Watchdog counter value to provided value (7-bits T[6:0]) + * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset + * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles + * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) + * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled) + * @rmtoll CR T LL_WWDG_SetCounter + * @param WWDGx WWDG Instance + * @param Counter 0..0x7F (7 bit counter value) + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) +{ + MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter); +} + +/** + * @brief Return current Watchdog Counter Value (7 bits counter value) + * @rmtoll CR T LL_WWDG_GetCounter + * @param WWDGx WWDG Instance + * @retval 7 bit Watchdog Counter value + */ +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) +{ + return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T)); +} + +/** + * @brief Set the time base of the prescaler (WDGTB). + * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter + * is decremented every (4096 x 2expWDGTB) PCLK cycles + * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler + * @param WWDGx WWDG Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler) +{ + MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler); +} + +/** + * @brief Return current Watchdog Prescaler Value + * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler + * @param WWDGx WWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + */ +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) +{ + return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); +} + +/** + * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]). + * @note This window value defines when write in the WWDG_CR register + * to program Watchdog counter is allowed. + * Watchdog counter value update must occur only when the counter value + * is lower than the Watchdog window register value. + * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value + * (in the control register) is refreshed before the downcounter has reached + * the watchdog window register value. + * Physically is possible to set the Window lower then 0x40 but it is not recommended. + * To generate an immediate reset, it is possible to set the Counter lower than 0x40. + * @rmtoll CFR W LL_WWDG_SetWindow + * @param WWDGx WWDG Instance + * @param Window 0x00..0x7F (7 bit Window value) + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) +{ + MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window); +} + +/** + * @brief Return current Watchdog Window Value (7 bits value) + * @rmtoll CFR W LL_WWDG_GetWindow + * @param WWDGx WWDG Instance + * @retval 7 bit Watchdog Window value + */ +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) +{ + return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W)); +} + +/** + * @} + */ + +/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ +/** + * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not. + * @note This bit is set by hardware when the counter has reached the value 0x40. + * It must be cleared by software by writing 0. + * A write of 1 has no effect. This bit is also set if the interrupt is not enabled. + * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)); +} + +/** + * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF) + * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx) +{ + WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF); +} + +/** + * @} + */ + +/** @defgroup WWDG_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable the Early Wakeup Interrupt. + * @note When set, an interrupt occurs whenever the counter reaches value 0x40. + * This interrupt is only cleared by hardware after a reset + * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) +{ + SET_BIT(WWDGx->CFR, WWDG_CFR_EWI); +} + +/** + * @brief Check if Early Wakeup Interrupt is enabled + * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WWDG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F1xx_LL_WWDG_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F1/serial_api.c b/targets/TARGET_STM/TARGET_STM32F1/serial_api.c index 8d7940508f4..cf0df17d7cb 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/serial_api.c +++ b/targets/TARGET_STM/TARGET_STM32F1/serial_api.c @@ -158,19 +158,19 @@ void serial_free(serial_t *obj) // Reset UART and disable clock if (obj_s->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); + __HAL_RCC_USART1_FORCE_RESET(); + __HAL_RCC_USART1_RELEASE_RESET(); + __HAL_RCC_USART1_CLK_DISABLE(); } if (obj_s->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); + __HAL_RCC_USART2_FORCE_RESET(); + __HAL_RCC_USART2_RELEASE_RESET(); + __HAL_RCC_USART2_CLK_DISABLE(); } if (obj_s->uart == UART_3) { - __USART3_FORCE_RESET(); - __USART3_RELEASE_RESET(); - __USART3_CLK_DISABLE(); + __HAL_RCC_USART3_FORCE_RESET(); + __HAL_RCC_USART3_RELEASE_RESET(); + __HAL_RCC_USART3_CLK_DISABLE(); } // Configure GPIOs @@ -750,10 +750,10 @@ void serial_tx_abort_asynch(serial_t *obj) // reset states huart->TxXferCount = 0; // update handle state - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { - huart->State = HAL_UART_STATE_BUSY_RX; + if(huart->gState == HAL_UART_STATE_BUSY_TX_RX) { + huart->gState = HAL_UART_STATE_BUSY_RX; } else { - huart->State = HAL_UART_STATE_READY; + huart->gState = HAL_UART_STATE_READY; } } @@ -780,10 +780,10 @@ void serial_rx_abort_asynch(serial_t *obj) // reset states huart->RxXferCount = 0; // update handle state - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) { - huart->State = HAL_UART_STATE_BUSY_TX; + if(huart->RxState == HAL_UART_STATE_BUSY_TX_RX) { + huart->RxState = HAL_UART_STATE_BUSY_TX; } else { - huart->State = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; } } diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PeripheralPins.c index 74561a1e979..9e2f6a80f00 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PeripheralPins.c @@ -57,8 +57,8 @@ const PinMap PinMap_ADC[] = { {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 // choice: PA_5 with ADC_1 {PA_6_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // choice: PA_6 with ADC_2 {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 -// {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Ethernet RMII RX Data Valid -// {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Ethernet RMII RX Data Valid + {PA_7_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Ethernet RMII RX Data Valid - used when JP6 ON - choice: PA_7 with ADC_2 + {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Ethernet RMII RX Data Valid - used when JP6 ON - choice: PA_7 with ADC_2 // {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // LED1 // {PB_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // LED1 {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 @@ -142,10 +142,10 @@ const PinMap PinMap_PWM[] = { {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 {PA_6_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // choice: PA_6 with PWM_13 -// {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Ethernet RMII RX Data Valid -// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Ethernet RMII RX Data Valid -// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Ethernet RMII RX Data Valid -// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Ethernet RMII RX Data Valid + {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Ethernet RMII RX Data Valid - used when JP6 ON - choice: PA_7 with PWM_14 + {PA_7_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Ethernet RMII RX Data Valid - used when JP6 ON - choice: PA_7 with PWM_14 + {PA_7_ALT1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Ethernet RMII RX Data Valid - used when JP6 ON - choice: PA_7 with PWM_14 + {PA_7_ALT2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Ethernet RMII RX Data Valid - used when JP6 ON - choice: PA_7 with PWM_14 // {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // USB SOF // {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // USB VBUS // {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // USB ID @@ -263,8 +263,10 @@ const PinMap PinMap_UART_CTS[] = { //*** SPI *** const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Ethernet RMII RX Data Valid // D11 - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Ethernet RMII RX Data Valid - used when JP6 ON - ARDUINO D11 (default configuration) + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files // {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // choice: PB_5 with SPI_1 {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h index a2be4910002..71ae5402e34 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/PinNames.h @@ -58,6 +58,9 @@ typedef enum { PA_6 = 0x06, PA_6_ALT0 = 0x06|ALT0, PA_7 = 0x07, + PA_7_ALT0 = 0x07|ALT0, + PA_7_ALT1 = 0x07|ALT1, + PA_7_ALT2 = 0x07|ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -218,7 +221,7 @@ typedef enum { D8 = PF_12, D9 = PD_15, D10 = PD_14, - D11 = PA_7, + D11 = STM32_D11_SPI_ETHERNET_PIN, /* config in targets.json file */ D12 = PA_6, D13 = PA_5, D14 = PB_9, diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd.h index afc7234c16c..624dc3bd9bd 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd.h @@ -232,7 +232,7 @@ typedef struct * @{ */ #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) &= (uint16_t)(~(__INTERRUPT__)))) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) = (uint16_t)(~(__INTERRUPT__)))) // MBED fix #define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE #define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE) @@ -622,9 +622,9 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @retval None */ #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK)) + ( PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_CTR_TX ) & ~USB_EP_CTR_RX & USB_EPREG_MASK)) // MBED fix #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\ - PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK)) + ( PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_CTR_RX ) & ~USB_EP_CTR_TX & USB_EPREG_MASK)) // MBED fix /** * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralPins.c index 84644dd9599..615052deff4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PeripheralPins.c @@ -57,8 +57,8 @@ const PinMap PinMap_ADC[] = { // {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - ARDUINO D13 {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - ARDUINO D12 // {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - ARDUINO D12 -// {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 (pin used by ethernet when JP6 ON) - ARDUINO D11 - {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (pin used by ethernet when JP6 ON) - ARDUINO D11 +// {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) + {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) // {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 (pin used by LED1) // {PB_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 (pin used by LED1) {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 @@ -140,12 +140,12 @@ const PinMap PinMap_PWM[] = { // {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - ARDUINO A0 // {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - ARDUINO D13 {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - ARDUINO D13 -// {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - ARDUINO D12 +// {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - ARDUINO D12 {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO D12 - {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (pin used by ethernet when JP6 ON) - ARDUINO D11 -// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 -// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (pin used by ethernet when JP6 ON) - ARDUINO D11 -// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 + {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) +// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) +// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 (pin used by usb) // {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 (pin used by usb) @@ -159,7 +159,9 @@ const PinMap PinMap_PWM[] = { {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 (pin used by LED2) // {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - ARDUINO D15 @@ -268,8 +270,10 @@ const PinMap PinMap_UART_CTS[] = { //*** SPI *** const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // (pin used by ethernet when JP6 ON) - ARDUINO D11 - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // pin used by ethernet when JP6 ON - ARDUINO D11 (default configuration) + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files // {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO A2 @@ -330,7 +334,9 @@ const PinMap PinMap_CAN_RD[] = { {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h index 5b1c1b4ab87..85cb275a6fe 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h @@ -183,7 +183,7 @@ typedef enum { D8 = PF_12, D9 = PD_15, D10 = PD_14, - D11 = PA_7, + D11 = STM32_D11_SPI_ETHERNET_PIN, /* config in targets.json file */ D12 = PA_6, D13 = PA_5, D14 = PB_9, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf index 94c7d061c01..8dcb1a8fea4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/stm32f429xx_flash.icf @@ -15,8 +15,8 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF; define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF; /*-Sizes-*/ -/*Heap 64K and stack 24K */ -define symbol __ICFEDIT_size_cstack__ = 0x6000; +/*Heap 64K and stack 4K */ +define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_heap__ = 0x10000; /**** End of ICF editor section. ###ICF###*/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralPins.c index 84644dd9599..615052deff4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PeripheralPins.c @@ -57,8 +57,8 @@ const PinMap PinMap_ADC[] = { // {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - ARDUINO D13 {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - ARDUINO D12 // {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - ARDUINO D12 -// {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 (pin used by ethernet when JP6 ON) - ARDUINO D11 - {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (pin used by ethernet when JP6 ON) - ARDUINO D11 +// {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) + {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) // {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 (pin used by LED1) // {PB_0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 (pin used by LED1) {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 @@ -140,12 +140,12 @@ const PinMap PinMap_PWM[] = { // {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 - ARDUINO A0 // {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - ARDUINO D13 {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - ARDUINO D13 -// {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - ARDUINO D12 +// {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - ARDUINO D12 {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO D12 - {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (pin used by ethernet when JP6 ON) - ARDUINO D11 -// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 -// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (pin used by ethernet when JP6 ON) - ARDUINO D11 -// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 + {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) +// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) +// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) +// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (pin used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 (pin used by usb) // {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 (pin used by usb) @@ -159,7 +159,9 @@ const PinMap PinMap_PWM[] = { {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 (pin used by LED2) // {PB_8, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 - ARDUINO D15 @@ -268,8 +270,10 @@ const PinMap PinMap_UART_CTS[] = { //*** SPI *** const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // (pin used by ethernet when JP6 ON) - ARDUINO D11 - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // pin used by ethernet when JP6 ON - ARDUINO D11 (default configuration) + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files // {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO A2 @@ -330,7 +334,9 @@ const PinMap PinMap_CAN_RD[] = { {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h index 5b1c1b4ab87..85cb275a6fe 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h @@ -183,7 +183,7 @@ typedef enum { D8 = PF_12, D9 = PD_15, D10 = PD_14, - D11 = PA_7, + D11 = STM32_D11_SPI_ETHERNET_PIN, /* config in targets.json file */ D12 = PA_6, D13 = PA_5, D14 = PB_9, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar index dd60053c00c..02bb74ed986 100644 Binary files a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar and b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar differ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a index 1925def5733..bfac450c732 100644 Binary files a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a and b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a differ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a index 63914a7e5e5..eff3e49dddf 100644 Binary files a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a and b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a differ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h index eef737b63ba..24be80d57af 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h @@ -18,20 +18,26 @@ #define ODIN_WIFI_INTERFACE_H #include "WiFiInterface.h" -#include "Callback.h" -#include "mbed_events.h" - -#include "rtos.h" -#include "cmsis_os.h" #include "emac_api.h" + +#include "mbed.h" +#include "netsocket/WiFiAccessPoint.h" #include "nsapi_types.h" #include "lwip/netif.h" +#include "rtos.h" +#include "cb_wlan.h" -typedef Queue MsgQueue; - -class OdinWiFiInterface; +#define ODIN_WIFI_MAX_MAC_ADDR_STR (18) +#define ODIN_WIFI_SCAN_CACHE_SIZE (5) -struct PrivContext; +struct odin_wifi_msg_s; +struct user_connect_s; +struct user_scan_s; +struct user_ap_start_s; +struct wlan_status_started_s; +struct wlan_status_connected_s; +struct wlan_status_connection_failure_s; +struct wlan_scan_indication_s; /** OdinWiFiInterface class * Implementation of the WiFiInterface for the ODIN-W2 module @@ -74,7 +80,8 @@ class OdinWiFiInterface : public WiFiInterface * @param channel Channel on which the connection is to be made, or 0 for any (Default: 0) * @return 0 on success, or error code on failure */ - virtual nsapi_error_t connect(const char *ssid, + virtual nsapi_error_t connect( + const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE, uint8_t channel = 0); @@ -115,7 +122,7 @@ class OdinWiFiInterface : public WiFiInterface /** Get the local network mask * * @return Null-terminated representation of the local network mask - * or null if no network mask has been recieved + * or null if no network mask has been received */ virtual const char *get_netmask(); @@ -177,44 +184,161 @@ class OdinWiFiInterface : public WiFiInterface * specified since the Wi-Fi driver might need some time to finish and cleanup. * @return 0 on success, negative error code on failure */ - virtual void set_timeout(int timeout); + virtual nsapi_error_t set_timeout(int ms); virtual NetworkStack *get_stack(); protected: private: - - nsapi_error_t connect_async(const char *ssid, - const char *pass, - nsapi_security_t security = NSAPI_SECURITY_NONE, - uint8_t channel = 0, - void *data = NULL, - unsigned timeout = 0); - - bool start(bool debug); - bool stop(); - - char _mac_addr_str[18]; - // Private context to share between C and C++ calls - PrivContext* _priv_context; - const char *_ssid; - const char *_pass; - char _ip_address[IPADDR_STRLEN_MAX]; - char _netmask[IPADDR_STRLEN_MAX]; - char _gateway[IPADDR_STRLEN_MAX]; - nsapi_security_t _security; - uint8_t _channel; - bool _use_dhcp; - int _timeout; - // Event queue when the driver context need to be used - EventQueue* _odin_event_queue; - int32_t target_id; - // Event queue for sending start up and connection events from driver to this class - MsgQueue _event_queue; - // Message queue for sending scan events from driver to this class - osMessageQId _scan_msg_queue_id; - osMessageQDef_t _queue_def; + + enum OdinWifiState { + S_NOT_INITIALISED = 1, + S_WAIT_START, + S_STARTED, + S_WAIT_STOP, + + S_STA_IDLE, + S_STA_WAIT_CONNECT, + S_STA_CONNECTED, + S_STA_DISCONNECTED_WAIT_CONNECT, + S_STA_CONNECTION_FAIL_WAIT_DISCONNECT, + //S_STA_LINK_LOSS_WAIT_DISCONNECT, + S_STA_WAIT_DISCONNECT, + + S_AP_IDLE, + S_AP_WAIT_START, + S_AP_STARTED, + S_AP_WAIT_STOP, + S_AP_FAIL_WAIT_STOP, + S_AP_WAIT_DRV_STOP, + S_AP_WAIT_DRV_START, + + S_INVALID + }; + + struct sta_s { + const char *ssid; + const char *passwd; + nsapi_security_t security; + uint8_t channel; + bool use_dhcp; + int timeout_ms; + char ip_address[IPADDR_STRLEN_MAX]; + char netmask[IPADDR_STRLEN_MAX]; + char gateway[IPADDR_STRLEN_MAX]; + }; + + struct ap_s { + const char *ssid; + const char *passwd; + nsapi_security_t security; + uint8_t channel; + bool use_dhcp; + + char ip_address[IPADDR_STRLEN_MAX]; + char netmask[IPADDR_STRLEN_MAX]; + char gateway[IPADDR_STRLEN_MAX]; + + int cnt_connected; + + nsapi_error_t error_code; + }; + + struct scan_cache_s { + int count; + uint8_t last_channel; + cbWLAN_MACAddress bssid[ODIN_WIFI_SCAN_CACHE_SIZE]; + }; + + OdinWifiState entry_connect_fail_wait_disconnect(); + OdinWifiState entry_wait_connect(); + OdinWifiState entry_wait_disconnect(); + //OdinWifiState entry_link_loss_wait_disconnect(void); + OdinWifiState entry_ap_wait_start(); + OdinWifiState entry_ap_started(); + OdinWifiState entry_ap_wait_stop(); + OdinWifiState entry_ap_fail_wait_stop(); + OdinWifiState entry_ap_wait_drv_stop(); + OdinWifiState entry_ap_wait_drv_start(); + + void handle_in_msg(); + void handle_cached_msg(); + + void handle_user_connect(user_connect_s *user_connect); + void handle_user_disconnect(); + void handle_user_scan(user_scan_s *user_scan); + void handle_user_connect_timeout(); + void handle_user_stop(); + + void handle_user_ap_start(user_ap_start_s *user_ap_start); + void handle_user_ap_stop(); + + void handle_wlan_status_started(wlan_status_started_s *start); + void handle_wlan_status_stopped(void); + void handle_wlan_status_error(void); + void handle_wlan_status_connecting(void); + void handle_wlan_status_connected(wlan_status_connected_s *wlan_connect); + void handle_wlan_status_connection_failure(wlan_status_connection_failure_s *connect_failure); + void handle_wlan_status_disconnected(void); + void handle_wlan_scan_indication(); + + void handle_wlan_status_ap_up(); + void handle_wlan_status_ap_down(); + + void init(bool debug); + nsapi_error_t wlan_set_channel(uint8_t channel); + nsapi_error_t wlan_connect( + const char *ssid, + const char *passwd, + nsapi_security_t security); + nsapi_error_t wlan_ap_start( + const char *ssid, + const char *pass, + nsapi_security_t security, + uint8_t channel); + + void timeout_user_connect(); + void update_scan_list(cbWLAN_ScanIndicationInfo *scan_info); + void send_user_response_msg(unsigned int type, nsapi_error_t error_code); + void wlan_status_indication(cbWLAN_StatusIndicationInfo status, void *data); + void wlan_scan_indication(cbWLAN_ScanIndicationInfo *scan_info, cb_boolean is_last_result); + + static bool _wlan_initialized; // Controls that cbWLAN is initiated only once + static emac_interface_t* _emac; // Not possible to remove added interfaces to the network stack => static and re-use + static int32_t _target_id; + + OdinWifiState _state; + OdinWifiState _state_sta; + OdinWifiState _state_ap; + + struct sta_s _sta; + struct ap_s _ap; + nsapi_stack_t _stack; + char _mac_addr_str[ODIN_WIFI_MAX_MAC_ADDR_STR]; + + cbWLAN_StatusConnectedInfo _wlan_status_connected_info; + cbWLAN_StatusDisconnectedInfo _wlan_status_disconnected_info; + + bool _scan_active; + WiFiAccessPoint *_scan_list; + nsapi_size_t _scan_list_size; + nsapi_size_t _scan_list_cnt; + struct scan_cache_s _scan_cache; + + friend struct wlan_callb_s; + + Mutex _mutex; + Queue _in_queue; + Queue _out_queue; + Queue _cache_queue; + MemoryPool *_msg_pool; + Thread _thread; + //Timeout _timeout; //Randomly lost interrupts/callbacks; replaced by Timer + Timer _timer; + + bool _debug; + int _dbg_timeout; }; #endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h index 9a8b73ae367..d55b2a1f1a5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/bt_types.h @@ -1,5 +1,5 @@ /*--------------------------------------------------------------------------- - * Copyright (c) 2016, u-blox Malmĥ, All Rights Reserved + * Copyright (c) 2016, u-blox Malmö, All Rights Reserved * SPDX-License-Identifier: LicenseRef-PBL * * This file and the related binary are licensed under the @@ -65,6 +65,11 @@ #define PACKET_TYPE_ALL (PACKET_TYPE_DM1 | PACKET_TYPE_DH1 | PACKET_TYPE_DM3 | PACKET_TYPE_DH3 | PACKET_TYPE_DM5 | PACKET_TYPE_DH5) +#define BD_ADDR_IS_STATIC_RANDOM(BdAddress) ((BdAddress[0] & 0xC0) == 0xC0) +#define BD_ADDR_IS_NON_RESOLVABLE(BdAddress) ((BdAddress[0] & 0xC0) == 0x00) +#define BD_ADDR_IS_RESOLVABLE(BdAddress) ((BdAddress[0] & 0xC0) == 0x40) + +#define BT_INVALID_STATIC_LINK_KEY (0) /*=========================================================================== * TYPES *=========================================================================*/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h index 4fe40ca6956..8e402076b5a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_conn_man.h @@ -129,6 +129,17 @@ typedef struct cb_char serviceName[cbBCM_SERVICE_NAME_MAX_LEN]; } cbBCM_ConnectionInfo; +typedef struct +{ + cb_uint8 flags; /** Reserved for future use. */ + cb_uint8 flowDirection; /** 0x00 for Outgoing Flow and 0x01 for Incoming Flow */ + cb_uint8 serviceType; /** 0x00 No Traffic; 0x01 Best Effort; 0x02 Guaranteed */ + cb_uint32 tokenRate; /** Token Rate in octets per second */ + cb_uint32 tokenBucketSize; /** Token Bucket Size in octets */ + cb_uint32 peakBandwidth; /** Peak Bandwidth in octets per second */ + cb_uint32 latency; /** Latency in microseconds */ +} cbBCM_FlowSpecParams; + typedef void (*cbBCM_ConnectInd)( cbBCM_Handle handle, cbBCM_ConnectionInfo info); @@ -156,7 +167,7 @@ typedef struct typedef void(*cbBCM_RoleDiscoveryCallback)( cbBCM_Handle handle, cb_int8 status, - cb_int8 role); + cb_uint8 role); typedef void (*cbBCM_RssiCallback)( cbBCM_Handle handle, @@ -226,6 +237,13 @@ typedef void(*cbBCM_LinkQualityCallback)( cbBCM_LinkQualityEvt linkQualityEvt, uint8 linkQuality); +typedef void(*cbBCM_ServiceClassEnabled)(cb_uint8 serviceChannel); + +typedef void(*cbBCM_SetFlowSpecCallback)( + cb_uint8 status, + cbBCM_Handle handle, + cbBCM_FlowSpecParams parameters); + /*=========================================================================== * FUNCTIONS *=========================================================================*/ @@ -245,12 +263,14 @@ extern void cbBCM_init(void); * @param pServerChannel Pointer to return variable. The server channel is used to identify * incoming connections. * @param pConnectionCallback Callback structure for connection management. + * @param pServiceClassEnabled Callback structure to inform when service is running. * @return If the operation is successful cbBCM_OK is returned. */ extern cb_int32 cbBCM_enableServerProfileSpp( cb_char *pServiceName, cb_uint8 *pServerChannel, - cbBCM_ConnectionCallback *pConnectionCallback); + cbBCM_ConnectionCallback *pConnectionCallback, + cbBCM_ServiceClassEnabled pServiceClassEnabled); /** * Enable a Dial Up Networking Profile (DUN)service record to @@ -260,12 +280,14 @@ extern cb_int32 cbBCM_enableServerProfileSpp( * @param pServerChannel Pointer to return variable. The server channel is used to identify * incoming connections. * @param pConnectionCallback Callback structure for connection management. + * @param pServiceClassEnabled Callback structure to inform when service is running. * @return If the operation is successful cbBCM_OK is returned. */ extern cb_int32 cbBCM_enableServerProfileDun( cb_char *pServiceName, cb_uint8 *pServerChannel, - cbBCM_ConnectionCallback *pConnectionCallback); + cbBCM_ConnectionCallback *pConnectionCallback, + cbBCM_ServiceClassEnabled pServiceClassEnabled); /** * Enable a service record with an application specific UUID. @@ -276,13 +298,15 @@ extern cb_int32 cbBCM_enableServerProfileDun( * @param pServerChannel Pointer to return variable. The server channel is used to identify * incoming connections. * @param pConnectionCallback Callback structure for connection management. + * @param pServiceClassEnabled Callback structure to inform when service is running. * @return If the operation is successful cbBCM_OK is returned. */ extern cb_int32 cbBCM_enableServerProfileUuid128( cb_uint8 *pUuid128, cb_char *pServiceName, cb_uint8 *pServerChannel, - cbBCM_ConnectionCallback *pConnectionCallback); + cbBCM_ConnectionCallback *pConnectionCallback, + cbBCM_ServiceClassEnabled pServiceClassEnabled); /** @@ -295,12 +319,14 @@ extern cb_int32 cbBCM_enableServerProfileUuid128( * @param pServiceName The name of the service * @param role The PAN role of the local device * @param pConnectionCallback Callback structure for connection management. +* @param pServiceClassEnabled Callback structure to inform when service is running. * @return If the operation is successful cbBCM_OK is returned. */ extern cb_int32 cbBCM_enableServerProfilePan( cb_char *pServiceName, cbBCM_PAN_Role role, - cbBCM_ConnectionCallback *pConnectionCallback); + cbBCM_ConnectionCallback *pConnectionCallback, + cbBCM_ServiceClassEnabled pServiceClassEnabled); /** * Enable device id service record.The device id service record is a method by which @@ -393,7 +419,7 @@ extern cb_uint16 cbBCM_getMaxLinksLE(void); * @param serverChannel RFCOMM server channel that shall be used. Set to * cbBCM_INVALID_SERVER_CHANNEL to perform automatic * service search to find the server channel. - * @param pAclParameters Link configuration including link supervision timeout + * @param pAclParameters Link configuration including link supervision timeout * and master slave policy. Pass NULL to use default connection * parameters. * @param pConnectionCallback Callback structure for connection management. @@ -439,7 +465,7 @@ extern cb_int32 cbBCM_rspConnectSppCnf( * @param serverChannel RFCOMM server channel that shall be used. Set to * cbBCM_INVALID_SERVER_CHANNEL to perform automatic * service search to find the server channel. - * @param pAclParameters Link configuration including link supervision timeout + * @param pAclParameters Link configuration including link supervision timeout * and master slave policy. Pass NULL to use default connection * parameters. * @param pConnectionCallback Callback structure for connection management. @@ -457,7 +483,7 @@ extern cbBCM_Handle cbBCM_reqConnectDun( * Accept or reject an incoming DUN connection. This is a * response to a cbBCM_ConnectInd connection indication. * - * @param handle Connection handle + * @param handle Connection handle * @param accept TRUE to accept the incoming connection. FALSE to reject. * @return If the operation is successful cbBCM_OK is returned. @@ -505,7 +531,7 @@ extern cbBCM_Handle cbBCM_reqConnectUuid( * Accept or reject an incoming SPP connection. This is a * response to a cbBCM_ConnectInd connection indication. * - * @param handle Connection handle + * @param handle Connection handle * @param accept TRUE to accept the incoming connection. FALSE to reject. * @return If the operation is successful cbBCM_OK is returned. @@ -542,7 +568,7 @@ extern cbBCM_Handle cbBCM_reqConnectPan( * Accept or reject an incoming PAN connection. This is a * response to a cbBCM_ConnectInd connection indication. * -* @param handle Connection handle +* @param handle Connection handle * @param accept TRUE to accept the incoming connection. * FALSE to reject. * @return If the operation is successful cbBCM_OK is returned. @@ -604,7 +630,7 @@ extern cbBCM_Handle cbBCM_reqConnectSps( /** * Accept or reject an incoming SPS connection. This is a * response to a cbBCM_ConnectInd connection indication. - * @param handle Connection handle + * @param handle Connection handle * @param accept TRUE to accept the incoming connection. * FALSE to reject. * @return If the operation is successful cbBCM_OK is returned. @@ -813,10 +839,50 @@ extern cb_int32 cbBCM_registerDataCallback( extern cbBCM_Handle cbBCM_getProtocolHandle( cbBCM_Handle handle); +/** +* @brief Get the bcm id from acl handle for an active connection. +* +* @param handle Connection handle +* @return bcm handle. +*/ +extern cbBCM_Handle cbBCM_getIdFromAclHandle(TConnHandle aclHandle); + +/** +* @brief Get the acl handle from bcm handle. +* +* @param handle bcm handle +* @return acl handle +*/ +extern TConnHandle cbBCM_getAclFromIdHandle(cbBCM_Handle bcmHandle); +/** +* @brief This will send cbHCI_cmdFlowSpecification command for the specified link +* with the specified parameters. +* @param handle Connection handle +* @param parameters Flow Specification parameters. For details see Bluetooth Core +* Specification [Vol 3] Part A, Section 5.3 +* @param flowSpecCallback Callback contains the data in Flow Specification Complete event +* @return If the operation is successful cbBCM_OK is returned. +*/ +extern cb_int32 cbBCM_setFlowSpecification( + cbBCM_Handle handle, + cbBCM_FlowSpecParams parameters, + cbBCM_SetFlowSpecCallback flowSpecCallback); + +/** +* @brief Change which packet types can be used for the connection identified by the handle +* @param handle Connection handle +* @param aclPacketType bit map according to packet types defined in bt_types.h +* @return If the operation is successful cbBCM_OK is returned. +*/ +extern cb_int32 cbBCM_changeConnectionPacketType( + cbBCM_Handle handle, + TPacketType aclPacketType); + #ifdef __cplusplus } #endif + #endif /* _CB_BT_CONN_MAN_H_ */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h index 240081d526e..101c0e45ce0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_man.h @@ -141,6 +141,7 @@ typedef void (*cbBM_ChannelMapCallb)( TChannelMap *pChMap); typedef void (*cbBM_InitComplete)(void); +typedef void(*cbBM_LocalAddressCb)(void); typedef enum { @@ -149,6 +150,17 @@ typedef enum cbBM_LE_ROLE_PERIPHERAL = 2, } cbBM_LeRole; +typedef struct +{ + cb_uint8 flags; + cb_uint8 flowDirection; + cb_uint8 serviceType; + cb_uint32 tokenRate; + cb_uint32 tokenBucketSize; + cb_uint32 peakBandwidth; + cb_uint32 latency; +} cbBM_FlowSpecParams; + /** * Bluetooth Manager initialization parameters. */ @@ -157,12 +169,13 @@ typedef struct TBdAddr address; /** Bluetooth address that shall be assigned to controller. Pass invalidBdAddress to use controller default address*/ cbBM_LeRole leRole; /** Bluetooth low energy role */ cb_int8 maxOutputPower; /** Maximum output power. */ - cb_uint32 nvdsStartIdLinkKeysClassic; /** Start id for CLASSIC link keys storage in NVDS. */ - cb_uint32 maxLinkKeysClassic; /** Max number of CLASSIC link keys */ - cb_uint32 nvdsStartIdLinkKeysLe; /** Start id for BLE link keys storage in NVDS. */ - cb_uint32 maxLinkKeysLe; /** Max number of link keys BLE*/ + cb_int32 nvdsStartIdLinkKeysClassic; /** Start id for CLASSIC link keys storage in NVDS. */ + cb_int32 maxLinkKeysClassic; /** Max number of CLASSIC link keys */ + cb_int32 nvdsStartIdLinkKeysLe; /** Start id for BLE link keys storage in NVDS. */ + cb_int32 maxLinkKeysLe; /** Max number of link keys BLE*/ } cbBM_InitParams; +typedef void(*cbBM_ServiceEnabled)(cb_uint8 serviceChannel); /*=========================================================================== * FUNCTIONS *=========================================================================*/ @@ -184,12 +197,70 @@ extern void cbBM_init( cbBM_InitParams *pInitParameters, cbBM_InitComplete initCompleteCallback); +/** +* This function sets the default link supervision timeout. The specified timeout will +* apply for new connections. +* @param linkSupervisionTimeout timeout in milliseconds +* @return If the operation is successful cbBM_OK is returned. +*/ +extern cb_int32 cbBM_setLinkSupervisionTimeout( + cb_uint16 linkSupervisionTimeout); + +/** +* This function gets the default link supervision timeout. +* @return link supervision timeout in milliseconds. +*/ +extern cb_uint16 cbBM_getLinkSupervisionTimeout(void); + +/** +* This function enables or disables the fast connect feature (interlaced page scan). +* @param fastConnect +* @return cbBM_OK if in parameter is valid. +*/ +extern cb_int32 cbBM_setFastConnect( + cb_boolean fastConnect); +/** +* This function gets whether the fast connect feature is enabled or disabled. +* @return TRUE if feature is enabled +*/ +extern cb_boolean cbBM_getFastConnect(void); + +/** +* This function enables or disables the fast discovery feature (interlaced inquiry scan). +* @param fastDiscovery +* @return cbBM_OK if in parameter is valid. +*/ +extern cb_int32 cbBM_setFastDiscovery( + cb_boolean fastDiscovery); +/** +* This function gets whether the fast discovery feature is enabled or disabled. +* @return TRUE if feature is enabled +*/ +extern cb_boolean cbBM_getFastDiscovery(void); /** * This function sets all default parameters for LE. * This function needs to be called before the cbBM_init. */ extern void cbBM_setDefaultValuesLeParams(void); +/** +* This function executes HCI_cmdWrScanEnable command according to parameters. +* @param discoverableMode discoverable mode +* @param connectableMode connectable mode +* @return true if HCI command could be executed. +*/ +extern cb_int32 cbBM_updateScan( + cbBM_DiscoverableMode discoverableMode, + cbBM_ConnectableMode connectableMode); + +/** + * Get the current Bluetooth address of the device from radio. This can + * be a way to get a alive-message from the radio. + * + * @param callback to application when address has been read. + */ +extern void cbBM_checkRadioAlive(cbBM_LocalAddressCb callback); + /** * Get the current Bluetooth address of the device. * @param pAddress Pointer to return variable. @@ -335,9 +406,11 @@ extern cb_int32 cbBM_remoteName( * Add service class to inquiry response data. Typically * not used by the application. * @param uuid16 The UUID to add + * @param pCallback callback to indicate service is enabled. + * @param serviceChannel channel the service is started on. * @return If the operation is successful cbBM_OK is returned. */ -extern cb_int32 cbBM_addServiceClass(cb_uint16 uuid16); +extern cb_int32 cbBM_addServiceClass(cb_uint16 uuid16, cbBM_ServiceEnabled pCallback,cb_uint8 serviceChannel); /** * Check if service class is already registered. @@ -350,9 +423,11 @@ cb_boolean cbBM_isServiceClassRegistered(cb_uint16 uuid16 ); * Add service class to inquiry response data. Typically * not used by the application. * @param uuid128 The UUID to add. + * @param pCallback callback to indicate service is enabled. + * @param serviceChannel channel the service is started on. * @return If the operation is successful cbBM_OK is returned. */ -extern cb_int32 cbBM_add128BitsServiceClass(cb_uint8* uuid128); +extern cb_int32 cbBM_add128BitsServiceClass(cb_uint8* uuid128, cbBM_ServiceEnabled pCallback, cb_uint8 serviceChannel); /** * Set maximum Bluetooth Classic ACL links the stack @@ -521,7 +596,7 @@ extern cb_int32 cbBM_deviceDiscoveryLeCancel(void); /** * Perform a remote name request for Bluetooth Low Energy. * @param pAddress Pointer to address of remote device. - * @param remoteNameCallback Callback used to notify the the completion of the + * @param remoteNameCallback Callback used to notify the the completion of the * name request. * @return If the operation is successfully initiated cbBM_OK is returned. */ @@ -560,6 +635,9 @@ void cbBM_getConnectParameters(TAclParamsLe* aclParams); */ void cbBM_getRemoteNameReqParameters(TAclParamsLe* aclParams); + +cb_int32 cbBM_setForceClassicNotSupportedInAdv(cb_boolean enforceDisable); +cb_boolean cbBM_getForceClassicNotSupportedInAdv(void); /* * Sets the LE parameter. * @newValue new parameter value. diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h index cfc7e8cb885..4072c1168b7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_pan.h @@ -14,7 +14,7 @@ * See the License for the specific language governing permissions and * limitations under the License. * - * Component : Bluetooth Serial + * Component : Bluetooth PAN Data Manager * File : cb_bt_pan.h * * Description : Data management for PAN profile diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h index c6a38b49af7..f002fc45a5d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_sec_man.h @@ -346,7 +346,7 @@ extern cb_int32 cbBSM_getAllNumberBondedDevices( * @return If the operation is successful cbBSM_OK is returned. */ extern cb_int32 cbBSM_getBondedDevice( - uint32 deviceIndex, + cb_int32 deviceIndex, TBdAddr* pBdAddr, cb_boolean pIsLe); @@ -365,6 +365,14 @@ extern cb_int32 cbBSM_deleteBondedDevice(TBdAddr* pBdAddress); */ extern cb_int32 cbBSM_deleteAllBondedDevices(void); +/** +* Initializes the static Link Keys for both classic and LE. +* nvdsId: nvds id for the static link key, +* (0) disables the use of a static link key. +* +* @return cbBSM_OK. +*/ +cb_int32 cbBSM_setStaticLinkKeyNvdsId(cb_int32 nvdsId); #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h index 6cbc8b3767d..aa2f149da6e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h @@ -89,7 +89,7 @@ extern cb_int32 cbBTM_enableDUT(cbBTM_TestCallback callback); * 0x03 = BT EDR 3MB (8-DPSK) * 0x04 = BT LE (BLE, GMSK) * 0x05 = ANT (GFSK) - * @param testPattern Range: 0x00 - 0x07 + * @param testPattern Range: 0x00 - 0x07 * 0x00 = PN9 * 0x01 = PN15 * 0x02 = ZOZO (101010101010101010) @@ -165,7 +165,7 @@ extern cb_int32 cbBTM_tiDrpbTesterConRx( * @param frequencyMode 0x00 = Hopping 0x03 = Single frequency * @param txSingleFrequency Transmission frequency in MHz,Range 2402 - 2480, 0xFFFF = no TX * @param rxSingleFrequency Transmission frequency in MHz,Range 2402 - 2480, 0xFFFF = no RX - * @param aclDataPattern ACL TX packet data pattern Range: 0x00 - 0x05 + * @param aclDataPattern ACL TX packet data pattern Range: 0x00 - 0x05 * 0x00 = All 0 * 0x01 = All 1 * 0x02 = ZOZO (101010101010101010) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h new file mode 100644 index 00000000000..3d96ba8dbf5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_cert_utils.h @@ -0,0 +1,80 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2016, u-blox Malmö, All Rights Reserved + * SPDX-License-Identifier: LicenseRef-PBL + * + * This file and the related binary are licensed under the + * Permissive Binary License, Version 1.0 (the "License"); + * you may not use these files except in compliance with the License. + * + * You may obtain a copy of the License here: + * LICENSE-permissive-binary-license-1.0.txt and at + * https://www.mbed.com/licenses/PBL-1.0 + * + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Component : WLAN + * File : cb_cert_utils.h + * + * Description : + *-------------------------------------------------------------------------*/ + +/** + * @file cb_cert_utils.h The main WLAN component interface. + * All functions declared extern needs to be provided by another/upper layer. + * @ingroup wlan + */ + +#ifndef _CB_CERT_UTILS_H_ +#define _CB_CERT_UTILS_H_ + +#include "cb_types.h" +#include "cb_status.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/*=========================================================================== + * DEFINES + *=========================================================================*/ +#define cbCERT_CRT_MAX_CHAIN_LENGTH 5ul + +/*=========================================================================== + * TYPES + *=========================================================================*/ + +typedef struct cbCERT_Stream_s cbCERT_Stream; +typedef cb_uint32 cbCERT_StreamPosition; + +/** + * Stream vtable interface used by WLAN supplicant to access SSL certificates + * for WPA Enterprise authentication. + * + * @ingroup wlan + */ +struct cbCERT_Stream_s { + cb_int32(*read)(const cbCERT_Stream *stream, void *buf, cb_uint32 count); /**< Read function pointer, place count bytes in buf. */ + cb_int32(*write)(const cbCERT_Stream *stream, void *buf, cb_uint32 count); /**< Read function pointer, place count bytes in buf. */ + void(*rewind)(const cbCERT_Stream *stream); /**< Rewind function pointer, rewind stream internal iterator to the beginning. Mandatory for all streams. */ + void(*setPosition)(const cbCERT_Stream *stream, cbCERT_StreamPosition position); /**< Set absolute position. */ + cbCERT_StreamPosition(*getPosition)(const cbCERT_Stream *stream); /**< Get current position. */ + cb_uint32(*getSize)(const cbCERT_Stream *stream); /**< GetSize function pointer, return total size of stream contents. */ +}; + +/*=========================================================================== + * CERT API + *=========================================================================*/ + +cbRTSL_Status cbCERT_Util_parseDERCert(cbCERT_Stream const * const certificate, cbCERT_Stream const * const outputStream); +cbRTSL_Status cbCERT_Util_parseDERKey(cbCERT_Stream const * const key, cbCERT_Stream const * const outputStream); +cbRTSL_Status cbCERT_Util_parsePEMCert(cbCERT_Stream const * const certificate, cbCERT_Stream const * const outputStream); +cbRTSL_Status cbCERT_Util_parsePEMKey(cbCERT_Stream const * const certificate, cb_char const * const key, cb_uint32 keyLength, cbCERT_Stream const * const outputStream); + +#ifdef __cplusplus +} +#endif + +#endif /* _CB_CERT_UTILS_H_ */ + diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h index d41f6544229..94f5d13b2ef 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h @@ -31,9 +31,9 @@ * app must wait until all responses from an outstanding request have been * received. * - In the callback of the request another request can not be done except when - * - The request is interrupted by setting the return value to FALSE - * or when in the last callback which contains an error code. - * - Most of the GATT requests can be interrupted by returning FALSE in the + * the request is interrupted by setting the return value to FALSE + * or when in the last callback which contains an error code. + * - Most of the GATT requests can be interrupted by returning FALSE in the * callback. * * See Bluetooth 4.0 specification for more info on GATT and ATT chapters: diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h index 23656acb8aa..d2286c6dd49 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h @@ -76,7 +76,7 @@ extern "C" { * cbGATT_CLIENT_CHAR_CONFIG - callback that is called when remote device writes the client config cbGATT_ServerWriteClientConfig * cbGATT_SERVER_CHAR_CONFIG - callback that is called when remote device writes the server config cbGATT_ServerWriteServerConfig * cbGATT_CHAR_USER_DESC and all other CHARACTERISTICS value - cbGATT_ServerWriteAttr callback - * @param pAttrHandle Pointer where to write the attribute handle in case it's needed by the app. + * @param pAttrHandle Pointer where to write the attribute handle in case it's needed by the app. * If not needed, pass NULL. Will be written after the service has been added. */ typedef struct @@ -152,7 +152,7 @@ typedef cbGATT_ErrorCode (*cbGATT_ServerReadAttr)( * @param pAttr Pointer to attribute record * @param pAttrValue Pointer where to get the data * @param length The length. - * @param writeMethod Which write method the client is using. + * @param writeMethod Which write method the client is using. * This depends on the properties in the attribute table. * @param offset The offset of the written data * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed. @@ -183,7 +183,7 @@ typedef cbGATT_ErrorCode (*cbGATT_ServerReadClientConfig)( * @param connHandle Connection handle * @param attrHandle Handle of the attribute value * @param config The config to be stored - * @param writeMethod Which write method the client is using. + * @param writeMethod Which write method the client is using. * This depends on the properties in the attribute table. * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed. */ @@ -210,7 +210,7 @@ typedef cbGATT_ErrorCode (*cbGATT_ServerReadServerConfig)( * @param connHandle Connection handle * @param attrHandle Handle of the attribute value * @param config The config to be stored - * @param writeMethod Which write method the client is using. + * @param writeMethod Which write method the client is using. * This depends on the properties in the attribute table. * @return cbGATT_ERROR_CODE_OK if accepted or some cbGATT_ERROR_CODE_* code when failed. */ @@ -254,7 +254,7 @@ cb_int32 cbGATT_deregisterAllServers(void); /** * Send notification to GATT client. The characteristicValueNotificationCnf * callback will be called when finished and a new notification can be sent. - * The client config notification must have been enabled by the GATT client + * The client config notification must have been enabled by the GATT client * before an notification can be sent. * @param connHandle Connection handle * @param attrHandle Handle of the attribute value @@ -264,16 +264,16 @@ cb_int32 cbGATT_deregisterAllServers(void); * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed. */ cb_int32 cbGATT_notification( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint8* pData, - cb_uint16 length, + TConnHandle connHandle, + cb_uint16 attrHandle, + cb_uint8* pData, + cb_uint16 length, cb_uint8 appHandle); /** * Send indication to GATT client. The characteristicValueIndicationCnf * callback will be called when finished and a new indication can be sent. - * The client config indication must have been enabled by the GATT client + * The client config indication must have been enabled by the GATT client * before an indication can be sent. * @param connHandle Connection handle * @param attrHandle Handle of the attribute value @@ -283,17 +283,17 @@ cb_int32 cbGATT_notification( * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed. */ cb_int32 cbGATT_indication( - TConnHandle connHandle, - cb_uint16 attrHandle, - cb_uint8* pData, - cb_uint16 length, + TConnHandle connHandle, + cb_uint16 attrHandle, + cb_uint8* pData, + cb_uint16 length, cb_uint8 appHandle); /** * Delay write respone to client, see cbGATT_ServerWriteAttr * @param connHandle Connection handle * @param attrHandle Handle of the attribute value - * @param errorCode Error code, use cbGATT_ERROR_CODE_OK if OK otherwise some cbGATT_ERROR_CODE_* + * @param errorCode Error code, use cbGATT_ERROR_CODE_OK if OK otherwise some cbGATT_ERROR_CODE_* * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed. */ cb_int32 cbGATT_writeRsp( @@ -305,15 +305,15 @@ cb_int32 cbGATT_writeRsp( * Add service list to attribute database * @param pAttrList Attribute list * @param attrListSize Size of the attribute list - * @param startHandle Start handle. Note that startHandle for the application - * should start at lowest 1024, cbGATT_APP_START_SERVICE_HANDLE. + * @param startHandle Start handle. Note that startHandle for the application + * should start at lowest 1024, cbGATT_APP_START_SERVICE_HANDLE. * 1-1023 is reserved for GATT/GAP and other u-blox services. * @return cbGATT_OK if succeeded or some cbGATT_ERROR* when failed. */ cb_int32 cbGATT_addService( const cbGATT_Attribute* pAttrList, - cb_uint16 attrListSize, - cb_int16 startHandle); + cb_uint16 attrListSize, + cb_uint16 startHandle); /** * NOTE: Only for tests diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h index b0b3f5cba55..df4887ed3ce 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h @@ -59,6 +59,11 @@ typedef enum { cbHW_IRQ_LOW = 12U }cbHW_PRIO_LVL; +typedef enum { + cbHW_SYSTICK_DISABLED, + cbHW_SYSTICK_LOW_FREQ, + cbHW_SYSTICK_DEFAULT, +} cbHW_SysTickMode; /*=========================================================================== * TYPES *=========================================================================*/ @@ -79,6 +84,7 @@ void cbHW_enterSleepMode(void); void cbHW_enterStopMode(void); void cbHW_setWakeupEvent(void); void cbHW_resetWakeupEvent(void); +void cbHW_setSysTickMode(cbHW_SysTickMode sysTickMode); /** * Wait for specified amount of microseconds. May be interrupt dependent. @@ -143,4 +149,3 @@ void cbHW_enableAllIrq(void); #endif - diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h index 9e2f5d72de6..c1c51444936 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h @@ -26,7 +26,9 @@ *=========================================================================*/ #define OK(status) (status == cbSTATUS_OK) - +#define BUSY(status) (status == cbSTATUS_BUSY) +#define ERR(status) (status == cbSTATUS_ERROR) + /*=========================================================================== * TYPES *=========================================================================*/ @@ -36,6 +38,7 @@ cbSTATUS_OK, cbSTATUS_ERROR, cbSTATUS_BUSY, + cbSTATUS_RECEIVE_DATA_MODE, cbSTATUS_TIMEOUT } cbRTSL_Status; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h index a451e9ff8e1..b5f2992a543 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h @@ -31,6 +31,7 @@ #include "cb_types.h" #include "cb_wlan_types.h" +#include "cb_cert_utils.h" #include "cb_status.h" #ifdef __cplusplus @@ -75,25 +76,6 @@ extern "C" { /*=========================================================================== * TYPES *=========================================================================*/ - -typedef struct cbWLAN_Stream_s cbWLAN_Stream; -typedef cb_uint32 cbWLAN_StreamPosition; - -/** - * Stream vtable interface used by WLAN supplicant to access SSL certificates - * for WPA Enterprise authentication. - * - * @ingroup wlan - */ -struct cbWLAN_Stream_s { - cb_int32 (*read)(const cbWLAN_Stream *stream, void *buf, cb_uint32 count); /**< Read function pointer, place count bytes in buf. */ - cb_int32 (*write)(const cbWLAN_Stream *stream, void *buf, cb_uint32 count); /**< Read function pointer, place count bytes in buf. */ - void (*rewind)(const cbWLAN_Stream *stream); /**< Rewind function pointer, rewind stream internal iterator to the beginning. Mandatory for all streams. */ - void (*setPosition)(const cbWLAN_Stream *stream, cbWLAN_StreamPosition position); /**< Set absolute position. */ - cbWLAN_StreamPosition (*getPosition)(const cbWLAN_Stream *stream); /**< Get current position. */ - cb_uint32 (*getSize)(const cbWLAN_Stream *stream); /**< GetSize function pointer, return total size of stream contents. */ -}; - /** * Start parameters passed to WLAN driver. * @@ -178,8 +160,8 @@ typedef struct cbWLAN_EnterpriseConnectParameters { cb_uint8 username[cbWLAN_MAX_USERNAME_LENGTH]; /**< Username string. */ cb_uint8 passphrase[cbWLAN_MAX_PASSPHRASE_LENGTH]; /**< Passphrase string. */ cb_uint8 domain[cbWLAN_MAX_DOMAIN_LENGTH]; /**< Domain string. */ - cbWLAN_Stream *clientCertificate; /**< Stream handle to provide SSL certificate for authentication. */ - cbWLAN_Stream *clientPrivateKey; /**< STream handle to provide SSL private key for authentication. */ + cbCERT_Stream *clientCertificate; /**< Stream handle to provide SSL certificate for authentication. */ + cbCERT_Stream *clientPrivateKey; /**< STream handle to provide SSL private key for authentication. */ } cbWLAN_EnterpriseConnectParameters; /** @@ -200,9 +182,10 @@ typedef struct cbWLAN_CommonApParameters { * @ingroup wlan */ typedef struct cbWLAN_WPAPSKApParameters { - cbWLAN_CipherSuite rsnCiphers; /**< Bit field indicating which ciphers that shall be displayed in RSN information elements. If 0 no RSN information elements is added to beacons and probe responses. */ - cbWLAN_CipherSuite wpaCiphers; /**< Bit field indicating which ciphers that shall be displayed in WPA information elements. If 0 no WPA information elements is added to beacons and probe responses. */ - cbWLAN_WPAPSK psk; /**< WPA pre-shared key*/ + cbWLAN_CipherSuite rsnCiphers; /**< Bit field indicating which ciphers that shall be displayed in RSN information elements. If 0 no RSN information elements is added to beacons and probe responses. */ + cbWLAN_CipherSuite wpaCiphers; /**< Bit field indicating which ciphers that shall be displayed in WPA information elements. If 0 no WPA information elements is added to beacons and probe responses. */ + cbWLAN_WPAPSK psk; /**< WPA pre-shared key*/ + cb_uint32 gtkRekeyInterval; /**< Group rekey interval in seconds */ } cbWLAN_WPAPSKApParameters; @@ -286,8 +269,11 @@ typedef enum { cbWLAN_IOCTL_GET_DTIM_ENABLE, //!< Get DTIM enable 0, disable 1 enable cbWLAN_IOCTL_SET_SLEEP_TIMEOUT, //!< Set enter power save entry delay (in ms). Power save mode will be entered only if there no activity during this delay cbWLAN_IOCTL_GET_SLEEP_TIMEOUT, //!< Get enter power save entry delay (in ms). Power save mode will be entered only if there no activity during this delay - cbWLAN_IOCTL_LAST, + cbWLAN_IOCTL_SET_GSETTING = 1000, //!< Pipe to @ref cbWM_gSet. + cbWLAN_IOCTL_SET_TSETTING = 2000, //!< Pipe to @ref cbWM_tSet. + cbWLAN_IOCTL_GET_GSETTING = 3000, //!< Pipe to @ref cbWM_gGet. + cbWLAN_IOCTL_GET_TSETTING = 4000, //!< Pipe to @ref cbWM_tGet. } cbWLAN_Ioctl; /** diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c index 4ffd98d3a2b..b71176bf28c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c @@ -762,9 +762,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; // FIX } } /* FIFO Error Interrupt management ******************************************/ @@ -777,9 +774,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; // FIX } } /* Direct Mode Error Interrupt management ***********************************/ @@ -792,9 +786,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; // FIX } } /* Half Transfer Complete Interrupt management ******************************/ @@ -811,9 +802,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; // FIX - if(hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ @@ -823,9 +811,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Current memory buffer used is Memory 1 */ else { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM1; // FIX - if(hdma->XferM1HalfCpltCallback != NULL) { /* Half transfer callback */ @@ -842,9 +827,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) hdma->Instance->CR &= ~(DMA_IT_HT); } - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; // FIX - if(hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ @@ -893,9 +875,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_MEM1; // FIX - if(hdma->XferM1CpltCallback != NULL) { /* Transfer complete Callback for memory1 */ @@ -905,9 +884,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Current memory buffer used is Memory 1 */ else { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_MEM0; // FIX - if(hdma->XferCpltCallback != NULL) { /* Transfer complete Callback for memory0 */ @@ -918,9 +894,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ else { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_READY_MEM0; // FIX - if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) { /* Disable the transfer complete interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h index d2c9e828d41..13258838fe4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h @@ -122,13 +122,7 @@ typedef enum { HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_READY_MEM0 = 0x11U, /*!< DMA Mem0 process success */ // FIX - HAL_DMA_STATE_READY_MEM1 = 0x21U, /*!< DMA Mem1 process success */ // FIX - HAL_DMA_STATE_READY_HALF_MEM0 = 0x31U, /*!< DMA Mem0 Half process success */ // FIX - HAL_DMA_STATE_READY_HALF_MEM1 = 0x41U, /*!< DMA Mem1 Half process success */ // FIX HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ - HAL_DMA_STATE_BUSY_MEM0 = 0x12U, /*!< DMA Mem0 process is ongoing */ // FIX - HAL_DMA_STATE_BUSY_MEM1 = 0x22U, /*!< DMA Mem1 process is ongoing */ // FIX HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralPins.c index 2d285b3386b..7908d384477 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PeripheralPins.c @@ -48,7 +48,7 @@ const PinMap PinMap_ADC[] = { {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - ARDUINO D13 {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - ARDUINO D12 - {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (JP6) - ARDUINO D11 + {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) // {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 (used by LED1) {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,10, 0)}, // ADC1_IN10 - ARDUINO A1 @@ -124,10 +124,10 @@ const PinMap PinMap_PWM[] = { // {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - // {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (used by ethernet) - // {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (used by ethernet) - // {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (used by ethernet) - // {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (used by ethernet) + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) + // {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (used by ethernet when JP6 ON) + // {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (used by ethernet when JP6 ON) + // {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (used by ethernet when JP6 ON) {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 (used by USB) // {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 (used by USB) @@ -142,7 +142,9 @@ const PinMap PinMap_PWM[] = { // {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 (used by LED2) {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 @@ -271,12 +273,14 @@ const PinMap PinMap_UART_CTS[] = { //*** SPI *** const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO D11 (remove JP6 to use it) + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // used by ethernet when JP6 ON - ARDUINO D11 (default configuration) {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files // {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - // {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (used by Ethernet) + // {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (used by ethernet) {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO A2 {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, @@ -314,7 +318,7 @@ const PinMap PinMap_SPI_SCLK[] = { {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - // {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // (used by Ethernet) + // {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // (used by ethernet) {NC, NC, 0} }; @@ -332,11 +336,15 @@ const PinMap PinMap_SPI_SSEL[] = { {NC, NC, 0} }; +//*** CAN *** + const PinMap PinMap_CAN_RD[] = { {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {PB_12 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, {PD_0 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h index 1be99b84927..e370605c0e8 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/PinNames.h @@ -183,7 +183,7 @@ typedef enum { D8 = PF_12, D9 = PD_15, D10 = PD_14, - D11 = PA_7, + D11 = STM32_D11_SPI_ETHERNET_PIN, /* config in targets.json file */ D12 = PA_6, D13 = PA_5, D14 = PB_9, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralPins.c index 2d285b3386b..7908d384477 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PeripheralPins.c @@ -48,7 +48,7 @@ const PinMap PinMap_ADC[] = { {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - ARDUINO D13 {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - ARDUINO D12 - {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (JP6) - ARDUINO D11 + {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) // {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 (used by LED1) {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,10, 0)}, // ADC1_IN10 - ARDUINO A1 @@ -124,10 +124,10 @@ const PinMap PinMap_PWM[] = { // {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - // {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (used by ethernet) - // {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (used by ethernet) - // {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (used by ethernet) - // {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (used by ethernet) + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) + // {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (used by ethernet when JP6 ON) + // {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (used by ethernet when JP6 ON) + // {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (used by ethernet when JP6 ON) {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 (used by USB) // {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 (used by USB) @@ -142,7 +142,9 @@ const PinMap PinMap_PWM[] = { // {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 (used by LED2) {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 @@ -271,12 +273,14 @@ const PinMap PinMap_UART_CTS[] = { //*** SPI *** const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO D11 (remove JP6 to use it) + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // used by ethernet when JP6 ON - ARDUINO D11 (default configuration) {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files // {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - // {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (used by Ethernet) + // {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (used by ethernet) {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO A2 {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, @@ -314,7 +318,7 @@ const PinMap PinMap_SPI_SCLK[] = { {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - // {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // (used by Ethernet) + // {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // (used by ethernet) {NC, NC, 0} }; @@ -332,11 +336,15 @@ const PinMap PinMap_SPI_SSEL[] = { {NC, NC, 0} }; +//*** CAN *** + const PinMap PinMap_CAN_RD[] = { {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {PB_12 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, {PD_0 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, - {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_5 , CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h index 1be99b84927..e370605c0e8 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/PinNames.h @@ -183,7 +183,7 @@ typedef enum { D8 = PF_12, D9 = PD_15, D10 = PD_14, - D11 = PA_7, + D11 = STM32_D11_SPI_ETHERNET_PIN, /* config in targets.json file */ D12 = PA_6, D13 = PA_5, D14 = PB_9, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralPins.c index 915695e14b9..8f520ad7a58 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PeripheralPins.c @@ -48,7 +48,7 @@ const PinMap PinMap_ADC[] = { {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 - ARDUINO D13 {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - ARDUINO D12 - {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (JP6) - ARDUINO D11 + {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 (used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) // {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 (used by LED1) {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,10, 0)}, // ADC1_IN10 - ARDUINO A1 @@ -124,10 +124,10 @@ const PinMap PinMap_PWM[] = { // {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // {PA_6, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 - // {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (used by ethernet) - // {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (used by ethernet) - // {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (used by ethernet) - // {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (used by ethernet) + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N (used by ethernet when JP6 ON) - ARDUINO D11 (default configuration) + // {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 (used by ethernet when JP6 ON) + // {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N (used by ethernet when JP6 ON) + // {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 (used by ethernet when JP6 ON) {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 (used by USB) // {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 (used by USB) @@ -142,7 +142,9 @@ const PinMap PinMap_PWM[] = { // {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 (used by LED2) {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 @@ -271,12 +273,14 @@ const PinMap PinMap_UART_CTS[] = { //*** SPI *** const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO D11 (remove JP6 to use it) + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // used by ethernet when JP6 ON - ARDUINO D11 (default configuration) {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files // {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, - // {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (used by Ethernet) + // {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // (used by ethernet) {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // ARDUINO A2 {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, @@ -314,7 +318,7 @@ const PinMap PinMap_SPI_SCLK[] = { {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, - // {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // (used by Ethernet) + // {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // (used by ethernet) {NC, NC, 0} }; @@ -338,7 +342,9 @@ const PinMap PinMap_CAN_RD[] = { {PA_8, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {PB_3, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, - {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // ARDUINO D11 (need HW and SW updates) + // HW solder bridge update : SB121 off, SB122 on + // SW : config from json files {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h index 1be99b84927..e370605c0e8 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/PinNames.h @@ -183,7 +183,7 @@ typedef enum { D8 = PF_12, D9 = PD_15, D10 = PD_14, - D11 = PA_7, + D11 = STM32_D11_SPI_ETHERNET_PIN, /* config in targets.json file */ D12 = PA_6, D13 = PA_5, D14 = PB_9, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralNames.h new file mode 100644 index 00000000000..087804bb409 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralNames.h @@ -0,0 +1,81 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_4 = (int)USART4_BASE, + UART_5 = (int)USART5_BASE, + LPUART_1 = (int)LPUART1_BASE +} UARTName; + +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_3 +#define STDIO_UART UART_2 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_21 = (int)TIM21_BASE, + PWM_22 = (int)TIM22_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralPins.c new file mode 100644 index 00000000000..49baeaec073 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PeripheralPins.c @@ -0,0 +1,213 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ARDUINO A0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // Pin not available on any connector +// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ARDUINO D1 - Used by STDIO_UART_TX +// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ARDUINO D0 - Used by STDIO_UART_RX + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ARDUINO A2 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // CN3.7 - Used also to drive LED2 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // Pin not available on any connector + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // Pin not available on any connector + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // Pin not available on any connector + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // Pin not available on any connector + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // Pin not available on any connector + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // Pin not available on any connector + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // Pin not available on any connector + {NC, NC, 0} +}; + +const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // Internal channel + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // Internal channel + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // Internal channel + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ARDUINO A2 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // CN3.7 - Used also to drive LED2 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, // ARDUINO D2 + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)}, // Pin not available on any connector + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, // ARDUINO D5 - Used also to drive LED4 + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D14 + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, // Pin not available on any connector + {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, // ARDUINO D12 + {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)}, // Pin not available on any connector + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)}, // ARDUINO D7 + {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, // ARDUINO D8 + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, // ARDUINO D10 - Used also to drive LED3 + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO D15 + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, // Pin not available on any connector + {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)}, // ARDUINO D13 + {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)}, // Pin not available on any connector + {NC, NC, 0} +}; + +//*** PWM *** +// Pins using TIM21 cannot be used as TIM21 is already used by ticker. +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // ARDUINO A0 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // Pin not available on any connector +// {PA_2, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // ARDUINO D1 - Used by STDIO_UART_TX +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // ARDUINO D1 - Used by STDIO_UART_TX +// {PA_3, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // ARDUINO D0 - Used by STDIO_UART_RX +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // ARDUINO D0 - Used by STDIO_UART_RX + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // CN3.7 - Used also to drive LED2 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // Pin not available on any connector + {PA_6_ALT0, PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // Pin not available on any connector + {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // Pin not available on any connector + {PA_7_ALT0, PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // Pin not available on any connector + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // Pin not available on any connector + {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // Pin not available on any connector + {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // Pin not available on any connector + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // Pin not available on any connector + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // Pin not available on any connector + {PB_4_ALT0, PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // Pin not available on any connector + {PB_5, PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // ARDUINO D4 - Used also to drive LED1 + {PB_5_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM3, 2, 0)}, // ARDUINO D4 - Used also to drive LED1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // Pin not available on any connector + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // Pin not available on any connector +// {PB_13, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 1, 0)}, // ARDUINO D13 - TIM21 used by ticker +// {PB_14, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 2, 0)}, // ARDUINO D12 - TIM21 used by ticker + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, // ARDUINO A0 + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // ARDUINO D1 - Used by STDIO_UART_TX +// {PA_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // ARDUINO D1 - UART2 is already used by STDIO_UART_TX + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // ARDUINO D8 + {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Warning: this pin is used by SWCLK + {PA_14_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Warning: this pin is used by SWCLK + {PB_3, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, // Pin not available on any connector + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, // ARDUINO D10 - Used also to drive LED3 + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Pin not available on any connector + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, // Pin not available on any connector + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Pin not available on any connector + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, // Pin not available on any connector + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // ARDUINO D0 - Used by STDIO_UART_RX +// {PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // ARDUINO D0 - UART2 is already used by STDIO_UART_RX + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // ARDUINO D2 + {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Warning: this pin is used by SWDIO + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Pin not available on any connector + {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, // Pin not available on any connector + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, // ARDUINO D5 - Used also to drive LED4 + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_LPUART1)}, // Pin not available on any connector + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Pin not available on any connector + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Pin not available on any connector + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Pin not available on any connector + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // CN3.14 + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, // Pin not available on any connector + {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Pin not available on any connector + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, // Pin not available on any connector + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)}, // ARDUINO D4 - Used also to drive LED1 + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)}, // ARDUINO D9 + {PB_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // ARDUINO D12 + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // ARDUINO A0 + {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // Pin not available on any connector + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // CN3.15 + {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_USART1)}, // Pin not available on any connector + {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)}, // ARDUINO D5 - Used also to drive LED4 + {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, // ARDUINO D13 + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Pin not available on any connector + {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // CN3.14 + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // ARDUINO D4 - Used also to drive LED1 + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, // ARDUINO D11 + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Pin not available on any connector + {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // CN3.15 + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Pin not available on any connector + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, // ARDUINO D12 + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)}, // Pin not available on any connector + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // CN3.7 - Used also to drive LED2 + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Pin not available on any connector + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Pin not available on any connector + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, // ARDUINO D13 + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // ARDUINO A2 + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Pin not available on any connector + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO D14 + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)}, // ARDUINO D9 + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h new file mode 100644 index 00000000000..8cc9c39e5e7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/PinNames.h @@ -0,0 +1,149 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_6_ALT0 = PA_6|ALT0, + PA_7 = 0x07, + PA_7_ALT0 = PA_7|ALT0, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_14_ALT0 = PA_14|ALT0, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_4_ALT0 = PB_4|ALT0, + PB_5 = 0x15, + PB_5_ALT0 = PB_5|ALT0, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + + PH_0 = 0x70, + PH_1 = 0x71, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Arduino connector namings + A0 = PA_0, + A1 = PA_0, // Alias + A2 = PA_4, + A3 = PA_4, // Alias + A4 = PB_9, // SB11 must be closed + A5 = PB_8, // SB12 must be closed + D0 = PA_3, + D1 = PA_2, + D2 = PA_10, + D3 = PB_13, + D4 = PB_5, + D5 = PB_7, + D6 = PB_2, + D7 = PA_8, + D8 = PA_9, + D9 = PB_12, + D10 = PB_6, + D11 = PB_15, + D12 = PB_14, + D13 = PB_13, // SB2 must be closed + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + LED1 = PB_5, // Green + LED2 = PA_5, // Red + LED3 = PB_6, // Blue + LED4 = PB_7, // Red + USER_BUTTON = PB_2, + SERIAL_TX = PA_2, + SERIAL_RX = PA_3, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + I2C_SCL = D15, + I2C_SDA = D14, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + PWM_OUT = D13, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/startup_stm32l072xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/startup_stm32l072xx.S new file mode 100644 index 00000000000..f36d2dce03a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/startup_stm32l072xx.S @@ -0,0 +1,244 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l072xx.s +;* Author : MCD Application Team +;* Version : V1.7.1 +;* Date : 25-November-2016 +;* Description : STM32l072xx Devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C lbrary (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20005000 ; Top of RAM TODO à verifier + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD USART4_5_IRQHandler ; USART4 and USART5 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM21_IRQHandler ; TIM21 + DCD I2C3_IRQHandler ; I2C3 + DCD TIM22_IRQHandler ; TIM22 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD RNG_LPUART1_IRQHandler ; RNG and LPUART1 + DCD 0 ; Reserved + DCD USB_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT USART4_5_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM21_IRQHandler [WEAK] + EXPORT TIM22_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT I2C3_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT RNG_LPUART1_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_6_7_IRQHandler +ADC1_COMP_IRQHandler +LPTIM1_IRQHandler +USART4_5_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +TIM21_IRQHandler +TIM22_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +I2C3_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +RNG_LPUART1_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct new file mode 100644 index 00000000000..c4e915ba952 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000) +LR_IROM1 0x08000000 0x30000 { ; load region size_region + + ER_IROM1 0x08000000 0x30000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM + RW_IRAM1 (0x20000000+0xC0) (0x5000-0xC0) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/startup_stm32l072xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/startup_stm32l072xx.S new file mode 100644 index 00000000000..653372010ce --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/startup_stm32l072xx.S @@ -0,0 +1,217 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l072xx.s +;* Author : MCD Application Team +;* Version : V1.7.1 +;* Date : 25-November-2016 +;* Description : STM32l072xx Devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C lbrary (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* + +__initial_sp EQU 0x20005000 ; Top of RAM TODO à verifier + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD USART4_5_IRQHandler ; USART4 and USART5 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM21_IRQHandler ; TIM21 + DCD I2C3_IRQHandler ; I2C3 + DCD TIM22_IRQHandler ; TIM22 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD RNG_LPUART1_IRQHandler ; RNG and LPUART1 + DCD 0 ; Reserved + DCD USB_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT USART4_5_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT TIM21_IRQHandler [WEAK] + EXPORT TIM22_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT I2C3_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT RNG_LPUART1_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_6_7_IRQHandler +ADC1_COMP_IRQHandler +LPTIM1_IRQHandler +USART4_5_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +TIM21_IRQHandler +TIM22_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +I2C3_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +RNG_LPUART1_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l073xz.sct b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l073xz.sct new file mode 100644 index 00000000000..c4e915ba952 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l073xz.sct @@ -0,0 +1,45 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000) +LR_IROM1 0x08000000 0x30000 { ; load region size_region + + ER_IROM1 0x08000000 0x30000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM + RW_IRAM1 (0x20000000+0xC0) (0x5000-0xC0) { ; RW data + .ANY (+RW +ZI) + } + +} + diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 00000000000..bb665909b98 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_GCC_ARM/STM32L072XZ.ld b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_GCC_ARM/STM32L072XZ.ld new file mode 100644 index 00000000000..91fa744aa61 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_GCC_ARM/STM32L072XZ.ld @@ -0,0 +1,153 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 192k + RAM (rwx) : ORIGIN = 0x200000C0, LENGTH = 20K - 0xC0 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_GCC_ARM/startup_stm32l072xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_GCC_ARM/startup_stm32l072xx.S new file mode 100644 index 00000000000..1aad893bcbd --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_GCC_ARM/startup_stm32l072xx.S @@ -0,0 +1,288 @@ +/** + ****************************************************************************** + * @file startup_stm32l072xx.s + * @author MCD Application Team + * @version V1.7.1 + * @date 25-November-2016 + * @brief STM32L072xx Devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0+ processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0plus + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + bl _start + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_CRS_IRQHandler /* RCC and CRS */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word TSC_IRQHandler /* TSC */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/ + .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word USART4_5_IRQHandler /* USART4 and USART 5 */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC */ + .word TIM7_IRQHandler /* TIM7 */ + .word 0 /* Reserved */ + .word TIM21_IRQHandler /* TIM21 */ + .word I2C3_IRQHandler /* I2C3 */ + .word TIM22_IRQHandler /* TIM22 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word RNG_LPUART1_IRQHandler /* RNG and LPUART1 */ + .word 0 /* Reserved */ + .word USB_IRQHandler /* USB */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_6_7_IRQHandler + .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler + + .weak ADC1_COMP_IRQHandler + .thumb_set ADC1_COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak USART4_5_IRQHandler + .thumb_set USART4_5_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak TIM21_IRQHandler + .thumb_set TIM21_IRQHandler,Default_Handler + + .weak I2C3_IRQHandler + .thumb_set I2C3_IRQHandler,Default_Handler + + .weak TIM22_IRQHandler + .thumb_set TIM22_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak RNG_LPUART1_IRQHandler + .thumb_set RNG_LPUART1_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_IAR/startup_stm32l072xx.S b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_IAR/startup_stm32l072xx.S new file mode 100644 index 00000000000..4476016ea2d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_IAR/startup_stm32l072xx.S @@ -0,0 +1,343 @@ +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l072xx.s +;* Author : MCD Application Team +;* Version : V1.7.1 +;* Date : 25-November-2016 +;* Description : STM32L072xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;*******************************************************************************/ +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC_CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD USART4_5_IRQHandler ; USART4 and USART5 + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD TIM7_IRQHandler ; TIM7 + DCD 0 ; Reserved + DCD TIM21_IRQHandler ; TIM21 + DCD I2C3_IRQHandler ; I2C3 + DCD TIM22_IRQHandler ; TIM22 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD RNG_LPUART1_IRQHandler ; RNG and LPUART1 + DCD 0 ; Reserved + DCD USB_IRQHandler ; USB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + + PUBWEAK RCC_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_CRS_IRQHandler + B RCC_CRS_IRQHandler + + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + + PUBWEAK DMA1_Channel4_5_6_7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_6_7_IRQHandler + B DMA1_Channel4_5_6_7_IRQHandler + + + PUBWEAK ADC1_COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_COMP_IRQHandler + B ADC1_COMP_IRQHandler + + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + + PUBWEAK USART4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART4_5_IRQHandler + B USART4_5_IRQHandler + + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK TIM21_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM21_IRQHandler + B TIM21_IRQHandler + + PUBWEAK I2C3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_IRQHandler + B I2C3_IRQHandler + + PUBWEAK TIM22_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM22_IRQHandler + B TIM22_IRQHandler + + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + + PUBWEAK I2C2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_IRQHandler + B I2C2_IRQHandler + + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + + PUBWEAK RNG_LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_LPUART1_IRQHandler + B RNG_LPUART1_IRQHandler + + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_IAR/stm32l072xx.icf b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_IAR/stm32l072xx.icf new file mode 100644 index 00000000000..65a11a2b35a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_IAR/stm32l072xx.icf @@ -0,0 +1,30 @@ +/* [ROM = 192kb = 0x30000] */ +define symbol __intvec_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_end__ = 0x0802FFFF; + +/* [RAM = 20kb = 0x5000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */ +define symbol __region_RAM_start__ = 0x200000C0; +define symbol __region_RAM_end__ = 0x20004FFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +/* Stack and Heap */ +define symbol __size_cstack__ = 0x500; +define symbol __size_heap__ = 0x1000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/cmsis.h new file mode 100644 index 00000000000..734947a235d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32l0xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/cmsis_nvic.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/cmsis_nvic.c new file mode 100644 index 00000000000..41a742b4aa1 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/cmsis_nvic.c @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#include "cmsis_nvic.h" + +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + uint32_t *vectors = (uint32_t *)SCB->VTOR; + uint32_t i; + + // Copy and switch to dynamic vectors if the first time called + if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { + uint32_t *old_vectors = vectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; + } + vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)SCB->VTOR; + return vectors[IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/cmsis_nvic.h new file mode 100644 index 00000000000..baba2251b18 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/cmsis_nvic.h @@ -0,0 +1,54 @@ +/* mbed Microcontroller Library + * CMSIS-style functionality to support dynamic vectors + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF +// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM +#define NVIC_NUM_VECTORS 48 +#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h new file mode 100644 index 00000000000..e79a4e7568d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h @@ -0,0 +1,64 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32l0xx.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM21 +#define TIM_MST_IRQ TIM21_IRQn +#define TIM_MST_RCC __TIM21_CLK_ENABLE() + +#define TIM_MST_RESET_ON __TIM21_FORCE_RESET() +#define TIM_MST_RESET_OFF __TIM21_RELEASE_RESET() + +#define TIM_MST_16BIT 1 // 1=16-bit timer, 0=32-bit timer + +#define TIM_MST_PCLK 2 // Select the peripheral clock number (1 or 2) + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/stm32l072xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/stm32l072xx.h new file mode 100644 index 00000000000..a38c8690efc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/stm32l072xx.h @@ -0,0 +1,7683 @@ +/** + ****************************************************************************** + * @file stm32l072xx.h + * @author MCD Application Team + * @version V1.7.1 + * @date 25-November-2016 + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for stm32l072xx devices. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l072xx + * @{ + */ + +#ifndef __STM32L072xx_H +#define __STM32L072xx_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ +#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief stm32l072xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ +/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ + +/****** STM32L-0 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TSC_IRQn = 8, /*!< TSC Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ + LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ + USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 Interrupt */ + TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ + TIM7_IRQn = 18, /*!< TIM7 Interrupt */ + TIM21_IRQn = 20, /*!< TIM21 Interrupt */ + I2C3_IRQn = 21, /*!< I2C3 Interrupt */ + TIM22_IRQn = 22, /*!< TIM22 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ + USB_IRQn = 31, /*!< USB global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" +#include "system_stm32l0xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ + __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ + __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ + uint32_t RESERVED3; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ + uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ + uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; +} ADC_Common_TypeDef; + + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + + +/** +* @brief CRC calculation unit +*/ + +typedef struct +{ +__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ +__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ +uint8_t RESERVED0; /*!< Reserved, 0x05 */ +uint16_t RESERVED1; /*!< Reserved, 0x06 */ +__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +uint32_t RESERVED2; /*!< Reserved, 0x0C */ +__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ +__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ + +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ +} DMA_Request_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l0xx + * @{ + */ + +#ifndef __STM32L0xx_H +#define __STM32L0xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32L0) +#define STM32L0 +#endif /* STM32L0 */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32L011xx) && !defined (STM32L021xx) && \ + !defined (STM32L031xx) && !defined (STM32L041xx) && \ + !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \ + !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \ + !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \ + !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \ + /* #define STM32L011xx */ + /* #define STM32L021xx */ + /* #define STM32L031xx */ /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */ + /* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */ + /* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */ + /* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */ + /* #define STM32L053xx */ /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */ + /* #define STM32L061xx */ /*!< */ + /* #define STM32L062xx */ /*!< STM32L062K8 */ + /* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */ + /* #define STM32L071xx */ /*!< */ + #define STM32L072xx /*!< */ + /* #define STM32L073xx */ /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */ + /* #define STM32L081xx */ /*!< */ + /* #define STM32L082xx */ /*!< */ + /* #define STM32L083xx */ /*!< */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +#define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V1.7.0 + */ +#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ +#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\ + |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32L0xx_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ +#if defined(STM32L011xx) + #include "stm32l011xx.h" +#elif defined(STM32L021xx) + #include "stm32l021xx.h" +#elif defined(STM32L031xx) + #include "stm32l031xx.h" +#elif defined(STM32L041xx) + #include "stm32l041xx.h" +#elif defined(STM32L051xx) + #include "stm32l051xx.h" +#elif defined(STM32L052xx) + #include "stm32l052xx.h" +#elif defined(STM32L053xx) + #include "stm32l053xx.h" +#elif defined(STM32L062xx) + #include "stm32l062xx.h" +#elif defined(STM32L063xx) + #include "stm32l063xx.h" +#elif defined(STM32L061xx) + #include "stm32l061xx.h" +#elif defined(STM32L071xx) + #include "stm32l071xx.h" +#elif defined(STM32L072xx) + #include "stm32l072xx.h" +#elif defined(STM32L073xx) + #include "stm32l073xx.h" +#elif defined(STM32L082xx) + #include "stm32l082xx.h" +#elif defined(STM32L083xx) + #include "stm32l083xx.h" +#elif defined(STM32L081xx) + #include "stm32l081xx.h" +#else + #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macro + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32l0xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32L0xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_stm32l0xx.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_stm32l0xx.c new file mode 100644 index 00000000000..736df4d433a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_stm32l0xx.c @@ -0,0 +1,480 @@ +/** + ****************************************************************************** + * @file system_stm32l0xx.c + * @author MCD Application Team + * @version V1.7.0 + * @date 31-May-2016 + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 16 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 32 | 32 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 32 | 32 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 32 | 32 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 32 | 32 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | YES | YES + *----------------------------------------------------------------------------- + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l0xx_system + * @{ + */ + +/** @addtogroup STM32L0xx_System_Private_Includes + * @{ + */ + +#include "stm32l0xx.h" +#include "hal_tick.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_Defines + * @{ + */ +/************************* Miscellaneous Configuration ************************/ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_Macros + * @{ + */ + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (0) /* Use external clock */ +#define USE_PLL_HSE_XTAL (0) /* Use external xtal */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 32000000; + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes + * @{ + */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit (void) +{ +/*!< Set MSION bit */ + RCC->CR |= (uint32_t)0x00000100U; + + /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ + RCC->CFGR &= (uint32_t) 0x88FF400CU; + + /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFF6U; + + /*!< Reset HSI48ON bit */ + RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; + + /*!< Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFFU; + + /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ + RCC->CFGR &= (uint32_t)0xFF02FFFFU; + + /*!< Disable all interrupts */ + RCC->CIER = 0x00000000U; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + + /* Configure the Cube driver */ + SystemCoreClock = 8000000; // At this stage the HSI is used as system clock + HAL_Init(); + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + /* Reset the timer to avoid issues after the RAM initialization */ + TIM_MST_RESET_ON; + TIM_MST_RESET_OFF; +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI + * value as defined by the MSI range. + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00U: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); + break; + case 0x04U: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x08U: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x0CU: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + pllmul = PLLMulTable[(pllmul >> 18U)]; + plldiv = (plldiv >> 22U) + 1U; + + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + + if (pllsource == 0x00U) + { + /* HSI oscillator clock selected as PLL clock entry */ + SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); + } + else + { + /* HSE selected as PLL clock entry */ + SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); + } + break; + default: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ + #if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) + #endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) + { + while(1) + { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1); +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Used to gain time after DeepSleep in case HSI is used */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + return 0; + } + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + if (bypass == 0) + { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } + else + { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \ + !defined (STM32L011xx) && !defined (STM32L021xx) + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */ +#endif + // PLLCLK = (8 MHz * 8)/2 = 32 MHz + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8; + RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + //else + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \ + !defined (STM32L011xx) && !defined (STM32L021xx) + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */ +#endif + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + // PLLCLK = (16 MHz * 6)/3 = 32 MHz + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_6; + RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_3; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return 0; // FAIL + } + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */ + while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {}; + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_stm32l0xx.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_stm32l0xx.h new file mode 100644 index 00000000000..fcf76495699 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_stm32l0xx.h @@ -0,0 +1,128 @@ +/** + ****************************************************************************** + * @file system_stm32l0xx.h + * @author MCD Application Team + * @version V1.7.0 + * @date 31-May-2016 + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l0xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32L0XX_H +#define __SYSTEM_STM32L0XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32L0xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32L0xx_System_Exported_types + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +/* +*/ +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32L0XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/objects.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/objects.h new file mode 100644 index 00000000000..63dc73c511b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/objects.h @@ -0,0 +1,79 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct analogin_s { + ADCName adc; + PinName pin; + uint32_t channel; +}; + +struct dac_s { + DACName dac; + PinName pin; + uint32_t channel; +}; + +struct trng_s { + RNG_HandleTypeDef handle; +}; + +#include "common_objects.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.c index 7466e9989a7..69eca7e257f 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc_ex.c @@ -271,7 +271,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } -#if defined (STM32L071xx) || (STM32L072xx) || defined(STM32L073xx) || \ +#if defined (STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || \ defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) /*------------------------------ I2C3 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) diff --git a/targets/TARGET_STM/gpio_api.c b/targets/TARGET_STM/gpio_api.c index d309b956933..60d300d32cd 100644 --- a/targets/TARGET_STM/gpio_api.c +++ b/targets/TARGET_STM/gpio_api.c @@ -41,34 +41,34 @@ GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx) { switch (port_idx) { case PortA: gpio_add = GPIOA_BASE; - __GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); break; case PortB: gpio_add = GPIOB_BASE; - __GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); break; #if defined(GPIOC_BASE) case PortC: gpio_add = GPIOC_BASE; - __GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); break; #endif #if defined GPIOD_BASE case PortD: gpio_add = GPIOD_BASE; - __GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); break; #endif #if defined GPIOE_BASE case PortE: gpio_add = GPIOE_BASE; - __GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); break; #endif #if defined GPIOF_BASE case PortF: gpio_add = GPIOF_BASE; - __GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); break; #endif #if defined GPIOG_BASE @@ -78,31 +78,31 @@ GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx) { HAL_PWREx_EnableVddIO2(); #endif gpio_add = GPIOG_BASE; - __GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); break; #endif #if defined GPIOH_BASE case PortH: gpio_add = GPIOH_BASE; - __GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); break; #endif #if defined GPIOI_BASE case PortI: gpio_add = GPIOI_BASE; - __GPIOI_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); break; #endif #if defined GPIOJ_BASE case PortJ: gpio_add = GPIOJ_BASE; - __GPIOJ_CLK_ENABLE(); + __HAL_RCC_GPIOJ_CLK_ENABLE(); break; #endif #if defined GPIOK_BASE case PortK: gpio_add = GPIOK_BASE; - __GPIOK_CLK_ENABLE(); + __HAL_RCC_GPIOK_CLK_ENABLE(); break; #endif default: diff --git a/targets/TARGET_STM/hal_tick_16b.c b/targets/TARGET_STM/hal_tick_16b.c index 7133b35e8a7..150c25c677e 100644 --- a/targets/TARGET_STM/hal_tick_16b.c +++ b/targets/TARGET_STM/hal_tick_16b.c @@ -84,12 +84,12 @@ void timer_oc_irq_handler(void) if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) { if (__HAL_TIM_GET_IT_SOURCE(&TimMasterHandle, TIM_IT_CC2) == SET) { __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2); - uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle); + uint32_t val = __HAL_TIM_GET_COUNTER(&TimMasterHandle); if ((val - PreviousVal) >= HAL_TICK_DELAY) { // Increment HAL variable HAL_IncTick(); // Prepare next interrupt - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); PreviousVal = val; #if DEBUG_TICK > 0 HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); @@ -128,8 +128,8 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) // Configure output compare channel 2 for HAL tick HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); - PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + PreviousVal = __HAL_TIM_GET_COUNTER(&TimMasterHandle); + __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); // Configure interrupts // Update interrupt used for 32-bit counter @@ -155,7 +155,7 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) HAL_TIM_Base_Start(&TimMasterHandle); #if DEBUG_TICK > 0 - __GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; diff --git a/targets/TARGET_STM/hal_tick_32b.c b/targets/TARGET_STM/hal_tick_32b.c index 0f9c3dccad2..3ccd52b4ee5 100644 --- a/targets/TARGET_STM/hal_tick_32b.c +++ b/targets/TARGET_STM/hal_tick_32b.c @@ -47,7 +47,7 @@ void timer_irq_handler(void) // Increment HAL variable HAL_IncTick(); // Prepare next interrupt - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); + __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY); PreviousVal = val; #if DEBUG_TICK > 0 HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6); @@ -115,11 +115,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) // Channel 2 for HAL tick HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2); PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle); - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); + __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); #if DEBUG_TICK > 0 - __GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = GPIO_PIN_6; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c index 23e4fa6d13c..2c1cddf7c38 100644 --- a/targets/TARGET_STM/i2c_api.c +++ b/targets/TARGET_STM/i2c_api.c @@ -436,9 +436,9 @@ void i2c_frequency(i2c_t *obj, int hz) // I2C configuration handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLED; - handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLED; - handle->Init.NoStretchMode = I2C_NOSTRETCH_DISABLED; + handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + handle->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; handle->Init.OwnAddress1 = 0; handle->Init.OwnAddress2 = 0; HAL_I2C_Init(handle); diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index 14fdd3380d6..f0d09701bf8 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -572,6 +572,21 @@ #define OS_CLOCK 32000000 #endif +#elif defined(TARGET_STM32L072CZ) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20005000UL) +#endif +#ifndef OS_TASKCNT +#define OS_TASKCNT 6 +#endif +#ifndef OS_MAINSTKSIZE +#define OS_MAINSTKSIZE 112 +#endif +#ifndef OS_CLOCK +#define OS_CLOCK 32000000 +#endif + #elif defined(TARGET_STM32L073RZ) #ifndef INITIAL_SP diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 7e97c2ef422..66255db0caa 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -83,7 +83,7 @@ void rtc_init(void) error("PeriphClkInitStruct RTC failed with LSE\n"); } #else /* !RTC_LSI */ - __PWR_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); // Reset Backup domain __HAL_RCC_BACKUPRESET_FORCE(); @@ -147,7 +147,7 @@ void rtc_free(void) { #if RTC_LSI // Enable Power clock - __PWR_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); // Enable access to Backup domain HAL_PWR_EnableBkUpAccess(); diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c index f756102e396..ba3f27371db 100644 --- a/targets/TARGET_STM/stm_spi_api.c +++ b/targets/TARGET_STM/stm_spi_api.c @@ -158,11 +158,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel handle->Init.Direction = SPI_DIRECTION_2LINES; handle->Init.CLKPhase = SPI_PHASE_1EDGE; handle->Init.CLKPolarity = SPI_POLARITY_LOW; - handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; + handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; handle->Init.CRCPolynomial = 7; handle->Init.DataSize = SPI_DATASIZE_8BIT; handle->Init.FirstBit = SPI_FIRSTBIT_MSB; - handle->Init.TIMode = SPI_TIMODE_DISABLED; + handle->Init.TIMode = SPI_TIMODE_DISABLE; init_spi(obj); } @@ -357,7 +357,7 @@ int spi_master_write(spi_t *obj, int value) size = (handle->Init.DataSize == SPI_DATASIZE_16BIT) ? 2 : 1; /* Use 10ms timeout */ - ret = HAL_SPI_TransmitReceive(handle,(uint8_t*)&value,(uint8_t*)&Rx,size,10); + ret = HAL_SPI_TransmitReceive(handle,(uint8_t*)&value,(uint8_t*)&Rx,size,HAL_MAX_DELAY); if(ret == HAL_OK) { return Rx; diff --git a/targets/TARGET_STM/us_ticker_16b.c b/targets/TARGET_STM/us_ticker_16b.c index 0b4f3747d71..8480391dbd8 100644 --- a/targets/TARGET_STM/us_ticker_16b.c +++ b/targets/TARGET_STM/us_ticker_16b.c @@ -35,7 +35,7 @@ void set_compare(uint16_t count) { TimMasterHandle.Instance = TIM_MST; // Set new output compare value - __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count); + __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_1, count); // Enable IT __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1); } diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/startup_W7500.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/startup_W7500.S index 2808b2ad576..48966901cbc 100644 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/startup_W7500.S +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_GCC_ARM/startup_W7500.S @@ -188,8 +188,8 @@ Reset_Handler: .LC3: #endif /* __STARTUP_CLEAR_BSS */ - /*bl _start*/ - bl main + bl _start + //bl main .pool .size Reset_Handler, . - Reset_Handler diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/W7500_Flash.icf b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/W7500_Flash.icf new file mode 100644 index 00000000000..dd71139d172 --- /dev/null +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/W7500_Flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00020000; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20004000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x00000400; +define symbol __ICFEDIT_size_heap__ = 0x00000400; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.s b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.s new file mode 100644 index 00000000000..1b28c47f624 --- /dev/null +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.s @@ -0,0 +1,305 @@ +;/******************************************************************************************************************************************************* +; * Copyright ¨Ï 2016 +; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the Ħ°SoftwareĦħ), +; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, +; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +; +; * THE SOFTWARE IS PROVIDED Ħ°AS ISĦħ, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +;*********************************************************************************************************************************************************/ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V1.08 +; * @date 23. November 2012 +; * +; * @note +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Exterval Interrupts + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK SSP0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP0_Handler + B SSP0_Handler + + PUBWEAK SSP1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP1_Handler + B SSP1_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B UART2_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK PORT0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_Handler + B PORT0_Handler + + PUBWEAK PORT1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_Handler + B PORT1_Handler + + PUBWEAK PORT2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_Handler + B PORT2_Handler + + PUBWEAK PORT3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_Handler + B PORT3_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK DUALTIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER0_Handler + B DUALTIMER0_Handler + + PUBWEAK DUALTIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER1_Handler + B DUALTIMER1_Handler + + PUBWEAK PWM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM0_Handler + B PWM0_Handler + + PUBWEAK PWM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM1_Handler + B PWM1_Handler + + PUBWEAK PWM2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM2_Handler + B PWM2_Handler + + PUBWEAK PWM3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM3_Handler + B PWM3_Handler + + PUBWEAK PWM4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM4_Handler + B PWM4_Handler + + PUBWEAK PWM5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM5_Handler + B PWM5_Handler + + PUBWEAK PWM6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM6_Handler + B PWM6_Handler + + PUBWEAK PWM7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM7_Handler + B PWM7_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK ADC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_Handler + B ADC_Handler + + PUBWEAK WZTOE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WZTOE_Handler + B WZTOE_Handler + + PUBWEAK EXTI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI_Handler + B EXTI_Handler + + END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.S index 2808b2ad576..48966901cbc 100644 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.S +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.S @@ -188,8 +188,8 @@ Reset_Handler: .LC3: #endif /* __STARTUP_CLEAR_BSS */ - /*bl _start*/ - bl main + bl _start + //bl main .pool .size Reset_Handler, . - Reset_Handler diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.o b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.o deleted file mode 100644 index 61549404812..00000000000 Binary files a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_GCC_ARM/startup_W7500.o and /dev/null differ diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/W7500_Flash.icf b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/W7500_Flash.icf new file mode 100644 index 00000000000..dd71139d172 --- /dev/null +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/W7500_Flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00020000; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20004000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x00000400; +define symbol __ICFEDIT_size_heap__ = 0x00000400; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.s b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.s new file mode 100644 index 00000000000..1b28c47f624 --- /dev/null +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.s @@ -0,0 +1,305 @@ +;/******************************************************************************************************************************************************* +; * Copyright ¨Ï 2016 +; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the Ħ°SoftwareĦħ), +; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, +; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +; +; * THE SOFTWARE IS PROVIDED Ħ°AS ISĦħ, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +;*********************************************************************************************************************************************************/ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V1.08 +; * @date 23. November 2012 +; * +; * @note +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Exterval Interrupts + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK SSP0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP0_Handler + B SSP0_Handler + + PUBWEAK SSP1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP1_Handler + B SSP1_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B UART2_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK PORT0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_Handler + B PORT0_Handler + + PUBWEAK PORT1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_Handler + B PORT1_Handler + + PUBWEAK PORT2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_Handler + B PORT2_Handler + + PUBWEAK PORT3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_Handler + B PORT3_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK DUALTIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER0_Handler + B DUALTIMER0_Handler + + PUBWEAK DUALTIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER1_Handler + B DUALTIMER1_Handler + + PUBWEAK PWM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM0_Handler + B PWM0_Handler + + PUBWEAK PWM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM1_Handler + B PWM1_Handler + + PUBWEAK PWM2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM2_Handler + B PWM2_Handler + + PUBWEAK PWM3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM3_Handler + B PWM3_Handler + + PUBWEAK PWM4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM4_Handler + B PWM4_Handler + + PUBWEAK PWM5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM5_Handler + B PWM5_Handler + + PUBWEAK PWM6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM6_Handler + B PWM6_Handler + + PUBWEAK PWM7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM7_Handler + B PWM7_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK ADC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_Handler + B ADC_Handler + + PUBWEAK WZTOE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WZTOE_Handler + B WZTOE_Handler + + PUBWEAK EXTI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI_Handler + B EXTI_Handler + + END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/startup_W7500.S b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/startup_W7500.S index 2808b2ad576..48966901cbc 100644 --- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/startup_W7500.S +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_GCC_ARM/startup_W7500.S @@ -188,8 +188,8 @@ Reset_Handler: .LC3: #endif /* __STARTUP_CLEAR_BSS */ - /*bl _start*/ - bl main + bl _start + //bl main .pool .size Reset_Handler, . - Reset_Handler diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/W7500_Flash.icf b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/W7500_Flash.icf new file mode 100644 index 00000000000..dd71139d172 --- /dev/null +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/W7500_Flash.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x00020000; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20004000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x00000400; +define symbol __ICFEDIT_size_heap__ = 0x00000400; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.s b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.s new file mode 100644 index 00000000000..1b28c47f624 --- /dev/null +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.s @@ -0,0 +1,305 @@ +;/******************************************************************************************************************************************************* +; * Copyright ¨Ï 2016 +; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the Ħ°SoftwareĦħ), +; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, +; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +; +; * THE SOFTWARE IS PROVIDED Ħ°AS ISĦħ, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +;*********************************************************************************************************************************************************/ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V1.08 +; * @date 23. November 2012 +; * +; * @note +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Exterval Interrupts + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK SSP0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP0_Handler + B SSP0_Handler + + PUBWEAK SSP1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP1_Handler + B SSP1_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B UART2_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK PORT0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_Handler + B PORT0_Handler + + PUBWEAK PORT1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_Handler + B PORT1_Handler + + PUBWEAK PORT2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_Handler + B PORT2_Handler + + PUBWEAK PORT3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_Handler + B PORT3_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK DUALTIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER0_Handler + B DUALTIMER0_Handler + + PUBWEAK DUALTIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER1_Handler + B DUALTIMER1_Handler + + PUBWEAK PWM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM0_Handler + B PWM0_Handler + + PUBWEAK PWM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM1_Handler + B PWM1_Handler + + PUBWEAK PWM2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM2_Handler + B PWM2_Handler + + PUBWEAK PWM3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM3_Handler + B PWM3_Handler + + PUBWEAK PWM4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM4_Handler + B PWM4_Handler + + PUBWEAK PWM5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM5_Handler + B PWM5_Handler + + PUBWEAK PWM6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM6_Handler + B PWM6_Handler + + PUBWEAK PWM7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM7_Handler + B PWM7_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK ADC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_Handler + B ADC_Handler + + PUBWEAK WZTOE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WZTOE_Handler + B WZTOE_Handler + + PUBWEAK EXTI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI_Handler + B EXTI_Handler + + END diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.c b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.c index c713cc56980..294bfa7eeea 100644 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.c +++ b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_adc.c @@ -36,20 +36,21 @@ uint8_t ADC_IsInterrupt (void) void ADC_InterruptClear (void) { - ADC->ADC_INT = ADC_INTCLEAR; + ADC->ADC_INT = ADC_INTCLEAR; } void ADC_Init (void) { - // ADC_CLK on - ADC_PowerDownEnable(DISABLE); - //ADC_ChannelSelect(num); + // ADC_CLK on + ADC_PowerDownEnable(ENABLE); + ADC_PowerDownEnable(DISABLE); + //ADC_ChannelSelect(num); } void ADC_DeInit (void) { - // ADC_CLK off - ADC_PowerDownEnable(ENABLE); - ADC_InterruptMask(DISABLE); + // ADC_CLK off + ADC_PowerDownEnable(ENABLE); + ADC_InterruptMask(DISABLE); } diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_gpio.c b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_gpio.c index 1257eb4fa8b..7af2ab0cdd4 100644 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_gpio.c +++ b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_gpio.c @@ -67,6 +67,8 @@ void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); // assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); + GPIOx->INTTYPESET = 0x00FF; + if (GPIOx == GPIOA) px_pcr = PA_PCR; else if (GPIOx == GPIOB) px_pcr = PB_PCR; else if (GPIOx == GPIOC) px_pcr = PC_PCR; @@ -260,26 +262,30 @@ void HAL_PAD_AFConfig(PAD_Type Px, uint16_t GPIO_Pin, PAD_AF_TypeDef P_AF) if(Px == PAD_PA) { assert_param(IS_PA_NUM(i)); - PA_AFSR->Port[i] &= ~(0x03ul); - PA_AFSR->Port[i] |= P_AF; + //PA_AFSR->Port[i] &= ~(0x03ul); + //PA_AFSR->Port[i] |= P_AF; + PA_AFSR->Port[i] = P_AF; } else if(Px == PAD_PB) { assert_param(IS_PB_NUM(i)); - PB_AFSR->Port[i] &= ~(0x03ul); - PB_AFSR->Port[i] |= P_AF; + //PB_AFSR->Port[i] &= ~(0x03ul); + //PB_AFSR->Port[i] |= P_AF; + PB_AFSR->Port[i] = P_AF; } else if(Px == PAD_PC) { assert_param(IS_PC_NUM(i)); - PC_AFSR->Port[i] &= ~(0x03ul); - PC_AFSR->Port[i] |= P_AF; + //PC_AFSR->Port[i] &= ~(0x03ul); + //PC_AFSR->Port[i] |= P_AF; + PC_AFSR->Port[i] = P_AF; } else { assert_param(IS_PD_NUM(i)); - PD_AFSR->Port[i] &= ~(0x03ul); - PD_AFSR->Port[i] |= P_AF; + //PD_AFSR->Port[i] &= ~(0x03ul); + //PD_AFSR->Port[i] |= P_AF; + PD_AFSR->Port[i] = P_AF; } } } diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c index 560e154980f..e7436ef509a 100644 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c +++ b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.c @@ -1,21 +1,59 @@ +/******************************************************************************************************************************************************* + * Copyright ¨Ï 2016 + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the Ħ°SoftwareĦħ), + * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED Ħ°AS ISĦħ, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*********************************************************************************************************************************************************/ /** ****************************************************************************** - * @file W7500x_uart.c - * @author - * @version - * @date - * @brief + * @file W7500x_stdPeriph_Driver/src/W7500x_uart.c + * @author IOP Team + * @version v1.0.0 + * @date 01-May-2015 + * @brief This file contains all the functions prototypes for the uart + * firmware library. ****************************************************************************** - * @attention * - * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ -#include "W7500x.h" #include "W7500x_uart.h" +/** @addtogroup W7500x_Periph_Driver + * @{ + */ + +/** @defgroup UART + * @brief UART driver modules + * @{ + */ + + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup UART_Private_Functions + * @{ + */ + +/** + * @brief Fills each UART_InitStruct member with its default value. + * @param UART_StructInit: pointer to a UART_InitTypeDef structure which will + * be initialized. + * @retval None + */ void UART_StructInit(UART_InitTypeDef* UART_InitStruct) { /* UART_InitStruct members default value */ @@ -24,20 +62,34 @@ void UART_StructInit(UART_InitTypeDef* UART_InitStruct) UART_InitStruct->UART_StopBits = UART_StopBits_1; UART_InitStruct->UART_Parity = UART_Parity_No ; UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx; - UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None ; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None ; } +/* Function check */ +/* This function is checking now. Update or remove maybe. */ +//Why be???? void UART_DeInit(UART_TypeDef *UARTx) { } +/** + * @brief Initializes the UART peripheral according to the specified + * parameters in the UART_InitStruct . + * @param UARTx: where x can be 1, 2 or 3 + * @param UART_InitStruct: pointer to a UART_InitTypeDef structure that contains + * the configuration information for the specified UART peripheral. + * @retval None + */ + uint32_t UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct) { + float baud_divisor; - uint32_t tmpreg=0x00, uartclock=0x00; - uint32_t integer_baud = 0x00, fractional_baud = 0x00; + uint32_t tmpreg=0x00, uartclock=0x00; + uint32_t integer_baud = 0x00, fractional_baud = 0x00; + /* Check the parameters */ assert_param(IS_UART_01_PERIPH(UARTx)); assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength)); assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity)); @@ -45,53 +97,101 @@ uint32_t UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct) assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl)); assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode)); + /* Write to UART CR */ + UARTx->CR &= ~(UART_CR_UARTEN); - UARTx->CR &= ~(UART_CR_UARTEN); - - // Set baudrate - CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; // Set UART Clock using internal Oscilator ( 8MHz ) - uartclock = (8000000UL) / (1 << CRG->UARTCLK_PVSR); + /* Set baudrate */ + /* CRG_UARTCLK_SSR_RCLK: Set UART Clock using internal Oscilator ( 8MHz ) */ + /* CRG_UARTCLK_SSR_OCLK: Set UART Clock using external Oscilator */ + CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; // Set UART Clock using internal Oscilator ( 8MHz ) + //CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_OCLK; // Set UART Clock using external Oscilator - baud_divisor = ((float)uartclock / (16 * UART_InitStruct->UART_BaudRate)); - integer_baud = (uint32_t)baud_divisor; - fractional_baud = (uint32_t)((baud_divisor - integer_baud) * 64 + 0.5); + /* Set uartclock */ + uartclock = (8000000UL) / (1 << CRG->UARTCLK_PVSR); + + /*----------------------------- UARTx IBRD and FBRD Configuration ------------------------------*/ + baud_divisor = ((float)uartclock / (16 * UART_InitStruct->UART_BaudRate)); + integer_baud = (uint32_t)baud_divisor; + fractional_baud = (uint32_t)((baud_divisor - integer_baud) * 64 + 0.5); - UARTx->IBRD = integer_baud; - UARTx->FBRD = fractional_baud; + UARTx->IBRD = integer_baud; + UARTx->FBRD = fractional_baud; tmpreg = UARTx->LCR_H; tmpreg &= ~(0x00EE); tmpreg |= (UART_InitStruct->UART_WordLength | UART_InitStruct->UART_StopBits | UART_InitStruct->UART_Parity); - UARTx->LCR_H |= tmpreg; + UARTx->LCR_H = tmpreg; tmpreg = UARTx->CR; tmpreg &= ~(UART_CR_CTSEn | UART_CR_RTSEn | UART_CR_RXE | UART_CR_TXE | UART_CR_UARTEN); tmpreg |= (UART_InitStruct->UART_Mode | UART_InitStruct->UART_HardwareFlowControl); - UARTx->CR |= tmpreg; + UARTx->CR = tmpreg; + + /* Debug */ + /* UARTx->LCR_H |=0x10; */ + /* UARTx->IFLS | = 0x00; */ UARTx->CR |= UART_CR_UARTEN; return 0; } +/** + * @brief UART_FIFO_Enable + * @param case rx_fifo_level=0: 1/8 full, case rx_fifo_level=1: 1/4 full, case rx_fifo_level=2: 1/2 full, + * case rx_fifo_level=3: 3/4 full, case rx_fifo_level=4: 7/8 full + * @param case tx_fifo_level=0: 1/8 full, case tx_fifo_level=1: 1/4 full, case tx_fifo_level=2: 1/2 full, + * case tx_fifo_level=3: 3/4 full, case tx_fifo_level=4: 7/8 full + * @retval None + */ + +void UART_FIFO_Enable(UART_TypeDef *UARTx, uint16_t rx_fifo_level, uint16_t tx_fifo_level) +{ + UARTx->LCR_H |= UART_LCR_H_FEN; + UARTx->IFLS = (UART_IFLS_RXIFLSEL(rx_fifo_level) | UART_IFLS_TXIFLSEL(tx_fifo_level)); +} + +/** + * @brief UART_FIFO_Disable + * @param UARTx: Define structure at "W7500x.h" + * @retval None + */ +void UART_FIFO_Disable(UART_TypeDef *UARTx) +{ + UARTx->LCR_H &= ~(UART_LCR_H_FEN); +} +/** + * @brief UART_SendData + * @param UARTx: Define structure at "W7500x.h" + * @param Data: Unsigned short value + * @retval None + */ void UART_SendData(UART_TypeDef* UARTx, uint16_t Data) { + /* Check the parameters */ assert_param(IS_UART_01_PERIPH(UARTx)); - UARTx->DR = Data; } - +/** + * @brief UART_ReceiveData + * @param UARTx: Define structure at "W7500x.h" + * @retval None + */ uint16_t UART_ReceiveData(UART_TypeDef* UARTx) { + /* Check the parameters */ assert_param(IS_UART_01_PERIPH(UARTx)); - return (uint16_t)(UARTx->DR); } - +/** + * @brief UART_SendBreak + * @param UARTx: Define structure at "W7500x.h" + * @retval None + */ void UART_SendBreak(UART_TypeDef* UARTx) { assert_param(IS_UART_01_PERIPH(UARTx)); @@ -99,11 +199,17 @@ void UART_SendBreak(UART_TypeDef* UARTx) UARTx->LCR_H |= UART_LCR_H_BRK; } - +/** + * @brief UART_GetRecvStatus + * @param UARTx: Define structure at "W7500x.h" + * @param UART_RECV_STATUS + * @retval bitstatus + */ FlagStatus UART_GetRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS) { FlagStatus bitstatus = RESET; - + + /* Check the parameters */ assert_param(IS_UART_01_PERIPH(UARTx)); assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS)); @@ -119,29 +225,44 @@ FlagStatus UART_GetRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS) return bitstatus; } - +/** + * @brief UART_ClearRecvStatus + * @param UARTx: Define structure at "W7500x.h" + * @param UART_RECV_STATUS + * @retval None + */ void UART_ClearRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS) { + /* Check the parameters */ assert_param(IS_UART_01_PERIPH(UARTx)); assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS)); + /* Set STATUS.ECR*/ UARTx->STATUS.ECR = (uint16_t)UART_RECV_STATUS; } - +/** + * @brief UART_GetFlagStatus + * @param UARTx: Define structure at "W7500x.h" + * @param UART_FLAG + * @retval bitstatus + */ FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG) { FlagStatus bitstatus = RESET; + /* Check the parameters */ assert_param(IS_UART_01_PERIPH(UARTx)); assert_param(IS_UART_FLAG(UART_FLAG)); if ((UARTx->FR & UART_FLAG) != (uint16_t)RESET) { + /* bitstatus setting to SET*/ bitstatus = SET; } else { + /*bitstatus setting to RESET*/ bitstatus = RESET; } @@ -149,109 +270,194 @@ FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG) } -/* +/* Function check */ +/* This function is checking now. Update or remove maybe. */ +//Why be? + void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG) { } -*/ + +/** + * @brief UART_ITConfig + * @param UARTx: Define structure at "W7500x.h" + * @param UART_IT + * @param NewState + * @retval None + */ void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState) { + /* Check the parameters */ assert_param(IS_UART_01_PERIPH(UARTx)); assert_param(IS_UART_IT_FLAG(UART_IT)); if ( NewState != DISABLE ) { + /*Set the IMSC*/ UARTx->IMSC |= UART_IT; } else { + /*Set the ICR*/ UARTx->ICR |= UART_IT; } } - +/** + * @brief UART_GetITStatus + * @param UARTx: Define structure at "W7500x.h" + * @param UART_IT + * @param bitstatus + * @retval None + */ ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT) { ITStatus bitstatus = RESET; - + /* Check the parameters */ assert_param(IS_UART_01_PERIPH(UARTx)); assert_param(IS_UART_IT_FLAG(UART_IT)); if ((UARTx->MIS & UART_IT) != (uint16_t)RESET) { + /*Set bitstatus = SET */ bitstatus = SET; } else { + /*Set bitstatus = RESET */ bitstatus = RESET; } return bitstatus; } +/** + * @brief UART_ITPendingBit + * @param UARTx: Define structure at "W7500x.h" + * @param UART_IT + * @retval None + */ void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT) { + /* Check the parameters */ assert_param(IS_UART_01_PERIPH(UARTx)); assert_param(IS_UART_IT_FLAG(UART_IT)); + /* Set ICR */ UARTx->ICR |= UART_IT; } +/** + * @brief UART_DMA_Config + * @param UARTx: Define structure at "W7500x.h" + * @param UART_DMA_CONTROL + * @retval None + */ +void UART_DMA_Config(UART_TypeDef* UARTx, uint16_t UART_DMA_CONTROL) +{ + /* Check the parameters */ + assert_param(IS_UART_01_PERIPH(UARTx)); + assert_param(IS_UART_DMA_CONTROL(UART_DMA_CONTROL)); + + /*Set DMACR */ + UARTx->DMACR |= UART_DMA_CONTROL; +} +/* Function check */ +/* This function is checking now. Update or remove maybe. */ +//Why be? void S_UART_DeInit() { } +/** + * @brief S_UART_Init + * @param baud + * @retval None + */ uint32_t S_UART_Init(uint32_t baud) { uint32_t tmpreg=0x00; S_UART_SetBaud(baud); + /* Set temp register for UART2 CTRL */ tmpreg = UART2->CTRL; tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN); tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN); + + /* Write to UART2 CTRL */ UART2->CTRL = tmpreg; return 0; } +/** + * @brief S_UART_SetBaud + * @param baud + * @retval None + */ void S_UART_SetBaud(uint32_t baud) { uint32_t uartclock = 0x00, integer_baud = 0x00; + + /* Check the parameters */ + assert_param(IS_UART_MODE(S_UART_InitStruct->UART_Mode)); if(CRG->FCLK_SSR == CRG_FCLK_SSR_RCLK) { - uartclock = INTERN_XTAL; + /* Set uartclock: INTERN_XTAL */ + uartclock = INTERN_XTAL; } else if(CRG->FCLK_SSR == CRG_FCLK_SSR_OCLK) { + /* Set uartclock: EXTERN_XTAL */ uartclock = EXTERN_XTAL; } else { + /* Set uartclock: GetSystemClock */ uartclock = GetSystemClock(); } + /* Set (Calculate) integer_baud */ integer_baud = (uint32_t)(uartclock / baud); + /* Write UART2 BAUDDIV */ UART2->BAUDDIV = integer_baud; } + +/** + * @brief S_UART_SendData + * @param Data + * @retval None + */ void S_UART_SendData(uint16_t Data) { while(UART2->STATE & S_UART_STATE_TX_BUF_FULL); + /* Write UART2 DATA */ UART2->DATA = Data; } + +/** + * @brief S_UART_ReceiveData + * @retval UART2 DATA + */ uint16_t S_UART_ReceiveData() { return (uint16_t)(UART2->DATA); } +/** + * @brief S_UART_GetFlagStatus + * @param UART_STATE + * @retval bitstatus + */ FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_STATE) { FlagStatus bitstatus = RESET; @@ -270,6 +476,13 @@ FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_STATE) return bitstatus; } + +/** + * @brief S_UART_SetCTRL + * @param S_UART_CTRL + * @param NewState + * @retval None + */ void S_UART_SetCTRL(uint16_t S_UART_CTRL, FunctionalState NewState) { if ( NewState != DISABLE ) @@ -283,49 +496,77 @@ void S_UART_SetCTRL(uint16_t S_UART_CTRL, FunctionalState NewState) } +/** + * @brief S_UART_ITConfig + * @param S_UART_CTRL + * @param NewState + * @retval None + */ void S_UART_ITConfig(uint16_t S_UART_CTRL, FunctionalState NewState) { + /* Check the parameters */ assert_param(IS_S_UART_CTRL_FLAG(S_UART_CTRL)); if ( NewState != DISABLE ) { + /* Set UART2 CTRL: S_UART_CTRL */ UART2->CTRL |= S_UART_CTRL; } else { + /*Set UART2 CTRL: ~S_UART_CTRL */ UART2->CTRL &= ~(S_UART_CTRL); } } + +/** + * @brief S_UART_GetTStatus + * @param S_UART_INTSTATUS + * @retval bitstatus + */ ITStatus S_UART_GetITStatus(uint16_t S_UART_INTSTATUS) { ITStatus bitstatus = RESET; - + + /* Check the parameters */ assert_param(IS_S_UART_INTSATUS(S_UART_INTSTATUS)); if ((UART2->INT.STATUS & (S_UART_INTSTATUS)) != (uint16_t) RESET) { + /* Set bitstatus: SET */ bitstatus = SET; } else { + /* Set bitstatus: RESET */ bitstatus = RESET; } return bitstatus; } + +/** + * @brief S_UART_ClearITPendingBit + * @param S_UART_INTSTATUS + * @retval None + */ void S_UART_ClearITPendingBit(uint16_t S_UART_INTSTATUS) { + /* Check the parameters */ assert_param(IS_S_UART_INTSATUS(S_UART_INTSTATUS)); - + /* Write UART2 INT.CLEAR: S_UART_INSTATUS */ UART2->INT.CLEAR |= (S_UART_INTSTATUS); } + /**************************************************/ // It will be moved to application board's driver */ /**************************************************/ + + uint8_t UartPutc(UART_TypeDef* UARTx, uint8_t ch) { UART_SendData(UARTx,ch); @@ -335,6 +576,8 @@ uint8_t UartPutc(UART_TypeDef* UARTx, uint8_t ch) return (ch); } + + void UartPuts(UART_TypeDef* UARTx, uint8_t *str) { uint8_t ch; @@ -349,6 +592,7 @@ void UartPuts(UART_TypeDef* UARTx, uint8_t *str) }while(ch != 0); } + uint8_t UartGetc(UART_TypeDef* UARTx) { while(UARTx->FR & UART_FR_RXFE); @@ -364,6 +608,8 @@ uint8_t S_UartPutc(uint8_t ch) return (ch); } + + void S_UartPuts(uint8_t *str) { uint8_t ch; @@ -378,6 +624,7 @@ void S_UartPuts(uint8_t *str) }while(ch != 0); } + uint8_t S_UartGetc() { while( (UART2->STATE & S_UART_STATE_RX_BUF_FULL) == 0 ); @@ -385,3 +632,16 @@ uint8_t S_UartGetc() } +/** + * @} + */ + + +/** + * @} + */ + + +/** + * @} + */ diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h index cc0b897b353..e85d3d73ca4 100644 --- a/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h +++ b/targets/TARGET_WIZNET/TARGET_W7500x/W7500x_Peripheral_Library/W7500x_uart.h @@ -1,9 +1,22 @@ +/******************************************************************************************************************************************************* + * Copyright ¨Ï 2016 + * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the Ħ°SoftwareĦħ), + * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED Ħ°AS ISĦħ, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +*********************************************************************************************************************************************************/ /** ****************************************************************************** - * @file - * @author - * @version - * @date + * @file W7500x_stdPeriph_Driver/inc/W7500x_uart.h + * @author IOP Team + * @version V1.0.0 + * @date 01-May-2015 * @brief This file contains all the functions prototypes for the UART * firmware library. ****************************************************************************** @@ -23,6 +36,15 @@ #include "W7500x.h" +/** @addtogroup W7500x_Periph_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + + /** * @brief UART Init Structure definition */ @@ -108,7 +130,8 @@ typedef struct #define UART_Mode_Rx ((uint16_t)(UART_CR_RXE)) #define UART_Mode_Tx ((uint16_t)(UART_CR_TXE)) #define IS_UART_MODE(MODE) (((MODE) == UART_Mode_Rx) || \ - ((MODE) == UART_Mode_Tx)) + ((MODE) == UART_Mode_Tx) || \ + ((MODE) == (UART_Mode_Rx | UART_Mode_Tx))) /** * @} @@ -133,6 +156,22 @@ typedef struct */ +/** @addtogroup UART_DMA_Control + * @{ + */ + +#define UART_DMAControl_DMAONERR ((uint16_t)UART_DMACR_DMAONERR) +#define UART_DMAControl_RXDMAE ((uint16_t)UART_DMACR_TXDMAE) +#define UART_DMAControl_TXDMAE ((uint16_t)UART_DMACR_RXDMAE) +#define IS_UART_DMA_CONTROL(CONTROL) \ + (((CONTROL) == UART_DMAControl_DMAONERR) || \ + ((CONTROL) == UART_DMAControl_TXDMAE) || \ + ((CONTROL) == UART_DMAControl_RXDMAE)) +/** + * @} + */ + + /** @addtogroup UART_Receive Status * @{ */ @@ -183,7 +222,7 @@ typedef struct #define UART_IT_FLAG_FEI ((uint16_t)0x01UL << 7) /*!< Framing error interrupt */ #define UART_IT_FLAG_RTI ((uint16_t)0x01UL << 6) /*!< Receive timeout interrupt */ #define UART_IT_FLAG_TXI ((uint16_t)0x01UL << 5) /*!< Transmit interrupt */ -#define UART_IT_FLAG_RXI ((uint16_t)0x01UL << 4) /*!< Receive interrupt */ +#define UART_IT_FLAG_RXI ((uint16_t)0x01UL << 4) /*!< Receive interrupt */ #define UART_IT_FLAG_DSRMI ((uint16_t)0x01UL << 3) /*!< UARTDSR modem interrupt */ #define UART_IT_FLAG_DCDMI ((uint16_t)0x01UL << 2) /*!< UARTDCD modem interrupt */ #define UART_IT_FLAG_CTSMI ((uint16_t)0x01UL << 1) /*!< UARTCTS modem interrupt */ @@ -273,6 +312,8 @@ typedef struct void UART_StructInit (UART_InitTypeDef* UART_InitStruct); uint32_t UART_Init (UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_FIFO_Enable (UART_TypeDef *UARTx, uint16_t rx_fifo_level, uint16_t tx_fifo_level); +void UART_FIFO_Disable (UART_TypeDef *UARTx); void UART_SendData (UART_TypeDef* UARTx, uint16_t Data); uint16_t UART_ReceiveData (UART_TypeDef* UARTx); void UART_SendBreak (UART_TypeDef* UARTx); @@ -281,6 +322,7 @@ FlagStatus UART_GetFlagStatus (UART_TypeDef* UARTx, uint16_t UART_FLAG); void UART_ITConfig (UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState); ITStatus UART_GetITStatus (UART_TypeDef* UARTx, uint16_t UART_IT); void UART_ClearITPendingBit (UART_TypeDef* UARTx, uint16_t UART_IT); +void UART_DMA_Config(UART_TypeDef* UARTx, uint16_t UART_DMA_CONTROL); uint8_t UartPutc (UART_TypeDef* UARTx, uint8_t ch); void UartPuts (UART_TypeDef* UARTx, uint8_t *str); @@ -311,3 +353,10 @@ void S_UART_ClearITPendingBit(uint16_t S_UART_IT); #endif // __W7500X_UART_H +/** + * @} + */ + +/** + * @} + */ diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/analogin_api.c b/targets/TARGET_WIZNET/TARGET_W7500x/analogin_api.c index a6998b91e5b..14fd15d73b3 100644 --- a/targets/TARGET_WIZNET/TARGET_W7500x/analogin_api.c +++ b/targets/TARGET_WIZNET/TARGET_W7500x/analogin_api.c @@ -42,8 +42,6 @@ ADC_TypeDef * AdcHandle; -static int adc_inited = 0; - void analogin_init(analogin_t *obj, PinName pin) { // Get the peripheral name from the pin and assign it to the object @@ -57,12 +55,8 @@ void analogin_init(analogin_t *obj, PinName pin) // Save pin number for the read function obj->pin = pin; - // The ADC initialization is done once - if (adc_inited == 0) { - adc_inited = 1; - - ADC_Init(); - } + // The ADC initialization + ADC_Init(); } static inline uint16_t adc_read(analogin_t *obj) diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c b/targets/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c index 10ef6ae19b6..d64ee892467 100644 --- a/targets/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c +++ b/targets/TARGET_WIZNET/TARGET_W7500x/gpio_irq_api.c @@ -43,6 +43,7 @@ static gpio_irq_handler irq_handler; static uint32_t channel_ids[4][16]; + #ifdef __cplusplus extern "C"{ #endif @@ -50,6 +51,7 @@ void port_generic_handler(GPIO_TypeDef* GPIOx, uint32_t port_num); void PORT0_Handler(void) { + NVIC_ClearPendingIRQ(PORT0_IRQn); port_generic_handler(GPIOA, 0); } @@ -99,6 +101,8 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 obj->pin_num = WIZ_PIN_NUM(pin); obj->pin_index = WIZ_PIN_INDEX(pin); + //gpio_irq_disable(obj); + if (pin == NC) return -1; if(obj->port_num == 0) @@ -110,10 +114,11 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 else obj->irq_n = PORT3_IRQn; - //obj->event = EDGE_FALL; obj->pin = pin; - + obj->event = EDGE_NONE; + // Enable EXTI interrupt + NVIC_ClearPendingIRQ(obj->irq_n); NVIC_EnableIRQ(obj->irq_n); channel_ids[obj->port_num][obj->pin_num] = id; @@ -141,10 +146,13 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) obj->rise_null = 0; } else if (event == IRQ_FALL) { - gpio->INTPOLSET &= ~obj->pin_index; + gpio->INTPOLCLR |= obj->pin_index; obj->event = EDGE_FALL; obj->fall_null = 0; } + + + gpio->INTENCLR |= obj->pin_index; gpio->INTTYPESET |= obj->pin_index; gpio->INTENSET |= obj->pin_index; diff --git a/targets/TARGET_WIZNET/TARGET_W7500x/pinmap.c b/targets/TARGET_WIZNET/TARGET_W7500x/pinmap.c index c69be952a2a..4c1470e1a49 100644 --- a/targets/TARGET_WIZNET/TARGET_W7500x/pinmap.c +++ b/targets/TARGET_WIZNET/TARGET_W7500x/pinmap.c @@ -117,17 +117,29 @@ void pin_mode(PinName pin, PinMode pupd) uint32_t port_num = WIZ_PORT(pin); uint32_t pin_num = WIZ_PIN_NUM(pin); - switch(port_num) { + switch(port_num) { case PortA: + if(pupd != 0) { + PA_PCR->Port[pin_num] &= 0xFFFFFFFC; + } PA_PCR->Port[pin_num] |= pupd; break; case PortB: + if(pupd != 0) { + PB_PCR->Port[pin_num] &= 0xFFFFFFFC; + } PB_PCR->Port[pin_num] |= pupd; break; case PortC: + if(pupd != 0) { + PC_PCR->Port[pin_num] &= 0xFFFFFFFC; + } PC_PCR->Port[pin_num] |= pupd; break; case PortD: + if(pupd != 0) { + PD_PCR->Port[pin_num] &= 0xFFFFFFFC; + } PD_PCR->Port[pin_num] |= pupd; break; default: diff --git a/targets/TARGET_WIZNET/mbed_rtx.h b/targets/TARGET_WIZNET/mbed_rtx.h new file mode 100644 index 00000000000..c475509da13 --- /dev/null +++ b/targets/TARGET_WIZNET/mbed_rtx.h @@ -0,0 +1,67 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#if defined(TARGET_WIZWIKI_W7500) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20004000UL) +#endif +#ifndef OS_TASKCNT +#define OS_TASKCNT 6 +#endif +#ifndef OS_MAINSTKSIZE +#define OS_MAINSTKSIZE 128 +#endif +#ifndef OS_CLOCK +#define OS_CLOCK 20000000 +#endif + +#elif defined(TARGET_WIZWIKI_W7500P) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20004000UL) +#endif +#ifndef OS_TASKCNT +#define OS_TASKCNT 6 +#endif +#ifndef OS_MAINSTKSIZE +#define OS_MAINSTKSIZE 128 +#endif +#ifndef OS_CLOCK +#define OS_CLOCK 20000000 +#endif + +#elif defined(TARGET_WIZWIKI_W7500ECO) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20004000UL) +#endif +#ifndef OS_TASKCNT +#define OS_TASKCNT 6 +#endif +#ifndef OS_MAINSTKSIZE +#define OS_MAINSTKSIZE 128 +#endif +#ifndef OS_CLOCK +#define OS_CLOCK 20000000 +#endif + +#endif // + +#endif // MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index d3b6cf857b2..fee1dbaf479 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -564,6 +564,23 @@ "release_versions": ["2", "5"], "device_name": "MKW41Z512xxx4" }, + "MCU_K24F1M": { + "core": "Cortex-M4F", + "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], + "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "MCU_K24F", "KPSDK_MCUS", "KPSDK_CODE", "FLASH_CMSIS_ALGO"], + "is_disk_virtual": true, + "public": false, + "macros": ["CPU_MK24FN1M0VDC12", "FSL_RTOS_MBED"], + "inherits": ["Target"], + "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"], + "device_name": "MK24FN1M0xxx12" + }, + "RO359B": { + "supported_form_factors": ["ARDUINO"], + "inherits": ["MCU_K24F1M"], + "detect_code": ["1022"], + "release_versions": ["2", "5"] + }, "K64F": { "supported_form_factors": ["ARDUINO"], "core": "Cortex-M4F", @@ -730,6 +747,13 @@ "default_toolchain": "ARM", "extra_labels": ["STM", "STM32F2", "STM32F207ZG"], "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], + "config": { + "d11_configuration": { + "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)", + "value": "PA_7", + "macro_name": "STM32_D11_SPI_ETHERNET_PIN" + } + }, "inherits": ["Target"], "detect_code": ["0835"], "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USBHOST_OTHER"], @@ -877,6 +901,13 @@ "inherits": ["Target"], "core": "Cortex-M4F", "default_toolchain": "ARM", + "config": { + "d11_configuration": { + "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)", + "value": "PA_7", + "macro_name": "STM32_D11_SPI_ETHERNET_PIN" + } + }, "extra_labels": ["STM", "STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx", "STM32F429xI", "FLASH_CMSIS_ALGO"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], "progen": {"target": "nucleo-f429zi"}, @@ -893,6 +924,13 @@ "inherits": ["Target"], "core": "Cortex-M4F", "default_toolchain": "ARM", + "config": { + "d11_configuration": { + "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)", + "value": "PA_7", + "macro_name": "STM32_D11_SPI_ETHERNET_PIN" + } + }, "extra_labels": ["STM", "STM32F4", "STM32F439", "STM32F439ZI", "STM32F439xx", "STM32F439xI", "FLASH_CMSIS_ALGO"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], "progen": {"target": "nucleo-f439zi"}, @@ -948,6 +986,13 @@ "extra_labels": ["STM", "STM32F7", "STM32F746", "STM32F746xG", "STM32F746ZG"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], "default_toolchain": "ARM", + "config": { + "d11_configuration": { + "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)", + "value": "PA_7", + "macro_name": "STM32_D11_SPI_ETHERNET_PIN" + } + }, "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USBHOST_OTHER"], "supported_form_factors": ["ARDUINO"], "detect_code": ["0816"], @@ -962,6 +1007,13 @@ "extra_labels": ["STM", "STM32F7", "STM32F756", "STM32F756xG", "STM32F756ZG"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], "default_toolchain": "ARM", + "config": { + "d11_configuration": { + "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)", + "value": "PA_7", + "macro_name": "STM32_D11_SPI_ETHERNET_PIN" + } + }, "supported_form_factors": ["ARDUINO"], "detect_code": ["0819"], "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"], @@ -975,6 +1027,13 @@ "extra_labels": ["STM", "STM32F7", "STM32F767", "STM32F767xI", "STM32F767ZI"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], "default_toolchain": "ARM", + "config": { + "d11_configuration": { + "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)", + "value": "PA_7", + "macro_name": "STM32_D11_SPI_ETHERNET_PIN" + } + }, "supported_form_factors": ["ARDUINO"], "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USBHOST_OTHER"], "detect_code": ["0818"], @@ -1199,6 +1258,19 @@ "release_versions": ["2"], "device_name": "STM32L053C8" }, + "DISCO_L072CZ_LRWAN1": { + "inherits": ["Target"], + "core": "Cortex-M0+", + "default_toolchain": "ARM", + "extra_labels": ["STM", "STM32L0", "STM32L072CZ", "STM32L072xx"], + "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"], + "supported_form_factors": ["ARDUINO", "MORPHO"], + "macros": ["RTC_LSI=1"], + "detect_code": ["0833"], + "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"], + "release_versions": ["2", "5"], + "device_name": "STM32L072CZ" + }, "DISCO_F746NG": { "inherits": ["Target"], "core": "Cortex-M7F", @@ -1321,7 +1393,7 @@ "extra_labels": ["STM", "STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx", "FLASH_CMSIS_ALGO"], "macros": ["HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","MBEDTLS_ARC4_C","MBEDTLS_DES_C","MBEDTLS_MD4_C","MBEDTLS_MD5_C","MBEDTLS_SHA1_C"], "inherits": ["Target"], - "device_has": ["ANALOGIN", "CAN", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"], + "device_has": ["ANALOGIN", "CAN", "EMAC", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"], "features": ["LWIP"], "release_versions": ["5"], "device_name": "STM32F439ZI", @@ -2451,27 +2523,27 @@ "supported_form_factors": ["ARDUINO"], "core": "Cortex-M0", "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500"], - "supported_toolchains": ["uARM", "ARM"], + "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"], "inherits": ["Target"], "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"], - "release_versions": ["2"] + "release_versions": ["2", "5"] }, "WIZWIKI_W7500P": { "supported_form_factors": ["ARDUINO"], "core": "Cortex-M0", "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500P"], - "supported_toolchains": ["uARM", "ARM"], + "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"], "inherits": ["Target"], "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"], - "release_versions": ["2"] + "release_versions": ["2", "5"] }, "WIZWIKI_W7500ECO": { "inherits": ["Target"], "core": "Cortex-M0", "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500ECO"], - "supported_toolchains": ["uARM", "ARM"], + "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"], "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"], - "release_versions": ["2"] + "release_versions": ["2", "5"] }, "SAMR21G18A": { "inherits": ["Target"], @@ -2536,7 +2608,7 @@ "TARGET_MCU_NRF51822" ], "MERGE_BOOTLOADER": false, - "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822_UNIFIED", "NRF5"], + "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822_UNIFIED", "NRF5", "SDK11"], "OUTPUT_EXT": "hex", "is_disk_virtual": true, "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], @@ -2592,7 +2664,7 @@ "inherits": ["Target"], "core": "Cortex-M4F", "macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132"], - "extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5"], + "extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5", "SDK11", "NRF52_COMMON"], "OUTPUT_EXT": "hex", "is_disk_virtual": true, "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], @@ -2672,7 +2744,7 @@ "inherits": ["Target"], "core": "Cortex-M4F", "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5"], - "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5_SDK13"], + "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5", "SDK13", "NRF52_COMMON"], "OUTPUT_EXT": "hex", "is_disk_virtual": true, "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], diff --git a/tools/build_travis.py b/tools/build_travis.py index d40404d9af8..6b21be150a2 100644 --- a/tools/build_travis.py +++ b/tools/build_travis.py @@ -127,7 +127,7 @@ { "target": "SAMD21G18A", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "SAML21J18A", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "DISCO_L476VG", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb"] }, - + { "target": "DISCO_L072CZ_LRWAN1", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos"] }, { "target": "NUMAKER_PFM_NUC472", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb"] }, { "target": "NUMAKER_PFM_M453", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb"] }, ) @@ -251,6 +251,12 @@ "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], "rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"], "usb" : ["USB_1", "USB_2" ,"USB_3"], + } + }, + {"target": "DISCO_L072CZ_LRWAN1", + "toolchains": "GCC_ARM", + "tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"], + "rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"], } }, {"target": "NUMAKER_PFM_NUC472", diff --git a/tools/export/coide/__init__.py b/tools/export/coide/__init__.py index 5c570921c5e..87ffda57117 100644 --- a/tools/export/coide/__init__.py +++ b/tools/export/coide/__init__.py @@ -30,7 +30,6 @@ class CoIDE(Exporter): 'ARCH_PRO', 'ARCH_MAX', 'UBLOX_C027', - 'NUCLEO_L011K4', 'NUCLEO_L053R8', 'NUCLEO_L152RE', 'NUCLEO_F030R8', @@ -39,18 +38,14 @@ class CoIDE(Exporter): 'NUCLEO_F072RB', 'NUCLEO_F091RC', 'NUCLEO_F103RB', - 'NUCLEO_F207ZG', 'NUCLEO_F302R8', 'NUCLEO_F303K8', 'NUCLEO_F303RE', 'NUCLEO_F334R8', - 'NUCLEO_F303ZE', 'NUCLEO_F401RE', 'NUCLEO_F410RB', 'NUCLEO_F411RE', - 'NUCLEO_F429ZI', 'NUCLEO_F446RE', - 'NUCLEO_F446ZE', 'DISCO_L053C8', 'DISCO_F051R8', 'DISCO_F100RB', @@ -59,7 +54,6 @@ class CoIDE(Exporter): 'DISCO_F401VC', 'DISCO_F407VG', 'DISCO_F429ZI', - 'DISCO_F469NI', 'MTS_MDOT_F405RG', 'MTS_MDOT_F411RE', 'MOTE_L152RC', diff --git a/tools/export/embitz/__init__.py b/tools/export/embitz/__init__.py index 08ae1a971c5..c308728d2d7 100644 --- a/tools/export/embitz/__init__.py +++ b/tools/export/embitz/__init__.py @@ -21,7 +21,8 @@ POST_BINARY_WHITELIST = set([ "TEENSY3_1Code.binary_hook", - "LPCTargetCode.lpc_patch" + "LPCTargetCode.lpc_patch", + "LPC4088Code.binary_hook" ]) diff --git a/tools/export/gnuarmeclipse/__init__.py b/tools/export/gnuarmeclipse/__init__.py index 9217e6cd4d5..0ed9e69a430 100644 --- a/tools/export/gnuarmeclipse/__init__.py +++ b/tools/export/gnuarmeclipse/__init__.py @@ -61,7 +61,8 @@ def id(self): POST_BINARY_WHITELIST = set([ "TEENSY3_1Code.binary_hook", "MCU_NRF51Code.binary_hook", - "LPCTargetCode.lpc_patch" + "LPCTargetCode.lpc_patch", + "LPC4088Code.binary_hook" ]) class GNUARMEclipse(Exporter): diff --git a/tools/export/iar/__init__.py b/tools/export/iar/__init__.py index eea02fc1e16..e32118f4bf1 100644 --- a/tools/export/iar/__init__.py +++ b/tools/export/iar/__init__.py @@ -114,7 +114,7 @@ def generate(self): template = ["--vla", "--no_static_destruction"] # Flag invalid if set in template # Optimizations are also set in template - invalid_flag = lambda x: x in template or re.match("-O(\d|time|n)", x) + invalid_flag = lambda x: x in template or re.match("-O(\d|time|n|hz?)", x) flags['c_flags'] = [flag for flag in c_flags if not invalid_flag(flag)] try: diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index 34ea0ecb665..7ab30b32891 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -74,6 +74,9 @@ "STM32F446RE": { "OGChipSelectEditMenu": "STM32F446RE\tST STM32F446RE" }, + "STM32L072CZ": { + "OGChipSelectEditMenu": "STM32L072CZ\tST STM32L072CZ" + }, "STM32L073RZ": { "OGChipSelectEditMenu": "STM32L073RZ\tST STM32L073RZ" }, diff --git a/tools/export/makefile/__init__.py b/tools/export/makefile/__init__.py index 866a2dd8dec..c76bac7e1fe 100644 --- a/tools/export/makefile/__init__.py +++ b/tools/export/makefile/__init__.py @@ -38,7 +38,8 @@ class Makefile(Exporter): POST_BINARY_WHITELIST = set([ "MCU_NRF51Code.binary_hook", "TEENSY3_1Code.binary_hook", - "LPCTargetCode.lpc_patch" + "LPCTargetCode.lpc_patch", + "LPC4088Code.binary_hook" ]) def generate(self): diff --git a/tools/export/sw4stm32/__init__.py b/tools/export/sw4stm32/__init__.py index 9b046c72aed..963e47b81fd 100644 --- a/tools/export/sw4stm32/__init__.py +++ b/tools/export/sw4stm32/__init__.py @@ -25,46 +25,47 @@ class Sw4STM32(Exporter): TOOLCHAIN = 'GCC_ARM' BOARDS = { - 'B96B_F446VE': {'name': 'B96B-F446VE', 'mcuId': 'STM32F446VETx'}, - 'DISCO_F051R8': {'name': 'STM32F0DISCOVERY', 'mcuId': 'STM32F051R8Tx'}, - 'DISCO_F303VC': {'name': 'STM32F3DISCOVERY', 'mcuId': 'STM32F303VCTx'}, - 'DISCO_F334C8': {'name': 'STM32F3348DISCOVERY', 'mcuId': 'STM32F334C8Tx'}, - 'DISCO_F401VC': {'name': 'STM32F401C-DISCO', 'mcuId': 'STM32F401VCTx'}, - 'DISCO_F407VG': {'name': 'STM32F4DISCOVERY', 'mcuId': 'STM32F407VGTx'}, - 'DISCO_F429ZI': {'name': 'STM32F429I-DISCO', 'mcuId': 'STM32F429ZITx'}, - 'DISCO_F469NI': {'name': 'DISCO-F469NI', 'mcuId': 'STM32F469NIHx'}, - 'DISCO_F746NG': {'name': 'STM32F746G-DISCO', 'mcuId': 'STM32F746NGHx'}, - 'DISCO_F769NI': {'name': 'DISCO-F769NI', 'mcuId': 'STM32F769NIHx'}, - 'DISCO_L053C8': {'name': 'STM32L0538DISCOVERY', 'mcuId': 'STM32L053C8Tx'}, - 'DISCO_L476VG': {'name': 'STM32L476G-DISCO', 'mcuId': 'STM32L476VGTx'}, - 'NUCLEO_F030R8': {'name': 'NUCLEO-F030R8', 'mcuId': 'STM32F030R8Tx'}, - 'NUCLEO_F031K6': {'name': 'NUCLEO-F031K6', 'mcuId': 'STM32F031K6Tx'}, - 'NUCLEO_F042K6': {'name': 'NUCLEO-F042K6', 'mcuId': 'STM32F042K6Tx'}, - 'NUCLEO_F070RB': {'name': 'NUCLEO-F070RB', 'mcuId': 'STM32F070RBTx'}, - 'NUCLEO_F072RB': {'name': 'NUCLEO-F072RB', 'mcuId': 'STM32F072RBTx'}, - 'NUCLEO_F091RC': {'name': 'NUCLEO-F091RC', 'mcuId': 'STM32F091RCTx'}, - 'NUCLEO_F103RB': {'name': 'NUCLEO-F103RB', 'mcuId': 'STM32F103RBTx'}, - 'NUCLEO_F207ZG': {'name': 'NUCLEO-F207ZG', 'mcuId': 'STM32F207ZGTx'}, - 'NUCLEO_F302R8': {'name': 'NUCLEO-F302R8', 'mcuId': 'STM32F302R8Tx'}, - 'NUCLEO_F303K8': {'name': 'NUCLEO-F303K8', 'mcuId': 'STM32F303K8Tx'}, - 'NUCLEO_F303RE': {'name': 'NUCLEO-F303RE', 'mcuId': 'STM32F303RETx'}, - 'NUCLEO_F303ZE': {'name': 'NUCLEO-F303ZE', 'mcuId': 'STM32F303ZETx'}, - 'NUCLEO_F334R8': {'name': 'NUCLEO-F334R8', 'mcuId': 'STM32F334R8Tx'}, - 'NUCLEO_F401RE': {'name': 'NUCLEO-F401RE', 'mcuId': 'STM32F401RETx'}, - 'NUCLEO_F410RB': {'name': 'NUCLEO-F410RB', 'mcuId': 'STM32F410RBTx'}, - 'NUCLEO_F411RE': {'name': 'NUCLEO-F411RE', 'mcuId': 'STM32F411RETx'}, - 'NUCLEO_F429ZI': {'name': 'NUCLEO-F429ZI', 'mcuId': 'STM32F429ZITx'}, - 'NUCLEO_F446RE': {'name': 'NUCLEO-F446RE', 'mcuId': 'STM32F446RETx'}, - 'NUCLEO_F446ZE': {'name': 'NUCLEO-F446ZE', 'mcuId': 'STM32F446ZETx'}, - 'NUCLEO_F746ZG': {'name': 'NUCLEO-F746ZG', 'mcuId': 'STM32F746ZGTx'}, - 'NUCLEO_F767ZI': {'name': 'NUCLEO-F767ZI', 'mcuId': 'STM32F767ZITx'}, - 'NUCLEO_L011K4': {'name': 'NUCLEO-L011K4', 'mcuId': 'STM32L011K4Tx'}, - 'NUCLEO_L031K6': {'name': 'NUCLEO-L031K6', 'mcuId': 'STM32L031K6Tx'}, - 'NUCLEO_L053R8': {'name': 'NUCLEO-L053R8', 'mcuId': 'STM32L053R8Tx'}, - 'NUCLEO_L073RZ': {'name': 'NUCLEO-L073RZ', 'mcuId': 'STM32L073RZTx'}, - 'NUCLEO_L152RE': {'name': 'NUCLEO-L152RE', 'mcuId': 'STM32L152RETx'}, - 'NUCLEO_L432KC': {'name': 'NUCLEO-L432KC', 'mcuId': 'STM32L432KCUx'}, - 'NUCLEO_L476RG': {'name': 'NUCLEO-L476RG', 'mcuId': 'STM32L476RGTx'}, + 'B96B_F446VE': {'name': 'B96B-F446VE', 'mcuId': 'STM32F446VETx'}, + 'DISCO_F051R8': {'name': 'STM32F0DISCOVERY', 'mcuId': 'STM32F051R8Tx'}, + 'DISCO_F303VC': {'name': 'STM32F3DISCOVERY', 'mcuId': 'STM32F303VCTx'}, + 'DISCO_F334C8': {'name': 'STM32F3348DISCOVERY', 'mcuId': 'STM32F334C8Tx'}, + 'DISCO_F401VC': {'name': 'STM32F401C-DISCO', 'mcuId': 'STM32F401VCTx'}, + 'DISCO_F407VG': {'name': 'STM32F4DISCOVERY', 'mcuId': 'STM32F407VGTx'}, + 'DISCO_F429ZI': {'name': 'STM32F429I-DISCO', 'mcuId': 'STM32F429ZITx'}, + 'DISCO_F469NI': {'name': 'DISCO-F469NI', 'mcuId': 'STM32F469NIHx'}, + 'DISCO_F746NG': {'name': 'STM32F746G-DISCO', 'mcuId': 'STM32F746NGHx'}, + 'DISCO_F769NI': {'name': 'DISCO-F769NI', 'mcuId': 'STM32F769NIHx'}, + 'DISCO_L053C8': {'name': 'STM32L0538DISCOVERY', 'mcuId': 'STM32L053C8Tx'}, + 'DISCO_L072CZ_LRWAN1': {'name': 'DISCO-L072CZ-LRWAN1', 'mcuId': 'STM32L072CZTx'}, + 'DISCO_L476VG': {'name': 'STM32L476G-DISCO', 'mcuId': 'STM32L476VGTx'}, + 'NUCLEO_F030R8': {'name': 'NUCLEO-F030R8', 'mcuId': 'STM32F030R8Tx'}, + 'NUCLEO_F031K6': {'name': 'NUCLEO-F031K6', 'mcuId': 'STM32F031K6Tx'}, + 'NUCLEO_F042K6': {'name': 'NUCLEO-F042K6', 'mcuId': 'STM32F042K6Tx'}, + 'NUCLEO_F070RB': {'name': 'NUCLEO-F070RB', 'mcuId': 'STM32F070RBTx'}, + 'NUCLEO_F072RB': {'name': 'NUCLEO-F072RB', 'mcuId': 'STM32F072RBTx'}, + 'NUCLEO_F091RC': {'name': 'NUCLEO-F091RC', 'mcuId': 'STM32F091RCTx'}, + 'NUCLEO_F103RB': {'name': 'NUCLEO-F103RB', 'mcuId': 'STM32F103RBTx'}, + 'NUCLEO_F207ZG': {'name': 'NUCLEO-F207ZG', 'mcuId': 'STM32F207ZGTx'}, + 'NUCLEO_F302R8': {'name': 'NUCLEO-F302R8', 'mcuId': 'STM32F302R8Tx'}, + 'NUCLEO_F303K8': {'name': 'NUCLEO-F303K8', 'mcuId': 'STM32F303K8Tx'}, + 'NUCLEO_F303RE': {'name': 'NUCLEO-F303RE', 'mcuId': 'STM32F303RETx'}, + 'NUCLEO_F303ZE': {'name': 'NUCLEO-F303ZE', 'mcuId': 'STM32F303ZETx'}, + 'NUCLEO_F334R8': {'name': 'NUCLEO-F334R8', 'mcuId': 'STM32F334R8Tx'}, + 'NUCLEO_F401RE': {'name': 'NUCLEO-F401RE', 'mcuId': 'STM32F401RETx'}, + 'NUCLEO_F410RB': {'name': 'NUCLEO-F410RB', 'mcuId': 'STM32F410RBTx'}, + 'NUCLEO_F411RE': {'name': 'NUCLEO-F411RE', 'mcuId': 'STM32F411RETx'}, + 'NUCLEO_F429ZI': {'name': 'NUCLEO-F429ZI', 'mcuId': 'STM32F429ZITx'}, + 'NUCLEO_F446RE': {'name': 'NUCLEO-F446RE', 'mcuId': 'STM32F446RETx'}, + 'NUCLEO_F446ZE': {'name': 'NUCLEO-F446ZE', 'mcuId': 'STM32F446ZETx'}, + 'NUCLEO_F746ZG': {'name': 'NUCLEO-F746ZG', 'mcuId': 'STM32F746ZGTx'}, + 'NUCLEO_F767ZI': {'name': 'NUCLEO-F767ZI', 'mcuId': 'STM32F767ZITx'}, + 'NUCLEO_L011K4': {'name': 'NUCLEO-L011K4', 'mcuId': 'STM32L011K4Tx'}, + 'NUCLEO_L031K6': {'name': 'NUCLEO-L031K6', 'mcuId': 'STM32L031K6Tx'}, + 'NUCLEO_L053R8': {'name': 'NUCLEO-L053R8', 'mcuId': 'STM32L053R8Tx'}, + 'NUCLEO_L073RZ': {'name': 'NUCLEO-L073RZ', 'mcuId': 'STM32L073RZTx'}, + 'NUCLEO_L152RE': {'name': 'NUCLEO-L152RE', 'mcuId': 'STM32L152RETx'}, + 'NUCLEO_L432KC': {'name': 'NUCLEO-L432KC', 'mcuId': 'STM32L432KCUx'}, + 'NUCLEO_L476RG': {'name': 'NUCLEO-L476RG', 'mcuId': 'STM32L476RGTx'}, } TARGETS = BOARDS.keys() diff --git a/tools/targets.py b/tools/targets.py index 84ae222b1cc..edcd33181dc 100644 --- a/tools/targets.py +++ b/tools/targets.py @@ -489,7 +489,7 @@ def binary_hook(t_self, resources, _, binf): binh.merge(blh) with open(binf.replace(".bin", ".hex"), "w") as fileout: - binh.tofile(fileout, format='hex') + binh.write_hex_file(fileout, write_start_addr=False) class NCS36510TargetCode: @staticmethod diff --git a/tools/tests.py b/tools/tests.py index a7e2647070a..afee638c829 100644 --- a/tools/tests.py +++ b/tools/tests.py @@ -187,7 +187,7 @@ "peripherals": ["analog_loop"], "mcu": ["LPC1768", "LPC2368", "LPC2460", "KL25Z", "K64F", "K66F", "K22F", "LPC4088", "LPC1549", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_F302R8", "NUCLEO_F303K8", "NUCLEO_F303RE", "NUCLEO_F207ZG", - "NUCLEO_F334R8", "NUCLEO_F303ZE", "NUCLEO_L053R8", "NUCLEO_L073RZ", "NUCLEO_L152RE", + "NUCLEO_F334R8", "NUCLEO_F303ZE", "NUCLEO_L053R8", "DISCO_L072CZ_LRWAN1", "NUCLEO_L073RZ", "NUCLEO_L152RE", "NUCLEO_F410RB", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F429ZI", "DISCO_F407VG", "NUCLEO_F746ZG", "NUCLEO_L476RG", "DISCO_L053C8", "DISCO_F334C8", "DISCO_L476VG", "DISCO_F469NI", "DISCO_F429ZI", "DISCO_F769NI", @@ -693,7 +693,7 @@ "KL25Z", "KL05Z", "K22F", "K64F", "K66F", "KL43Z", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F412ZG", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F070RB", "NUCLEO_F207ZG", - "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_L072CZ_LRWAN1", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303ZE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", "NUMAKER_PFM_NUC472", "NUMAKER_PFM_M453", @@ -708,7 +708,7 @@ "KL25Z", "KL05Z", "K22F", "K64F", "K66F", "KL43Z", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F412ZG", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", - "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_L072CZ_LRWAN1", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F446ZE", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", @@ -724,7 +724,7 @@ "KL25Z", "KL05Z", "K22F", "K64F", "K66F", "KL43Z", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F412ZG", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", - "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_L072CZ_LRWAN1", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", @@ -741,7 +741,7 @@ "KL25Z", "KL05Z", "K22F", "K64F", "K66F", "KL43Z", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F412ZG", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", - "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_L072CZ_LRWAN1", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", @@ -758,7 +758,7 @@ "KL25Z", "KL05Z", "K22F", "K64F", "K66F", "KL43Z", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F412ZG", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", - "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_L072CZ_LRWAN1", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", @@ -774,7 +774,7 @@ "KL25Z", "KL05Z", "K22F", "K64F", "K66F", "KL43Z", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F412ZG", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", - "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_L072CZ_LRWAN1", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", @@ -791,7 +791,7 @@ "KL25Z", "KL05Z", "K22F", "K64F", "K66F", "KL43Z", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F412ZG", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", - "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_L072CZ_LRWAN1", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800", @@ -807,7 +807,7 @@ "KL25Z", "KL05Z", "K22F", "K64F", "K66F", "KL43Z", "KL46Z", "HEXIWEAR", "RZ_A1H", "VK_RZ_A1H", "DISCO_F407VG", "DISCO_F429ZI", "NUCLEO_F411RE", "NUCLEO_F412ZG", "DISCO_F469NI", "NUCLEO_F410RB", "NUCLEO_F429ZI", "NUCLEO_F401RE", "NUCLEO_F334R8", "DISCO_F334C8", "NUCLEO_F302R8", "NUCLEO_F303ZE", "NUCLEO_F070RB", "NUCLEO_F207ZG", - "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", + "DISCO_L072CZ_LRWAN1", "NUCLEO_L073RZ", "NUCLEO_F072RB", "NUCLEO_F091RC", "NUCLEO_L432KC", "DISCO_L476VG", "NUCLEO_L476RG", "DISCO_F401VC", "NUCLEO_F303RE", "NUCLEO_F303K8", "MAXWSNENV", "MAX32600MBED", "NUCLEO_L152RE", "NUCLEO_F446RE", "NUCLEO_F446ZE", "NUCLEO_F103RB", "DISCO_F746NG", "NUCLEO_F746ZG", "MOTE_L152RC", "B96B_F446VE", "EFM32HG_STK3400", "EFM32PG_STK3401", "EFM32LG_STK3600", "EFM32GG_STK3700", "EFM32WG_STK3800",